2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28 #include <linux/spinlock.h>
29 #include <linux/ioctl.h>
31 /* platform driver name to register */
32 #define NVT_DRIVER_NAME "nuvoton-cir"
34 /* debugging module parameter */
38 #define nvt_dbg(text, ...) \
41 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
43 #define nvt_dbg_verbose(text, ...) \
46 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
48 #define nvt_dbg_wake(text, ...) \
51 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
55 * Original lirc driver said min value of 76, and recommended value of 256
56 * for the buffer length, but then used 2048. Never mind that the size of the
57 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
58 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
59 * and I don't have TX-capable hardware to test/debug on...
61 #define TX_BUF_LEN 256
64 #define SIO_ID_MASK 0xfff0
68 NVT_W83667HG
= 0xa510,
77 enum nvt_chip_ver chip_ver
;
93 unsigned int buf_count
;
94 unsigned int cur_buf_num
;
95 wait_queue_head_t queue
;
99 /* EFER Config register index/data pair */
103 /* hardware I/O settings */
104 unsigned long cir_addr
;
105 unsigned long cir_wake_addr
;
108 enum nvt_chip_ver chip_ver
;
113 /* hardware features */
114 bool hw_learning_capable
;
118 bool learning_enabled
;
120 /* carrier period = 1 / frequency */
125 #define ST_TX_NONE 0x0
126 #define ST_TX_REQUEST 0x2
127 #define ST_TX_REPLY 0x4
129 /* buffer packet constants */
130 #define BUF_PULSE_BIT 0x80
131 #define BUF_LEN_MASK 0x7f
132 #define BUF_REPEAT_BYTE 0x70
133 #define BUF_REPEAT_MASK 0xf0
137 /* total length of CIR and CIR WAKE */
138 #define CIR_IOREG_LENGTH 0x0f
140 /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */
141 #define CIR_RX_LIMIT_COUNT (IR_DEFAULT_TIMEOUT / US_TO_NS(SAMPLE_PERIOD))
144 #define CIR_IRCON 0x00
145 #define CIR_IRSTS 0x01
146 #define CIR_IREN 0x02
147 #define CIR_RXFCONT 0x03
150 #define CIR_SLCH 0x06
151 #define CIR_SLCL 0x07
152 #define CIR_FIFOCON 0x08
153 #define CIR_IRFIFOSTS 0x09
154 #define CIR_SRXFIFO 0x0a
155 #define CIR_TXFCONT 0x0b
156 #define CIR_STXFIFO 0x0c
157 #define CIR_FCCH 0x0d
158 #define CIR_FCCL 0x0e
159 #define CIR_IRFSM 0x0f
161 /* CIR IRCON settings */
162 #define CIR_IRCON_RECV 0x80
163 #define CIR_IRCON_WIREN 0x40
164 #define CIR_IRCON_TXEN 0x20
165 #define CIR_IRCON_RXEN 0x10
166 #define CIR_IRCON_WRXINV 0x08
167 #define CIR_IRCON_RXINV 0x04
169 #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00
170 #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01
171 #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02
172 #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
174 /* FIXME: make this a runtime option */
175 /* select sample period as 50us */
176 #define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
178 /* CIR IRSTS settings */
179 #define CIR_IRSTS_RDR 0x80
180 #define CIR_IRSTS_RTR 0x40
181 #define CIR_IRSTS_PE 0x20
182 #define CIR_IRSTS_RFO 0x10
183 #define CIR_IRSTS_TE 0x08
184 #define CIR_IRSTS_TTR 0x04
185 #define CIR_IRSTS_TFU 0x02
186 #define CIR_IRSTS_GH 0x01
188 /* CIR IREN settings */
189 #define CIR_IREN_RDR 0x80
190 #define CIR_IREN_RTR 0x40
191 #define CIR_IREN_PE 0x20
192 #define CIR_IREN_RFO 0x10
193 #define CIR_IREN_TE 0x08
194 #define CIR_IREN_TTR 0x04
195 #define CIR_IREN_TFU 0x02
196 #define CIR_IREN_GH 0x01
198 /* CIR FIFOCON settings */
199 #define CIR_FIFOCON_TXFIFOCLR 0x80
201 #define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00
202 #define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10
203 #define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20
204 #define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30
206 /* FIXME: make this a runtime option */
207 /* select TX trigger level as 16 */
208 #define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16
210 #define CIR_FIFOCON_RXFIFOCLR 0x08
212 #define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00
213 #define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01
214 #define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02
215 #define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03
217 /* FIXME: make this a runtime option */
218 /* select RX trigger level as 24 */
219 #define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24
221 /* CIR IRFIFOSTS settings */
222 #define CIR_IRFIFOSTS_IR_PENDING 0x80
223 #define CIR_IRFIFOSTS_RX_GS 0x40
224 #define CIR_IRFIFOSTS_RX_FTA 0x20
225 #define CIR_IRFIFOSTS_RX_EMPTY 0x10
226 #define CIR_IRFIFOSTS_RX_FULL 0x08
227 #define CIR_IRFIFOSTS_TX_FTA 0x04
228 #define CIR_IRFIFOSTS_TX_EMPTY 0x02
229 #define CIR_IRFIFOSTS_TX_FULL 0x01
232 /* CIR WAKE UP Regs */
233 #define CIR_WAKE_IRCON 0x00
234 #define CIR_WAKE_IRSTS 0x01
235 #define CIR_WAKE_IREN 0x02
236 #define CIR_WAKE_FIFO_CMP_DEEP 0x03
237 #define CIR_WAKE_FIFO_CMP_TOL 0x04
238 #define CIR_WAKE_FIFO_COUNT 0x05
239 #define CIR_WAKE_SLCH 0x06
240 #define CIR_WAKE_SLCL 0x07
241 #define CIR_WAKE_FIFOCON 0x08
242 #define CIR_WAKE_SRXFSTS 0x09
243 #define CIR_WAKE_SAMPLE_RX_FIFO 0x0a
244 #define CIR_WAKE_WR_FIFO_DATA 0x0b
245 #define CIR_WAKE_RD_FIFO_ONLY 0x0c
246 #define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d
247 #define CIR_WAKE_FIFO_IGNORE 0x0e
248 #define CIR_WAKE_IRFSM 0x0f
250 /* CIR WAKE UP IRCON settings */
251 #define CIR_WAKE_IRCON_DEC_RST 0x80
252 #define CIR_WAKE_IRCON_MODE1 0x40
253 #define CIR_WAKE_IRCON_MODE0 0x20
254 #define CIR_WAKE_IRCON_RXEN 0x10
255 #define CIR_WAKE_IRCON_R 0x08
256 #define CIR_WAKE_IRCON_RXINV 0x04
258 /* FIXME/jarod: make this a runtime option */
259 /* select a same sample period like cir register */
260 #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
262 /* CIR WAKE IRSTS Bits */
263 #define CIR_WAKE_IRSTS_RDR 0x80
264 #define CIR_WAKE_IRSTS_RTR 0x40
265 #define CIR_WAKE_IRSTS_PE 0x20
266 #define CIR_WAKE_IRSTS_RFO 0x10
267 #define CIR_WAKE_IRSTS_GH 0x08
268 #define CIR_WAKE_IRSTS_IR_PENDING 0x01
270 /* CIR WAKE UP IREN Bits */
271 #define CIR_WAKE_IREN_RDR 0x80
272 #define CIR_WAKE_IREN_RTR 0x40
273 #define CIR_WAKE_IREN_PE 0x20
274 #define CIR_WAKE_IREN_RFO 0x10
275 #define CIR_WAKE_IREN_GH 0x08
277 /* CIR WAKE FIFOCON settings */
278 #define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08
280 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00
281 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01
282 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02
283 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03
285 /* FIXME: make this a runtime option */
286 /* select WAKE UP RX trigger level as 67 */
287 #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
289 /* CIR WAKE SRXFSTS settings */
290 #define CIR_WAKE_IRFIFOSTS_RX_GS 0x80
291 #define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40
292 #define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20
293 #define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10
296 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
297 * the system comparing only 65 bytes (fails with this set to 67)
299 #define CIR_WAKE_FIFO_CMP_BYTES 65
300 /* CIR Wake byte comparison tolerance */
301 #define CIR_WAKE_CMP_TOLERANCE 5
304 * Extended Function Enable Registers:
305 * Extended Function Index Register
306 * Extended Function Data Register
311 /* Possible alternate EFER values, depends on how the chip is wired */
312 #define CR_EFIR2 0x4e
313 #define CR_EFDR2 0x4f
315 /* Extended Function Mode enable/disable magic values */
316 #define EFER_EFM_ENABLE 0x87
317 #define EFER_EFM_DISABLE 0xaa
319 /* Config regs we need to care about */
320 #define CR_SOFTWARE_RESET 0x02
321 #define CR_LOGICAL_DEV_SEL 0x07
322 #define CR_CHIP_ID_HI 0x20
323 #define CR_CHIP_ID_LO 0x21
324 #define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
325 #define CR_OUTPUT_PIN_SEL 0x27
326 #define CR_MULTIFUNC_PIN_SEL 0x2c
327 #define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
328 /* next three regs valid for both the CIR and CIR_WAKE logical devices */
329 #define CR_CIR_BASE_ADDR_HI 0x60
330 #define CR_CIR_BASE_ADDR_LO 0x61
331 #define CR_CIR_IRQ_RSRC 0x70
332 /* next three regs valid only for ACPI logical dev */
333 #define CR_ACPI_CIR_WAKE 0xe0
334 #define CR_ACPI_IRQ_EVENTS 0xf6
335 #define CR_ACPI_IRQ_EVENTS2 0xf7
337 /* Logical devices that we need to care about */
338 #define LOGICAL_DEV_LPT 0x01
339 #define LOGICAL_DEV_CIR 0x06
340 #define LOGICAL_DEV_ACPI 0x0a
341 #define LOGICAL_DEV_CIR_WAKE 0x0e
343 #define LOGICAL_DEV_DISABLE 0x00
344 #define LOGICAL_DEV_ENABLE 0x01
346 #define CIR_WAKE_ENABLE_BIT 0x08
347 #define PME_INTR_CIR_PASS_BIT 0x08
349 /* w83677hg CIR pin config */
350 #define OUTPUT_PIN_SEL_MASK 0xbc
351 #define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
352 #define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
354 /* w83667hg CIR pin config */
355 #define MULTIFUNC_PIN_SEL_MASK 0x1f
356 #define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
357 #define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
359 /* MCE CIR signal length, related on sample period */
361 /* MCE CIR controller signal length: about 43ms
362 * 43ms / 50us (sample period) * 0.85 (inaccuracy)
364 #define CONTROLLER_BUF_LEN_MIN 830
366 /* MCE CIR keyboard signal length: about 26ms
367 * 26ms / 50us (sample period) * 0.85 (inaccuracy)
369 #define KEYBOARD_BUF_LEN_MAX 650
370 #define KEYBOARD_BUF_LEN_MIN 610
372 /* MCE CIR mouse signal length: about 24ms
373 * 24ms / 50us (sample period) * 0.85 (inaccuracy)
375 #define MOUSE_BUF_LEN_MIN 565
377 #define CIR_SAMPLE_PERIOD 50
378 #define CIR_SAMPLE_LOW_INACCURACY 0.85
380 /* MAX silence time that driver will sent to lirc */
381 #define MAX_SILENCE_TIME 60000
383 #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
384 #define SAMPLE_PERIOD 100
386 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
387 #define SAMPLE_PERIOD 50
389 #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
390 #define SAMPLE_PERIOD 25
393 #define SAMPLE_PERIOD 1
396 /* as VISTA MCE definition, valid carrier value */
397 #define MAX_CARRIER 60000
398 #define MIN_CARRIER 30000
400 /* max wakeup sequence length */
401 #define WAKEUP_MAX_SIZE 65
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