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[deliverable/linux.git] / drivers / media / rc / winbond-cir.c
1 /*
2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
3 * SuperI/O chips.
4 *
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
8 *
9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2009 - 2010 David Härdeman <david@hardeman.nu>
11 *
12 * Dedicated to my daughter Matilda, without whose loving attention this
13 * driver would have been finished in half the time and with a fraction
14 * of the bugs.
15 *
16 * Written using:
17 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
18 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
19 * o DSDT dumps
20 *
21 * Supported features:
22 * o IR Receive
23 * o IR Transmit
24 * o Wake-On-CIR functionality
25 *
26 * To do:
27 * o Learning
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License as published by
31 * the Free Software Foundation; either version 2 of the License, or
32 * (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
42 */
43
44 #include <linux/module.h>
45 #include <linux/pnp.h>
46 #include <linux/interrupt.h>
47 #include <linux/timer.h>
48 #include <linux/leds.h>
49 #include <linux/spinlock.h>
50 #include <linux/pci_ids.h>
51 #include <linux/io.h>
52 #include <linux/bitrev.h>
53 #include <linux/slab.h>
54 #include <linux/wait.h>
55 #include <linux/sched.h>
56 #include <media/rc-core.h>
57
58 #define DRVNAME "winbond-cir"
59
60 /* CEIR Wake-Up Registers, relative to data->wbase */
61 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
62 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
63 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
64 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
65 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
66 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
67 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
68 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
69 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
70 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
71
72 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
73 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
74 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
75 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
76 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
77 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
78
79 /* SP3 Banked Registers, relative to data->sbase */
80 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
81 /* Bank 0 */
82 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
83 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
84 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
85 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
86 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
87 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
88 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
89 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
90 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
91 /* Bank 2 */
92 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
93 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
94 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
95 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
96 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
97 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
98 /* Bank 3 */
99 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
100 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
101 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
102 /* Bank 4 */
103 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
104 /* Bank 5 */
105 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
106 /* Bank 6 */
107 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
108 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
109 /* Bank 7 */
110 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
111 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
112 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
113 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
114 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
115
116 /*
117 * Magic values follow
118 */
119
120 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
121 #define WBCIR_IRQ_NONE 0x00
122 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
123 #define WBCIR_IRQ_RX 0x01
124 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
125 #define WBCIR_IRQ_TX_LOW 0x02
126 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
127 #define WBCIR_IRQ_ERR 0x04
128 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
129 #define WBCIR_IRQ_TX_EMPTY 0x20
130 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
131 #define WBCIR_LED_ENABLE 0x80
132 /* RX data available bit for WBCIR_REG_SP3_LSR */
133 #define WBCIR_RX_AVAIL 0x01
134 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
135 #define WBCIR_RX_OVERRUN 0x02
136 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
137 #define WBCIR_TX_EOT 0x04
138 /* RX disable bit for WBCIR_REG_SP3_ASCR */
139 #define WBCIR_RX_DISABLE 0x20
140 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
141 #define WBCIR_TX_UNDERRUN 0x40
142 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
143 #define WBCIR_EXT_ENABLE 0x01
144 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
145 #define WBCIR_REGSEL_COMPARE 0x10
146 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
147 #define WBCIR_REGSEL_MASK 0x20
148 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
149 #define WBCIR_REG_ADDR0 0x00
150
151 /* Valid banks for the SP3 UART */
152 enum wbcir_bank {
153 WBCIR_BANK_0 = 0x00,
154 WBCIR_BANK_1 = 0x80,
155 WBCIR_BANK_2 = 0xE0,
156 WBCIR_BANK_3 = 0xE4,
157 WBCIR_BANK_4 = 0xE8,
158 WBCIR_BANK_5 = 0xEC,
159 WBCIR_BANK_6 = 0xF0,
160 WBCIR_BANK_7 = 0xF4,
161 };
162
163 /* Supported power-on IR Protocols */
164 enum wbcir_protocol {
165 IR_PROTOCOL_RC5 = 0x0,
166 IR_PROTOCOL_NEC = 0x1,
167 IR_PROTOCOL_RC6 = 0x2,
168 };
169
170 /* Possible states for IR reception */
171 enum wbcir_rxstate {
172 WBCIR_RXSTATE_INACTIVE = 0,
173 WBCIR_RXSTATE_ACTIVE,
174 WBCIR_RXSTATE_ERROR
175 };
176
177 /* Possible states for IR transmission */
178 enum wbcir_txstate {
179 WBCIR_TXSTATE_INACTIVE = 0,
180 WBCIR_TXSTATE_ACTIVE,
181 WBCIR_TXSTATE_DONE,
182 WBCIR_TXSTATE_ERROR
183 };
184
185 /* Misc */
186 #define WBCIR_NAME "Winbond CIR"
187 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
188 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
189 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
190 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
191 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
192 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
193
194 /* Per-device data */
195 struct wbcir_data {
196 spinlock_t spinlock;
197 struct rc_dev *dev;
198 struct led_classdev led;
199
200 unsigned long wbase; /* Wake-Up Baseaddr */
201 unsigned long ebase; /* Enhanced Func. Baseaddr */
202 unsigned long sbase; /* Serial Port Baseaddr */
203 unsigned int irq; /* Serial Port IRQ */
204 u8 irqmask;
205
206 /* RX state */
207 enum wbcir_rxstate rxstate;
208 struct led_trigger *rxtrigger;
209 struct ir_raw_event rxev;
210
211 /* TX state */
212 enum wbcir_txstate txstate;
213 struct led_trigger *txtrigger;
214 u32 txlen;
215 u32 txoff;
216 u32 *txbuf;
217 wait_queue_head_t txwaitq;
218 u8 txmask;
219 u32 txcarrier;
220 };
221
222 static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
223 module_param(protocol, uint, 0444);
224 MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command "
225 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
226
227 static int invert; /* default = 0 */
228 module_param(invert, bool, 0444);
229 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
230
231 static int txandrx; /* default = 0 */
232 module_param(txandrx, bool, 0444);
233 MODULE_PARM_DESC(invert, "Allow simultaneous TX and RX");
234
235 static unsigned int wake_sc = 0x800F040C;
236 module_param(wake_sc, uint, 0644);
237 MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
238
239 static unsigned int wake_rc6mode = 6;
240 module_param(wake_rc6mode, uint, 0644);
241 MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command "
242 "(0 = 0, 6 = 6A, default)");
243
244
245
246 /*****************************************************************************
247 *
248 * UTILITY FUNCTIONS
249 *
250 *****************************************************************************/
251
252 /* Caller needs to hold wbcir_lock */
253 static void
254 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
255 {
256 u8 val;
257
258 val = inb(addr);
259 val = ((val & ~mask) | (bits & mask));
260 outb(val, addr);
261 }
262
263 /* Selects the register bank for the serial port */
264 static inline void
265 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
266 {
267 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
268 }
269
270 static inline void
271 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
272 {
273 if (data->irqmask == irqmask)
274 return;
275
276 wbcir_select_bank(data, WBCIR_BANK_0);
277 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
278 data->irqmask = irqmask;
279 }
280
281 static enum led_brightness
282 wbcir_led_brightness_get(struct led_classdev *led_cdev)
283 {
284 struct wbcir_data *data = container_of(led_cdev,
285 struct wbcir_data,
286 led);
287
288 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
289 return LED_FULL;
290 else
291 return LED_OFF;
292 }
293
294 static void
295 wbcir_led_brightness_set(struct led_classdev *led_cdev,
296 enum led_brightness brightness)
297 {
298 struct wbcir_data *data = container_of(led_cdev,
299 struct wbcir_data,
300 led);
301
302 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
303 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
304 WBCIR_LED_ENABLE);
305 }
306
307 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
308 static u8
309 wbcir_to_rc6cells(u8 val)
310 {
311 u8 coded = 0x00;
312 int i;
313
314 val &= 0x0F;
315 for (i = 0; i < 4; i++) {
316 if (val & 0x01)
317 coded |= 0x02 << (i * 2);
318 else
319 coded |= 0x01 << (i * 2);
320 val >>= 1;
321 }
322
323 return coded;
324 }
325
326 /*****************************************************************************
327 *
328 * INTERRUPT FUNCTIONS
329 *
330 *****************************************************************************/
331
332 static void
333 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
334 {
335 u8 irdata[8];
336 bool disable = true;
337 unsigned int i;
338
339 if (data->rxstate == WBCIR_RXSTATE_INACTIVE) {
340 data->rxstate = WBCIR_RXSTATE_ACTIVE;
341 led_trigger_event(data->rxtrigger, LED_FULL);
342 }
343
344 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
345 insb(data->sbase + WBCIR_REG_SP3_RXDATA, &irdata[0], 8);
346
347 for (i = 0; i < 8; i++) {
348 u8 pulse;
349 u32 duration;
350
351 if (irdata[i] != 0xFF && irdata[i] != 0x00)
352 disable = false;
353
354 if (data->rxstate == WBCIR_RXSTATE_ERROR)
355 continue;
356
357 pulse = irdata[i] & 0x80 ? false : true;
358 duration = (irdata[i] & 0x7F) * 10000; /* ns */
359
360 if (data->rxev.pulse != pulse) {
361 if (data->rxev.duration != 0) {
362 ir_raw_event_store(data->dev, &data->rxev);
363 data->rxev.duration = 0;
364 }
365
366 data->rxev.pulse = pulse;
367 }
368
369 data->rxev.duration += duration;
370 }
371
372 if (disable) {
373 if (data->rxev.duration != 0 &&
374 data->rxstate != WBCIR_RXSTATE_ERROR) {
375 ir_raw_event_store(data->dev, &data->rxev);
376 data->rxev.duration = 0;
377 }
378
379 /* Set RXINACTIVE */
380 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
381
382 /* Drain the FIFO */
383 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL)
384 inb(data->sbase + WBCIR_REG_SP3_RXDATA);
385
386 ir_raw_event_reset(data->dev);
387 led_trigger_event(data->rxtrigger, LED_OFF);
388 data->rxstate = WBCIR_RXSTATE_INACTIVE;
389 }
390
391 ir_raw_event_handle(data->dev);
392 }
393
394 static void
395 wbcir_irq_tx(struct wbcir_data *data)
396 {
397 unsigned int space;
398 unsigned int used;
399 u8 bytes[16];
400 u8 byte;
401
402 if (!data->txbuf)
403 return;
404
405 switch (data->txstate) {
406 case WBCIR_TXSTATE_INACTIVE:
407 /* TX FIFO empty */
408 space = 16;
409 led_trigger_event(data->txtrigger, LED_FULL);
410 break;
411 case WBCIR_TXSTATE_ACTIVE:
412 /* TX FIFO low (3 bytes or less) */
413 space = 13;
414 break;
415 case WBCIR_TXSTATE_ERROR:
416 space = 0;
417 break;
418 default:
419 return;
420 }
421
422 /*
423 * TX data is run-length coded in bytes: YXXXXXXX
424 * Y = space (1) or pulse (0)
425 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
426 */
427 for (used = 0; used < space && data->txoff != data->txlen; used++) {
428 if (data->txbuf[data->txoff] == 0) {
429 data->txoff++;
430 continue;
431 }
432 byte = min((u32)0x80, data->txbuf[data->txoff]);
433 data->txbuf[data->txoff] -= byte;
434 byte--;
435 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
436 bytes[used] = byte;
437 }
438
439 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
440 data->txoff++;
441
442 if (used == 0) {
443 /* Finished */
444 if (data->txstate == WBCIR_TXSTATE_ERROR)
445 /* Clear TX underrun bit */
446 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
447 else
448 data->txstate = WBCIR_TXSTATE_DONE;
449 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
450 led_trigger_event(data->txtrigger, LED_OFF);
451 wake_up(&data->txwaitq);
452 } else if (data->txoff == data->txlen) {
453 /* At the end of transmission, tell the hw before last byte */
454 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
455 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
456 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
457 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
458 WBCIR_IRQ_TX_EMPTY);
459 } else {
460 /* More data to follow... */
461 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
462 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
463 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
464 WBCIR_IRQ_TX_LOW);
465 data->txstate = WBCIR_TXSTATE_ACTIVE;
466 }
467 }
468 }
469
470 static irqreturn_t
471 wbcir_irq_handler(int irqno, void *cookie)
472 {
473 struct pnp_dev *device = cookie;
474 struct wbcir_data *data = pnp_get_drvdata(device);
475 unsigned long flags;
476 u8 status;
477
478 spin_lock_irqsave(&data->spinlock, flags);
479 wbcir_select_bank(data, WBCIR_BANK_0);
480 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
481 status &= data->irqmask;
482
483 if (!status) {
484 spin_unlock_irqrestore(&data->spinlock, flags);
485 return IRQ_NONE;
486 }
487
488 if (status & WBCIR_IRQ_ERR) {
489 /* RX overflow? (read clears bit) */
490 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
491 data->rxstate = WBCIR_RXSTATE_ERROR;
492 ir_raw_event_reset(data->dev);
493 }
494
495 /* TX underflow? */
496 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
497 data->txstate = WBCIR_TXSTATE_ERROR;
498 }
499
500 if (status & WBCIR_IRQ_RX)
501 wbcir_irq_rx(data, device);
502
503 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
504 wbcir_irq_tx(data);
505
506 spin_unlock_irqrestore(&data->spinlock, flags);
507 return IRQ_HANDLED;
508 }
509
510 /*****************************************************************************
511 *
512 * RC-CORE INTERFACE FUNCTIONS
513 *
514 *****************************************************************************/
515
516 static int
517 wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
518 {
519 struct wbcir_data *data = dev->priv;
520 unsigned long flags;
521 u8 val;
522 u32 freq;
523
524 freq = DIV_ROUND_CLOSEST(carrier, 1000);
525 if (freq < 30 || freq > 60)
526 return -EINVAL;
527
528 switch (freq) {
529 case 58:
530 case 59:
531 case 60:
532 val = freq - 58;
533 freq *= 1000;
534 break;
535 case 57:
536 val = freq - 27;
537 freq = 56900;
538 break;
539 default:
540 val = freq - 27;
541 freq *= 1000;
542 break;
543 }
544
545 spin_lock_irqsave(&data->spinlock, flags);
546 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
547 spin_unlock_irqrestore(&data->spinlock, flags);
548 return -EBUSY;
549 }
550
551 if (data->txcarrier != freq) {
552 wbcir_select_bank(data, WBCIR_BANK_7);
553 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
554 data->txcarrier = freq;
555 }
556
557 spin_unlock_irqrestore(&data->spinlock, flags);
558 return 0;
559 }
560
561 static int
562 wbcir_txmask(struct rc_dev *dev, u32 mask)
563 {
564 struct wbcir_data *data = dev->priv;
565 unsigned long flags;
566 u8 val;
567
568 /* Four outputs, only one output can be enabled at a time */
569 switch (mask) {
570 case 0x1:
571 val = 0x0;
572 break;
573 case 0x2:
574 val = 0x1;
575 break;
576 case 0x4:
577 val = 0x2;
578 break;
579 case 0x8:
580 val = 0x3;
581 break;
582 default:
583 return -EINVAL;
584 }
585
586 spin_lock_irqsave(&data->spinlock, flags);
587 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
588 spin_unlock_irqrestore(&data->spinlock, flags);
589 return -EBUSY;
590 }
591
592 if (data->txmask != mask) {
593 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
594 data->txmask = mask;
595 }
596
597 spin_unlock_irqrestore(&data->spinlock, flags);
598 return 0;
599 }
600
601 static int
602 wbcir_tx(struct rc_dev *dev, int *buf, u32 bufsize)
603 {
604 struct wbcir_data *data = dev->priv;
605 u32 count;
606 unsigned i;
607 unsigned long flags;
608
609 /* bufsize has been sanity checked by the caller */
610 count = bufsize / sizeof(int);
611
612 /* Not sure if this is possible, but better safe than sorry */
613 spin_lock_irqsave(&data->spinlock, flags);
614 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
615 spin_unlock_irqrestore(&data->spinlock, flags);
616 return -EBUSY;
617 }
618
619 /* Convert values to multiples of 10us */
620 for (i = 0; i < count; i++)
621 buf[i] = DIV_ROUND_CLOSEST(buf[i], 10);
622
623 /* Fill the TX fifo once, the irq handler will do the rest */
624 data->txbuf = buf;
625 data->txlen = count;
626 data->txoff = 0;
627 wbcir_irq_tx(data);
628
629 /* Wait for the TX to complete */
630 while (data->txstate == WBCIR_TXSTATE_ACTIVE) {
631 spin_unlock_irqrestore(&data->spinlock, flags);
632 wait_event(data->txwaitq, data->txstate != WBCIR_TXSTATE_ACTIVE);
633 spin_lock_irqsave(&data->spinlock, flags);
634 }
635
636 /* We're done */
637 if (data->txstate == WBCIR_TXSTATE_ERROR)
638 count = -EAGAIN;
639 data->txstate = WBCIR_TXSTATE_INACTIVE;
640 data->txbuf = NULL;
641 spin_unlock_irqrestore(&data->spinlock, flags);
642
643 return count;
644 }
645
646 /*****************************************************************************
647 *
648 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
649 *
650 *****************************************************************************/
651
652 static void
653 wbcir_shutdown(struct pnp_dev *device)
654 {
655 struct device *dev = &device->dev;
656 struct wbcir_data *data = pnp_get_drvdata(device);
657 bool do_wake = true;
658 u8 match[11];
659 u8 mask[11];
660 u8 rc6_csl = 0;
661 int i;
662
663 memset(match, 0, sizeof(match));
664 memset(mask, 0, sizeof(mask));
665
666 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
667 do_wake = false;
668 goto finish;
669 }
670
671 switch (protocol) {
672 case IR_PROTOCOL_RC5:
673 if (wake_sc > 0xFFF) {
674 do_wake = false;
675 dev_err(dev, "RC5 - Invalid wake scancode\n");
676 break;
677 }
678
679 /* Mask = 13 bits, ex toggle */
680 mask[0] = 0xFF;
681 mask[1] = 0x17;
682
683 match[0] = (wake_sc & 0x003F); /* 6 command bits */
684 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
685 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
686 if (!(wake_sc & 0x0040)) /* 2nd start bit */
687 match[1] |= 0x10;
688
689 break;
690
691 case IR_PROTOCOL_NEC:
692 if (wake_sc > 0xFFFFFF) {
693 do_wake = false;
694 dev_err(dev, "NEC - Invalid wake scancode\n");
695 break;
696 }
697
698 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
699
700 match[1] = bitrev8((wake_sc & 0xFF));
701 match[0] = ~match[1];
702
703 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
704 if (wake_sc > 0xFFFF)
705 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
706 else
707 match[2] = ~match[3];
708
709 break;
710
711 case IR_PROTOCOL_RC6:
712
713 if (wake_rc6mode == 0) {
714 if (wake_sc > 0xFFFF) {
715 do_wake = false;
716 dev_err(dev, "RC6 - Invalid wake scancode\n");
717 break;
718 }
719
720 /* Command */
721 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
722 mask[0] = 0xFF;
723 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
724 mask[1] = 0xFF;
725
726 /* Address */
727 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
728 mask[2] = 0xFF;
729 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
730 mask[3] = 0xFF;
731
732 /* Header */
733 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
734 mask[4] = 0xF0;
735 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
736 mask[5] = 0x0F;
737
738 rc6_csl = 44;
739
740 } else if (wake_rc6mode == 6) {
741 i = 0;
742
743 /* Command */
744 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
745 mask[i++] = 0xFF;
746 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
747 mask[i++] = 0xFF;
748
749 /* Address + Toggle */
750 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
751 mask[i++] = 0xFF;
752 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
753 mask[i++] = 0x3F;
754
755 /* Customer bits 7 - 0 */
756 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
757 mask[i++] = 0xFF;
758 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
759 mask[i++] = 0xFF;
760
761 if (wake_sc & 0x80000000) {
762 /* Customer range bit and bits 15 - 8 */
763 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
764 mask[i++] = 0xFF;
765 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
766 mask[i++] = 0xFF;
767 rc6_csl = 76;
768 } else if (wake_sc <= 0x007FFFFF) {
769 rc6_csl = 60;
770 } else {
771 do_wake = false;
772 dev_err(dev, "RC6 - Invalid wake scancode\n");
773 break;
774 }
775
776 /* Header */
777 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
778 mask[i++] = 0xFF;
779 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
780 mask[i++] = 0x0F;
781
782 } else {
783 do_wake = false;
784 dev_err(dev, "RC6 - Invalid wake mode\n");
785 }
786
787 break;
788
789 default:
790 do_wake = false;
791 break;
792 }
793
794 finish:
795 if (do_wake) {
796 /* Set compare and compare mask */
797 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
798 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
799 0x3F);
800 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
801 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
802 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
803 0x3F);
804 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
805
806 /* RC6 Compare String Len */
807 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
808
809 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
810 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
811
812 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
813 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
814
815 /* Set CEIR_EN */
816 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
817
818 } else {
819 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
820 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
821
822 /* Clear CEIR_EN */
823 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
824 }
825
826 /*
827 * ACPI will set the HW disable bit for SP3 which means that the
828 * output signals are left in an undefined state which may cause
829 * spurious interrupts which we need to ignore until the hardware
830 * is reinitialized.
831 */
832 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
833 disable_irq(data->irq);
834
835 /* Disable LED */
836 led_trigger_event(data->rxtrigger, LED_OFF);
837 led_trigger_event(data->txtrigger, LED_OFF);
838 }
839
840 static int
841 wbcir_suspend(struct pnp_dev *device, pm_message_t state)
842 {
843 wbcir_shutdown(device);
844 return 0;
845 }
846
847 static void
848 wbcir_init_hw(struct wbcir_data *data)
849 {
850 u8 tmp;
851
852 /* Disable interrupts */
853 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
854
855 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
856 tmp = protocol << 4;
857 if (invert)
858 tmp |= 0x08;
859 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
860
861 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
862 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
863
864 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
865 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
866
867 /* Set RC5 cell time to correspond to 36 kHz */
868 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
869
870 /* Set IRTX_INV */
871 if (invert)
872 outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL);
873 else
874 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
875
876 /*
877 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
878 * set SP3_IRRX_SW to binary 01, helpfully not documented
879 */
880 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
881 data->txmask = 0x1;
882
883 /* Enable extended mode */
884 wbcir_select_bank(data, WBCIR_BANK_2);
885 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
886
887 /*
888 * Configure baud generator, IR data will be sampled at
889 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
890 *
891 * The ECIR registers include a flag to change the
892 * 24Mhz clock freq to 48Mhz.
893 *
894 * It's not documented in the specs, but fifo levels
895 * other than 16 seems to be unsupported.
896 */
897
898 /* prescaler 1.0, tx/rx fifo lvl 16 */
899 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
900
901 /* Set baud divisor to generate one byte per bit/cell */
902 switch (protocol) {
903 case IR_PROTOCOL_RC5:
904 outb(0xA7, data->sbase + WBCIR_REG_SP3_BGDL);
905 break;
906 case IR_PROTOCOL_RC6:
907 outb(0x53, data->sbase + WBCIR_REG_SP3_BGDL);
908 break;
909 case IR_PROTOCOL_NEC:
910 outb(0x69, data->sbase + WBCIR_REG_SP3_BGDL);
911 break;
912 }
913 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
914
915 /* Set CEIR mode */
916 wbcir_select_bank(data, WBCIR_BANK_0);
917 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
918 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
919 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
920
921 /* Disable RX demod, run-length encoding/decoding, set freq span */
922 wbcir_select_bank(data, WBCIR_BANK_7);
923 outb(0x10, data->sbase + WBCIR_REG_SP3_RCCFG);
924
925 /* Disable timer */
926 wbcir_select_bank(data, WBCIR_BANK_4);
927 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
928
929 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
930 wbcir_select_bank(data, WBCIR_BANK_5);
931 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
932
933 /* Disable CRC */
934 wbcir_select_bank(data, WBCIR_BANK_6);
935 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
936
937 /* Set RX demodulation freq, not really used */
938 wbcir_select_bank(data, WBCIR_BANK_7);
939 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
940
941 /* Set TX modulation, 36kHz, 7us pulse width */
942 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
943 data->txcarrier = 36000;
944
945 /* Set invert and pin direction */
946 if (invert)
947 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
948 else
949 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
950
951 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
952 wbcir_select_bank(data, WBCIR_BANK_0);
953 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
954
955 /* Clear AUX status bits */
956 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
957
958 /* Clear RX state */
959 data->rxstate = WBCIR_RXSTATE_INACTIVE;
960 data->rxev.duration = 0;
961 ir_raw_event_reset(data->dev);
962 ir_raw_event_handle(data->dev);
963
964 /*
965 * Check TX state, if we did a suspend/resume cycle while TX was
966 * active, we will have a process waiting in txwaitq.
967 */
968 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
969 data->txstate = WBCIR_TXSTATE_ERROR;
970 wake_up(&data->txwaitq);
971 }
972
973 /* Enable interrupts */
974 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
975 }
976
977 static int
978 wbcir_resume(struct pnp_dev *device)
979 {
980 struct wbcir_data *data = pnp_get_drvdata(device);
981
982 wbcir_init_hw(data);
983 enable_irq(data->irq);
984
985 return 0;
986 }
987
988 static int __devinit
989 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
990 {
991 struct device *dev = &device->dev;
992 struct wbcir_data *data;
993 int err;
994
995 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
996 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
997 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
998 dev_err(dev, "Invalid resources\n");
999 return -ENODEV;
1000 }
1001
1002 data = kzalloc(sizeof(*data), GFP_KERNEL);
1003 if (!data) {
1004 err = -ENOMEM;
1005 goto exit;
1006 }
1007
1008 pnp_set_drvdata(device, data);
1009
1010 spin_lock_init(&data->spinlock);
1011 init_waitqueue_head(&data->txwaitq);
1012 data->ebase = pnp_port_start(device, 0);
1013 data->wbase = pnp_port_start(device, 1);
1014 data->sbase = pnp_port_start(device, 2);
1015 data->irq = pnp_irq(device, 0);
1016
1017 if (data->wbase == 0 || data->ebase == 0 ||
1018 data->sbase == 0 || data->irq == 0) {
1019 err = -ENODEV;
1020 dev_err(dev, "Invalid resources\n");
1021 goto exit_free_data;
1022 }
1023
1024 dev_dbg(&device->dev, "Found device "
1025 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
1026 data->wbase, data->ebase, data->sbase, data->irq);
1027
1028 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1029 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1030 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1031 err = -EBUSY;
1032 goto exit_free_data;
1033 }
1034
1035 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1036 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1037 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1038 err = -EBUSY;
1039 goto exit_release_wbase;
1040 }
1041
1042 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1043 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1044 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1045 err = -EBUSY;
1046 goto exit_release_ebase;
1047 }
1048
1049 err = request_irq(data->irq, wbcir_irq_handler,
1050 IRQF_DISABLED, DRVNAME, device);
1051 if (err) {
1052 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1053 err = -EBUSY;
1054 goto exit_release_sbase;
1055 }
1056
1057 led_trigger_register_simple("cir-tx", &data->txtrigger);
1058 if (!data->txtrigger) {
1059 err = -ENOMEM;
1060 goto exit_free_irq;
1061 }
1062
1063 led_trigger_register_simple("cir-rx", &data->rxtrigger);
1064 if (!data->rxtrigger) {
1065 err = -ENOMEM;
1066 goto exit_unregister_txtrigger;
1067 }
1068
1069 data->led.name = "cir::activity";
1070 data->led.default_trigger = "cir-rx";
1071 data->led.brightness_set = wbcir_led_brightness_set;
1072 data->led.brightness_get = wbcir_led_brightness_get;
1073 err = led_classdev_register(&device->dev, &data->led);
1074 if (err)
1075 goto exit_unregister_rxtrigger;
1076
1077 data->dev = rc_allocate_device();
1078 if (!data->dev) {
1079 err = -ENOMEM;
1080 goto exit_unregister_led;
1081 }
1082
1083 data->dev->driver_name = WBCIR_NAME;
1084 data->dev->input_name = WBCIR_NAME;
1085 data->dev->input_phys = "wbcir/cir0";
1086 data->dev->input_id.bustype = BUS_HOST;
1087 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1088 data->dev->input_id.product = WBCIR_ID_FAMILY;
1089 data->dev->input_id.version = WBCIR_ID_CHIP;
1090 data->dev->map_name = RC_MAP_RC6_MCE;
1091 data->dev->s_tx_mask = wbcir_txmask;
1092 data->dev->s_tx_carrier = wbcir_txcarrier;
1093 data->dev->tx_ir = wbcir_tx;
1094 data->dev->priv = data;
1095 data->dev->dev.parent = &device->dev;
1096
1097 err = rc_register_device(data->dev);
1098 if (err)
1099 goto exit_free_rc;
1100
1101 device_init_wakeup(&device->dev, 1);
1102
1103 wbcir_init_hw(data);
1104
1105 return 0;
1106
1107 exit_free_rc:
1108 rc_free_device(data->dev);
1109 exit_unregister_led:
1110 led_classdev_unregister(&data->led);
1111 exit_unregister_rxtrigger:
1112 led_trigger_unregister_simple(data->rxtrigger);
1113 exit_unregister_txtrigger:
1114 led_trigger_unregister_simple(data->txtrigger);
1115 exit_free_irq:
1116 free_irq(data->irq, device);
1117 exit_release_sbase:
1118 release_region(data->sbase, SP_IOMEM_LEN);
1119 exit_release_ebase:
1120 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1121 exit_release_wbase:
1122 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1123 exit_free_data:
1124 kfree(data);
1125 pnp_set_drvdata(device, NULL);
1126 exit:
1127 return err;
1128 }
1129
1130 static void __devexit
1131 wbcir_remove(struct pnp_dev *device)
1132 {
1133 struct wbcir_data *data = pnp_get_drvdata(device);
1134
1135 /* Disable interrupts */
1136 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1137 free_irq(data->irq, device);
1138
1139 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1140 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1141
1142 /* Clear CEIR_EN */
1143 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1144
1145 /* Clear BUFF_EN, END_EN, MATCH_EN */
1146 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1147
1148 rc_unregister_device(data->dev);
1149
1150 led_trigger_unregister_simple(data->rxtrigger);
1151 led_trigger_unregister_simple(data->txtrigger);
1152 led_classdev_unregister(&data->led);
1153
1154 /* This is ok since &data->led isn't actually used */
1155 wbcir_led_brightness_set(&data->led, LED_OFF);
1156
1157 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1158 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1159 release_region(data->sbase, SP_IOMEM_LEN);
1160
1161 kfree(data);
1162
1163 pnp_set_drvdata(device, NULL);
1164 }
1165
1166 static const struct pnp_device_id wbcir_ids[] = {
1167 { "WEC1022", 0 },
1168 { "", 0 }
1169 };
1170 MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1171
1172 static struct pnp_driver wbcir_driver = {
1173 .name = WBCIR_NAME,
1174 .id_table = wbcir_ids,
1175 .probe = wbcir_probe,
1176 .remove = __devexit_p(wbcir_remove),
1177 .suspend = wbcir_suspend,
1178 .resume = wbcir_resume,
1179 .shutdown = wbcir_shutdown
1180 };
1181
1182 static int __init
1183 wbcir_init(void)
1184 {
1185 int ret;
1186
1187 switch (protocol) {
1188 case IR_PROTOCOL_RC5:
1189 case IR_PROTOCOL_NEC:
1190 case IR_PROTOCOL_RC6:
1191 break;
1192 default:
1193 printk(KERN_ERR DRVNAME ": Invalid power-on protocol\n");
1194 }
1195
1196 ret = pnp_register_driver(&wbcir_driver);
1197 if (ret)
1198 printk(KERN_ERR DRVNAME ": Unable to register driver\n");
1199
1200 return ret;
1201 }
1202
1203 static void __exit
1204 wbcir_exit(void)
1205 {
1206 pnp_unregister_driver(&wbcir_driver);
1207 }
1208
1209 module_init(wbcir_init);
1210 module_exit(wbcir_exit);
1211
1212 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1213 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1214 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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