drivers/media/video/cx18/cx18-io.c

   1 /*
   2  *  cx18 driver PCI memory mapped IO access routines
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@radix.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20  *  02111-1307  USA
  21  */
  22
  23 #include "cx18-driver.h"
  24 #include "cx18-io.h"
  25 #include "cx18-irq.h"
  26
  27 void cx18_log_statistics(struct cx18 *cx)
  28 {
  29         int i;
  30
  31         if (!(cx18_debug & CX18_DBGFLG_INFO))
  32                 return;
  33
  34         for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
  35                 CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
  36                                 atomic_read(&cx->mmio_stats.retried_write[i]));
  37         for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++)
  38                 CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
  39                                 atomic_read(&cx->mmio_stats.retried_read[i]));
  40         return;
  41 }
  42
  43 void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
  44 {
  45         int i;
  46         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
  47                 cx18_raw_writel_noretry(cx, val, addr);
  48                 if (val == cx18_raw_readl_noretry(cx, addr))
  49                         break;
  50         }
  51         cx18_log_write_retries(cx, i, addr);
  52 }
  53
  54 u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
  55 {
  56         int i;
  57         u32 val;
  58         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
  59                 val = cx18_raw_readl_noretry(cx, addr);
  60                 if (val != 0xffffffff) /* PCI bus read error */
  61                         break;
  62         }
  63         cx18_log_read_retries(cx, i, addr);
  64         return val;
  65 }
  66
  67 u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
  68 {
  69         int i;
  70         u16 val;
  71         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
  72                 val = cx18_raw_readw_noretry(cx, addr);
  73                 if (val != 0xffff) /* PCI bus read error */
  74                         break;
  75         }
  76         cx18_log_read_retries(cx, i, addr);
  77         return val;
  78 }
  79
  80 void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
  81 {
  82         int i;
  83         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
  84                 cx18_writel_noretry(cx, val, addr);
  85                 if (val == cx18_readl_noretry(cx, addr))
  86                         break;
  87         }
  88         cx18_log_write_retries(cx, i, addr);
  89 }
  90
  91 void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
  92                          u32 eval, u32 mask)
  93 {
  94         int i;
  95         eval &= mask;
  96         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
  97                 cx18_writel_noretry(cx, val, addr);
  98                 if (eval == (cx18_readl_noretry(cx, addr) & mask))
  99                         break;
 100         }
 101         cx18_log_write_retries(cx, i, addr);
 102 }
 103
 104 void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
 105 {
 106         int i;
 107         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
 108                 cx18_writew_noretry(cx, val, addr);
 109                 if (val == cx18_readw_noretry(cx, addr))
 110                         break;
 111         }
 112         cx18_log_write_retries(cx, i, addr);
 113 }
 114
 115 void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
 116 {
 117         int i;
 118         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
 119                 cx18_writeb_noretry(cx, val, addr);
 120                 if (val == cx18_readb_noretry(cx, addr))
 121                         break;
 122         }
 123         cx18_log_write_retries(cx, i, addr);
 124 }
 125
 126 u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
 127 {
 128         int i;
 129         u32 val;
 130         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
 131                 val = cx18_readl_noretry(cx, addr);
 132                 if (val != 0xffffffff) /* PCI bus read error */
 133                         break;
 134         }
 135         cx18_log_read_retries(cx, i, addr);
 136         return val;
 137 }
 138
 139 u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
 140 {
 141         int i;
 142         u16 val;
 143         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
 144                 val = cx18_readw_noretry(cx, addr);
 145                 if (val != 0xffff) /* PCI bus read error */
 146                         break;
 147         }
 148         cx18_log_read_retries(cx, i, addr);
 149         return val;
 150 }
 151
 152 u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
 153 {
 154         int i;
 155         u8 val;
 156         for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) {
 157                 val = cx18_readb_noretry(cx, addr);
 158                 if (val != 0xff) /* PCI bus read error */
 159                         break;
 160         }
 161         cx18_log_read_retries(cx, i, addr);
 162         return val;
 163 }
 164
 165 void cx18_memcpy_fromio(struct cx18 *cx, void *to,
 166                         const void __iomem *from, unsigned int len)
 167 {
 168         const u8 __iomem *src = from;
 169         u8 *dst = to;
 170
 171         /* Align reads on the CX23418's addresses */
 172         if ((len > 0) && ((unsigned long) src & 1)) {
 173                 *dst = cx18_readb(cx, src);
 174                 len--;
 175                 dst++;
 176                 src++;
 177         }
 178         if ((len > 1) && ((unsigned long) src & 2)) {
 179                 *((u16 *)dst) = cx18_raw_readw(cx, src);
 180                 len -= 2;
 181                 dst += 2;
 182                 src += 2;
 183         }
 184         while (len > 3) {
 185                 *((u32 *)dst) = cx18_raw_readl(cx, src);
 186                 len -= 4;
 187                 dst += 4;
 188                 src += 4;
 189         }
 190         if (len > 1) {
 191                 *((u16 *)dst) = cx18_raw_readw(cx, src);
 192                 len -= 2;
 193                 dst += 2;
 194                 src += 2;
 195         }
 196         if (len > 0)
 197                 *dst = cx18_readb(cx, src);
 198 }
 199
 200 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
 201 {
 202         u8 __iomem *dst = addr;
 203         u16 val2 = val | (val << 8);
 204         u32 val4 = val2 | (val2 << 16);
 205
 206         /* Align writes on the CX23418's addresses */
 207         if ((count > 0) && ((unsigned long)dst & 1)) {
 208                 cx18_writeb(cx, (u8) val, dst);
 209                 count--;
 210                 dst++;
 211         }
 212         if ((count > 1) && ((unsigned long)dst & 2)) {
 213                 cx18_writew(cx, val2, dst);
 214                 count -= 2;
 215                 dst += 2;
 216         }
 217         while (count > 3) {
 218                 cx18_writel(cx, val4, dst);
 219                 count -= 4;
 220                 dst += 4;
 221         }
 222         if (count > 1) {
 223                 cx18_writew(cx, val2, dst);
 224                 count -= 2;
 225                 dst += 2;
 226         }
 227         if (count > 0)
 228                 cx18_writeb(cx, (u8) val, dst);
 229 }
 230
 231 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
 232 {
 233         u32 r;
 234         cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
 235         r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
 236         cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
 237 }
 238
 239 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
 240 {
 241         u32 r;
 242         r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
 243         cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI);
 244 }
 245
 246 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
 247 {
 248         u32 r;
 249         cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
 250         r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
 251         cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
 252 }
 253
 254 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
 255 {
 256         u32 r;
 257         r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
 258         cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI);
 259 }
 260
 261 void cx18_setup_page(struct cx18 *cx, u32 addr)
 262 {
 263         u32 val;
 264         val = cx18_read_reg(cx, 0xD000F8);
 265         val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
 266         cx18_write_reg(cx, val, 0xD000F8);
 267 }