2 * Driver for the Conexant CX23885 PCIe bridge
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
37 MODULE_LICENSE("GPL");
39 static unsigned int debug
;
40 module_param(debug
,int,0644);
41 MODULE_PARM_DESC(debug
,"enable debug messages");
43 static unsigned int card
[] = {[0 ... (CX23885_MAXBOARDS
- 1)] = UNSET
};
44 module_param_array(card
, int, NULL
, 0444);
45 MODULE_PARM_DESC(card
,"card type");
47 #define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
52 static unsigned int cx23885_devcount
;
54 static DEFINE_MUTEX(devlist
);
55 LIST_HEAD(cx23885_devlist
);
57 #define NO_SYNC_LINE (-1U)
59 /* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
62 * 1 line = 16 bytes of CDT
64 * cdt size = 16 * linesize
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
79 static struct sram_channel cx23885_sram_channels
[] = {
82 .cmds_start
= 0x10000,
83 .ctrl_start
= 0x10380,
87 .ptr1_reg
= DMA1_PTR1
,
88 .ptr2_reg
= DMA1_PTR2
,
89 .cnt1_reg
= DMA1_CNT1
,
90 .cnt2_reg
= DMA1_CNT2
,
99 .ptr1_reg
= DMA2_PTR1
,
100 .ptr2_reg
= DMA2_PTR2
,
101 .cnt1_reg
= DMA2_CNT1
,
102 .cnt2_reg
= DMA2_CNT2
,
106 .cmds_start
= 0x100A0,
107 .ctrl_start
= 0x10400,
109 .fifo_start
= 0x5000,
111 .ptr1_reg
= DMA3_PTR1
,
112 .ptr2_reg
= DMA3_PTR2
,
113 .cnt1_reg
= DMA3_CNT1
,
114 .cnt2_reg
= DMA3_CNT2
,
123 .ptr1_reg
= DMA4_PTR1
,
124 .ptr2_reg
= DMA4_PTR2
,
125 .cnt1_reg
= DMA4_CNT1
,
126 .cnt2_reg
= DMA4_CNT2
,
135 .ptr1_reg
= DMA5_PTR1
,
136 .ptr2_reg
= DMA5_PTR2
,
137 .cnt1_reg
= DMA5_CNT1
,
138 .cnt2_reg
= DMA5_CNT2
,
142 .cmds_start
= 0x10140,
143 .ctrl_start
= 0x10440,
145 .fifo_start
= 0x6000,
147 .ptr1_reg
= DMA5_PTR1
,
148 .ptr2_reg
= DMA5_PTR2
,
149 .cnt1_reg
= DMA5_CNT1
,
150 .cnt2_reg
= DMA5_CNT2
,
159 .ptr1_reg
= DMA6_PTR1
,
160 .ptr2_reg
= DMA6_PTR2
,
161 .cnt1_reg
= DMA6_CNT1
,
162 .cnt2_reg
= DMA6_CNT2
,
171 .ptr1_reg
= DMA7_PTR1
,
172 .ptr2_reg
= DMA7_PTR2
,
173 .cnt1_reg
= DMA7_CNT1
,
174 .cnt2_reg
= DMA7_CNT2
,
183 .ptr1_reg
= DMA8_PTR1
,
184 .ptr2_reg
= DMA8_PTR2
,
185 .cnt1_reg
= DMA8_CNT1
,
186 .cnt2_reg
= DMA8_CNT2
,
190 static struct sram_channel cx23887_sram_channels
[] = {
193 .cmds_start
= 0x10000,
194 .ctrl_start
= 0x105b0,
198 .ptr1_reg
= DMA1_PTR1
,
199 .ptr2_reg
= DMA1_PTR2
,
200 .cnt1_reg
= DMA1_CNT1
,
201 .cnt2_reg
= DMA1_CNT2
,
210 .ptr1_reg
= DMA2_PTR1
,
211 .ptr2_reg
= DMA2_PTR2
,
212 .cnt1_reg
= DMA2_CNT1
,
213 .cnt2_reg
= DMA2_CNT2
,
217 .cmds_start
= 0x100A0,
218 .ctrl_start
= 0x10630,
220 .fifo_start
= 0x5000,
222 .ptr1_reg
= DMA3_PTR1
,
223 .ptr2_reg
= DMA3_PTR2
,
224 .cnt1_reg
= DMA3_CNT1
,
225 .cnt2_reg
= DMA3_CNT2
,
234 .ptr1_reg
= DMA4_PTR1
,
235 .ptr2_reg
= DMA4_PTR2
,
236 .cnt1_reg
= DMA4_CNT1
,
237 .cnt2_reg
= DMA4_CNT2
,
246 .ptr1_reg
= DMA5_PTR1
,
247 .ptr2_reg
= DMA5_PTR2
,
248 .cnt1_reg
= DMA5_CNT1
,
249 .cnt2_reg
= DMA5_CNT2
,
253 .cmds_start
= 0x10140,
254 .ctrl_start
= 0x10670,
256 .fifo_start
= 0x6000,
258 .ptr1_reg
= DMA5_PTR1
,
259 .ptr2_reg
= DMA5_PTR2
,
260 .cnt1_reg
= DMA5_CNT1
,
261 .cnt2_reg
= DMA5_CNT2
,
270 .ptr1_reg
= DMA6_PTR1
,
271 .ptr2_reg
= DMA6_PTR2
,
272 .cnt1_reg
= DMA6_CNT1
,
273 .cnt2_reg
= DMA6_CNT2
,
282 .ptr1_reg
= DMA7_PTR1
,
283 .ptr2_reg
= DMA7_PTR2
,
284 .cnt1_reg
= DMA7_CNT1
,
285 .cnt2_reg
= DMA7_CNT2
,
294 .ptr1_reg
= DMA8_PTR1
,
295 .ptr2_reg
= DMA8_PTR2
,
296 .cnt1_reg
= DMA8_CNT1
,
297 .cnt2_reg
= DMA8_CNT2
,
301 static int cx23885_risc_decode(u32 risc
)
303 static char *instr
[16] = {
304 [RISC_SYNC
>> 28] = "sync",
305 [RISC_WRITE
>> 28] = "write",
306 [RISC_WRITEC
>> 28] = "writec",
307 [RISC_READ
>> 28] = "read",
308 [RISC_READC
>> 28] = "readc",
309 [RISC_JUMP
>> 28] = "jump",
310 [RISC_SKIP
>> 28] = "skip",
311 [RISC_WRITERM
>> 28] = "writerm",
312 [RISC_WRITECM
>> 28] = "writecm",
313 [RISC_WRITECR
>> 28] = "writecr",
315 static int incr
[16] = {
316 [RISC_WRITE
>> 28] = 3,
317 [RISC_JUMP
>> 28] = 3,
318 [RISC_SKIP
>> 28] = 1,
319 [RISC_SYNC
>> 28] = 1,
320 [RISC_WRITERM
>> 28] = 3,
321 [RISC_WRITECM
>> 28] = 3,
322 [RISC_WRITECR
>> 28] = 4,
324 static char *bits
[] = {
325 "12", "13", "14", "resync",
326 "cnt0", "cnt1", "18", "19",
327 "20", "21", "22", "23",
328 "irq1", "irq2", "eol", "sol",
332 printk("0x%08x [ %s", risc
,
333 instr
[risc
>> 28] ? instr
[risc
>> 28] : "INVALID");
334 for (i
= ARRAY_SIZE(bits
) - 1; i
>= 0; i
--)
335 if (risc
& (1 << (i
+ 12)))
336 printk(" %s", bits
[i
]);
337 printk(" count=%d ]\n", risc
& 0xfff);
338 return incr
[risc
>> 28] ? incr
[risc
>> 28] : 1;
341 void cx23885_wakeup(struct cx23885_tsport
*port
,
342 struct cx23885_dmaqueue
*q
, u32 count
)
344 struct cx23885_dev
*dev
= port
->dev
;
345 struct cx23885_buffer
*buf
;
348 for (bc
= 0;; bc
++) {
349 if (list_empty(&q
->active
))
351 buf
= list_entry(q
->active
.next
,
352 struct cx23885_buffer
, vb
.queue
);
354 /* count comes from the hw and is is 16bit wide --
355 * this trick handles wrap-arounds correctly for
356 * up to 32767 buffers in flight... */
357 if ((s16
) (count
- buf
->count
) < 0)
360 do_gettimeofday(&buf
->vb
.ts
);
361 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf
, buf
->vb
.i
,
363 buf
->vb
.state
= VIDEOBUF_DONE
;
364 list_del(&buf
->vb
.queue
);
365 wake_up(&buf
->vb
.done
);
367 if (list_empty(&q
->active
)) {
368 del_timer(&q
->timeout
);
370 mod_timer(&q
->timeout
, jiffies
+ BUFFER_TIMEOUT
);
373 printk("%s: %d buffers handled (should be 1)\n",
377 int cx23885_sram_channel_setup(struct cx23885_dev
*dev
,
378 struct sram_channel
*ch
,
379 unsigned int bpl
, u32 risc
)
381 unsigned int i
, lines
;
384 if (ch
->cmds_start
== 0)
386 dprintk(1, "%s() Erasing channel [%s]\n", __func__
,
388 cx_write(ch
->ptr1_reg
, 0);
389 cx_write(ch
->ptr2_reg
, 0);
390 cx_write(ch
->cnt2_reg
, 0);
391 cx_write(ch
->cnt1_reg
, 0);
394 dprintk(1, "%s() Configuring channel [%s]\n", __func__
,
398 bpl
= (bpl
+ 7) & ~7; /* alignment */
400 lines
= ch
->fifo_size
/ bpl
;
405 cx_write(8 + 0, RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
410 for (i
= 0; i
< lines
; i
++) {
411 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__
, cdt
+ 16*i
,
412 ch
->fifo_start
+ bpl
*i
);
413 cx_write(cdt
+ 16*i
, ch
->fifo_start
+ bpl
*i
);
414 cx_write(cdt
+ 16*i
+ 4, 0);
415 cx_write(cdt
+ 16*i
+ 8, 0);
416 cx_write(cdt
+ 16*i
+ 12, 0);
421 cx_write(ch
->cmds_start
+ 0, 8);
423 cx_write(ch
->cmds_start
+ 0, risc
);
424 cx_write(ch
->cmds_start
+ 4, 0); /* 64 bits 63-32 */
425 cx_write(ch
->cmds_start
+ 8, cdt
);
426 cx_write(ch
->cmds_start
+ 12, (lines
*16) >> 3);
427 cx_write(ch
->cmds_start
+ 16, ch
->ctrl_start
);
429 cx_write(ch
->cmds_start
+ 20, 0x80000000 | (64 >> 2) );
431 cx_write(ch
->cmds_start
+ 20, 64 >> 2);
432 for (i
= 24; i
< 80; i
+= 4)
433 cx_write(ch
->cmds_start
+ i
, 0);
436 cx_write(ch
->ptr1_reg
, ch
->fifo_start
);
437 cx_write(ch
->ptr2_reg
, cdt
);
438 cx_write(ch
->cnt2_reg
, (lines
*16) >> 3);
439 cx_write(ch
->cnt1_reg
, (bpl
>> 3) -1);
441 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
450 void cx23885_sram_channel_dump(struct cx23885_dev
*dev
,
451 struct sram_channel
*ch
)
453 static char *name
[] = {
470 unsigned int i
, j
, n
;
472 printk("%s: %s - dma channel status dump\n",
473 dev
->name
, ch
->name
);
474 for (i
= 0; i
< ARRAY_SIZE(name
); i
++)
475 printk("%s: cmds: %-15s: 0x%08x\n",
477 cx_read(ch
->cmds_start
+ 4*i
));
479 for (i
= 0; i
< 4; i
++) {
480 risc
= cx_read(ch
->cmds_start
+ 4 * (i
+ 14));
481 printk("%s: risc%d: ", dev
->name
, i
);
482 cx23885_risc_decode(risc
);
484 for (i
= 0; i
< (64 >> 2); i
+= n
) {
485 risc
= cx_read(ch
->ctrl_start
+ 4 * i
);
486 /* No consideration for bits 63-32 */
488 printk("%s: (0x%08x) iq %x: ", dev
->name
,
489 ch
->ctrl_start
+ 4 * i
, i
);
490 n
= cx23885_risc_decode(risc
);
491 for (j
= 1; j
< n
; j
++) {
492 risc
= cx_read(ch
->ctrl_start
+ 4 * (i
+ j
));
493 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
494 dev
->name
, i
+j
, risc
, j
);
498 printk("%s: fifo: 0x%08x -> 0x%x\n",
499 dev
->name
, ch
->fifo_start
, ch
->fifo_start
+ch
->fifo_size
);
500 printk("%s: ctrl: 0x%08x -> 0x%x\n",
501 dev
->name
, ch
->ctrl_start
, ch
->ctrl_start
+ 6*16);
502 printk("%s: ptr1_reg: 0x%08x\n",
503 dev
->name
, cx_read(ch
->ptr1_reg
));
504 printk("%s: ptr2_reg: 0x%08x\n",
505 dev
->name
, cx_read(ch
->ptr2_reg
));
506 printk("%s: cnt1_reg: 0x%08x\n",
507 dev
->name
, cx_read(ch
->cnt1_reg
));
508 printk("%s: cnt2_reg: 0x%08x\n",
509 dev
->name
, cx_read(ch
->cnt2_reg
));
512 static void cx23885_risc_disasm(struct cx23885_tsport
*port
,
513 struct btcx_riscmem
*risc
)
515 struct cx23885_dev
*dev
= port
->dev
;
516 unsigned int i
, j
, n
;
518 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
519 dev
->name
, risc
->cpu
, (unsigned long)risc
->dma
);
520 for (i
= 0; i
< (risc
->size
>> 2); i
+= n
) {
521 printk("%s: %04d: ", dev
->name
, i
);
522 n
= cx23885_risc_decode(le32_to_cpu(risc
->cpu
[i
]));
523 for (j
= 1; j
< n
; j
++)
524 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
525 dev
->name
, i
+ j
, risc
->cpu
[i
+ j
], j
);
526 if (risc
->cpu
[i
] == cpu_to_le32(RISC_JUMP
))
531 static void cx23885_shutdown(struct cx23885_dev
*dev
)
533 /* disable RISC controller */
534 cx_write(DEV_CNTRL2
, 0);
536 /* Disable all IR activity */
537 cx_write(IR_CNTRL_REG
, 0);
539 /* Disable Video A/B activity */
540 cx_write(VID_A_DMA_CTL
, 0);
541 cx_write(VID_B_DMA_CTL
, 0);
542 cx_write(VID_C_DMA_CTL
, 0);
544 /* Disable Audio activity */
545 cx_write(AUD_INT_DMA_CTL
, 0);
546 cx_write(AUD_EXT_DMA_CTL
, 0);
548 /* Disable Serial port */
549 cx_write(UART_CTL
, 0);
551 /* Disable Interrupts */
552 cx_write(PCI_INT_MSK
, 0);
553 cx_write(VID_A_INT_MSK
, 0);
554 cx_write(VID_B_INT_MSK
, 0);
555 cx_write(VID_C_INT_MSK
, 0);
556 cx_write(AUDIO_INT_INT_MSK
, 0);
557 cx_write(AUDIO_EXT_INT_MSK
, 0);
561 static void cx23885_reset(struct cx23885_dev
*dev
)
563 dprintk(1, "%s()\n", __func__
);
565 cx23885_shutdown(dev
);
567 cx_write(PCI_INT_STAT
, 0xffffffff);
568 cx_write(VID_A_INT_STAT
, 0xffffffff);
569 cx_write(VID_B_INT_STAT
, 0xffffffff);
570 cx_write(VID_C_INT_STAT
, 0xffffffff);
571 cx_write(AUDIO_INT_INT_STAT
, 0xffffffff);
572 cx_write(AUDIO_EXT_INT_STAT
, 0xffffffff);
573 cx_write(CLK_DELAY
, cx_read(CLK_DELAY
) & 0x80000000);
574 cx_write(PAD_CTRL
, 0x00500300);
578 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH01
],
580 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH02
], 128, 0);
581 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH03
],
583 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH04
], 128, 0);
584 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH05
], 128, 0);
585 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH06
],
587 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH07
], 128, 0);
588 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH08
], 128, 0);
589 cx23885_sram_channel_setup(dev
, &dev
->sram_channels
[SRAM_CH09
], 128, 0);
591 cx23885_gpio_setup(dev
);
595 static int cx23885_pci_quirks(struct cx23885_dev
*dev
)
597 dprintk(1, "%s()\n", __func__
);
599 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
600 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
601 * occur on the cx23887 bridge.
603 if(dev
->bridge
== CX23885_BRIDGE_885
)
604 cx_clear(RDR_TLCTL0
, 1 << 4);
609 static int get_resources(struct cx23885_dev
*dev
)
611 if (request_mem_region(pci_resource_start(dev
->pci
,0),
612 pci_resource_len(dev
->pci
,0),
616 printk(KERN_ERR
"%s: can't get MMIO memory @ 0x%llx\n",
617 dev
->name
, (unsigned long long)pci_resource_start(dev
->pci
,0));
622 static void cx23885_timeout(unsigned long data
);
623 int cx23885_risc_stopper(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
624 u32 reg
, u32 mask
, u32 value
);
626 static int cx23885_init_tsport(struct cx23885_dev
*dev
, struct cx23885_tsport
*port
, int portno
)
628 dprintk(1, "%s(portno=%d)\n", __func__
, portno
);
630 /* Transport bus init dma queue - Common settings */
631 port
->dma_ctl_val
= 0x11; /* Enable RISC controller and Fifo */
632 port
->ts_int_msk_val
= 0x1111; /* TS port bits for RISC */
633 port
->vld_misc_val
= 0x0;
634 port
->hw_sop_ctrl_val
= (0x47 << 16 | 188 << 4);
636 spin_lock_init(&port
->slock
);
640 INIT_LIST_HEAD(&port
->mpegq
.active
);
641 INIT_LIST_HEAD(&port
->mpegq
.queued
);
642 port
->mpegq
.timeout
.function
= cx23885_timeout
;
643 port
->mpegq
.timeout
.data
= (unsigned long)port
;
644 init_timer(&port
->mpegq
.timeout
);
648 port
->reg_gpcnt
= VID_B_GPCNT
;
649 port
->reg_gpcnt_ctl
= VID_B_GPCNT_CTL
;
650 port
->reg_dma_ctl
= VID_B_DMA_CTL
;
651 port
->reg_lngth
= VID_B_LNGTH
;
652 port
->reg_hw_sop_ctrl
= VID_B_HW_SOP_CTL
;
653 port
->reg_gen_ctrl
= VID_B_GEN_CTL
;
654 port
->reg_bd_pkt_status
= VID_B_BD_PKT_STATUS
;
655 port
->reg_sop_status
= VID_B_SOP_STATUS
;
656 port
->reg_fifo_ovfl_stat
= VID_B_FIFO_OVFL_STAT
;
657 port
->reg_vld_misc
= VID_B_VLD_MISC
;
658 port
->reg_ts_clk_en
= VID_B_TS_CLK_EN
;
659 port
->reg_src_sel
= VID_B_SRC_SEL
;
660 port
->reg_ts_int_msk
= VID_B_INT_MSK
;
661 port
->reg_ts_int_stat
= VID_B_INT_STAT
;
662 port
->sram_chno
= SRAM_CH03
; /* VID_B */
663 port
->pci_irqmask
= 0x02; /* VID_B bit1 */
666 port
->reg_gpcnt
= VID_C_GPCNT
;
667 port
->reg_gpcnt_ctl
= VID_C_GPCNT_CTL
;
668 port
->reg_dma_ctl
= VID_C_DMA_CTL
;
669 port
->reg_lngth
= VID_C_LNGTH
;
670 port
->reg_hw_sop_ctrl
= VID_C_HW_SOP_CTL
;
671 port
->reg_gen_ctrl
= VID_C_GEN_CTL
;
672 port
->reg_bd_pkt_status
= VID_C_BD_PKT_STATUS
;
673 port
->reg_sop_status
= VID_C_SOP_STATUS
;
674 port
->reg_fifo_ovfl_stat
= VID_C_FIFO_OVFL_STAT
;
675 port
->reg_vld_misc
= VID_C_VLD_MISC
;
676 port
->reg_ts_clk_en
= VID_C_TS_CLK_EN
;
677 port
->reg_src_sel
= 0;
678 port
->reg_ts_int_msk
= VID_C_INT_MSK
;
679 port
->reg_ts_int_stat
= VID_C_INT_STAT
;
680 port
->sram_chno
= SRAM_CH06
; /* VID_C */
681 port
->pci_irqmask
= 0x04; /* VID_C bit2 */
687 cx23885_risc_stopper(dev
->pci
, &port
->mpegq
.stopper
,
688 port
->reg_dma_ctl
, port
->dma_ctl_val
, 0x00);
693 static void cx23885_dev_checkrevision(struct cx23885_dev
*dev
)
695 switch (cx_read(RDR_CFG2
) & 0xff) {
698 dev
->hwrevision
= 0xa0;
702 dev
->hwrevision
= 0xa1;
706 dev
->hwrevision
= 0xb0;
710 dev
->hwrevision
= 0xc0;
714 dev
->hwrevision
= 0xc0;
717 dev
->hwrevision
= 0xb1;
720 printk(KERN_ERR
"%s() New hardware revision found 0x%x\n",
721 __func__
, dev
->hwrevision
);
724 printk(KERN_INFO
"%s() Hardware revision = 0x%02x\n",
725 __func__
, dev
->hwrevision
);
727 printk(KERN_ERR
"%s() Hardware revision unknown 0x%x\n",
728 __func__
, dev
->hwrevision
);
731 static int cx23885_dev_setup(struct cx23885_dev
*dev
)
735 mutex_init(&dev
->lock
);
737 atomic_inc(&dev
->refcount
);
739 dev
->nr
= cx23885_devcount
++;
740 sprintf(dev
->name
, "cx23885[%d]", dev
->nr
);
742 mutex_lock(&devlist
);
743 list_add_tail(&dev
->devlist
, &cx23885_devlist
);
744 mutex_unlock(&devlist
);
746 /* Configure the internal memory */
747 if(dev
->pci
->device
== 0x8880) {
748 dev
->bridge
= CX23885_BRIDGE_887
;
749 /* Apply a sensible clock frequency for the PCIe bridge */
750 dev
->clk_freq
= 25000000;
751 dev
->sram_channels
= cx23887_sram_channels
;
753 if(dev
->pci
->device
== 0x8852) {
754 dev
->bridge
= CX23885_BRIDGE_885
;
755 /* Apply a sensible clock frequency for the PCIe bridge */
756 dev
->clk_freq
= 28000000;
757 dev
->sram_channels
= cx23885_sram_channels
;
761 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
762 __func__
, dev
->bridge
);
766 if (card
[dev
->nr
] < cx23885_bcount
)
767 dev
->board
= card
[dev
->nr
];
768 for (i
= 0; UNSET
== dev
->board
&& i
< cx23885_idcount
; i
++)
769 if (dev
->pci
->subsystem_vendor
== cx23885_subids
[i
].subvendor
&&
770 dev
->pci
->subsystem_device
== cx23885_subids
[i
].subdevice
)
771 dev
->board
= cx23885_subids
[i
].card
;
772 if (UNSET
== dev
->board
) {
773 dev
->board
= CX23885_BOARD_UNKNOWN
;
774 cx23885_card_list(dev
);
777 /* If the user specific a clk freq override, apply it */
778 if (cx23885_boards
[dev
->board
].clk_freq
> 0)
779 dev
->clk_freq
= cx23885_boards
[dev
->board
].clk_freq
;
781 dev
->pci_bus
= dev
->pci
->bus
->number
;
782 dev
->pci_slot
= PCI_SLOT(dev
->pci
->devfn
);
783 dev
->pci_irqmask
= 0x001f00;
785 /* External Master 1 Bus */
786 dev
->i2c_bus
[0].nr
= 0;
787 dev
->i2c_bus
[0].dev
= dev
;
788 dev
->i2c_bus
[0].reg_stat
= I2C1_STAT
;
789 dev
->i2c_bus
[0].reg_ctrl
= I2C1_CTRL
;
790 dev
->i2c_bus
[0].reg_addr
= I2C1_ADDR
;
791 dev
->i2c_bus
[0].reg_rdata
= I2C1_RDATA
;
792 dev
->i2c_bus
[0].reg_wdata
= I2C1_WDATA
;
793 dev
->i2c_bus
[0].i2c_period
= (0x9d << 24); /* 100kHz */
795 /* External Master 2 Bus */
796 dev
->i2c_bus
[1].nr
= 1;
797 dev
->i2c_bus
[1].dev
= dev
;
798 dev
->i2c_bus
[1].reg_stat
= I2C2_STAT
;
799 dev
->i2c_bus
[1].reg_ctrl
= I2C2_CTRL
;
800 dev
->i2c_bus
[1].reg_addr
= I2C2_ADDR
;
801 dev
->i2c_bus
[1].reg_rdata
= I2C2_RDATA
;
802 dev
->i2c_bus
[1].reg_wdata
= I2C2_WDATA
;
803 dev
->i2c_bus
[1].i2c_period
= (0x9d << 24); /* 100kHz */
805 /* Internal Master 3 Bus */
806 dev
->i2c_bus
[2].nr
= 2;
807 dev
->i2c_bus
[2].dev
= dev
;
808 dev
->i2c_bus
[2].reg_stat
= I2C3_STAT
;
809 dev
->i2c_bus
[2].reg_ctrl
= I2C3_CTRL
;
810 dev
->i2c_bus
[2].reg_addr
= I2C3_ADDR
;
811 dev
->i2c_bus
[2].reg_rdata
= I2C3_RDATA
;
812 dev
->i2c_bus
[2].reg_wdata
= I2C3_WDATA
;
813 dev
->i2c_bus
[2].i2c_period
= (0x07 << 24); /* 1.95MHz */
815 if ((cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_DVB
) ||
816 (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
))
817 cx23885_init_tsport(dev
, &dev
->ts1
, 1);
819 if ((cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_DVB
) ||
820 (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_ENCODER
))
821 cx23885_init_tsport(dev
, &dev
->ts2
, 2);
823 if (get_resources(dev
) < 0) {
824 printk(KERN_ERR
"CORE %s No more PCIe resources for "
825 "subsystem: %04x:%04x\n",
826 dev
->name
, dev
->pci
->subsystem_vendor
,
827 dev
->pci
->subsystem_device
);
834 dev
->lmmio
= ioremap(pci_resource_start(dev
->pci
,0),
835 pci_resource_len(dev
->pci
,0));
837 dev
->bmmio
= (u8 __iomem
*)dev
->lmmio
;
839 printk(KERN_INFO
"CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
840 dev
->name
, dev
->pci
->subsystem_vendor
,
841 dev
->pci
->subsystem_device
, cx23885_boards
[dev
->board
].name
,
842 dev
->board
, card
[dev
->nr
] == dev
->board
?
843 "insmod option" : "autodetected");
845 cx23885_pci_quirks(dev
);
847 /* Assume some sensible defaults */
848 dev
->tuner_type
= cx23885_boards
[dev
->board
].tuner_type
;
849 dev
->tuner_addr
= cx23885_boards
[dev
->board
].tuner_addr
;
850 dev
->radio_type
= cx23885_boards
[dev
->board
].radio_type
;
851 dev
->radio_addr
= cx23885_boards
[dev
->board
].radio_addr
;
853 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
854 __func__
, dev
->tuner_type
, dev
->tuner_addr
);
855 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
856 __func__
, dev
->radio_type
, dev
->radio_addr
);
861 cx23885_i2c_register(&dev
->i2c_bus
[0]);
862 cx23885_i2c_register(&dev
->i2c_bus
[1]);
863 cx23885_i2c_register(&dev
->i2c_bus
[2]);
864 cx23885_card_setup(dev
);
865 cx23885_call_i2c_clients (&dev
->i2c_bus
[0], TUNER_SET_STANDBY
, NULL
);
866 cx23885_ir_init(dev
);
868 if (cx23885_boards
[dev
->board
].porta
== CX23885_ANALOG_VIDEO
) {
869 if (cx23885_video_register(dev
) < 0) {
870 printk(KERN_ERR
"%s() Failed to register analog "
871 "video adapters on VID_A\n", __func__
);
875 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_DVB
) {
876 if (cx23885_dvb_register(&dev
->ts1
) < 0) {
877 printk(KERN_ERR
"%s() Failed to register dvb adapters on VID_B\n",
881 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
) {
882 if (cx23885_417_register(dev
) < 0) {
884 "%s() Failed to register 417 on VID_B\n",
889 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_DVB
) {
890 if (cx23885_dvb_register(&dev
->ts2
) < 0) {
892 "%s() Failed to register dvb on VID_C\n",
896 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_ENCODER
) {
897 if (cx23885_417_register(dev
) < 0) {
899 "%s() Failed to register 417 on VID_C\n",
904 cx23885_dev_checkrevision(dev
);
909 static void cx23885_dev_unregister(struct cx23885_dev
*dev
)
911 release_mem_region(pci_resource_start(dev
->pci
,0),
912 pci_resource_len(dev
->pci
,0));
914 if (!atomic_dec_and_test(&dev
->refcount
))
917 if (cx23885_boards
[dev
->board
].porta
== CX23885_ANALOG_VIDEO
)
918 cx23885_video_unregister(dev
);
920 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_DVB
)
921 cx23885_dvb_unregister(&dev
->ts1
);
923 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
)
924 cx23885_417_unregister(dev
);
926 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_DVB
)
927 cx23885_dvb_unregister(&dev
->ts2
);
929 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_ENCODER
)
930 cx23885_417_unregister(dev
);
932 cx23885_i2c_unregister(&dev
->i2c_bus
[2]);
933 cx23885_i2c_unregister(&dev
->i2c_bus
[1]);
934 cx23885_i2c_unregister(&dev
->i2c_bus
[0]);
939 static __le32
* cx23885_risc_field(__le32
*rp
, struct scatterlist
*sglist
,
940 unsigned int offset
, u32 sync_line
,
941 unsigned int bpl
, unsigned int padding
,
944 struct scatterlist
*sg
;
945 unsigned int line
, todo
;
947 /* sync instruction */
948 if (sync_line
!= NO_SYNC_LINE
)
949 *(rp
++) = cpu_to_le32(RISC_RESYNC
| sync_line
);
953 for (line
= 0; line
< lines
; line
++) {
954 while (offset
&& offset
>= sg_dma_len(sg
)) {
955 offset
-= sg_dma_len(sg
);
958 if (bpl
<= sg_dma_len(sg
)-offset
) {
959 /* fits into current chunk */
960 *(rp
++)=cpu_to_le32(RISC_WRITE
|RISC_SOL
|RISC_EOL
|bpl
);
961 *(rp
++)=cpu_to_le32(sg_dma_address(sg
)+offset
);
962 *(rp
++)=cpu_to_le32(0); /* bits 63-32 */
965 /* scanline needs to be split */
967 *(rp
++)=cpu_to_le32(RISC_WRITE
|RISC_SOL
|
968 (sg_dma_len(sg
)-offset
));
969 *(rp
++)=cpu_to_le32(sg_dma_address(sg
)+offset
);
970 *(rp
++)=cpu_to_le32(0); /* bits 63-32 */
971 todo
-= (sg_dma_len(sg
)-offset
);
974 while (todo
> sg_dma_len(sg
)) {
975 *(rp
++)=cpu_to_le32(RISC_WRITE
|
977 *(rp
++)=cpu_to_le32(sg_dma_address(sg
));
978 *(rp
++)=cpu_to_le32(0); /* bits 63-32 */
979 todo
-= sg_dma_len(sg
);
982 *(rp
++)=cpu_to_le32(RISC_WRITE
|RISC_EOL
|todo
);
983 *(rp
++)=cpu_to_le32(sg_dma_address(sg
));
984 *(rp
++)=cpu_to_le32(0); /* bits 63-32 */
993 int cx23885_risc_buffer(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
994 struct scatterlist
*sglist
, unsigned int top_offset
,
995 unsigned int bottom_offset
, unsigned int bpl
,
996 unsigned int padding
, unsigned int lines
)
998 u32 instructions
, fields
;
1003 if (UNSET
!= top_offset
)
1005 if (UNSET
!= bottom_offset
)
1008 /* estimate risc mem: worst case is one write per page border +
1009 one write per scan line + syncs + jump (all 2 dwords). Padding
1010 can cause next bpl to start close to a page border. First DMA
1011 region may be smaller than PAGE_SIZE */
1012 /* write and jump need and extra dword */
1013 instructions
= fields
* (1 + ((bpl
+ padding
) * lines
) / PAGE_SIZE
+ lines
);
1015 if ((rc
= btcx_riscmem_alloc(pci
,risc
,instructions
*12)) < 0)
1018 /* write risc instructions */
1020 if (UNSET
!= top_offset
)
1021 rp
= cx23885_risc_field(rp
, sglist
, top_offset
, 0,
1022 bpl
, padding
, lines
);
1023 if (UNSET
!= bottom_offset
)
1024 rp
= cx23885_risc_field(rp
, sglist
, bottom_offset
, 0x200,
1025 bpl
, padding
, lines
);
1027 /* save pointer to jmp instruction address */
1029 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof (*risc
->cpu
) > risc
->size
);
1033 static int cx23885_risc_databuffer(struct pci_dev
*pci
,
1034 struct btcx_riscmem
*risc
,
1035 struct scatterlist
*sglist
,
1043 /* estimate risc mem: worst case is one write per page border +
1044 one write per scan line + syncs + jump (all 2 dwords). Here
1045 there is no padding and no sync. First DMA region may be smaller
1047 /* Jump and write need an extra dword */
1048 instructions
= 1 + (bpl
* lines
) / PAGE_SIZE
+ lines
;
1051 if ((rc
= btcx_riscmem_alloc(pci
,risc
,instructions
*12)) < 0)
1054 /* write risc instructions */
1056 rp
= cx23885_risc_field(rp
, sglist
, 0, NO_SYNC_LINE
, bpl
, 0, lines
);
1058 /* save pointer to jmp instruction address */
1060 BUG_ON((risc
->jmp
- risc
->cpu
+ 2) * sizeof (*risc
->cpu
) > risc
->size
);
1064 int cx23885_risc_stopper(struct pci_dev
*pci
, struct btcx_riscmem
*risc
,
1065 u32 reg
, u32 mask
, u32 value
)
1070 if ((rc
= btcx_riscmem_alloc(pci
, risc
, 4*16)) < 0)
1073 /* write risc instructions */
1075 *(rp
++) = cpu_to_le32(RISC_WRITECR
| RISC_IRQ2
);
1076 *(rp
++) = cpu_to_le32(reg
);
1077 *(rp
++) = cpu_to_le32(value
);
1078 *(rp
++) = cpu_to_le32(mask
);
1079 *(rp
++) = cpu_to_le32(RISC_JUMP
);
1080 *(rp
++) = cpu_to_le32(risc
->dma
);
1081 *(rp
++) = cpu_to_le32(0); /* bits 63-32 */
1085 void cx23885_free_buffer(struct videobuf_queue
*q
, struct cx23885_buffer
*buf
)
1087 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
1089 BUG_ON(in_interrupt());
1090 videobuf_waiton(&buf
->vb
, 0, 0);
1091 videobuf_dma_unmap(q
, dma
);
1092 videobuf_dma_free(dma
);
1093 btcx_riscmem_free(to_pci_dev(q
->dev
), &buf
->risc
);
1094 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
1097 static void cx23885_tsport_reg_dump(struct cx23885_tsport
*port
)
1099 struct cx23885_dev
*dev
= port
->dev
;
1101 dprintk(1, "%s() Register Dump\n", __func__
);
1102 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__
,
1103 cx_read(DEV_CNTRL2
));
1104 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__
,
1105 cx_read(PCI_INT_MSK
));
1106 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__
,
1107 cx_read(AUDIO_INT_INT_MSK
));
1108 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__
,
1109 cx_read(AUD_INT_DMA_CTL
));
1110 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__
,
1111 cx_read(AUDIO_EXT_INT_MSK
));
1112 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__
,
1113 cx_read(AUD_EXT_DMA_CTL
));
1114 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__
,
1116 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__
,
1117 cx_read(ALT_PIN_OUT_SEL
));
1118 dprintk(1, "%s() GPIO2 0x%08X\n", __func__
,
1120 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__
,
1121 port
->reg_gpcnt
, cx_read(port
->reg_gpcnt
));
1122 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__
,
1123 port
->reg_gpcnt_ctl
, cx_read(port
->reg_gpcnt_ctl
));
1124 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__
,
1125 port
->reg_dma_ctl
, cx_read(port
->reg_dma_ctl
));
1126 if (port
->reg_src_sel
)
1127 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__
,
1128 port
->reg_src_sel
, cx_read(port
->reg_src_sel
));
1129 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__
,
1130 port
->reg_lngth
, cx_read(port
->reg_lngth
));
1131 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__
,
1132 port
->reg_hw_sop_ctrl
, cx_read(port
->reg_hw_sop_ctrl
));
1133 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__
,
1134 port
->reg_gen_ctrl
, cx_read(port
->reg_gen_ctrl
));
1135 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__
,
1136 port
->reg_bd_pkt_status
, cx_read(port
->reg_bd_pkt_status
));
1137 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__
,
1138 port
->reg_sop_status
, cx_read(port
->reg_sop_status
));
1139 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__
,
1140 port
->reg_fifo_ovfl_stat
, cx_read(port
->reg_fifo_ovfl_stat
));
1141 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__
,
1142 port
->reg_vld_misc
, cx_read(port
->reg_vld_misc
));
1143 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__
,
1144 port
->reg_ts_clk_en
, cx_read(port
->reg_ts_clk_en
));
1145 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__
,
1146 port
->reg_ts_int_msk
, cx_read(port
->reg_ts_int_msk
));
1149 static int cx23885_start_dma(struct cx23885_tsport
*port
,
1150 struct cx23885_dmaqueue
*q
,
1151 struct cx23885_buffer
*buf
)
1153 struct cx23885_dev
*dev
= port
->dev
;
1156 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__
,
1157 buf
->vb
.width
, buf
->vb
.height
, buf
->vb
.field
);
1159 /* Stop the fifo and risc engine for this port */
1160 cx_clear(port
->reg_dma_ctl
, port
->dma_ctl_val
);
1162 /* setup fifo + format */
1163 cx23885_sram_channel_setup(dev
,
1164 &dev
->sram_channels
[ port
->sram_chno
],
1165 port
->ts_packet_size
, buf
->risc
.dma
);
1167 cx23885_sram_channel_dump(dev
, &dev
->sram_channels
[ port
->sram_chno
] );
1168 cx23885_risc_disasm(port
, &buf
->risc
);
1171 /* write TS length to chip */
1172 cx_write(port
->reg_lngth
, buf
->vb
.width
);
1174 if ( (!(cx23885_boards
[dev
->board
].portb
& CX23885_MPEG_DVB
)) &&
1175 (!(cx23885_boards
[dev
->board
].portc
& CX23885_MPEG_DVB
)) ) {
1176 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1178 cx23885_boards
[dev
->board
].portb
,
1179 cx23885_boards
[dev
->board
].portc
);
1183 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
)
1184 cx23885_av_clk(dev
, 0);
1188 /* If the port supports SRC SELECT, configure it */
1189 if(port
->reg_src_sel
)
1190 cx_write(port
->reg_src_sel
, port
->src_sel_val
);
1192 cx_write(port
->reg_hw_sop_ctrl
, port
->hw_sop_ctrl_val
);
1193 cx_write(port
->reg_ts_clk_en
, port
->ts_clk_en_val
);
1194 cx_write(port
->reg_vld_misc
, port
->vld_misc_val
);
1195 cx_write(port
->reg_gen_ctrl
, port
->gen_ctrl_val
);
1198 // NOTE: this is 2 (reserved) for portb, does it matter?
1199 /* reset counter to zero */
1200 cx_write(port
->reg_gpcnt_ctl
, 3);
1203 /* Set VIDB pins to input */
1204 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_DVB
) {
1205 reg
= cx_read(PAD_CTRL
);
1206 reg
&= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1207 cx_write(PAD_CTRL
, reg
);
1210 /* Set VIDC pins to input */
1211 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_DVB
) {
1212 reg
= cx_read(PAD_CTRL
);
1213 reg
&= ~0x4; /* Clear TS2_SOP_OE */
1214 cx_write(PAD_CTRL
, reg
);
1217 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
) {
1219 reg
= cx_read(PAD_CTRL
);
1220 reg
= reg
& ~0x1; /* Clear TS1_OE */
1222 /* FIXME, bit 2 writing here is questionable */
1223 /* set TS1_SOP_OE and TS1_OE_HI */
1225 cx_write(PAD_CTRL
, reg
);
1227 /* FIXME and these two registers should be documented. */
1228 cx_write(CLK_DELAY
, cx_read(CLK_DELAY
) | 0x80000011);
1229 cx_write(ALT_PIN_OUT_SEL
, 0x10100045);
1232 switch(dev
->bridge
) {
1233 case CX23885_BRIDGE_885
:
1234 case CX23885_BRIDGE_887
:
1236 dprintk(1, "%s() enabling TS int's and DMA\n", __func__
);
1237 cx_set(port
->reg_ts_int_msk
, port
->ts_int_msk_val
);
1238 cx_set(port
->reg_dma_ctl
, port
->dma_ctl_val
);
1239 cx_set(PCI_INT_MSK
, dev
->pci_irqmask
| port
->pci_irqmask
);
1245 cx_set(DEV_CNTRL2
, (1<<5)); /* Enable RISC controller */
1247 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
)
1248 cx23885_av_clk(dev
, 1);
1251 cx23885_tsport_reg_dump(port
);
1256 static int cx23885_stop_dma(struct cx23885_tsport
*port
)
1258 struct cx23885_dev
*dev
= port
->dev
;
1261 dprintk(1, "%s()\n", __func__
);
1263 /* Stop interrupts and DMA */
1264 cx_clear(port
->reg_ts_int_msk
, port
->ts_int_msk_val
);
1265 cx_clear(port
->reg_dma_ctl
, port
->dma_ctl_val
);
1267 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
) {
1269 reg
= cx_read(PAD_CTRL
);
1274 /* clear TS1_SOP_OE and TS1_OE_HI */
1276 cx_write(PAD_CTRL
, reg
);
1277 cx_write(port
->reg_src_sel
, 0);
1278 cx_write(port
->reg_gen_ctrl
, 8);
1282 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
)
1283 cx23885_av_clk(dev
, 0);
1288 int cx23885_restart_queue(struct cx23885_tsport
*port
,
1289 struct cx23885_dmaqueue
*q
)
1291 struct cx23885_dev
*dev
= port
->dev
;
1292 struct cx23885_buffer
*buf
;
1294 dprintk(5, "%s()\n", __func__
);
1295 if (list_empty(&q
->active
))
1297 struct cx23885_buffer
*prev
;
1300 dprintk(5, "%s() queue is empty\n", __func__
);
1303 if (list_empty(&q
->queued
))
1305 buf
= list_entry(q
->queued
.next
, struct cx23885_buffer
,
1308 list_del(&buf
->vb
.queue
);
1309 list_add_tail(&buf
->vb
.queue
, &q
->active
);
1310 cx23885_start_dma(port
, q
, buf
);
1311 buf
->vb
.state
= VIDEOBUF_ACTIVE
;
1312 buf
->count
= q
->count
++;
1313 mod_timer(&q
->timeout
, jiffies
+BUFFER_TIMEOUT
);
1314 dprintk(5, "[%p/%d] restart_queue - first active\n",
1317 } else if (prev
->vb
.width
== buf
->vb
.width
&&
1318 prev
->vb
.height
== buf
->vb
.height
&&
1319 prev
->fmt
== buf
->fmt
) {
1320 list_del(&buf
->vb
.queue
);
1321 list_add_tail(&buf
->vb
.queue
, &q
->active
);
1322 buf
->vb
.state
= VIDEOBUF_ACTIVE
;
1323 buf
->count
= q
->count
++;
1324 prev
->risc
.jmp
[1] = cpu_to_le32(buf
->risc
.dma
);
1325 prev
->risc
.jmp
[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1326 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1336 buf
= list_entry(q
->active
.next
, struct cx23885_buffer
, vb
.queue
);
1337 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1339 cx23885_start_dma(port
, q
, buf
);
1340 list_for_each_entry(buf
, &q
->active
, vb
.queue
)
1341 buf
->count
= q
->count
++;
1342 mod_timer(&q
->timeout
, jiffies
+ BUFFER_TIMEOUT
);
1346 /* ------------------------------------------------------------------ */
1348 int cx23885_buf_prepare(struct videobuf_queue
*q
, struct cx23885_tsport
*port
,
1349 struct cx23885_buffer
*buf
, enum v4l2_field field
)
1351 struct cx23885_dev
*dev
= port
->dev
;
1352 int size
= port
->ts_packet_size
* port
->ts_packet_count
;
1355 dprintk(1, "%s: %p\n", __func__
, buf
);
1356 if (0 != buf
->vb
.baddr
&& buf
->vb
.bsize
< size
)
1359 if (VIDEOBUF_NEEDS_INIT
== buf
->vb
.state
) {
1360 buf
->vb
.width
= port
->ts_packet_size
;
1361 buf
->vb
.height
= port
->ts_packet_count
;
1362 buf
->vb
.size
= size
;
1363 buf
->vb
.field
= field
/*V4L2_FIELD_TOP*/;
1365 if (0 != (rc
= videobuf_iolock(q
, &buf
->vb
, NULL
)))
1367 cx23885_risc_databuffer(dev
->pci
, &buf
->risc
,
1368 videobuf_to_dma(&buf
->vb
)->sglist
,
1369 buf
->vb
.width
, buf
->vb
.height
);
1371 buf
->vb
.state
= VIDEOBUF_PREPARED
;
1375 cx23885_free_buffer(q
, buf
);
1379 void cx23885_buf_queue(struct cx23885_tsport
*port
, struct cx23885_buffer
*buf
)
1381 struct cx23885_buffer
*prev
;
1382 struct cx23885_dev
*dev
= port
->dev
;
1383 struct cx23885_dmaqueue
*cx88q
= &port
->mpegq
;
1385 /* add jump to stopper */
1386 buf
->risc
.jmp
[0] = cpu_to_le32(RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
1387 buf
->risc
.jmp
[1] = cpu_to_le32(cx88q
->stopper
.dma
);
1388 buf
->risc
.jmp
[2] = cpu_to_le32(0); /* bits 63-32 */
1390 if (list_empty(&cx88q
->active
)) {
1391 dprintk( 1, "queue is empty - first active\n" );
1392 list_add_tail(&buf
->vb
.queue
, &cx88q
->active
);
1393 cx23885_start_dma(port
, cx88q
, buf
);
1394 buf
->vb
.state
= VIDEOBUF_ACTIVE
;
1395 buf
->count
= cx88q
->count
++;
1396 mod_timer(&cx88q
->timeout
, jiffies
+ BUFFER_TIMEOUT
);
1397 dprintk(1, "[%p/%d] %s - first active\n",
1398 buf
, buf
->vb
.i
, __func__
);
1400 dprintk( 1, "queue is not empty - append to active\n" );
1401 prev
= list_entry(cx88q
->active
.prev
, struct cx23885_buffer
,
1403 list_add_tail(&buf
->vb
.queue
, &cx88q
->active
);
1404 buf
->vb
.state
= VIDEOBUF_ACTIVE
;
1405 buf
->count
= cx88q
->count
++;
1406 prev
->risc
.jmp
[1] = cpu_to_le32(buf
->risc
.dma
);
1407 prev
->risc
.jmp
[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1408 dprintk( 1, "[%p/%d] %s - append to active\n",
1409 buf
, buf
->vb
.i
, __func__
);
1413 /* ----------------------------------------------------------- */
1415 static void do_cancel_buffers(struct cx23885_tsport
*port
, char *reason
,
1418 struct cx23885_dev
*dev
= port
->dev
;
1419 struct cx23885_dmaqueue
*q
= &port
->mpegq
;
1420 struct cx23885_buffer
*buf
;
1421 unsigned long flags
;
1423 spin_lock_irqsave(&port
->slock
, flags
);
1424 while (!list_empty(&q
->active
)) {
1425 buf
= list_entry(q
->active
.next
, struct cx23885_buffer
,
1427 list_del(&buf
->vb
.queue
);
1428 buf
->vb
.state
= VIDEOBUF_ERROR
;
1429 wake_up(&buf
->vb
.done
);
1430 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1431 buf
, buf
->vb
.i
, reason
, (unsigned long)buf
->risc
.dma
);
1434 dprintk(1, "restarting queue\n" );
1435 cx23885_restart_queue(port
, q
);
1437 spin_unlock_irqrestore(&port
->slock
, flags
);
1440 void cx23885_cancel_buffers(struct cx23885_tsport
*port
)
1442 struct cx23885_dev
*dev
= port
->dev
;
1443 struct cx23885_dmaqueue
*q
= &port
->mpegq
;
1445 dprintk(1, "%s()\n", __func__
);
1446 del_timer_sync(&q
->timeout
);
1447 cx23885_stop_dma(port
);
1448 do_cancel_buffers(port
, "cancel", 0);
1451 static void cx23885_timeout(unsigned long data
)
1453 struct cx23885_tsport
*port
= (struct cx23885_tsport
*)data
;
1454 struct cx23885_dev
*dev
= port
->dev
;
1456 dprintk(1, "%s()\n",__func__
);
1459 cx23885_sram_channel_dump(dev
, &dev
->sram_channels
[ port
->sram_chno
]);
1461 cx23885_stop_dma(port
);
1462 do_cancel_buffers(port
, "timeout", 1);
1465 int cx23885_irq_417(struct cx23885_dev
*dev
, u32 status
)
1467 /* FIXME: port1 assumption here. */
1468 struct cx23885_tsport
*port
= &dev
->ts1
;
1475 count
= cx_read(port
->reg_gpcnt
);
1476 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1477 status
, cx_read(port
->reg_ts_int_msk
), count
);
1479 if ((status
& VID_B_MSK_BAD_PKT
) ||
1480 (status
& VID_B_MSK_OPC_ERR
) ||
1481 (status
& VID_B_MSK_VBI_OPC_ERR
) ||
1482 (status
& VID_B_MSK_SYNC
) ||
1483 (status
& VID_B_MSK_VBI_SYNC
) ||
1484 (status
& VID_B_MSK_OF
) ||
1485 (status
& VID_B_MSK_VBI_OF
)) {
1486 printk(KERN_ERR
"%s: V4L mpeg risc op code error, status "
1487 "= 0x%x\n", dev
->name
, status
);
1488 if (status
& VID_B_MSK_BAD_PKT
)
1489 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1490 if (status
& VID_B_MSK_OPC_ERR
)
1491 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1492 if (status
& VID_B_MSK_VBI_OPC_ERR
)
1493 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1494 if (status
& VID_B_MSK_SYNC
)
1495 dprintk(1, " VID_B_MSK_SYNC\n");
1496 if (status
& VID_B_MSK_VBI_SYNC
)
1497 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1498 if (status
& VID_B_MSK_OF
)
1499 dprintk(1, " VID_B_MSK_OF\n");
1500 if (status
& VID_B_MSK_VBI_OF
)
1501 dprintk(1, " VID_B_MSK_VBI_OF\n");
1503 cx_clear(port
->reg_dma_ctl
, port
->dma_ctl_val
);
1504 cx23885_sram_channel_dump(dev
,
1505 &dev
->sram_channels
[port
->sram_chno
]);
1506 cx23885_417_check_encoder(dev
);
1507 } else if (status
& VID_B_MSK_RISCI1
) {
1508 dprintk(7, " VID_B_MSK_RISCI1\n");
1509 spin_lock(&port
->slock
);
1510 cx23885_wakeup(port
, &port
->mpegq
, count
);
1511 spin_unlock(&port
->slock
);
1512 } else if (status
& VID_B_MSK_RISCI2
) {
1513 dprintk(7, " VID_B_MSK_RISCI2\n");
1514 spin_lock(&port
->slock
);
1515 cx23885_restart_queue(port
, &port
->mpegq
);
1516 spin_unlock(&port
->slock
);
1519 cx_write(port
->reg_ts_int_stat
, status
);
1526 static int cx23885_irq_ts(struct cx23885_tsport
*port
, u32 status
)
1528 struct cx23885_dev
*dev
= port
->dev
;
1532 if ((status
& VID_BC_MSK_OPC_ERR
) ||
1533 (status
& VID_BC_MSK_BAD_PKT
) ||
1534 (status
& VID_BC_MSK_SYNC
) ||
1535 (status
& VID_BC_MSK_OF
))
1537 if (status
& VID_BC_MSK_OPC_ERR
)
1538 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR
);
1539 if (status
& VID_BC_MSK_BAD_PKT
)
1540 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT
);
1541 if (status
& VID_BC_MSK_SYNC
)
1542 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC
);
1543 if (status
& VID_BC_MSK_OF
)
1544 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF
);
1546 printk(KERN_ERR
"%s: mpeg risc op code error\n", dev
->name
);
1548 cx_clear(port
->reg_dma_ctl
, port
->dma_ctl_val
);
1549 cx23885_sram_channel_dump(dev
,
1550 &dev
->sram_channels
[port
->sram_chno
]);
1552 } else if (status
& VID_BC_MSK_RISCI1
) {
1554 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1
);
1556 spin_lock(&port
->slock
);
1557 count
= cx_read(port
->reg_gpcnt
);
1558 cx23885_wakeup(port
, &port
->mpegq
, count
);
1559 spin_unlock(&port
->slock
);
1561 } else if (status
& VID_BC_MSK_RISCI2
) {
1563 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2
);
1565 spin_lock(&port
->slock
);
1566 cx23885_restart_queue(port
, &port
->mpegq
);
1567 spin_unlock(&port
->slock
);
1571 cx_write(port
->reg_ts_int_stat
, status
);
1578 static irqreturn_t
cx23885_irq(int irq
, void *dev_id
)
1580 struct cx23885_dev
*dev
= dev_id
;
1581 struct cx23885_tsport
*ts1
= &dev
->ts1
;
1582 struct cx23885_tsport
*ts2
= &dev
->ts2
;
1583 u32 pci_status
, pci_mask
;
1584 u32 vida_status
, vida_mask
;
1585 u32 ts1_status
, ts1_mask
;
1586 u32 ts2_status
, ts2_mask
;
1587 int vida_count
= 0, ts1_count
= 0, ts2_count
= 0, handled
= 0;
1589 pci_status
= cx_read(PCI_INT_STAT
);
1590 pci_mask
= cx_read(PCI_INT_MSK
);
1591 vida_status
= cx_read(VID_A_INT_STAT
);
1592 vida_mask
= cx_read(VID_A_INT_MSK
);
1593 ts1_status
= cx_read(VID_B_INT_STAT
);
1594 ts1_mask
= cx_read(VID_B_INT_MSK
);
1595 ts2_status
= cx_read(VID_C_INT_STAT
);
1596 ts2_mask
= cx_read(VID_C_INT_MSK
);
1598 if ( (pci_status
== 0) && (ts2_status
== 0) && (ts1_status
== 0) )
1601 vida_count
= cx_read(VID_A_GPCNT
);
1602 ts1_count
= cx_read(ts1
->reg_gpcnt
);
1603 ts2_count
= cx_read(ts2
->reg_gpcnt
);
1604 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1605 pci_status
, pci_mask
);
1606 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1607 vida_status
, vida_mask
, vida_count
);
1608 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1609 ts1_status
, ts1_mask
, ts1_count
);
1610 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1611 ts2_status
, ts2_mask
, ts2_count
);
1613 if ( (pci_status
& PCI_MSK_RISC_RD
) ||
1614 (pci_status
& PCI_MSK_RISC_WR
) ||
1615 (pci_status
& PCI_MSK_AL_RD
) ||
1616 (pci_status
& PCI_MSK_AL_WR
) ||
1617 (pci_status
& PCI_MSK_APB_DMA
) ||
1618 (pci_status
& PCI_MSK_VID_C
) ||
1619 (pci_status
& PCI_MSK_VID_B
) ||
1620 (pci_status
& PCI_MSK_VID_A
) ||
1621 (pci_status
& PCI_MSK_AUD_INT
) ||
1622 (pci_status
& PCI_MSK_AUD_EXT
) )
1625 if (pci_status
& PCI_MSK_RISC_RD
)
1626 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD
);
1627 if (pci_status
& PCI_MSK_RISC_WR
)
1628 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR
);
1629 if (pci_status
& PCI_MSK_AL_RD
)
1630 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD
);
1631 if (pci_status
& PCI_MSK_AL_WR
)
1632 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR
);
1633 if (pci_status
& PCI_MSK_APB_DMA
)
1634 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA
);
1635 if (pci_status
& PCI_MSK_VID_C
)
1636 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C
);
1637 if (pci_status
& PCI_MSK_VID_B
)
1638 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B
);
1639 if (pci_status
& PCI_MSK_VID_A
)
1640 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A
);
1641 if (pci_status
& PCI_MSK_AUD_INT
)
1642 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT
);
1643 if (pci_status
& PCI_MSK_AUD_EXT
)
1644 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT
);
1649 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_DVB
)
1650 handled
+= cx23885_irq_ts(ts1
, ts1_status
);
1652 if (cx23885_boards
[dev
->board
].portb
== CX23885_MPEG_ENCODER
)
1653 handled
+= cx23885_irq_417(dev
, ts1_status
);
1657 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_DVB
)
1658 handled
+= cx23885_irq_ts(ts2
, ts2_status
);
1660 if (cx23885_boards
[dev
->board
].portc
== CX23885_MPEG_ENCODER
)
1661 handled
+= cx23885_irq_417(dev
, ts2_status
);
1665 handled
+= cx23885_video_irq(dev
, vida_status
);
1668 cx_write(PCI_INT_STAT
, pci_status
);
1670 return IRQ_RETVAL(handled
);
1673 static int __devinit
cx23885_initdev(struct pci_dev
*pci_dev
,
1674 const struct pci_device_id
*pci_id
)
1676 struct cx23885_dev
*dev
;
1679 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1685 if (pci_enable_device(pci_dev
)) {
1690 if (cx23885_dev_setup(dev
) < 0) {
1695 /* print pci info */
1696 pci_read_config_byte(pci_dev
, PCI_CLASS_REVISION
, &dev
->pci_rev
);
1697 pci_read_config_byte(pci_dev
, PCI_LATENCY_TIMER
, &dev
->pci_lat
);
1698 printk(KERN_INFO
"%s/0: found at %s, rev: %d, irq: %d, "
1699 "latency: %d, mmio: 0x%llx\n", dev
->name
,
1700 pci_name(pci_dev
), dev
->pci_rev
, pci_dev
->irq
,
1702 (unsigned long long)pci_resource_start(pci_dev
, 0));
1704 pci_set_master(pci_dev
);
1705 if (!pci_dma_supported(pci_dev
, 0xffffffff)) {
1706 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev
->name
);
1711 err
= request_irq(pci_dev
->irq
, cx23885_irq
,
1712 IRQF_SHARED
| IRQF_DISABLED
, dev
->name
, dev
);
1714 printk(KERN_ERR
"%s: can't get IRQ %d\n",
1715 dev
->name
, pci_dev
->irq
);
1719 pci_set_drvdata(pci_dev
, dev
);
1723 cx23885_dev_unregister(dev
);
1729 static void __devexit
cx23885_finidev(struct pci_dev
*pci_dev
)
1731 struct cx23885_dev
*dev
= pci_get_drvdata(pci_dev
);
1733 cx23885_shutdown(dev
);
1735 pci_disable_device(pci_dev
);
1737 /* unregister stuff */
1738 free_irq(pci_dev
->irq
, dev
);
1739 pci_set_drvdata(pci_dev
, NULL
);
1741 mutex_lock(&devlist
);
1742 list_del(&dev
->devlist
);
1743 mutex_unlock(&devlist
);
1745 cx23885_dev_unregister(dev
);
1749 static struct pci_device_id cx23885_pci_tbl
[] = {
1754 .subvendor
= PCI_ANY_ID
,
1755 .subdevice
= PCI_ANY_ID
,
1760 .subvendor
= PCI_ANY_ID
,
1761 .subdevice
= PCI_ANY_ID
,
1763 /* --- end of list --- */
1766 MODULE_DEVICE_TABLE(pci
, cx23885_pci_tbl
);
1768 static struct pci_driver cx23885_pci_driver
= {
1770 .id_table
= cx23885_pci_tbl
,
1771 .probe
= cx23885_initdev
,
1772 .remove
= __devexit_p(cx23885_finidev
),
1778 static int cx23885_init(void)
1780 printk(KERN_INFO
"cx23885 driver version %d.%d.%d loaded\n",
1781 (CX23885_VERSION_CODE
>> 16) & 0xff,
1782 (CX23885_VERSION_CODE
>> 8) & 0xff,
1783 CX23885_VERSION_CODE
& 0xff);
1785 printk(KERN_INFO
"cx23885: snapshot date %04d-%02d-%02d\n",
1786 SNAPSHOT
/10000, (SNAPSHOT
/100)%100, SNAPSHOT
%100);
1788 return pci_register_driver(&cx23885_pci_driver
);
1791 static void cx23885_fini(void)
1793 pci_unregister_driver(&cx23885_pci_driver
);
1796 module_init(cx23885_init
);
1797 module_exit(cx23885_fini
);
1799 /* ----------------------------------------------------------- */
1804 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off