drivers/media/video/cx23885/cx23885.h

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/pci.h>
  23 #include <linux/i2c.h>
  24 #include <linux/i2c-algo-bit.h>
  25 #include <linux/kdev_t.h>
  26
  27 #include <media/v4l2-device.h>
  28 #include <media/tuner.h>
  29 #include <media/tveeprom.h>
  30 #include <media/videobuf-dma-sg.h>
  31 #include <media/videobuf-dvb.h>
  32
  33 #include "btcx-risc.h"
  34 #include "cx23885-reg.h"
  35 #include "media/cx2341x.h"
  36
  37 #include <linux/version.h>
  38 #include <linux/mutex.h>
  39
  40 #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
  41
  42 #define UNSET (-1U)
  43
  44 #define CX23885_MAXBOARDS 8
  45
  46 /* Max number of inputs by card */
  47 #define MAX_CX23885_INPUT 8
  48 #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
  49 #define RESOURCE_OVERLAY       1
  50 #define RESOURCE_VIDEO         2
  51 #define RESOURCE_VBI           4
  52
  53 #define BUFFER_TIMEOUT     (HZ)  /* 0.5 seconds */
  54
  55 #define CX23885_BOARD_NOAUTO               UNSET
  56 #define CX23885_BOARD_UNKNOWN                  0
  57 #define CX23885_BOARD_HAUPPAUGE_HVR1800lp      1
  58 #define CX23885_BOARD_HAUPPAUGE_HVR1800        2
  59 #define CX23885_BOARD_HAUPPAUGE_HVR1250        3
  60 #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP   4
  61 #define CX23885_BOARD_HAUPPAUGE_HVR1500Q       5
  62 #define CX23885_BOARD_HAUPPAUGE_HVR1500        6
  63 #define CX23885_BOARD_HAUPPAUGE_HVR1200        7
  64 #define CX23885_BOARD_HAUPPAUGE_HVR1700        8
  65 #define CX23885_BOARD_HAUPPAUGE_HVR1400        9
  66 #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
  67 #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
  68 #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
  69 #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F   13
  70 #define CX23885_BOARD_TBS_6920                 14
  71 #define CX23885_BOARD_TEVII_S470               15
  72 #define CX23885_BOARD_DVBWORLD_2005            16
  73 #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI      17
  74 #define CX23885_BOARD_HAUPPAUGE_HVR1270        18
  75 #define CX23885_BOARD_HAUPPAUGE_HVR1275        19
  76 #define CX23885_BOARD_HAUPPAUGE_HVR1255        20
  77 #define CX23885_BOARD_HAUPPAUGE_HVR1210        21
  78
  79 #define GPIO_0 0x00000001
  80 #define GPIO_1 0x00000002
  81 #define GPIO_2 0x00000004
  82 #define GPIO_3 0x00000008
  83 #define GPIO_4 0x00000010
  84 #define GPIO_5 0x00000020
  85 #define GPIO_6 0x00000040
  86 #define GPIO_7 0x00000080
  87 #define GPIO_8 0x00000100
  88 #define GPIO_9 0x00000200
  89
  90 /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
  91 #define CX23885_NORMS (\
  92         V4L2_STD_NTSC_M |  V4L2_STD_NTSC_M_JP |  V4L2_STD_NTSC_443 | \
  93         V4L2_STD_PAL_BG |  V4L2_STD_PAL_DK    |  V4L2_STD_PAL_I    | \
  94         V4L2_STD_PAL_M  |  V4L2_STD_PAL_N     |  V4L2_STD_PAL_Nc   | \
  95         V4L2_STD_PAL_60 |  V4L2_STD_SECAM_L   |  V4L2_STD_SECAM_DK)
  96
  97 struct cx23885_fmt {
  98         char  *name;
  99         u32   fourcc;          /* v4l2 format id */
 100         int   depth;
 101         int   flags;
 102         u32   cxformat;
 103 };
 104
 105 struct cx23885_ctrl {
 106         struct v4l2_queryctrl v;
 107         u32                   off;
 108         u32                   reg;
 109         u32                   mask;
 110         u32                   shift;
 111 };
 112
 113 struct cx23885_tvnorm {
 114         char            *name;
 115         v4l2_std_id     id;
 116         u32             cxiformat;
 117         u32             cxoformat;
 118 };
 119
 120 struct cx23885_fh {
 121         struct cx23885_dev         *dev;
 122         enum v4l2_buf_type         type;
 123         int                        radio;
 124         u32                        resources;
 125
 126         /* video overlay */
 127         struct v4l2_window         win;
 128         struct v4l2_clip           *clips;
 129         unsigned int               nclips;
 130
 131         /* video capture */
 132         struct cx23885_fmt         *fmt;
 133         unsigned int               width, height;
 134
 135         /* vbi capture */
 136         struct videobuf_queue      vidq;
 137         struct videobuf_queue      vbiq;
 138
 139         /* MPEG Encoder specifics ONLY */
 140         struct videobuf_queue      mpegq;
 141         atomic_t                   v4l_reading;
 142 };
 143
 144 enum cx23885_itype {
 145         CX23885_VMUX_COMPOSITE1 = 1,
 146         CX23885_VMUX_COMPOSITE2,
 147         CX23885_VMUX_COMPOSITE3,
 148         CX23885_VMUX_COMPOSITE4,
 149         CX23885_VMUX_SVIDEO,
 150         CX23885_VMUX_TELEVISION,
 151         CX23885_VMUX_CABLE,
 152         CX23885_VMUX_DVB,
 153         CX23885_VMUX_DEBUG,
 154         CX23885_RADIO,
 155 };
 156
 157 enum cx23885_src_sel_type {
 158         CX23885_SRC_SEL_EXT_656_VIDEO = 0,
 159         CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
 160 };
 161
 162 /* buffer for one video frame */
 163 struct cx23885_buffer {
 164         /* common v4l buffer stuff -- must be first */
 165         struct videobuf_buffer vb;
 166
 167         /* cx23885 specific */
 168         unsigned int           bpl;
 169         struct btcx_riscmem    risc;
 170         struct cx23885_fmt     *fmt;
 171         u32                    count;
 172 };
 173
 174 struct cx23885_input {
 175         enum cx23885_itype type;
 176         unsigned int    vmux;
 177         u32             gpio0, gpio1, gpio2, gpio3;
 178 };
 179
 180 typedef enum {
 181         CX23885_MPEG_UNDEFINED = 0,
 182         CX23885_MPEG_DVB,
 183         CX23885_ANALOG_VIDEO,
 184         CX23885_MPEG_ENCODER,
 185 } port_t;
 186
 187 struct cx23885_board {
 188         char                    *name;
 189         port_t                  porta, portb, portc;
 190         unsigned int            tuner_type;
 191         unsigned int            radio_type;
 192         unsigned char           tuner_addr;
 193         unsigned char           radio_addr;
 194
 195         /* Vendors can and do run the PCIe bridge at different
 196          * clock rates, driven physically by crystals on the PCBs.
 197          * The core has to accomodate this. This allows the user
 198          * to add new boards with new frequencys. The value is
 199          * expressed in Hz.
 200          *
 201          * The core framework will default this value based on
 202          * current designs, but it can vary.
 203          */
 204         u32                     clk_freq;
 205         struct cx23885_input    input[MAX_CX23885_INPUT];
 206         int                     cimax; /* for NetUP */
 207 };
 208
 209 struct cx23885_subid {
 210         u16     subvendor;
 211         u16     subdevice;
 212         u32     card;
 213 };
 214
 215 struct cx23885_i2c {
 216         struct cx23885_dev *dev;
 217
 218         int                        nr;
 219
 220         /* i2c i/o */
 221         struct i2c_adapter         i2c_adap;
 222         struct i2c_algo_bit_data   i2c_algo;
 223         struct i2c_client          i2c_client;
 224         u32                        i2c_rc;
 225
 226         /* 885 registers used for raw addess */
 227         u32                        i2c_period;
 228         u32                        reg_ctrl;
 229         u32                        reg_stat;
 230         u32                        reg_addr;
 231         u32                        reg_rdata;
 232         u32                        reg_wdata;
 233 };
 234
 235 struct cx23885_dmaqueue {
 236         struct list_head       active;
 237         struct list_head       queued;
 238         struct timer_list      timeout;
 239         struct btcx_riscmem    stopper;
 240         u32                    count;
 241 };
 242
 243 struct cx23885_tsport {
 244         struct cx23885_dev *dev;
 245
 246         int                        nr;
 247         int                        sram_chno;
 248
 249         struct videobuf_dvb_frontends frontends;
 250
 251         /* dma queues */
 252         struct cx23885_dmaqueue    mpegq;
 253         u32                        ts_packet_size;
 254         u32                        ts_packet_count;
 255
 256         int                        width;
 257         int                        height;
 258
 259         spinlock_t                 slock;
 260
 261         /* registers */
 262         u32                        reg_gpcnt;
 263         u32                        reg_gpcnt_ctl;
 264         u32                        reg_dma_ctl;
 265         u32                        reg_lngth;
 266         u32                        reg_hw_sop_ctrl;
 267         u32                        reg_gen_ctrl;
 268         u32                        reg_bd_pkt_status;
 269         u32                        reg_sop_status;
 270         u32                        reg_fifo_ovfl_stat;
 271         u32                        reg_vld_misc;
 272         u32                        reg_ts_clk_en;
 273         u32                        reg_ts_int_msk;
 274         u32                        reg_ts_int_stat;
 275         u32                        reg_src_sel;
 276
 277         /* Default register vals */
 278         int                        pci_irqmask;
 279         u32                        dma_ctl_val;
 280         u32                        ts_int_msk_val;
 281         u32                        gen_ctrl_val;
 282         u32                        ts_clk_en_val;
 283         u32                        src_sel_val;
 284         u32                        vld_misc_val;
 285         u32                        hw_sop_ctrl_val;
 286
 287         /* Allow a single tsport to have multiple frontends */
 288         u32                        num_frontends;
 289         void                       *port_priv;
 290 };
 291
 292 struct cx23885_dev {
 293         struct list_head           devlist;
 294         atomic_t                   refcount;
 295         struct v4l2_device         v4l2_dev;
 296
 297         /* pci stuff */
 298         struct pci_dev             *pci;
 299         unsigned char              pci_rev, pci_lat;
 300         int                        pci_bus, pci_slot;
 301         u32                        __iomem *lmmio;
 302         u8                         __iomem *bmmio;
 303         int                        pci_irqmask;
 304         int                        hwrevision;
 305
 306         /* This valud is board specific and is used to configure the
 307          * AV core so we see nice clean and stable video and audio. */
 308         u32                        clk_freq;
 309
 310         /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
 311         struct cx23885_i2c         i2c_bus[3];
 312
 313         int                        nr;
 314         struct mutex               lock;
 315
 316         /* board details */
 317         unsigned int               board;
 318         char                       name[32];
 319
 320         struct cx23885_tsport      ts1, ts2;
 321
 322         /* sram configuration */
 323         struct sram_channel        *sram_channels;
 324
 325         enum {
 326                 CX23885_BRIDGE_UNDEFINED = 0,
 327                 CX23885_BRIDGE_885 = 885,
 328                 CX23885_BRIDGE_887 = 887,
 329         } bridge;
 330
 331         /* Analog video */
 332         u32                        resources;
 333         unsigned int               input;
 334         u32                        tvaudio;
 335         v4l2_std_id                tvnorm;
 336         unsigned int               tuner_type;
 337         unsigned char              tuner_addr;
 338         unsigned int               radio_type;
 339         unsigned char              radio_addr;
 340         unsigned int               has_radio;
 341         struct v4l2_subdev         *sd_cx25840;
 342
 343         /* V4l */
 344         u32                        freq;
 345         struct video_device        *video_dev;
 346         struct video_device        *vbi_dev;
 347         struct video_device        *radio_dev;
 348
 349         struct cx23885_dmaqueue    vidq;
 350         struct cx23885_dmaqueue    vbiq;
 351         spinlock_t                 slock;
 352
 353         /* MPEG Encoder ONLY settings */
 354         u32                        cx23417_mailbox;
 355         struct cx2341x_mpeg_params mpeg_params;
 356         struct video_device        *v4l_device;
 357         atomic_t                   v4l_reader_count;
 358         struct cx23885_tvnorm      encodernorm;
 359
 360 };
 361
 362 static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
 363 {
 364         return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
 365 }
 366
 367 #define call_all(dev, o, f, args...) \
 368         v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
 369
 370 extern struct list_head cx23885_devlist;
 371
 372 #define SRAM_CH01  0 /* Video A */
 373 #define SRAM_CH02  1 /* VBI A */
 374 #define SRAM_CH03  2 /* Video B */
 375 #define SRAM_CH04  3 /* Transport via B */
 376 #define SRAM_CH05  4 /* VBI B */
 377 #define SRAM_CH06  5 /* Video C */
 378 #define SRAM_CH07  6 /* Transport via C */
 379 #define SRAM_CH08  7 /* Audio Internal A */
 380 #define SRAM_CH09  8 /* Audio Internal B */
 381 #define SRAM_CH10  9 /* Audio External */
 382 #define SRAM_CH11 10 /* COMB_3D_N */
 383 #define SRAM_CH12 11 /* Comb 3D N1 */
 384 #define SRAM_CH13 12 /* Comb 3D N2 */
 385 #define SRAM_CH14 13 /* MOE Vid */
 386 #define SRAM_CH15 14 /* MOE RSLT */
 387
 388 struct sram_channel {
 389         char *name;
 390         u32  cmds_start;
 391         u32  ctrl_start;
 392         u32  cdt;
 393         u32  fifo_start;;
 394         u32  fifo_size;
 395         u32  ptr1_reg;
 396         u32  ptr2_reg;
 397         u32  cnt1_reg;
 398         u32  cnt2_reg;
 399         u32  jumponly;
 400 };
 401
 402 /* ----------------------------------------------------------- */
 403
 404 #define cx_read(reg)             readl(dev->lmmio + ((reg)>>2))
 405 #define cx_write(reg, value)     writel((value), dev->lmmio + ((reg)>>2))
 406
 407 #define cx_andor(reg, mask, value) \
 408   writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
 409   ((value) & (mask)), dev->lmmio+((reg)>>2))
 410
 411 #define cx_set(reg, bit)          cx_andor((reg), (bit), (bit))
 412 #define cx_clear(reg, bit)        cx_andor((reg), (bit), 0)
 413
 414 /* ----------------------------------------------------------- */
 415 /* cx23885-core.c                                              */
 416
 417 extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 418         struct sram_channel *ch,
 419         unsigned int bpl, u32 risc);
 420
 421 extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 422         struct sram_channel *ch);
 423
 424 extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 425         u32 reg, u32 mask, u32 value);
 426
 427 extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 428         struct scatterlist *sglist,
 429         unsigned int top_offset, unsigned int bottom_offset,
 430         unsigned int bpl, unsigned int padding, unsigned int lines);
 431
 432 void cx23885_cancel_buffers(struct cx23885_tsport *port);
 433
 434 extern int cx23885_restart_queue(struct cx23885_tsport *port,
 435                                 struct cx23885_dmaqueue *q);
 436
 437 extern void cx23885_wakeup(struct cx23885_tsport *port,
 438                            struct cx23885_dmaqueue *q, u32 count);
 439
 440 extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
 441 extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
 442 extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
 443         int asoutput);
 444
 445
 446 /* ----------------------------------------------------------- */
 447 /* cx23885-cards.c                                             */
 448 extern struct cx23885_board cx23885_boards[];
 449 extern const unsigned int cx23885_bcount;
 450
 451 extern struct cx23885_subid cx23885_subids[];
 452 extern const unsigned int cx23885_idcount;
 453
 454 extern int cx23885_tuner_callback(void *priv, int component,
 455         int command, int arg);
 456 extern void cx23885_card_list(struct cx23885_dev *dev);
 457 extern int  cx23885_ir_init(struct cx23885_dev *dev);
 458 extern void cx23885_gpio_setup(struct cx23885_dev *dev);
 459 extern void cx23885_card_setup(struct cx23885_dev *dev);
 460 extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
 461
 462 extern int cx23885_dvb_register(struct cx23885_tsport *port);
 463 extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
 464
 465 extern int cx23885_buf_prepare(struct videobuf_queue *q,
 466                                struct cx23885_tsport *port,
 467                                struct cx23885_buffer *buf,
 468                                enum v4l2_field field);
 469 extern void cx23885_buf_queue(struct cx23885_tsport *port,
 470                               struct cx23885_buffer *buf);
 471 extern void cx23885_free_buffer(struct videobuf_queue *q,
 472                                 struct cx23885_buffer *buf);
 473
 474 /* ----------------------------------------------------------- */
 475 /* cx23885-video.c                                             */
 476 /* Video */
 477 extern int cx23885_video_register(struct cx23885_dev *dev);
 478 extern void cx23885_video_unregister(struct cx23885_dev *dev);
 479 extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
 480
 481 /* ----------------------------------------------------------- */
 482 /* cx23885-vbi.c                                               */
 483 extern int cx23885_vbi_fmt(struct file *file, void *priv,
 484         struct v4l2_format *f);
 485 extern void cx23885_vbi_timeout(unsigned long data);
 486 extern struct videobuf_queue_ops cx23885_vbi_qops;
 487
 488 /* cx23885-i2c.c                                                */
 489 extern int cx23885_i2c_register(struct cx23885_i2c *bus);
 490 extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
 491 extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
 492
 493 /* ----------------------------------------------------------- */
 494 /* cx23885-417.c                                               */
 495 extern int cx23885_417_register(struct cx23885_dev *dev);
 496 extern void cx23885_417_unregister(struct cx23885_dev *dev);
 497 extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
 498 extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
 499 extern void cx23885_mc417_init(struct cx23885_dev *dev);
 500 extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
 501 extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
 502
 503
 504 /* ----------------------------------------------------------- */
 505 /* tv norms                                                    */
 506
 507 static inline unsigned int norm_maxw(v4l2_std_id norm)
 508 {
 509         return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
 510 }
 511
 512 static inline unsigned int norm_maxh(v4l2_std_id norm)
 513 {
 514         return (norm & V4L2_STD_625_50) ? 576 : 480;
 515 }
 516
 517 static inline unsigned int norm_swidth(v4l2_std_id norm)
 518 {
 519         return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
 520 }