2 * V4L2 Driver for i.MX27/i.MX25 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/mutex.h>
32 #include <linux/clk.h>
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-dev.h>
36 #include <media/videobuf2-core.h>
37 #include <media/videobuf2-dma-contig.h>
38 #include <media/soc_camera.h>
39 #include <media/soc_mediabus.h>
41 #include <linux/videodev2.h>
43 #include <mach/mx2_cam.h>
44 #include <mach/hardware.h>
48 #define MX2_CAM_DRV_NAME "mx2-camera"
49 #define MX2_CAM_VERSION "0.0.6"
50 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
53 #define CSICR1_RESET_VAL 0x40000800
54 #define CSICR2_RESET_VAL 0x0
55 #define CSICR3_RESET_VAL 0x0
57 /* csi control reg 1 */
58 #define CSICR1_SWAP16_EN (1 << 31)
59 #define CSICR1_EXT_VSYNC (1 << 30)
60 #define CSICR1_EOF_INTEN (1 << 29)
61 #define CSICR1_PRP_IF_EN (1 << 28)
62 #define CSICR1_CCIR_MODE (1 << 27)
63 #define CSICR1_COF_INTEN (1 << 26)
64 #define CSICR1_SF_OR_INTEN (1 << 25)
65 #define CSICR1_RF_OR_INTEN (1 << 24)
66 #define CSICR1_STATFF_LEVEL (3 << 22)
67 #define CSICR1_STATFF_INTEN (1 << 21)
68 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
69 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
70 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
71 #define CSICR1_RXFF_INTEN (1 << 18)
72 #define CSICR1_SOF_POL (1 << 17)
73 #define CSICR1_SOF_INTEN (1 << 16)
74 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
75 #define CSICR1_HSYNC_POL (1 << 11)
76 #define CSICR1_CCIR_EN (1 << 10)
77 #define CSICR1_MCLKEN (1 << 9)
78 #define CSICR1_FCC (1 << 8)
79 #define CSICR1_PACK_DIR (1 << 7)
80 #define CSICR1_CLR_STATFIFO (1 << 6)
81 #define CSICR1_CLR_RXFIFO (1 << 5)
82 #define CSICR1_GCLK_MODE (1 << 4)
83 #define CSICR1_INV_DATA (1 << 3)
84 #define CSICR1_INV_PCLK (1 << 2)
85 #define CSICR1_REDGE (1 << 1)
86 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
88 #define SHIFT_STATFF_LEVEL 22
89 #define SHIFT_RXFF_LEVEL 19
90 #define SHIFT_MCLKDIV 12
93 #define CSICR3_FRMCNT (0xFFFF << 16)
94 #define CSICR3_FRMCNT_RST (1 << 15)
95 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
96 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
97 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
98 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
99 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
100 #define CSICR3_CSI_SUP (1 << 3)
101 #define CSICR3_ZERO_PACK_EN (1 << 2)
102 #define CSICR3_ECC_INT_EN (1 << 1)
103 #define CSICR3_ECC_AUTO_EN (1 << 0)
105 #define SHIFT_FRMCNT 16
108 #define CSISR_SFF_OR_INT (1 << 25)
109 #define CSISR_RFF_OR_INT (1 << 24)
110 #define CSISR_STATFF_INT (1 << 21)
111 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
112 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
113 #define CSISR_RXFF_INT (1 << 18)
114 #define CSISR_EOF_INT (1 << 17)
115 #define CSISR_SOF_INT (1 << 16)
116 #define CSISR_F2_INT (1 << 15)
117 #define CSISR_F1_INT (1 << 14)
118 #define CSISR_COF_INT (1 << 13)
119 #define CSISR_ECC_INT (1 << 1)
120 #define CSISR_DRDY (1 << 0)
124 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
125 #define CSISTATFIFO 0x0c
126 #define CSIRFIFO 0x10
127 #define CSIRXCNT 0x14
128 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
129 #define CSIDMASA_STATFIFO 0x20
130 #define CSIDMATA_STATFIFO 0x24
131 #define CSIDMASA_FB1 0x28
132 #define CSIDMASA_FB2 0x2c
133 #define CSIFBUF_PARA 0x30
134 #define CSIIMAG_PARA 0x34
137 #define PRP_CNTL 0x00
138 #define PRP_INTR_CNTL 0x04
139 #define PRP_INTRSTATUS 0x08
140 #define PRP_SOURCE_Y_PTR 0x0c
141 #define PRP_SOURCE_CB_PTR 0x10
142 #define PRP_SOURCE_CR_PTR 0x14
143 #define PRP_DEST_RGB1_PTR 0x18
144 #define PRP_DEST_RGB2_PTR 0x1c
145 #define PRP_DEST_Y_PTR 0x20
146 #define PRP_DEST_CB_PTR 0x24
147 #define PRP_DEST_CR_PTR 0x28
148 #define PRP_SRC_FRAME_SIZE 0x2c
149 #define PRP_DEST_CH1_LINE_STRIDE 0x30
150 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
151 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
152 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
153 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
154 #define PRP_SRC_LINE_STRIDE 0x44
155 #define PRP_CSC_COEF_012 0x48
156 #define PRP_CSC_COEF_345 0x4c
157 #define PRP_CSC_COEF_678 0x50
158 #define PRP_CH1_RZ_HORI_COEF1 0x54
159 #define PRP_CH1_RZ_HORI_COEF2 0x58
160 #define PRP_CH1_RZ_HORI_VALID 0x5c
161 #define PRP_CH1_RZ_VERT_COEF1 0x60
162 #define PRP_CH1_RZ_VERT_COEF2 0x64
163 #define PRP_CH1_RZ_VERT_VALID 0x68
164 #define PRP_CH2_RZ_HORI_COEF1 0x6c
165 #define PRP_CH2_RZ_HORI_COEF2 0x70
166 #define PRP_CH2_RZ_HORI_VALID 0x74
167 #define PRP_CH2_RZ_VERT_COEF1 0x78
168 #define PRP_CH2_RZ_VERT_COEF2 0x7c
169 #define PRP_CH2_RZ_VERT_VALID 0x80
171 #define PRP_CNTL_CH1EN (1 << 0)
172 #define PRP_CNTL_CH2EN (1 << 1)
173 #define PRP_CNTL_CSIEN (1 << 2)
174 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
175 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
176 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
177 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
178 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
179 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
180 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
181 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
182 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
183 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
184 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
185 #define PRP_CNTL_CH1_LEN (1 << 9)
186 #define PRP_CNTL_CH2_LEN (1 << 10)
187 #define PRP_CNTL_SKIP_FRAME (1 << 11)
188 #define PRP_CNTL_SWRST (1 << 12)
189 #define PRP_CNTL_CLKEN (1 << 13)
190 #define PRP_CNTL_WEN (1 << 14)
191 #define PRP_CNTL_CH1BYP (1 << 15)
192 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
193 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
194 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
195 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
196 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
197 #define PRP_CNTL_CH2B1EN (1 << 29)
198 #define PRP_CNTL_CH2B2EN (1 << 30)
199 #define PRP_CNTL_CH2FEN (1 << 31)
201 /* IRQ Enable and status register */
202 #define PRP_INTR_RDERR (1 << 0)
203 #define PRP_INTR_CH1WERR (1 << 1)
204 #define PRP_INTR_CH2WERR (1 << 2)
205 #define PRP_INTR_CH1FC (1 << 3)
206 #define PRP_INTR_CH2FC (1 << 5)
207 #define PRP_INTR_LBOVF (1 << 7)
208 #define PRP_INTR_CH2OVF (1 << 8)
210 /* Resizing registers */
211 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
212 #define PRP_RZ_VALID_BILINEAR (1 << 31)
214 #define MAX_VIDEO_MEM 16
216 #define RESIZE_NUM_MIN 1
217 #define RESIZE_NUM_MAX 20
219 #define SZ_COEF (1 << BC_COEF)
221 #define RESIZE_DIR_H 0
222 #define RESIZE_DIR_V 1
224 #define RESIZE_ALGO_BILINEAR 0
225 #define RESIZE_ALGO_AVERAGING 1
237 /* prp resizing parameters */
238 struct emma_prp_resize
{
239 int algo
; /* type of algorithm used */
240 int len
; /* number of coefficients */
241 unsigned char s
[RESIZE_NUM_MAX
]; /* table of coefficients */
244 /* prp configuration for a client-host fmt pair */
246 enum v4l2_mbus_pixelcode in_fmt
;
248 struct mx2_prp_cfg cfg
;
251 enum mx2_buffer_state
{
257 struct mx2_buf_internal
{
258 struct list_head queue
;
263 /* buffer for one video frame */
265 /* common v4l buffer stuff -- must be first */
266 struct vb2_buffer vb
;
267 enum mx2_buffer_state state
;
268 struct mx2_buf_internal internal
;
271 struct mx2_camera_dev
{
273 struct soc_camera_host soc_host
;
274 struct soc_camera_device
*icd
;
275 struct clk
*clk_csi
, *clk_emma
;
277 unsigned int irq_csi
, irq_emma
;
278 void __iomem
*base_csi
, *base_emma
;
279 unsigned long base_dma
;
281 struct mx2_camera_platform_data
*pdata
;
282 struct resource
*res_csi
, *res_emma
;
283 unsigned long platform_flags
;
285 struct list_head capture
;
286 struct list_head active_bufs
;
287 struct list_head discard
;
292 struct mx2_buffer
*active
;
293 struct mx2_buffer
*fb1_active
;
294 struct mx2_buffer
*fb2_active
;
298 struct mx2_buf_internal buf_discard
[2];
299 void *discard_buffer
;
300 dma_addr_t discard_buffer_dma
;
302 struct mx2_fmt_cfg
*emma_prp
;
303 struct emma_prp_resize resizing
[2];
304 unsigned int s_width
, s_height
;
306 struct vb2_alloc_ctx
*alloc_ctx
;
309 static struct mx2_buffer
*mx2_ibuf_to_buf(struct mx2_buf_internal
*int_buf
)
311 return container_of(int_buf
, struct mx2_buffer
, internal
);
314 static struct mx2_fmt_cfg mx27_emma_prp_table
[] = {
316 * This is a generic configuration which is valid for most
317 * prp input-output format combinations.
318 * We set the incomming and outgoing pixelformat to a
319 * 16 Bit wide format and adjust the bytesperline
320 * accordingly. With this configuration the inputdata
321 * will not be changed by the emma and could be any type
322 * of 16 Bit Pixelformat.
329 .in_fmt
= PRP_CNTL_DATA_IN_RGB16
,
330 .out_fmt
= PRP_CNTL_CH1_OUT_RGB16
,
331 .src_pixel
= 0x2ca00565, /* RGB565 */
332 .ch1_pixel
= 0x2ca00565, /* RGB565 */
333 .irq_flags
= PRP_INTR_RDERR
| PRP_INTR_CH1WERR
|
334 PRP_INTR_CH1FC
| PRP_INTR_LBOVF
,
339 .in_fmt
= V4L2_MBUS_FMT_YUYV8_2X8
,
340 .out_fmt
= V4L2_PIX_FMT_YUV420
,
343 .in_fmt
= PRP_CNTL_DATA_IN_YUV422
,
344 .out_fmt
= PRP_CNTL_CH2_OUT_YUV420
,
345 .src_pixel
= 0x22000888, /* YUV422 (YUYV) */
346 .irq_flags
= PRP_INTR_RDERR
| PRP_INTR_CH2WERR
|
347 PRP_INTR_CH2FC
| PRP_INTR_LBOVF
|
349 .csicr1
= CSICR1_PACK_DIR
,
353 .in_fmt
= V4L2_MBUS_FMT_UYVY8_2X8
,
354 .out_fmt
= V4L2_PIX_FMT_YUV420
,
357 .in_fmt
= PRP_CNTL_DATA_IN_YUV422
,
358 .out_fmt
= PRP_CNTL_CH2_OUT_YUV420
,
359 .src_pixel
= 0x22000888, /* YUV422 (YUYV) */
360 .irq_flags
= PRP_INTR_RDERR
| PRP_INTR_CH2WERR
|
361 PRP_INTR_CH2FC
| PRP_INTR_LBOVF
|
363 .csicr1
= CSICR1_SWAP16_EN
,
368 static struct mx2_fmt_cfg
*mx27_emma_prp_get_format(
369 enum v4l2_mbus_pixelcode in_fmt
,
374 for (i
= 1; i
< ARRAY_SIZE(mx27_emma_prp_table
); i
++)
375 if ((mx27_emma_prp_table
[i
].in_fmt
== in_fmt
) &&
376 (mx27_emma_prp_table
[i
].out_fmt
== out_fmt
)) {
377 return &mx27_emma_prp_table
[i
];
379 /* If no match return the most generic configuration */
380 return &mx27_emma_prp_table
[0];
383 static void mx27_update_emma_buf(struct mx2_camera_dev
*pcdev
,
384 unsigned long phys
, int bufnum
)
386 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
388 if (prp
->cfg
.channel
== 1) {
389 writel(phys
, pcdev
->base_emma
+
390 PRP_DEST_RGB1_PTR
+ 4 * bufnum
);
392 writel(phys
, pcdev
->base_emma
+
393 PRP_DEST_Y_PTR
- 0x14 * bufnum
);
394 if (prp
->out_fmt
== V4L2_PIX_FMT_YUV420
) {
395 u32 imgsize
= pcdev
->icd
->user_height
*
396 pcdev
->icd
->user_width
;
398 writel(phys
+ imgsize
, pcdev
->base_emma
+
399 PRP_DEST_CB_PTR
- 0x14 * bufnum
);
400 writel(phys
+ ((5 * imgsize
) / 4), pcdev
->base_emma
+
401 PRP_DEST_CR_PTR
- 0x14 * bufnum
);
406 static void mx2_camera_deactivate(struct mx2_camera_dev
*pcdev
)
410 clk_disable(pcdev
->clk_csi
);
411 writel(0, pcdev
->base_csi
+ CSICR1
);
413 writel(0, pcdev
->base_emma
+ PRP_CNTL
);
414 } else if (cpu_is_mx25()) {
415 spin_lock_irqsave(&pcdev
->lock
, flags
);
416 pcdev
->fb1_active
= NULL
;
417 pcdev
->fb2_active
= NULL
;
418 writel(0, pcdev
->base_csi
+ CSIDMASA_FB1
);
419 writel(0, pcdev
->base_csi
+ CSIDMASA_FB2
);
420 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
425 * The following two functions absolutely depend on the fact, that
426 * there can be only one camera on mx2 camera sensor interface
428 static int mx2_camera_add_device(struct soc_camera_device
*icd
)
430 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
431 struct mx2_camera_dev
*pcdev
= ici
->priv
;
438 ret
= clk_enable(pcdev
->clk_csi
);
442 csicr1
= CSICR1_MCLKEN
;
445 csicr1
|= CSICR1_PRP_IF_EN
| CSICR1_FCC
|
446 CSICR1_RXFF_LEVEL(0);
447 } else if (cpu_is_mx27())
448 csicr1
|= CSICR1_SOF_INTEN
| CSICR1_RXFF_LEVEL(2);
450 pcdev
->csicr1
= csicr1
;
451 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
454 pcdev
->frame_count
= 0;
456 dev_info(icd
->parent
, "Camera driver attached to camera %d\n",
462 static void mx2_camera_remove_device(struct soc_camera_device
*icd
)
464 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
465 struct mx2_camera_dev
*pcdev
= ici
->priv
;
467 BUG_ON(icd
!= pcdev
->icd
);
469 dev_info(icd
->parent
, "Camera driver detached from camera %d\n",
472 mx2_camera_deactivate(pcdev
);
477 static void mx25_camera_frame_done(struct mx2_camera_dev
*pcdev
, int fb
,
480 struct vb2_buffer
*vb
;
481 struct mx2_buffer
*buf
;
482 struct mx2_buffer
**fb_active
= fb
== 1 ? &pcdev
->fb1_active
:
484 u32 fb_reg
= fb
== 1 ? CSIDMASA_FB1
: CSIDMASA_FB2
;
487 spin_lock_irqsave(&pcdev
->lock
, flags
);
489 if (*fb_active
== NULL
)
492 vb
= &(*fb_active
)->vb
;
493 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
494 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
496 do_gettimeofday(&vb
->v4l2_buf
.timestamp
);
497 vb
->v4l2_buf
.sequence
++;
498 vb2_buffer_done(vb
, VB2_BUF_STATE_DONE
);
500 if (list_empty(&pcdev
->capture
)) {
502 writel(0, pcdev
->base_csi
+ fb_reg
);
504 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
507 list_del(&buf
->internal
.queue
);
508 buf
->state
= MX2_STATE_ACTIVE
;
509 writel(vb2_dma_contig_plane_dma_addr(vb
, 0),
510 pcdev
->base_csi
+ fb_reg
);
516 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
519 static irqreturn_t
mx25_camera_irq(int irq_csi
, void *data
)
521 struct mx2_camera_dev
*pcdev
= data
;
522 u32 status
= readl(pcdev
->base_csi
+ CSISR
);
524 if (status
& CSISR_DMA_TSF_FB1_INT
)
525 mx25_camera_frame_done(pcdev
, 1, MX2_STATE_DONE
);
526 else if (status
& CSISR_DMA_TSF_FB2_INT
)
527 mx25_camera_frame_done(pcdev
, 2, MX2_STATE_DONE
);
529 /* FIXME: handle CSISR_RFF_OR_INT */
531 writel(status
, pcdev
->base_csi
+ CSISR
);
537 * Videobuf operations
539 static int mx2_videobuf_setup(struct vb2_queue
*vq
,
540 const struct v4l2_format
*fmt
,
541 unsigned int *count
, unsigned int *num_planes
,
542 unsigned int sizes
[], void *alloc_ctxs
[])
544 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vq
);
545 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
546 struct mx2_camera_dev
*pcdev
= ici
->priv
;
548 dev_dbg(icd
->parent
, "count=%d, size=%d\n", *count
, sizes
[0]);
550 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
554 alloc_ctxs
[0] = pcdev
->alloc_ctx
;
556 sizes
[0] = icd
->sizeimage
;
561 sizes
[0] * *count
> MAX_VIDEO_MEM
* 1024 * 1024)
562 *count
= (MAX_VIDEO_MEM
* 1024 * 1024) / sizes
[0];
569 static int mx2_videobuf_prepare(struct vb2_buffer
*vb
)
571 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
574 dev_dbg(icd
->parent
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
575 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
579 * This can be useful if you want to see if we actually fill
580 * the buffer with something
582 memset((void *)vb2_plane_vaddr(vb
, 0),
583 0xaa, vb2_get_plane_payload(vb
, 0));
586 vb2_set_plane_payload(vb
, 0, icd
->sizeimage
);
587 if (vb2_plane_vaddr(vb
, 0) &&
588 vb2_get_plane_payload(vb
, 0) > vb2_plane_size(vb
, 0)) {
599 static void mx2_videobuf_queue(struct vb2_buffer
*vb
)
601 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
602 struct soc_camera_host
*ici
=
603 to_soc_camera_host(icd
->parent
);
604 struct mx2_camera_dev
*pcdev
= ici
->priv
;
605 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
608 dev_dbg(icd
->parent
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
609 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
611 spin_lock_irqsave(&pcdev
->lock
, flags
);
613 buf
->state
= MX2_STATE_QUEUED
;
614 list_add_tail(&buf
->internal
.queue
, &pcdev
->capture
);
617 u32 csicr3
, dma_inten
= 0;
619 if (pcdev
->fb1_active
== NULL
) {
620 writel(vb2_dma_contig_plane_dma_addr(vb
, 0),
621 pcdev
->base_csi
+ CSIDMASA_FB1
);
622 pcdev
->fb1_active
= buf
;
623 dma_inten
= CSICR1_FB1_DMA_INTEN
;
624 } else if (pcdev
->fb2_active
== NULL
) {
625 writel(vb2_dma_contig_plane_dma_addr(vb
, 0),
626 pcdev
->base_csi
+ CSIDMASA_FB2
);
627 pcdev
->fb2_active
= buf
;
628 dma_inten
= CSICR1_FB2_DMA_INTEN
;
632 list_del(&buf
->internal
.queue
);
633 buf
->state
= MX2_STATE_ACTIVE
;
635 csicr3
= readl(pcdev
->base_csi
+ CSICR3
);
638 writel(csicr3
| CSICR3_DMA_REFLASH_RFF
,
639 pcdev
->base_csi
+ CSICR3
);
641 /* clear & enable interrupts */
642 writel(dma_inten
, pcdev
->base_csi
+ CSISR
);
643 pcdev
->csicr1
|= dma_inten
;
644 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
647 csicr3
|= CSICR3_DMA_REQ_EN_RFF
| CSICR3_RXFF_LEVEL(1);
648 writel(csicr3
, pcdev
->base_csi
+ CSICR3
);
652 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
655 static void mx2_videobuf_release(struct vb2_buffer
*vb
)
657 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
658 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
659 struct mx2_camera_dev
*pcdev
= ici
->priv
;
660 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
664 dev_dbg(icd
->parent
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
665 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
667 switch (buf
->state
) {
668 case MX2_STATE_ACTIVE
:
669 dev_info(icd
->parent
, "%s (active)\n", __func__
);
671 case MX2_STATE_QUEUED
:
672 dev_info(icd
->parent
, "%s (queued)\n", __func__
);
675 dev_info(icd
->parent
, "%s (unknown) %d\n", __func__
,
682 * Terminate only queued but inactive buffers. Active buffers are
683 * released when they become inactive after videobuf_waiton().
685 * FIXME: implement forced termination of active buffers for mx27 and
686 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
687 * state. This requires a specific handling for each of the these DMA
691 spin_lock_irqsave(&pcdev
->lock
, flags
);
692 if (cpu_is_mx25() && buf
->state
== MX2_STATE_ACTIVE
) {
693 if (pcdev
->fb1_active
== buf
) {
694 pcdev
->csicr1
&= ~CSICR1_FB1_DMA_INTEN
;
695 writel(0, pcdev
->base_csi
+ CSIDMASA_FB1
);
696 pcdev
->fb1_active
= NULL
;
697 } else if (pcdev
->fb2_active
== buf
) {
698 pcdev
->csicr1
&= ~CSICR1_FB2_DMA_INTEN
;
699 writel(0, pcdev
->base_csi
+ CSIDMASA_FB2
);
700 pcdev
->fb2_active
= NULL
;
702 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
704 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
707 static void mx27_camera_emma_buf_init(struct soc_camera_device
*icd
,
710 struct soc_camera_host
*ici
=
711 to_soc_camera_host(icd
->parent
);
712 struct mx2_camera_dev
*pcdev
= ici
->priv
;
713 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
715 writel((pcdev
->s_width
<< 16) | pcdev
->s_height
,
716 pcdev
->base_emma
+ PRP_SRC_FRAME_SIZE
);
717 writel(prp
->cfg
.src_pixel
,
718 pcdev
->base_emma
+ PRP_SRC_PIXEL_FORMAT_CNTL
);
719 if (prp
->cfg
.channel
== 1) {
720 writel((icd
->user_width
<< 16) | icd
->user_height
,
721 pcdev
->base_emma
+ PRP_CH1_OUT_IMAGE_SIZE
);
723 pcdev
->base_emma
+ PRP_DEST_CH1_LINE_STRIDE
);
724 writel(prp
->cfg
.ch1_pixel
,
725 pcdev
->base_emma
+ PRP_CH1_PIXEL_FORMAT_CNTL
);
726 } else { /* channel 2 */
727 writel((icd
->user_width
<< 16) | icd
->user_height
,
728 pcdev
->base_emma
+ PRP_CH2_OUT_IMAGE_SIZE
);
731 /* Enable interrupts */
732 writel(prp
->cfg
.irq_flags
, pcdev
->base_emma
+ PRP_INTR_CNTL
);
735 static void mx2_prp_resize_commit(struct mx2_camera_dev
*pcdev
)
739 for (dir
= RESIZE_DIR_H
; dir
<= RESIZE_DIR_V
; dir
++) {
740 unsigned char *s
= pcdev
->resizing
[dir
].s
;
741 int len
= pcdev
->resizing
[dir
].len
;
742 unsigned int coeff
[2] = {0, 0};
743 unsigned int valid
= 0;
749 for (i
= RESIZE_NUM_MAX
- 1; i
>= 0; i
--) {
753 coeff
[j
] = (coeff
[j
] << BC_COEF
) |
754 (s
[i
] & (SZ_COEF
- 1));
756 if (i
== 5 || i
== 15)
759 valid
= (valid
<< 1) | (s
[i
] >> BC_COEF
);
762 valid
|= PRP_RZ_VALID_TBL_LEN(len
);
764 if (pcdev
->resizing
[dir
].algo
== RESIZE_ALGO_BILINEAR
)
765 valid
|= PRP_RZ_VALID_BILINEAR
;
767 if (pcdev
->emma_prp
->cfg
.channel
== 1) {
768 if (dir
== RESIZE_DIR_H
) {
769 writel(coeff
[0], pcdev
->base_emma
+
770 PRP_CH1_RZ_HORI_COEF1
);
771 writel(coeff
[1], pcdev
->base_emma
+
772 PRP_CH1_RZ_HORI_COEF2
);
773 writel(valid
, pcdev
->base_emma
+
774 PRP_CH1_RZ_HORI_VALID
);
776 writel(coeff
[0], pcdev
->base_emma
+
777 PRP_CH1_RZ_VERT_COEF1
);
778 writel(coeff
[1], pcdev
->base_emma
+
779 PRP_CH1_RZ_VERT_COEF2
);
780 writel(valid
, pcdev
->base_emma
+
781 PRP_CH1_RZ_VERT_VALID
);
784 if (dir
== RESIZE_DIR_H
) {
785 writel(coeff
[0], pcdev
->base_emma
+
786 PRP_CH2_RZ_HORI_COEF1
);
787 writel(coeff
[1], pcdev
->base_emma
+
788 PRP_CH2_RZ_HORI_COEF2
);
789 writel(valid
, pcdev
->base_emma
+
790 PRP_CH2_RZ_HORI_VALID
);
792 writel(coeff
[0], pcdev
->base_emma
+
793 PRP_CH2_RZ_VERT_COEF1
);
794 writel(coeff
[1], pcdev
->base_emma
+
795 PRP_CH2_RZ_VERT_COEF2
);
796 writel(valid
, pcdev
->base_emma
+
797 PRP_CH2_RZ_VERT_VALID
);
803 static int mx2_start_streaming(struct vb2_queue
*q
, unsigned int count
)
805 struct soc_camera_device
*icd
= soc_camera_from_vb2q(q
);
806 struct soc_camera_host
*ici
=
807 to_soc_camera_host(icd
->parent
);
808 struct mx2_camera_dev
*pcdev
= ici
->priv
;
809 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
810 struct vb2_buffer
*vb
;
811 struct mx2_buffer
*buf
;
820 spin_lock_irqsave(&pcdev
->lock
, flags
);
822 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
824 buf
->internal
.bufnum
= 0;
826 buf
->state
= MX2_STATE_ACTIVE
;
828 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
829 mx27_update_emma_buf(pcdev
, phys
, buf
->internal
.bufnum
);
830 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
832 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
834 buf
->internal
.bufnum
= 1;
836 buf
->state
= MX2_STATE_ACTIVE
;
838 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
839 mx27_update_emma_buf(pcdev
, phys
, buf
->internal
.bufnum
);
840 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
842 bytesperline
= soc_mbus_bytes_per_line(icd
->user_width
,
843 icd
->current_fmt
->host_fmt
);
844 if (bytesperline
< 0)
848 * I didn't manage to properly enable/disable the prp
849 * on a per frame basis during running transfers,
850 * thus we allocate a buffer here and use it to
851 * discard frames when no buffer is available.
852 * Feel free to work on this ;)
854 pcdev
->discard_size
= icd
->user_height
* bytesperline
;
855 pcdev
->discard_buffer
= dma_alloc_coherent(ici
->v4l2_dev
.dev
,
856 pcdev
->discard_size
, &pcdev
->discard_buffer_dma
,
858 if (!pcdev
->discard_buffer
)
861 pcdev
->buf_discard
[0].discard
= true;
862 list_add_tail(&pcdev
->buf_discard
[0].queue
,
865 pcdev
->buf_discard
[1].discard
= true;
866 list_add_tail(&pcdev
->buf_discard
[1].queue
,
869 mx2_prp_resize_commit(pcdev
);
871 mx27_camera_emma_buf_init(icd
, bytesperline
);
873 if (prp
->cfg
.channel
== 1) {
874 writel(PRP_CNTL_CH1EN
|
880 PRP_CNTL_CH1_TSKIP(0) |
881 PRP_CNTL_IN_TSKIP(0),
882 pcdev
->base_emma
+ PRP_CNTL
);
884 writel(PRP_CNTL_CH2EN
|
889 PRP_CNTL_CH2_TSKIP(0) |
890 PRP_CNTL_IN_TSKIP(0),
891 pcdev
->base_emma
+ PRP_CNTL
);
893 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
899 static int mx2_stop_streaming(struct vb2_queue
*q
)
901 struct soc_camera_device
*icd
= soc_camera_from_vb2q(q
);
902 struct soc_camera_host
*ici
=
903 to_soc_camera_host(icd
->parent
);
904 struct mx2_camera_dev
*pcdev
= ici
->priv
;
905 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
911 spin_lock_irqsave(&pcdev
->lock
, flags
);
913 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
914 if (prp
->cfg
.channel
== 1) {
915 writel(cntl
& ~PRP_CNTL_CH1EN
,
916 pcdev
->base_emma
+ PRP_CNTL
);
918 writel(cntl
& ~PRP_CNTL_CH2EN
,
919 pcdev
->base_emma
+ PRP_CNTL
);
921 INIT_LIST_HEAD(&pcdev
->capture
);
922 INIT_LIST_HEAD(&pcdev
->active_bufs
);
923 INIT_LIST_HEAD(&pcdev
->discard
);
925 b
= pcdev
->discard_buffer
;
926 pcdev
->discard_buffer
= NULL
;
928 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
930 dma_free_coherent(ici
->v4l2_dev
.dev
,
931 pcdev
->discard_size
, b
, pcdev
->discard_buffer_dma
);
937 static struct vb2_ops mx2_videobuf_ops
= {
938 .queue_setup
= mx2_videobuf_setup
,
939 .buf_prepare
= mx2_videobuf_prepare
,
940 .buf_queue
= mx2_videobuf_queue
,
941 .buf_cleanup
= mx2_videobuf_release
,
942 .start_streaming
= mx2_start_streaming
,
943 .stop_streaming
= mx2_stop_streaming
,
946 static int mx2_camera_init_videobuf(struct vb2_queue
*q
,
947 struct soc_camera_device
*icd
)
949 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
950 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
952 q
->ops
= &mx2_videobuf_ops
;
953 q
->mem_ops
= &vb2_dma_contig_memops
;
954 q
->buf_struct_size
= sizeof(struct mx2_buffer
);
956 return vb2_queue_init(q
);
959 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
960 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
961 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
962 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
963 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
964 V4L2_MBUS_PCLK_SAMPLE_RISING | \
965 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
966 V4L2_MBUS_DATA_ACTIVE_HIGH | \
967 V4L2_MBUS_DATA_ACTIVE_LOW)
969 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev
*pcdev
)
974 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
975 writel(PRP_CNTL_SWRST
, pcdev
->base_emma
+ PRP_CNTL
);
976 while (count
++ < 100) {
977 if (!(readl(pcdev
->base_emma
+ PRP_CNTL
) & PRP_CNTL_SWRST
))
986 static int mx2_camera_set_bus_param(struct soc_camera_device
*icd
)
988 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
989 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
990 struct mx2_camera_dev
*pcdev
= ici
->priv
;
991 struct v4l2_mbus_config cfg
= {.type
= V4L2_MBUS_PARALLEL
,};
992 unsigned long common_flags
;
995 u32 csicr1
= pcdev
->csicr1
;
997 ret
= v4l2_subdev_call(sd
, video
, g_mbus_config
, &cfg
);
999 common_flags
= soc_mbus_config_compatible(&cfg
, MX2_BUS_FLAGS
);
1000 if (!common_flags
) {
1001 dev_warn(icd
->parent
,
1002 "Flags incompatible: camera 0x%x, host 0x%x\n",
1003 cfg
.flags
, MX2_BUS_FLAGS
);
1006 } else if (ret
!= -ENOIOCTLCMD
) {
1009 common_flags
= MX2_BUS_FLAGS
;
1012 if ((common_flags
& V4L2_MBUS_HSYNC_ACTIVE_HIGH
) &&
1013 (common_flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)) {
1014 if (pcdev
->platform_flags
& MX2_CAMERA_HSYNC_HIGH
)
1015 common_flags
&= ~V4L2_MBUS_HSYNC_ACTIVE_LOW
;
1017 common_flags
&= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH
;
1020 if ((common_flags
& V4L2_MBUS_PCLK_SAMPLE_RISING
) &&
1021 (common_flags
& V4L2_MBUS_PCLK_SAMPLE_FALLING
)) {
1022 if (pcdev
->platform_flags
& MX2_CAMERA_PCLK_SAMPLE_RISING
)
1023 common_flags
&= ~V4L2_MBUS_PCLK_SAMPLE_FALLING
;
1025 common_flags
&= ~V4L2_MBUS_PCLK_SAMPLE_RISING
;
1028 cfg
.flags
= common_flags
;
1029 ret
= v4l2_subdev_call(sd
, video
, s_mbus_config
, &cfg
);
1030 if (ret
< 0 && ret
!= -ENOIOCTLCMD
) {
1031 dev_dbg(icd
->parent
, "camera s_mbus_config(0x%lx) returned %d\n",
1036 csicr1
= (csicr1
& ~CSICR1_FMT_MASK
) | pcdev
->emma_prp
->cfg
.csicr1
;
1038 if (common_flags
& V4L2_MBUS_PCLK_SAMPLE_RISING
)
1039 csicr1
|= CSICR1_REDGE
;
1040 if (common_flags
& V4L2_MBUS_VSYNC_ACTIVE_HIGH
)
1041 csicr1
|= CSICR1_SOF_POL
;
1042 if (common_flags
& V4L2_MBUS_HSYNC_ACTIVE_HIGH
)
1043 csicr1
|= CSICR1_HSYNC_POL
;
1044 if (pcdev
->platform_flags
& MX2_CAMERA_EXT_VSYNC
)
1045 csicr1
|= CSICR1_EXT_VSYNC
;
1046 if (pcdev
->platform_flags
& MX2_CAMERA_CCIR
)
1047 csicr1
|= CSICR1_CCIR_EN
;
1048 if (pcdev
->platform_flags
& MX2_CAMERA_CCIR_INTERLACE
)
1049 csicr1
|= CSICR1_CCIR_MODE
;
1050 if (pcdev
->platform_flags
& MX2_CAMERA_GATED_CLOCK
)
1051 csicr1
|= CSICR1_GCLK_MODE
;
1052 if (pcdev
->platform_flags
& MX2_CAMERA_INV_DATA
)
1053 csicr1
|= CSICR1_INV_DATA
;
1055 pcdev
->csicr1
= csicr1
;
1057 bytesperline
= soc_mbus_bytes_per_line(icd
->user_width
,
1058 icd
->current_fmt
->host_fmt
);
1059 if (bytesperline
< 0)
1060 return bytesperline
;
1062 if (cpu_is_mx27()) {
1063 ret
= mx27_camera_emma_prp_reset(pcdev
);
1066 } else if (cpu_is_mx25()) {
1067 writel((bytesperline
* icd
->user_height
) >> 2,
1068 pcdev
->base_csi
+ CSIRXCNT
);
1069 writel((bytesperline
<< 16) | icd
->user_height
,
1070 pcdev
->base_csi
+ CSIIMAG_PARA
);
1073 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
1078 static int mx2_camera_set_crop(struct soc_camera_device
*icd
,
1079 struct v4l2_crop
*a
)
1081 struct v4l2_rect
*rect
= &a
->c
;
1082 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1083 struct v4l2_mbus_framefmt mf
;
1086 soc_camera_limit_side(&rect
->left
, &rect
->width
, 0, 2, 4096);
1087 soc_camera_limit_side(&rect
->top
, &rect
->height
, 0, 2, 4096);
1089 ret
= v4l2_subdev_call(sd
, video
, s_crop
, a
);
1093 /* The capture device might have changed its output */
1094 ret
= v4l2_subdev_call(sd
, video
, g_mbus_fmt
, &mf
);
1098 dev_dbg(icd
->parent
, "Sensor cropped %dx%d\n",
1099 mf
.width
, mf
.height
);
1101 icd
->user_width
= mf
.width
;
1102 icd
->user_height
= mf
.height
;
1107 static int mx2_camera_get_formats(struct soc_camera_device
*icd
,
1109 struct soc_camera_format_xlate
*xlate
)
1111 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1112 const struct soc_mbus_pixelfmt
*fmt
;
1113 struct device
*dev
= icd
->parent
;
1114 enum v4l2_mbus_pixelcode code
;
1115 int ret
, formats
= 0;
1117 ret
= v4l2_subdev_call(sd
, video
, enum_mbus_fmt
, idx
, &code
);
1119 /* no more formats */
1122 fmt
= soc_mbus_get_fmtdesc(code
);
1124 dev_err(dev
, "Invalid format code #%u: %d\n", idx
, code
);
1128 if (code
== V4L2_MBUS_FMT_YUYV8_2X8
||
1129 code
== V4L2_MBUS_FMT_UYVY8_2X8
) {
1133 * CH2 can output YUV420 which is a standard format in
1137 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8
);
1139 dev_dbg(dev
, "Providing host format %s for sensor code %d\n",
1140 xlate
->host_fmt
->name
, code
);
1145 /* Generic pass-trough */
1148 xlate
->host_fmt
= fmt
;
1155 static int mx2_emmaprp_resize(struct mx2_camera_dev
*pcdev
,
1156 struct v4l2_mbus_framefmt
*mf_in
,
1157 struct v4l2_pix_format
*pix_out
, bool apply
)
1163 for (dir
= RESIZE_DIR_H
; dir
<= RESIZE_DIR_V
; dir
++) {
1164 struct emma_prp_resize tmprsz
;
1165 unsigned char *s
= tmprsz
.s
;
1169 if (dir
== RESIZE_DIR_H
) {
1171 out
= pix_out
->width
;
1174 out
= pix_out
->height
;
1182 /* Calculate ratio */
1186 if (num
> RESIZE_NUM_MAX
)
1189 if ((num
>= 2 * den
) && (den
== 1) &&
1190 (num
< 9) && (!(num
& 0x01))) {
1194 /* Average scaling for >= 2:1 ratios */
1195 /* Support can be added for num >=9 and odd values */
1197 tmprsz
.algo
= RESIZE_ALGO_AVERAGING
;
1200 for (i
= 0; i
< (len
/ 2); i
++)
1204 for (i
= 0; i
< (len
/ 2); i
++) {
1207 for (j
= 0; j
< (len
/ 2); j
++)
1214 for (i
= (len
/ 2); i
< len
; i
++)
1215 s
[i
] = s
[len
- i
- 1];
1217 s
[len
- 1] |= SZ_COEF
;
1219 /* bilinear scaling for < 2:1 ratios */
1220 int v
; /* overflow counter */
1221 int coeff
, nxt
; /* table output */
1222 int in_pos_inc
= 2 * den
;
1224 int out_pos_inc
= 2 * num
;
1225 int init_carry
= num
- den
;
1226 int carry
= init_carry
;
1228 tmprsz
.algo
= RESIZE_ALGO_BILINEAR
;
1229 v
= den
+ in_pos_inc
;
1231 coeff
= v
- out_pos
;
1232 out_pos
+= out_pos_inc
;
1233 carry
+= out_pos_inc
;
1234 for (nxt
= 0; v
< out_pos
; nxt
++) {
1236 carry
-= in_pos_inc
;
1239 if (len
> RESIZE_NUM_MAX
)
1242 coeff
= ((coeff
<< BC_COEF
) +
1243 (in_pos_inc
>> 1)) / in_pos_inc
;
1245 if (coeff
>= (SZ_COEF
- 1))
1249 s
[len
] = (unsigned char)coeff
;
1252 for (i
= 1; i
< nxt
; i
++) {
1253 if (len
>= RESIZE_NUM_MAX
)
1258 } while (carry
!= init_carry
);
1261 if (dir
== RESIZE_DIR_H
)
1262 mf_in
->width
= pix_out
->width
;
1264 mf_in
->height
= pix_out
->height
;
1267 memcpy(&pcdev
->resizing
[dir
], &tmprsz
, sizeof(tmprsz
));
1272 static int mx2_camera_set_fmt(struct soc_camera_device
*icd
,
1273 struct v4l2_format
*f
)
1275 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
1276 struct mx2_camera_dev
*pcdev
= ici
->priv
;
1277 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1278 const struct soc_camera_format_xlate
*xlate
;
1279 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1280 struct v4l2_mbus_framefmt mf
;
1283 dev_dbg(icd
->parent
, "%s: requested params: width = %d, height = %d\n",
1284 __func__
, pix
->width
, pix
->height
);
1286 xlate
= soc_camera_xlate_by_fourcc(icd
, pix
->pixelformat
);
1288 dev_warn(icd
->parent
, "Format %x not found\n",
1293 mf
.width
= pix
->width
;
1294 mf
.height
= pix
->height
;
1295 mf
.field
= pix
->field
;
1296 mf
.colorspace
= pix
->colorspace
;
1297 mf
.code
= xlate
->code
;
1299 ret
= v4l2_subdev_call(sd
, video
, s_mbus_fmt
, &mf
);
1300 if (ret
< 0 && ret
!= -ENOIOCTLCMD
)
1303 /* Store width and height returned by the sensor for resizing */
1304 pcdev
->s_width
= mf
.width
;
1305 pcdev
->s_height
= mf
.height
;
1306 dev_dbg(icd
->parent
, "%s: sensor params: width = %d, height = %d\n",
1307 __func__
, pcdev
->s_width
, pcdev
->s_height
);
1309 pcdev
->emma_prp
= mx27_emma_prp_get_format(xlate
->code
,
1310 xlate
->host_fmt
->fourcc
);
1312 memset(pcdev
->resizing
, 0, sizeof(pcdev
->resizing
));
1313 if ((mf
.width
!= pix
->width
|| mf
.height
!= pix
->height
) &&
1314 pcdev
->emma_prp
->cfg
.in_fmt
== PRP_CNTL_DATA_IN_YUV422
) {
1315 if (mx2_emmaprp_resize(pcdev
, &mf
, pix
, true) < 0)
1316 dev_dbg(icd
->parent
, "%s: can't resize\n", __func__
);
1319 if (mf
.code
!= xlate
->code
)
1322 pix
->width
= mf
.width
;
1323 pix
->height
= mf
.height
;
1324 pix
->field
= mf
.field
;
1325 pix
->colorspace
= mf
.colorspace
;
1326 icd
->current_fmt
= xlate
;
1328 dev_dbg(icd
->parent
, "%s: returned params: width = %d, height = %d\n",
1329 __func__
, pix
->width
, pix
->height
);
1334 static int mx2_camera_try_fmt(struct soc_camera_device
*icd
,
1335 struct v4l2_format
*f
)
1337 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1338 const struct soc_camera_format_xlate
*xlate
;
1339 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1340 struct v4l2_mbus_framefmt mf
;
1341 __u32 pixfmt
= pix
->pixelformat
;
1342 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
1343 struct mx2_camera_dev
*pcdev
= ici
->priv
;
1344 unsigned int width_limit
;
1347 dev_dbg(icd
->parent
, "%s: requested params: width = %d, height = %d\n",
1348 __func__
, pix
->width
, pix
->height
);
1350 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1351 if (pixfmt
&& !xlate
) {
1352 dev_warn(icd
->parent
, "Format %x not found\n", pixfmt
);
1356 /* FIXME: implement MX27 limits */
1358 /* limit to MX25 hardware capabilities */
1359 if (cpu_is_mx25()) {
1360 if (xlate
->host_fmt
->bits_per_sample
<= 8)
1361 width_limit
= 0xffff * 4;
1363 width_limit
= 0xffff * 2;
1364 /* CSIIMAG_PARA limit */
1365 if (pix
->width
> width_limit
)
1366 pix
->width
= width_limit
;
1367 if (pix
->height
> 0xffff)
1368 pix
->height
= 0xffff;
1370 pix
->bytesperline
= soc_mbus_bytes_per_line(pix
->width
,
1372 if (pix
->bytesperline
< 0)
1373 return pix
->bytesperline
;
1374 pix
->sizeimage
= soc_mbus_image_size(xlate
->host_fmt
,
1375 pix
->bytesperline
, pix
->height
);
1376 /* Check against the CSIRXCNT limit */
1377 if (pix
->sizeimage
> 4 * 0x3ffff) {
1378 /* Adjust geometry, preserve aspect ratio */
1379 unsigned int new_height
= int_sqrt(div_u64(0x3ffffULL
*
1380 4 * pix
->height
, pix
->bytesperline
));
1381 pix
->width
= new_height
* pix
->width
/ pix
->height
;
1382 pix
->height
= new_height
;
1383 pix
->bytesperline
= soc_mbus_bytes_per_line(pix
->width
,
1385 BUG_ON(pix
->bytesperline
< 0);
1386 pix
->sizeimage
= soc_mbus_image_size(xlate
->host_fmt
,
1387 pix
->bytesperline
, pix
->height
);
1391 /* limit to sensor capabilities */
1392 mf
.width
= pix
->width
;
1393 mf
.height
= pix
->height
;
1394 mf
.field
= pix
->field
;
1395 mf
.colorspace
= pix
->colorspace
;
1396 mf
.code
= xlate
->code
;
1398 ret
= v4l2_subdev_call(sd
, video
, try_mbus_fmt
, &mf
);
1402 dev_dbg(icd
->parent
, "%s: sensor params: width = %d, height = %d\n",
1403 __func__
, pcdev
->s_width
, pcdev
->s_height
);
1405 /* If the sensor does not support image size try PrP resizing */
1406 pcdev
->emma_prp
= mx27_emma_prp_get_format(xlate
->code
,
1407 xlate
->host_fmt
->fourcc
);
1409 memset(pcdev
->resizing
, 0, sizeof(pcdev
->resizing
));
1410 if ((mf
.width
!= pix
->width
|| mf
.height
!= pix
->height
) &&
1411 pcdev
->emma_prp
->cfg
.in_fmt
== PRP_CNTL_DATA_IN_YUV422
) {
1412 if (mx2_emmaprp_resize(pcdev
, &mf
, pix
, false) < 0)
1413 dev_dbg(icd
->parent
, "%s: can't resize\n", __func__
);
1416 if (mf
.field
== V4L2_FIELD_ANY
)
1417 mf
.field
= V4L2_FIELD_NONE
;
1419 * Driver supports interlaced images provided they have
1420 * both fields so that they can be processed as if they
1423 if (mf
.field
!= V4L2_FIELD_NONE
&& !V4L2_FIELD_HAS_BOTH(mf
.field
)) {
1424 dev_err(icd
->parent
, "Field type %d unsupported.\n",
1429 pix
->width
= mf
.width
;
1430 pix
->height
= mf
.height
;
1431 pix
->field
= mf
.field
;
1432 pix
->colorspace
= mf
.colorspace
;
1434 dev_dbg(icd
->parent
, "%s: returned params: width = %d, height = %d\n",
1435 __func__
, pix
->width
, pix
->height
);
1440 static int mx2_camera_querycap(struct soc_camera_host
*ici
,
1441 struct v4l2_capability
*cap
)
1443 /* cap->name is set by the friendly caller:-> */
1444 strlcpy(cap
->card
, MX2_CAM_DRIVER_DESCRIPTION
, sizeof(cap
->card
));
1445 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
1450 static unsigned int mx2_camera_poll(struct file
*file
, poll_table
*pt
)
1452 struct soc_camera_device
*icd
= file
->private_data
;
1454 return vb2_poll(&icd
->vb2_vidq
, file
, pt
);
1457 static struct soc_camera_host_ops mx2_soc_camera_host_ops
= {
1458 .owner
= THIS_MODULE
,
1459 .add
= mx2_camera_add_device
,
1460 .remove
= mx2_camera_remove_device
,
1461 .set_fmt
= mx2_camera_set_fmt
,
1462 .set_crop
= mx2_camera_set_crop
,
1463 .get_formats
= mx2_camera_get_formats
,
1464 .try_fmt
= mx2_camera_try_fmt
,
1465 .init_videobuf2
= mx2_camera_init_videobuf
,
1466 .poll
= mx2_camera_poll
,
1467 .querycap
= mx2_camera_querycap
,
1468 .set_bus_param
= mx2_camera_set_bus_param
,
1471 static void mx27_camera_frame_done_emma(struct mx2_camera_dev
*pcdev
,
1472 int bufnum
, bool err
)
1475 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
1477 struct mx2_buf_internal
*ibuf
;
1478 struct mx2_buffer
*buf
;
1479 struct vb2_buffer
*vb
;
1482 ibuf
= list_first_entry(&pcdev
->active_bufs
, struct mx2_buf_internal
,
1485 BUG_ON(ibuf
->bufnum
!= bufnum
);
1487 if (ibuf
->discard
) {
1489 * Discard buffer must not be returned to user space.
1490 * Just return it to the discard queue.
1492 list_move_tail(pcdev
->active_bufs
.next
, &pcdev
->discard
);
1494 buf
= mx2_ibuf_to_buf(ibuf
);
1498 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
1499 if (prp
->cfg
.channel
== 1) {
1500 if (readl(pcdev
->base_emma
+ PRP_DEST_RGB1_PTR
+
1501 4 * bufnum
) != phys
) {
1502 dev_err(pcdev
->dev
, "%lx != %x\n", phys
,
1503 readl(pcdev
->base_emma
+
1504 PRP_DEST_RGB1_PTR
+ 4 * bufnum
));
1507 if (readl(pcdev
->base_emma
+ PRP_DEST_Y_PTR
-
1508 0x14 * bufnum
) != phys
) {
1509 dev_err(pcdev
->dev
, "%lx != %x\n", phys
,
1510 readl(pcdev
->base_emma
+
1511 PRP_DEST_Y_PTR
- 0x14 * bufnum
));
1515 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%p %lu\n", __func__
, vb
,
1516 vb2_plane_vaddr(vb
, 0),
1517 vb2_get_plane_payload(vb
, 0));
1519 list_del_init(&buf
->internal
.queue
);
1520 do_gettimeofday(&vb
->v4l2_buf
.timestamp
);
1521 vb
->v4l2_buf
.sequence
= pcdev
->frame_count
;
1523 vb2_buffer_done(vb
, VB2_BUF_STATE_ERROR
);
1525 vb2_buffer_done(vb
, VB2_BUF_STATE_DONE
);
1528 pcdev
->frame_count
++;
1530 if (list_empty(&pcdev
->capture
)) {
1531 if (list_empty(&pcdev
->discard
)) {
1532 dev_warn(pcdev
->dev
, "%s: trying to access empty discard list\n",
1537 ibuf
= list_first_entry(&pcdev
->discard
,
1538 struct mx2_buf_internal
, queue
);
1539 ibuf
->bufnum
= bufnum
;
1541 list_move_tail(pcdev
->discard
.next
, &pcdev
->active_bufs
);
1542 mx27_update_emma_buf(pcdev
, pcdev
->discard_buffer_dma
, bufnum
);
1546 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
1549 buf
->internal
.bufnum
= bufnum
;
1551 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
1554 buf
->state
= MX2_STATE_ACTIVE
;
1556 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
1557 mx27_update_emma_buf(pcdev
, phys
, bufnum
);
1560 static irqreturn_t
mx27_camera_emma_irq(int irq_emma
, void *data
)
1562 struct mx2_camera_dev
*pcdev
= data
;
1563 unsigned int status
= readl(pcdev
->base_emma
+ PRP_INTRSTATUS
);
1564 struct mx2_buf_internal
*ibuf
;
1566 spin_lock(&pcdev
->lock
);
1568 if (list_empty(&pcdev
->active_bufs
)) {
1569 dev_warn(pcdev
->dev
, "%s: called while active list is empty\n",
1573 spin_unlock(&pcdev
->lock
);
1578 if (status
& (1 << 7)) { /* overflow */
1579 u32 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
1580 writel(cntl
& ~(PRP_CNTL_CH1EN
| PRP_CNTL_CH2EN
),
1581 pcdev
->base_emma
+ PRP_CNTL
);
1582 writel(cntl
, pcdev
->base_emma
+ PRP_CNTL
);
1584 ibuf
= list_first_entry(&pcdev
->active_bufs
,
1585 struct mx2_buf_internal
, queue
);
1586 mx27_camera_frame_done_emma(pcdev
,
1587 ibuf
->bufnum
, true);
1589 status
&= ~(1 << 7);
1590 } else if (((status
& (3 << 5)) == (3 << 5)) ||
1591 ((status
& (3 << 3)) == (3 << 3))) {
1593 * Both buffers have triggered, process the one we're expecting
1596 ibuf
= list_first_entry(&pcdev
->active_bufs
,
1597 struct mx2_buf_internal
, queue
);
1598 mx27_camera_frame_done_emma(pcdev
, ibuf
->bufnum
, false);
1599 status
&= ~(1 << (6 - ibuf
->bufnum
)); /* mark processed */
1600 } else if ((status
& (1 << 6)) || (status
& (1 << 4))) {
1601 mx27_camera_frame_done_emma(pcdev
, 0, false);
1602 } else if ((status
& (1 << 5)) || (status
& (1 << 3))) {
1603 mx27_camera_frame_done_emma(pcdev
, 1, false);
1606 spin_unlock(&pcdev
->lock
);
1607 writel(status
, pcdev
->base_emma
+ PRP_INTRSTATUS
);
1612 static int __devinit
mx27_camera_emma_init(struct mx2_camera_dev
*pcdev
)
1614 struct resource
*res_emma
= pcdev
->res_emma
;
1617 if (!request_mem_region(res_emma
->start
, resource_size(res_emma
),
1618 MX2_CAM_DRV_NAME
)) {
1623 pcdev
->base_emma
= ioremap(res_emma
->start
, resource_size(res_emma
));
1624 if (!pcdev
->base_emma
) {
1629 err
= request_irq(pcdev
->irq_emma
, mx27_camera_emma_irq
, 0,
1630 MX2_CAM_DRV_NAME
, pcdev
);
1632 dev_err(pcdev
->dev
, "Camera EMMA interrupt register failed \n");
1636 pcdev
->clk_emma
= clk_get(NULL
, "emma");
1637 if (IS_ERR(pcdev
->clk_emma
)) {
1638 err
= PTR_ERR(pcdev
->clk_emma
);
1642 clk_enable(pcdev
->clk_emma
);
1644 err
= mx27_camera_emma_prp_reset(pcdev
);
1646 goto exit_clk_emma_put
;
1651 clk_disable(pcdev
->clk_emma
);
1652 clk_put(pcdev
->clk_emma
);
1654 free_irq(pcdev
->irq_emma
, pcdev
);
1656 iounmap(pcdev
->base_emma
);
1658 release_mem_region(res_emma
->start
, resource_size(res_emma
));
1663 static int __devinit
mx2_camera_probe(struct platform_device
*pdev
)
1665 struct mx2_camera_dev
*pcdev
;
1666 struct resource
*res_csi
, *res_emma
;
1667 void __iomem
*base_csi
;
1668 int irq_csi
, irq_emma
;
1671 dev_dbg(&pdev
->dev
, "initialising\n");
1673 res_csi
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1674 irq_csi
= platform_get_irq(pdev
, 0);
1675 if (res_csi
== NULL
|| irq_csi
< 0) {
1676 dev_err(&pdev
->dev
, "Missing platform resources data\n");
1681 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1683 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1688 pcdev
->clk_csi
= clk_get(&pdev
->dev
, NULL
);
1689 if (IS_ERR(pcdev
->clk_csi
)) {
1690 dev_err(&pdev
->dev
, "Could not get csi clock\n");
1691 err
= PTR_ERR(pcdev
->clk_csi
);
1695 pcdev
->res_csi
= res_csi
;
1696 pcdev
->pdata
= pdev
->dev
.platform_data
;
1700 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1702 rate
= clk_round_rate(pcdev
->clk_csi
, pcdev
->pdata
->clk
* 2);
1707 err
= clk_set_rate(pcdev
->clk_csi
, rate
);
1712 INIT_LIST_HEAD(&pcdev
->capture
);
1713 INIT_LIST_HEAD(&pcdev
->active_bufs
);
1714 INIT_LIST_HEAD(&pcdev
->discard
);
1715 spin_lock_init(&pcdev
->lock
);
1718 * Request the regions.
1720 if (!request_mem_region(res_csi
->start
, resource_size(res_csi
),
1721 MX2_CAM_DRV_NAME
)) {
1726 base_csi
= ioremap(res_csi
->start
, resource_size(res_csi
));
1731 pcdev
->irq_csi
= irq_csi
;
1732 pcdev
->base_csi
= base_csi
;
1733 pcdev
->base_dma
= res_csi
->start
;
1734 pcdev
->dev
= &pdev
->dev
;
1736 if (cpu_is_mx25()) {
1737 err
= request_irq(pcdev
->irq_csi
, mx25_camera_irq
, 0,
1738 MX2_CAM_DRV_NAME
, pcdev
);
1740 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1745 if (cpu_is_mx27()) {
1747 res_emma
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1748 irq_emma
= platform_get_irq(pdev
, 1);
1750 if (!res_emma
|| !irq_emma
) {
1751 dev_err(&pdev
->dev
, "no EMMA resources\n");
1755 pcdev
->res_emma
= res_emma
;
1756 pcdev
->irq_emma
= irq_emma
;
1757 if (mx27_camera_emma_init(pcdev
))
1761 pcdev
->soc_host
.drv_name
= MX2_CAM_DRV_NAME
,
1762 pcdev
->soc_host
.ops
= &mx2_soc_camera_host_ops
,
1763 pcdev
->soc_host
.priv
= pcdev
;
1764 pcdev
->soc_host
.v4l2_dev
.dev
= &pdev
->dev
;
1765 pcdev
->soc_host
.nr
= pdev
->id
;
1767 pcdev
->soc_host
.capabilities
= SOCAM_HOST_CAP_STRIDE
;
1769 pcdev
->alloc_ctx
= vb2_dma_contig_init_ctx(&pdev
->dev
);
1770 if (IS_ERR(pcdev
->alloc_ctx
)) {
1771 err
= PTR_ERR(pcdev
->alloc_ctx
);
1774 err
= soc_camera_host_register(&pcdev
->soc_host
);
1776 goto exit_free_emma
;
1778 dev_info(&pdev
->dev
, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1779 clk_get_rate(pcdev
->clk_csi
));
1784 vb2_dma_contig_cleanup_ctx(pcdev
->alloc_ctx
);
1786 if (cpu_is_mx27()) {
1787 free_irq(pcdev
->irq_emma
, pcdev
);
1788 clk_disable(pcdev
->clk_emma
);
1789 clk_put(pcdev
->clk_emma
);
1790 iounmap(pcdev
->base_emma
);
1791 release_mem_region(pcdev
->res_emma
->start
, resource_size(pcdev
->res_emma
));
1795 free_irq(pcdev
->irq_csi
, pcdev
);
1799 release_mem_region(res_csi
->start
, resource_size(res_csi
));
1801 clk_put(pcdev
->clk_csi
);
1808 static int __devexit
mx2_camera_remove(struct platform_device
*pdev
)
1810 struct soc_camera_host
*soc_host
= to_soc_camera_host(&pdev
->dev
);
1811 struct mx2_camera_dev
*pcdev
= container_of(soc_host
,
1812 struct mx2_camera_dev
, soc_host
);
1813 struct resource
*res
;
1815 clk_put(pcdev
->clk_csi
);
1817 free_irq(pcdev
->irq_csi
, pcdev
);
1819 free_irq(pcdev
->irq_emma
, pcdev
);
1821 soc_camera_host_unregister(&pcdev
->soc_host
);
1823 vb2_dma_contig_cleanup_ctx(pcdev
->alloc_ctx
);
1825 iounmap(pcdev
->base_csi
);
1827 if (cpu_is_mx27()) {
1828 clk_disable(pcdev
->clk_emma
);
1829 clk_put(pcdev
->clk_emma
);
1830 iounmap(pcdev
->base_emma
);
1831 res
= pcdev
->res_emma
;
1832 release_mem_region(res
->start
, resource_size(res
));
1835 res
= pcdev
->res_csi
;
1836 release_mem_region(res
->start
, resource_size(res
));
1840 dev_info(&pdev
->dev
, "MX2 Camera driver unloaded\n");
1845 static struct platform_driver mx2_camera_driver
= {
1847 .name
= MX2_CAM_DRV_NAME
,
1849 .remove
= __devexit_p(mx2_camera_remove
),
1853 static int __init
mx2_camera_init(void)
1855 return platform_driver_probe(&mx2_camera_driver
, &mx2_camera_probe
);
1858 static void __exit
mx2_camera_exit(void)
1860 return platform_driver_unregister(&mx2_camera_driver
);
1863 module_init(mx2_camera_init
);
1864 module_exit(mx2_camera_exit
);
1866 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1867 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1868 MODULE_LICENSE("GPL");
1869 MODULE_VERSION(MX2_CAM_VERSION
);