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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / drivers / media / video / mx2_camera.c
1 /*
2 * V4L2 Driver for i.MX27/i.MX25 camera host
3 *
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
26 #include <linux/mm.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/mutex.h>
32 #include <linux/clk.h>
33
34 #include <media/v4l2-common.h>
35 #include <media/v4l2-dev.h>
36 #include <media/videobuf2-core.h>
37 #include <media/videobuf2-dma-contig.h>
38 #include <media/soc_camera.h>
39 #include <media/soc_mediabus.h>
40
41 #include <linux/videodev2.h>
42
43 #include <mach/mx2_cam.h>
44 #include <mach/hardware.h>
45
46 #include <asm/dma.h>
47
48 #define MX2_CAM_DRV_NAME "mx2-camera"
49 #define MX2_CAM_VERSION "0.0.6"
50 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51
52 /* reset values */
53 #define CSICR1_RESET_VAL 0x40000800
54 #define CSICR2_RESET_VAL 0x0
55 #define CSICR3_RESET_VAL 0x0
56
57 /* csi control reg 1 */
58 #define CSICR1_SWAP16_EN (1 << 31)
59 #define CSICR1_EXT_VSYNC (1 << 30)
60 #define CSICR1_EOF_INTEN (1 << 29)
61 #define CSICR1_PRP_IF_EN (1 << 28)
62 #define CSICR1_CCIR_MODE (1 << 27)
63 #define CSICR1_COF_INTEN (1 << 26)
64 #define CSICR1_SF_OR_INTEN (1 << 25)
65 #define CSICR1_RF_OR_INTEN (1 << 24)
66 #define CSICR1_STATFF_LEVEL (3 << 22)
67 #define CSICR1_STATFF_INTEN (1 << 21)
68 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
69 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
70 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
71 #define CSICR1_RXFF_INTEN (1 << 18)
72 #define CSICR1_SOF_POL (1 << 17)
73 #define CSICR1_SOF_INTEN (1 << 16)
74 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
75 #define CSICR1_HSYNC_POL (1 << 11)
76 #define CSICR1_CCIR_EN (1 << 10)
77 #define CSICR1_MCLKEN (1 << 9)
78 #define CSICR1_FCC (1 << 8)
79 #define CSICR1_PACK_DIR (1 << 7)
80 #define CSICR1_CLR_STATFIFO (1 << 6)
81 #define CSICR1_CLR_RXFIFO (1 << 5)
82 #define CSICR1_GCLK_MODE (1 << 4)
83 #define CSICR1_INV_DATA (1 << 3)
84 #define CSICR1_INV_PCLK (1 << 2)
85 #define CSICR1_REDGE (1 << 1)
86
87 #define SHIFT_STATFF_LEVEL 22
88 #define SHIFT_RXFF_LEVEL 19
89 #define SHIFT_MCLKDIV 12
90
91 /* control reg 3 */
92 #define CSICR3_FRMCNT (0xFFFF << 16)
93 #define CSICR3_FRMCNT_RST (1 << 15)
94 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
95 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
96 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
97 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
98 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
99 #define CSICR3_CSI_SUP (1 << 3)
100 #define CSICR3_ZERO_PACK_EN (1 << 2)
101 #define CSICR3_ECC_INT_EN (1 << 1)
102 #define CSICR3_ECC_AUTO_EN (1 << 0)
103
104 #define SHIFT_FRMCNT 16
105
106 /* csi status reg */
107 #define CSISR_SFF_OR_INT (1 << 25)
108 #define CSISR_RFF_OR_INT (1 << 24)
109 #define CSISR_STATFF_INT (1 << 21)
110 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
111 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
112 #define CSISR_RXFF_INT (1 << 18)
113 #define CSISR_EOF_INT (1 << 17)
114 #define CSISR_SOF_INT (1 << 16)
115 #define CSISR_F2_INT (1 << 15)
116 #define CSISR_F1_INT (1 << 14)
117 #define CSISR_COF_INT (1 << 13)
118 #define CSISR_ECC_INT (1 << 1)
119 #define CSISR_DRDY (1 << 0)
120
121 #define CSICR1 0x00
122 #define CSICR2 0x04
123 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
124 #define CSISTATFIFO 0x0c
125 #define CSIRFIFO 0x10
126 #define CSIRXCNT 0x14
127 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
128 #define CSIDMASA_STATFIFO 0x20
129 #define CSIDMATA_STATFIFO 0x24
130 #define CSIDMASA_FB1 0x28
131 #define CSIDMASA_FB2 0x2c
132 #define CSIFBUF_PARA 0x30
133 #define CSIIMAG_PARA 0x34
134
135 /* EMMA PrP */
136 #define PRP_CNTL 0x00
137 #define PRP_INTR_CNTL 0x04
138 #define PRP_INTRSTATUS 0x08
139 #define PRP_SOURCE_Y_PTR 0x0c
140 #define PRP_SOURCE_CB_PTR 0x10
141 #define PRP_SOURCE_CR_PTR 0x14
142 #define PRP_DEST_RGB1_PTR 0x18
143 #define PRP_DEST_RGB2_PTR 0x1c
144 #define PRP_DEST_Y_PTR 0x20
145 #define PRP_DEST_CB_PTR 0x24
146 #define PRP_DEST_CR_PTR 0x28
147 #define PRP_SRC_FRAME_SIZE 0x2c
148 #define PRP_DEST_CH1_LINE_STRIDE 0x30
149 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
150 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
151 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
152 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
153 #define PRP_SRC_LINE_STRIDE 0x44
154 #define PRP_CSC_COEF_012 0x48
155 #define PRP_CSC_COEF_345 0x4c
156 #define PRP_CSC_COEF_678 0x50
157 #define PRP_CH1_RZ_HORI_COEF1 0x54
158 #define PRP_CH1_RZ_HORI_COEF2 0x58
159 #define PRP_CH1_RZ_HORI_VALID 0x5c
160 #define PRP_CH1_RZ_VERT_COEF1 0x60
161 #define PRP_CH1_RZ_VERT_COEF2 0x64
162 #define PRP_CH1_RZ_VERT_VALID 0x68
163 #define PRP_CH2_RZ_HORI_COEF1 0x6c
164 #define PRP_CH2_RZ_HORI_COEF2 0x70
165 #define PRP_CH2_RZ_HORI_VALID 0x74
166 #define PRP_CH2_RZ_VERT_COEF1 0x78
167 #define PRP_CH2_RZ_VERT_COEF2 0x7c
168 #define PRP_CH2_RZ_VERT_VALID 0x80
169
170 #define PRP_CNTL_CH1EN (1 << 0)
171 #define PRP_CNTL_CH2EN (1 << 1)
172 #define PRP_CNTL_CSIEN (1 << 2)
173 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
174 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
175 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
176 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
177 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
178 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
179 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
180 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
181 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
182 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
183 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
184 #define PRP_CNTL_CH1_LEN (1 << 9)
185 #define PRP_CNTL_CH2_LEN (1 << 10)
186 #define PRP_CNTL_SKIP_FRAME (1 << 11)
187 #define PRP_CNTL_SWRST (1 << 12)
188 #define PRP_CNTL_CLKEN (1 << 13)
189 #define PRP_CNTL_WEN (1 << 14)
190 #define PRP_CNTL_CH1BYP (1 << 15)
191 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
192 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
193 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
194 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
195 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
196 #define PRP_CNTL_CH2B1EN (1 << 29)
197 #define PRP_CNTL_CH2B2EN (1 << 30)
198 #define PRP_CNTL_CH2FEN (1 << 31)
199
200 /* IRQ Enable and status register */
201 #define PRP_INTR_RDERR (1 << 0)
202 #define PRP_INTR_CH1WERR (1 << 1)
203 #define PRP_INTR_CH2WERR (1 << 2)
204 #define PRP_INTR_CH1FC (1 << 3)
205 #define PRP_INTR_CH2FC (1 << 5)
206 #define PRP_INTR_LBOVF (1 << 7)
207 #define PRP_INTR_CH2OVF (1 << 8)
208
209 /* Resizing registers */
210 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
211 #define PRP_RZ_VALID_BILINEAR (1 << 31)
212
213 #define MAX_VIDEO_MEM 16
214
215 #define RESIZE_NUM_MIN 1
216 #define RESIZE_NUM_MAX 20
217 #define BC_COEF 3
218 #define SZ_COEF (1 << BC_COEF)
219
220 #define RESIZE_DIR_H 0
221 #define RESIZE_DIR_V 1
222
223 #define RESIZE_ALGO_BILINEAR 0
224 #define RESIZE_ALGO_AVERAGING 1
225
226 struct mx2_prp_cfg {
227 int channel;
228 u32 in_fmt;
229 u32 out_fmt;
230 u32 src_pixel;
231 u32 ch1_pixel;
232 u32 irq_flags;
233 };
234
235 /* prp resizing parameters */
236 struct emma_prp_resize {
237 int algo; /* type of algorithm used */
238 int len; /* number of coefficients */
239 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
240 };
241
242 /* prp configuration for a client-host fmt pair */
243 struct mx2_fmt_cfg {
244 enum v4l2_mbus_pixelcode in_fmt;
245 u32 out_fmt;
246 struct mx2_prp_cfg cfg;
247 };
248
249 enum mx2_buffer_state {
250 MX2_STATE_QUEUED,
251 MX2_STATE_ACTIVE,
252 MX2_STATE_DONE,
253 };
254
255 struct mx2_buf_internal {
256 struct list_head queue;
257 int bufnum;
258 bool discard;
259 };
260
261 /* buffer for one video frame */
262 struct mx2_buffer {
263 /* common v4l buffer stuff -- must be first */
264 struct vb2_buffer vb;
265 enum mx2_buffer_state state;
266 struct mx2_buf_internal internal;
267 };
268
269 struct mx2_camera_dev {
270 struct device *dev;
271 struct soc_camera_host soc_host;
272 struct soc_camera_device *icd;
273 struct clk *clk_csi, *clk_emma;
274
275 unsigned int irq_csi, irq_emma;
276 void __iomem *base_csi, *base_emma;
277 unsigned long base_dma;
278
279 struct mx2_camera_platform_data *pdata;
280 struct resource *res_csi, *res_emma;
281 unsigned long platform_flags;
282
283 struct list_head capture;
284 struct list_head active_bufs;
285 struct list_head discard;
286
287 spinlock_t lock;
288
289 int dma;
290 struct mx2_buffer *active;
291 struct mx2_buffer *fb1_active;
292 struct mx2_buffer *fb2_active;
293
294 u32 csicr1;
295
296 struct mx2_buf_internal buf_discard[2];
297 void *discard_buffer;
298 dma_addr_t discard_buffer_dma;
299 size_t discard_size;
300 struct mx2_fmt_cfg *emma_prp;
301 struct emma_prp_resize resizing[2];
302 unsigned int s_width, s_height;
303 u32 frame_count;
304 struct vb2_alloc_ctx *alloc_ctx;
305 };
306
307 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
308 {
309 return container_of(int_buf, struct mx2_buffer, internal);
310 }
311
312 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
313 /*
314 * This is a generic configuration which is valid for most
315 * prp input-output format combinations.
316 * We set the incomming and outgoing pixelformat to a
317 * 16 Bit wide format and adjust the bytesperline
318 * accordingly. With this configuration the inputdata
319 * will not be changed by the emma and could be any type
320 * of 16 Bit Pixelformat.
321 */
322 {
323 .in_fmt = 0,
324 .out_fmt = 0,
325 .cfg = {
326 .channel = 1,
327 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
328 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
329 .src_pixel = 0x2ca00565, /* RGB565 */
330 .ch1_pixel = 0x2ca00565, /* RGB565 */
331 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
332 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
333 }
334 },
335 {
336 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
337 .out_fmt = V4L2_PIX_FMT_YUV420,
338 .cfg = {
339 .channel = 2,
340 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
341 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
342 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
343 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
344 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
345 PRP_INTR_CH2OVF,
346 }
347 },
348 {
349 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
350 .out_fmt = V4L2_PIX_FMT_YUV420,
351 .cfg = {
352 .channel = 2,
353 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
354 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
355 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
356 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
357 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
358 PRP_INTR_CH2OVF,
359 }
360 },
361 };
362
363 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
364 enum v4l2_mbus_pixelcode in_fmt,
365 u32 out_fmt)
366 {
367 int i;
368
369 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
370 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
371 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
372 return &mx27_emma_prp_table[i];
373 }
374 /* If no match return the most generic configuration */
375 return &mx27_emma_prp_table[0];
376 };
377
378 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
379 unsigned long phys, int bufnum)
380 {
381 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
382
383 if (prp->cfg.channel == 1) {
384 writel(phys, pcdev->base_emma +
385 PRP_DEST_RGB1_PTR + 4 * bufnum);
386 } else {
387 writel(phys, pcdev->base_emma +
388 PRP_DEST_Y_PTR - 0x14 * bufnum);
389 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
390 u32 imgsize = pcdev->icd->user_height *
391 pcdev->icd->user_width;
392
393 writel(phys + imgsize, pcdev->base_emma +
394 PRP_DEST_CB_PTR - 0x14 * bufnum);
395 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
396 PRP_DEST_CR_PTR - 0x14 * bufnum);
397 }
398 }
399 }
400
401 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
402 {
403 unsigned long flags;
404
405 clk_disable(pcdev->clk_csi);
406 writel(0, pcdev->base_csi + CSICR1);
407 if (cpu_is_mx27()) {
408 writel(0, pcdev->base_emma + PRP_CNTL);
409 } else if (cpu_is_mx25()) {
410 spin_lock_irqsave(&pcdev->lock, flags);
411 pcdev->fb1_active = NULL;
412 pcdev->fb2_active = NULL;
413 writel(0, pcdev->base_csi + CSIDMASA_FB1);
414 writel(0, pcdev->base_csi + CSIDMASA_FB2);
415 spin_unlock_irqrestore(&pcdev->lock, flags);
416 }
417 }
418
419 /*
420 * The following two functions absolutely depend on the fact, that
421 * there can be only one camera on mx2 camera sensor interface
422 */
423 static int mx2_camera_add_device(struct soc_camera_device *icd)
424 {
425 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
426 struct mx2_camera_dev *pcdev = ici->priv;
427 int ret;
428 u32 csicr1;
429
430 if (pcdev->icd)
431 return -EBUSY;
432
433 ret = clk_enable(pcdev->clk_csi);
434 if (ret < 0)
435 return ret;
436
437 csicr1 = CSICR1_MCLKEN;
438
439 if (cpu_is_mx27()) {
440 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
441 CSICR1_RXFF_LEVEL(0);
442 } else if (cpu_is_mx27())
443 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
444
445 pcdev->csicr1 = csicr1;
446 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
447
448 pcdev->icd = icd;
449 pcdev->frame_count = 0;
450
451 dev_info(icd->parent, "Camera driver attached to camera %d\n",
452 icd->devnum);
453
454 return 0;
455 }
456
457 static void mx2_camera_remove_device(struct soc_camera_device *icd)
458 {
459 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
460 struct mx2_camera_dev *pcdev = ici->priv;
461
462 BUG_ON(icd != pcdev->icd);
463
464 dev_info(icd->parent, "Camera driver detached from camera %d\n",
465 icd->devnum);
466
467 mx2_camera_deactivate(pcdev);
468
469 pcdev->icd = NULL;
470 }
471
472 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
473 int state)
474 {
475 struct vb2_buffer *vb;
476 struct mx2_buffer *buf;
477 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
478 &pcdev->fb2_active;
479 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
480 unsigned long flags;
481
482 spin_lock_irqsave(&pcdev->lock, flags);
483
484 if (*fb_active == NULL)
485 goto out;
486
487 vb = &(*fb_active)->vb;
488 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
489 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
490
491 do_gettimeofday(&vb->v4l2_buf.timestamp);
492 vb->v4l2_buf.sequence++;
493 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
494
495 if (list_empty(&pcdev->capture)) {
496 buf = NULL;
497 writel(0, pcdev->base_csi + fb_reg);
498 } else {
499 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
500 internal.queue);
501 vb = &buf->vb;
502 list_del(&buf->internal.queue);
503 buf->state = MX2_STATE_ACTIVE;
504 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
505 pcdev->base_csi + fb_reg);
506 }
507
508 *fb_active = buf;
509
510 out:
511 spin_unlock_irqrestore(&pcdev->lock, flags);
512 }
513
514 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
515 {
516 struct mx2_camera_dev *pcdev = data;
517 u32 status = readl(pcdev->base_csi + CSISR);
518
519 if (status & CSISR_DMA_TSF_FB1_INT)
520 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
521 else if (status & CSISR_DMA_TSF_FB2_INT)
522 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
523
524 /* FIXME: handle CSISR_RFF_OR_INT */
525
526 writel(status, pcdev->base_csi + CSISR);
527
528 return IRQ_HANDLED;
529 }
530
531 /*
532 * Videobuf operations
533 */
534 static int mx2_videobuf_setup(struct vb2_queue *vq,
535 const struct v4l2_format *fmt,
536 unsigned int *count, unsigned int *num_planes,
537 unsigned int sizes[], void *alloc_ctxs[])
538 {
539 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
540 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
541 struct mx2_camera_dev *pcdev = ici->priv;
542
543 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
544
545 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
546 if (fmt != NULL)
547 return -ENOTTY;
548
549 alloc_ctxs[0] = pcdev->alloc_ctx;
550
551 sizes[0] = icd->sizeimage;
552
553 if (0 == *count)
554 *count = 32;
555 if (!*num_planes &&
556 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
557 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
558
559 *num_planes = 1;
560
561 return 0;
562 }
563
564 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
565 {
566 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
567 int ret = 0;
568
569 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
570 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
571
572 #ifdef DEBUG
573 /*
574 * This can be useful if you want to see if we actually fill
575 * the buffer with something
576 */
577 memset((void *)vb2_plane_vaddr(vb, 0),
578 0xaa, vb2_get_plane_payload(vb, 0));
579 #endif
580
581 vb2_set_plane_payload(vb, 0, icd->sizeimage);
582 if (vb2_plane_vaddr(vb, 0) &&
583 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
584 ret = -EINVAL;
585 goto out;
586 }
587
588 return 0;
589
590 out:
591 return ret;
592 }
593
594 static void mx2_videobuf_queue(struct vb2_buffer *vb)
595 {
596 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
597 struct soc_camera_host *ici =
598 to_soc_camera_host(icd->parent);
599 struct mx2_camera_dev *pcdev = ici->priv;
600 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
601 unsigned long flags;
602
603 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
604 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
605
606 spin_lock_irqsave(&pcdev->lock, flags);
607
608 buf->state = MX2_STATE_QUEUED;
609 list_add_tail(&buf->internal.queue, &pcdev->capture);
610
611 if (cpu_is_mx25()) {
612 u32 csicr3, dma_inten = 0;
613
614 if (pcdev->fb1_active == NULL) {
615 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
616 pcdev->base_csi + CSIDMASA_FB1);
617 pcdev->fb1_active = buf;
618 dma_inten = CSICR1_FB1_DMA_INTEN;
619 } else if (pcdev->fb2_active == NULL) {
620 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
621 pcdev->base_csi + CSIDMASA_FB2);
622 pcdev->fb2_active = buf;
623 dma_inten = CSICR1_FB2_DMA_INTEN;
624 }
625
626 if (dma_inten) {
627 list_del(&buf->internal.queue);
628 buf->state = MX2_STATE_ACTIVE;
629
630 csicr3 = readl(pcdev->base_csi + CSICR3);
631
632 /* Reflash DMA */
633 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
634 pcdev->base_csi + CSICR3);
635
636 /* clear & enable interrupts */
637 writel(dma_inten, pcdev->base_csi + CSISR);
638 pcdev->csicr1 |= dma_inten;
639 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
640
641 /* enable DMA */
642 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
643 writel(csicr3, pcdev->base_csi + CSICR3);
644 }
645 }
646
647 spin_unlock_irqrestore(&pcdev->lock, flags);
648 }
649
650 static void mx2_videobuf_release(struct vb2_buffer *vb)
651 {
652 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
653 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
654 struct mx2_camera_dev *pcdev = ici->priv;
655 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
656 unsigned long flags;
657
658 #ifdef DEBUG
659 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
660 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
661
662 switch (buf->state) {
663 case MX2_STATE_ACTIVE:
664 dev_info(icd->parent, "%s (active)\n", __func__);
665 break;
666 case MX2_STATE_QUEUED:
667 dev_info(icd->parent, "%s (queued)\n", __func__);
668 break;
669 default:
670 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
671 buf->state);
672 break;
673 }
674 #endif
675
676 /*
677 * Terminate only queued but inactive buffers. Active buffers are
678 * released when they become inactive after videobuf_waiton().
679 *
680 * FIXME: implement forced termination of active buffers for mx27 and
681 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
682 * state. This requires a specific handling for each of the these DMA
683 * types.
684 */
685
686 spin_lock_irqsave(&pcdev->lock, flags);
687 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
688 if (pcdev->fb1_active == buf) {
689 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
690 writel(0, pcdev->base_csi + CSIDMASA_FB1);
691 pcdev->fb1_active = NULL;
692 } else if (pcdev->fb2_active == buf) {
693 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
694 writel(0, pcdev->base_csi + CSIDMASA_FB2);
695 pcdev->fb2_active = NULL;
696 }
697 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
698 }
699 spin_unlock_irqrestore(&pcdev->lock, flags);
700 }
701
702 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
703 int bytesperline)
704 {
705 struct soc_camera_host *ici =
706 to_soc_camera_host(icd->parent);
707 struct mx2_camera_dev *pcdev = ici->priv;
708 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
709
710 writel((pcdev->s_width << 16) | pcdev->s_height,
711 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
712 writel(prp->cfg.src_pixel,
713 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
714 if (prp->cfg.channel == 1) {
715 writel((icd->user_width << 16) | icd->user_height,
716 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
717 writel(bytesperline,
718 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
719 writel(prp->cfg.ch1_pixel,
720 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
721 } else { /* channel 2 */
722 writel((icd->user_width << 16) | icd->user_height,
723 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
724 }
725
726 /* Enable interrupts */
727 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
728 }
729
730 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
731 {
732 int dir;
733
734 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
735 unsigned char *s = pcdev->resizing[dir].s;
736 int len = pcdev->resizing[dir].len;
737 unsigned int coeff[2] = {0, 0};
738 unsigned int valid = 0;
739 int i;
740
741 if (len == 0)
742 continue;
743
744 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
745 int j;
746
747 j = i > 9 ? 1 : 0;
748 coeff[j] = (coeff[j] << BC_COEF) |
749 (s[i] & (SZ_COEF - 1));
750
751 if (i == 5 || i == 15)
752 coeff[j] <<= 1;
753
754 valid = (valid << 1) | (s[i] >> BC_COEF);
755 }
756
757 valid |= PRP_RZ_VALID_TBL_LEN(len);
758
759 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
760 valid |= PRP_RZ_VALID_BILINEAR;
761
762 if (pcdev->emma_prp->cfg.channel == 1) {
763 if (dir == RESIZE_DIR_H) {
764 writel(coeff[0], pcdev->base_emma +
765 PRP_CH1_RZ_HORI_COEF1);
766 writel(coeff[1], pcdev->base_emma +
767 PRP_CH1_RZ_HORI_COEF2);
768 writel(valid, pcdev->base_emma +
769 PRP_CH1_RZ_HORI_VALID);
770 } else {
771 writel(coeff[0], pcdev->base_emma +
772 PRP_CH1_RZ_VERT_COEF1);
773 writel(coeff[1], pcdev->base_emma +
774 PRP_CH1_RZ_VERT_COEF2);
775 writel(valid, pcdev->base_emma +
776 PRP_CH1_RZ_VERT_VALID);
777 }
778 } else {
779 if (dir == RESIZE_DIR_H) {
780 writel(coeff[0], pcdev->base_emma +
781 PRP_CH2_RZ_HORI_COEF1);
782 writel(coeff[1], pcdev->base_emma +
783 PRP_CH2_RZ_HORI_COEF2);
784 writel(valid, pcdev->base_emma +
785 PRP_CH2_RZ_HORI_VALID);
786 } else {
787 writel(coeff[0], pcdev->base_emma +
788 PRP_CH2_RZ_VERT_COEF1);
789 writel(coeff[1], pcdev->base_emma +
790 PRP_CH2_RZ_VERT_COEF2);
791 writel(valid, pcdev->base_emma +
792 PRP_CH2_RZ_VERT_VALID);
793 }
794 }
795 }
796 }
797
798 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
799 {
800 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
801 struct soc_camera_host *ici =
802 to_soc_camera_host(icd->parent);
803 struct mx2_camera_dev *pcdev = ici->priv;
804 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
805 struct vb2_buffer *vb;
806 struct mx2_buffer *buf;
807 unsigned long phys;
808 int bytesperline;
809
810 if (cpu_is_mx27()) {
811 unsigned long flags;
812 if (count < 2)
813 return -EINVAL;
814
815 spin_lock_irqsave(&pcdev->lock, flags);
816
817 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
818 internal.queue);
819 buf->internal.bufnum = 0;
820 vb = &buf->vb;
821 buf->state = MX2_STATE_ACTIVE;
822
823 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
824 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
825 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
826
827 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
828 internal.queue);
829 buf->internal.bufnum = 1;
830 vb = &buf->vb;
831 buf->state = MX2_STATE_ACTIVE;
832
833 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
834 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
835 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
836
837 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
838 icd->current_fmt->host_fmt);
839 if (bytesperline < 0)
840 return bytesperline;
841
842 /*
843 * I didn't manage to properly enable/disable the prp
844 * on a per frame basis during running transfers,
845 * thus we allocate a buffer here and use it to
846 * discard frames when no buffer is available.
847 * Feel free to work on this ;)
848 */
849 pcdev->discard_size = icd->user_height * bytesperline;
850 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
851 pcdev->discard_size, &pcdev->discard_buffer_dma,
852 GFP_KERNEL);
853 if (!pcdev->discard_buffer)
854 return -ENOMEM;
855
856 pcdev->buf_discard[0].discard = true;
857 list_add_tail(&pcdev->buf_discard[0].queue,
858 &pcdev->discard);
859
860 pcdev->buf_discard[1].discard = true;
861 list_add_tail(&pcdev->buf_discard[1].queue,
862 &pcdev->discard);
863
864 mx2_prp_resize_commit(pcdev);
865
866 mx27_camera_emma_buf_init(icd, bytesperline);
867
868 if (prp->cfg.channel == 1) {
869 writel(PRP_CNTL_CH1EN |
870 PRP_CNTL_CSIEN |
871 prp->cfg.in_fmt |
872 prp->cfg.out_fmt |
873 PRP_CNTL_CH1_LEN |
874 PRP_CNTL_CH1BYP |
875 PRP_CNTL_CH1_TSKIP(0) |
876 PRP_CNTL_IN_TSKIP(0),
877 pcdev->base_emma + PRP_CNTL);
878 } else {
879 writel(PRP_CNTL_CH2EN |
880 PRP_CNTL_CSIEN |
881 prp->cfg.in_fmt |
882 prp->cfg.out_fmt |
883 PRP_CNTL_CH2_LEN |
884 PRP_CNTL_CH2_TSKIP(0) |
885 PRP_CNTL_IN_TSKIP(0),
886 pcdev->base_emma + PRP_CNTL);
887 }
888 spin_unlock_irqrestore(&pcdev->lock, flags);
889 }
890
891 return 0;
892 }
893
894 static int mx2_stop_streaming(struct vb2_queue *q)
895 {
896 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
897 struct soc_camera_host *ici =
898 to_soc_camera_host(icd->parent);
899 struct mx2_camera_dev *pcdev = ici->priv;
900 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
901 unsigned long flags;
902 void *b;
903 u32 cntl;
904
905 if (cpu_is_mx27()) {
906 spin_lock_irqsave(&pcdev->lock, flags);
907
908 cntl = readl(pcdev->base_emma + PRP_CNTL);
909 if (prp->cfg.channel == 1) {
910 writel(cntl & ~PRP_CNTL_CH1EN,
911 pcdev->base_emma + PRP_CNTL);
912 } else {
913 writel(cntl & ~PRP_CNTL_CH2EN,
914 pcdev->base_emma + PRP_CNTL);
915 }
916 INIT_LIST_HEAD(&pcdev->capture);
917 INIT_LIST_HEAD(&pcdev->active_bufs);
918 INIT_LIST_HEAD(&pcdev->discard);
919
920 b = pcdev->discard_buffer;
921 pcdev->discard_buffer = NULL;
922
923 spin_unlock_irqrestore(&pcdev->lock, flags);
924
925 dma_free_coherent(ici->v4l2_dev.dev,
926 pcdev->discard_size, b, pcdev->discard_buffer_dma);
927 }
928
929 return 0;
930 }
931
932 static struct vb2_ops mx2_videobuf_ops = {
933 .queue_setup = mx2_videobuf_setup,
934 .buf_prepare = mx2_videobuf_prepare,
935 .buf_queue = mx2_videobuf_queue,
936 .buf_cleanup = mx2_videobuf_release,
937 .start_streaming = mx2_start_streaming,
938 .stop_streaming = mx2_stop_streaming,
939 };
940
941 static int mx2_camera_init_videobuf(struct vb2_queue *q,
942 struct soc_camera_device *icd)
943 {
944 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
945 q->io_modes = VB2_MMAP | VB2_USERPTR;
946 q->drv_priv = icd;
947 q->ops = &mx2_videobuf_ops;
948 q->mem_ops = &vb2_dma_contig_memops;
949 q->buf_struct_size = sizeof(struct mx2_buffer);
950
951 return vb2_queue_init(q);
952 }
953
954 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
955 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
956 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
957 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
958 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
959 V4L2_MBUS_PCLK_SAMPLE_RISING | \
960 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
961 V4L2_MBUS_DATA_ACTIVE_HIGH | \
962 V4L2_MBUS_DATA_ACTIVE_LOW)
963
964 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
965 {
966 u32 cntl;
967 int count = 0;
968
969 cntl = readl(pcdev->base_emma + PRP_CNTL);
970 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
971 while (count++ < 100) {
972 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
973 return 0;
974 barrier();
975 udelay(1);
976 }
977
978 return -ETIMEDOUT;
979 }
980
981 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
982 {
983 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
984 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
985 struct mx2_camera_dev *pcdev = ici->priv;
986 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
987 const struct soc_camera_format_xlate *xlate;
988 unsigned long common_flags;
989 int ret;
990 int bytesperline;
991 u32 csicr1 = pcdev->csicr1;
992
993 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
994 if (!ret) {
995 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
996 if (!common_flags) {
997 dev_warn(icd->parent,
998 "Flags incompatible: camera 0x%x, host 0x%x\n",
999 cfg.flags, MX2_BUS_FLAGS);
1000 return -EINVAL;
1001 }
1002 } else if (ret != -ENOIOCTLCMD) {
1003 return ret;
1004 } else {
1005 common_flags = MX2_BUS_FLAGS;
1006 }
1007
1008 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1009 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1010 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
1011 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1012 else
1013 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1014 }
1015
1016 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1017 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1018 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
1019 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1020 else
1021 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1022 }
1023
1024 cfg.flags = common_flags;
1025 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1026 if (ret < 0 && ret != -ENOIOCTLCMD) {
1027 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1028 common_flags, ret);
1029 return ret;
1030 }
1031
1032 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1033 if (!xlate) {
1034 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1035 return -EINVAL;
1036 }
1037
1038 if (xlate->code == V4L2_MBUS_FMT_YUYV8_2X8) {
1039 csicr1 |= CSICR1_PACK_DIR;
1040 csicr1 &= ~CSICR1_SWAP16_EN;
1041 dev_dbg(icd->parent, "already yuyv format, don't convert\n");
1042 } else if (xlate->code == V4L2_MBUS_FMT_UYVY8_2X8) {
1043 csicr1 &= ~CSICR1_PACK_DIR;
1044 csicr1 |= CSICR1_SWAP16_EN;
1045 dev_dbg(icd->parent, "convert uyvy mbus format into yuyv\n");
1046 } else {
1047 dev_warn(icd->parent, "mbus format not supported\n");
1048 return -EINVAL;
1049 }
1050
1051 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1052 csicr1 |= CSICR1_REDGE;
1053 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1054 csicr1 |= CSICR1_SOF_POL;
1055 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1056 csicr1 |= CSICR1_HSYNC_POL;
1057 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
1058 csicr1 |= CSICR1_EXT_VSYNC;
1059 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
1060 csicr1 |= CSICR1_CCIR_EN;
1061 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
1062 csicr1 |= CSICR1_CCIR_MODE;
1063 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
1064 csicr1 |= CSICR1_GCLK_MODE;
1065 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
1066 csicr1 |= CSICR1_INV_DATA;
1067
1068 pcdev->csicr1 = csicr1;
1069
1070 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
1071 icd->current_fmt->host_fmt);
1072 if (bytesperline < 0)
1073 return bytesperline;
1074
1075 if (cpu_is_mx27()) {
1076 ret = mx27_camera_emma_prp_reset(pcdev);
1077 if (ret)
1078 return ret;
1079 } else if (cpu_is_mx25()) {
1080 writel((bytesperline * icd->user_height) >> 2,
1081 pcdev->base_csi + CSIRXCNT);
1082 writel((bytesperline << 16) | icd->user_height,
1083 pcdev->base_csi + CSIIMAG_PARA);
1084 }
1085
1086 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
1087
1088 return 0;
1089 }
1090
1091 static int mx2_camera_set_crop(struct soc_camera_device *icd,
1092 struct v4l2_crop *a)
1093 {
1094 struct v4l2_rect *rect = &a->c;
1095 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1096 struct v4l2_mbus_framefmt mf;
1097 int ret;
1098
1099 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
1100 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
1101
1102 ret = v4l2_subdev_call(sd, video, s_crop, a);
1103 if (ret < 0)
1104 return ret;
1105
1106 /* The capture device might have changed its output */
1107 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1108 if (ret < 0)
1109 return ret;
1110
1111 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
1112 mf.width, mf.height);
1113
1114 icd->user_width = mf.width;
1115 icd->user_height = mf.height;
1116
1117 return ret;
1118 }
1119
1120 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1121 unsigned int idx,
1122 struct soc_camera_format_xlate *xlate)
1123 {
1124 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1125 const struct soc_mbus_pixelfmt *fmt;
1126 struct device *dev = icd->parent;
1127 enum v4l2_mbus_pixelcode code;
1128 int ret, formats = 0;
1129
1130 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1131 if (ret < 0)
1132 /* no more formats */
1133 return 0;
1134
1135 fmt = soc_mbus_get_fmtdesc(code);
1136 if (!fmt) {
1137 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1138 return 0;
1139 }
1140
1141 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
1142 code == V4L2_MBUS_FMT_UYVY8_2X8) {
1143 formats++;
1144 if (xlate) {
1145 /*
1146 * CH2 can output YUV420 which is a standard format in
1147 * soc_mediabus.c
1148 */
1149 xlate->host_fmt =
1150 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1151 xlate->code = code;
1152 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1153 xlate->host_fmt->name, code);
1154 xlate++;
1155 }
1156 }
1157
1158 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
1159 formats++;
1160 if (xlate) {
1161 xlate->host_fmt =
1162 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
1163 xlate->code = code;
1164 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1165 xlate->host_fmt->name, code);
1166 xlate++;
1167 }
1168 }
1169
1170 /* Generic pass-trough */
1171 formats++;
1172 if (xlate) {
1173 xlate->host_fmt = fmt;
1174 xlate->code = code;
1175 xlate++;
1176 }
1177 return formats;
1178 }
1179
1180 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1181 struct v4l2_mbus_framefmt *mf_in,
1182 struct v4l2_pix_format *pix_out, bool apply)
1183 {
1184 int num, den;
1185 unsigned long m;
1186 int i, dir;
1187
1188 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1189 struct emma_prp_resize tmprsz;
1190 unsigned char *s = tmprsz.s;
1191 int len = 0;
1192 int in, out;
1193
1194 if (dir == RESIZE_DIR_H) {
1195 in = mf_in->width;
1196 out = pix_out->width;
1197 } else {
1198 in = mf_in->height;
1199 out = pix_out->height;
1200 }
1201
1202 if (in < out)
1203 return -EINVAL;
1204 else if (in == out)
1205 continue;
1206
1207 /* Calculate ratio */
1208 m = gcd(in, out);
1209 num = in / m;
1210 den = out / m;
1211 if (num > RESIZE_NUM_MAX)
1212 return -EINVAL;
1213
1214 if ((num >= 2 * den) && (den == 1) &&
1215 (num < 9) && (!(num & 0x01))) {
1216 int sum = 0;
1217 int j;
1218
1219 /* Average scaling for >= 2:1 ratios */
1220 /* Support can be added for num >=9 and odd values */
1221
1222 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1223 len = num;
1224
1225 for (i = 0; i < (len / 2); i++)
1226 s[i] = 8;
1227
1228 do {
1229 for (i = 0; i < (len / 2); i++) {
1230 s[i] = s[i] >> 1;
1231 sum = 0;
1232 for (j = 0; j < (len / 2); j++)
1233 sum += s[j];
1234 if (sum == 4)
1235 break;
1236 }
1237 } while (sum != 4);
1238
1239 for (i = (len / 2); i < len; i++)
1240 s[i] = s[len - i - 1];
1241
1242 s[len - 1] |= SZ_COEF;
1243 } else {
1244 /* bilinear scaling for < 2:1 ratios */
1245 int v; /* overflow counter */
1246 int coeff, nxt; /* table output */
1247 int in_pos_inc = 2 * den;
1248 int out_pos = num;
1249 int out_pos_inc = 2 * num;
1250 int init_carry = num - den;
1251 int carry = init_carry;
1252
1253 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1254 v = den + in_pos_inc;
1255 do {
1256 coeff = v - out_pos;
1257 out_pos += out_pos_inc;
1258 carry += out_pos_inc;
1259 for (nxt = 0; v < out_pos; nxt++) {
1260 v += in_pos_inc;
1261 carry -= in_pos_inc;
1262 }
1263
1264 if (len > RESIZE_NUM_MAX)
1265 return -EINVAL;
1266
1267 coeff = ((coeff << BC_COEF) +
1268 (in_pos_inc >> 1)) / in_pos_inc;
1269
1270 if (coeff >= (SZ_COEF - 1))
1271 coeff--;
1272
1273 coeff |= SZ_COEF;
1274 s[len] = (unsigned char)coeff;
1275 len++;
1276
1277 for (i = 1; i < nxt; i++) {
1278 if (len >= RESIZE_NUM_MAX)
1279 return -EINVAL;
1280 s[len] = 0;
1281 len++;
1282 }
1283 } while (carry != init_carry);
1284 }
1285 tmprsz.len = len;
1286 if (dir == RESIZE_DIR_H)
1287 mf_in->width = pix_out->width;
1288 else
1289 mf_in->height = pix_out->height;
1290
1291 if (apply)
1292 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1293 }
1294 return 0;
1295 }
1296
1297 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1298 struct v4l2_format *f)
1299 {
1300 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1301 struct mx2_camera_dev *pcdev = ici->priv;
1302 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1303 const struct soc_camera_format_xlate *xlate;
1304 struct v4l2_pix_format *pix = &f->fmt.pix;
1305 struct v4l2_mbus_framefmt mf;
1306 int ret;
1307
1308 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1309 __func__, pix->width, pix->height);
1310
1311 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1312 if (!xlate) {
1313 dev_warn(icd->parent, "Format %x not found\n",
1314 pix->pixelformat);
1315 return -EINVAL;
1316 }
1317
1318 mf.width = pix->width;
1319 mf.height = pix->height;
1320 mf.field = pix->field;
1321 mf.colorspace = pix->colorspace;
1322 mf.code = xlate->code;
1323
1324 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1325 if (ret < 0 && ret != -ENOIOCTLCMD)
1326 return ret;
1327
1328 /* Store width and height returned by the sensor for resizing */
1329 pcdev->s_width = mf.width;
1330 pcdev->s_height = mf.height;
1331 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1332 __func__, pcdev->s_width, pcdev->s_height);
1333
1334 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1335 xlate->host_fmt->fourcc);
1336
1337 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1338 if ((mf.width != pix->width || mf.height != pix->height) &&
1339 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1340 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1341 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1342 }
1343
1344 if (mf.code != xlate->code)
1345 return -EINVAL;
1346
1347 pix->width = mf.width;
1348 pix->height = mf.height;
1349 pix->field = mf.field;
1350 pix->colorspace = mf.colorspace;
1351 icd->current_fmt = xlate;
1352
1353 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1354 __func__, pix->width, pix->height);
1355
1356 return 0;
1357 }
1358
1359 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1360 struct v4l2_format *f)
1361 {
1362 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1363 const struct soc_camera_format_xlate *xlate;
1364 struct v4l2_pix_format *pix = &f->fmt.pix;
1365 struct v4l2_mbus_framefmt mf;
1366 __u32 pixfmt = pix->pixelformat;
1367 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1368 struct mx2_camera_dev *pcdev = ici->priv;
1369 unsigned int width_limit;
1370 int ret;
1371
1372 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1373 __func__, pix->width, pix->height);
1374
1375 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1376 if (pixfmt && !xlate) {
1377 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1378 return -EINVAL;
1379 }
1380
1381 /* FIXME: implement MX27 limits */
1382
1383 /* limit to MX25 hardware capabilities */
1384 if (cpu_is_mx25()) {
1385 if (xlate->host_fmt->bits_per_sample <= 8)
1386 width_limit = 0xffff * 4;
1387 else
1388 width_limit = 0xffff * 2;
1389 /* CSIIMAG_PARA limit */
1390 if (pix->width > width_limit)
1391 pix->width = width_limit;
1392 if (pix->height > 0xffff)
1393 pix->height = 0xffff;
1394
1395 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1396 xlate->host_fmt);
1397 if (pix->bytesperline < 0)
1398 return pix->bytesperline;
1399 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1400 pix->bytesperline, pix->height);
1401 /* Check against the CSIRXCNT limit */
1402 if (pix->sizeimage > 4 * 0x3ffff) {
1403 /* Adjust geometry, preserve aspect ratio */
1404 unsigned int new_height = int_sqrt(div_u64(0x3ffffULL *
1405 4 * pix->height, pix->bytesperline));
1406 pix->width = new_height * pix->width / pix->height;
1407 pix->height = new_height;
1408 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1409 xlate->host_fmt);
1410 BUG_ON(pix->bytesperline < 0);
1411 pix->sizeimage = soc_mbus_image_size(xlate->host_fmt,
1412 pix->bytesperline, pix->height);
1413 }
1414 }
1415
1416 /* limit to sensor capabilities */
1417 mf.width = pix->width;
1418 mf.height = pix->height;
1419 mf.field = pix->field;
1420 mf.colorspace = pix->colorspace;
1421 mf.code = xlate->code;
1422
1423 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1424 if (ret < 0)
1425 return ret;
1426
1427 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1428 __func__, pcdev->s_width, pcdev->s_height);
1429
1430 /* If the sensor does not support image size try PrP resizing */
1431 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1432 xlate->host_fmt->fourcc);
1433
1434 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1435 if ((mf.width != pix->width || mf.height != pix->height) &&
1436 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1437 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1438 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1439 }
1440
1441 if (mf.field == V4L2_FIELD_ANY)
1442 mf.field = V4L2_FIELD_NONE;
1443 /*
1444 * Driver supports interlaced images provided they have
1445 * both fields so that they can be processed as if they
1446 * were progressive.
1447 */
1448 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1449 dev_err(icd->parent, "Field type %d unsupported.\n",
1450 mf.field);
1451 return -EINVAL;
1452 }
1453
1454 pix->width = mf.width;
1455 pix->height = mf.height;
1456 pix->field = mf.field;
1457 pix->colorspace = mf.colorspace;
1458
1459 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1460 __func__, pix->width, pix->height);
1461
1462 return 0;
1463 }
1464
1465 static int mx2_camera_querycap(struct soc_camera_host *ici,
1466 struct v4l2_capability *cap)
1467 {
1468 /* cap->name is set by the friendly caller:-> */
1469 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1470 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1471
1472 return 0;
1473 }
1474
1475 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1476 {
1477 struct soc_camera_device *icd = file->private_data;
1478
1479 return vb2_poll(&icd->vb2_vidq, file, pt);
1480 }
1481
1482 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1483 .owner = THIS_MODULE,
1484 .add = mx2_camera_add_device,
1485 .remove = mx2_camera_remove_device,
1486 .set_fmt = mx2_camera_set_fmt,
1487 .set_crop = mx2_camera_set_crop,
1488 .get_formats = mx2_camera_get_formats,
1489 .try_fmt = mx2_camera_try_fmt,
1490 .init_videobuf2 = mx2_camera_init_videobuf,
1491 .poll = mx2_camera_poll,
1492 .querycap = mx2_camera_querycap,
1493 .set_bus_param = mx2_camera_set_bus_param,
1494 };
1495
1496 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1497 int bufnum, bool err)
1498 {
1499 #ifdef DEBUG
1500 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1501 #endif
1502 struct mx2_buf_internal *ibuf;
1503 struct mx2_buffer *buf;
1504 struct vb2_buffer *vb;
1505 unsigned long phys;
1506
1507 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1508 queue);
1509
1510 BUG_ON(ibuf->bufnum != bufnum);
1511
1512 if (ibuf->discard) {
1513 /*
1514 * Discard buffer must not be returned to user space.
1515 * Just return it to the discard queue.
1516 */
1517 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1518 } else {
1519 buf = mx2_ibuf_to_buf(ibuf);
1520
1521 vb = &buf->vb;
1522 #ifdef DEBUG
1523 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1524 if (prp->cfg.channel == 1) {
1525 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1526 4 * bufnum) != phys) {
1527 dev_err(pcdev->dev, "%lx != %x\n", phys,
1528 readl(pcdev->base_emma +
1529 PRP_DEST_RGB1_PTR + 4 * bufnum));
1530 }
1531 } else {
1532 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1533 0x14 * bufnum) != phys) {
1534 dev_err(pcdev->dev, "%lx != %x\n", phys,
1535 readl(pcdev->base_emma +
1536 PRP_DEST_Y_PTR - 0x14 * bufnum));
1537 }
1538 }
1539 #endif
1540 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1541 vb2_plane_vaddr(vb, 0),
1542 vb2_get_plane_payload(vb, 0));
1543
1544 list_del_init(&buf->internal.queue);
1545 do_gettimeofday(&vb->v4l2_buf.timestamp);
1546 vb->v4l2_buf.sequence = pcdev->frame_count;
1547 if (err)
1548 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1549 else
1550 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1551 }
1552
1553 pcdev->frame_count++;
1554
1555 if (list_empty(&pcdev->capture)) {
1556 if (list_empty(&pcdev->discard)) {
1557 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1558 __func__);
1559 return;
1560 }
1561
1562 ibuf = list_first_entry(&pcdev->discard,
1563 struct mx2_buf_internal, queue);
1564 ibuf->bufnum = bufnum;
1565
1566 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1567 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1568 return;
1569 }
1570
1571 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1572 internal.queue);
1573
1574 buf->internal.bufnum = bufnum;
1575
1576 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1577
1578 vb = &buf->vb;
1579 buf->state = MX2_STATE_ACTIVE;
1580
1581 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1582 mx27_update_emma_buf(pcdev, phys, bufnum);
1583 }
1584
1585 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1586 {
1587 struct mx2_camera_dev *pcdev = data;
1588 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1589 struct mx2_buf_internal *ibuf;
1590
1591 spin_lock(&pcdev->lock);
1592
1593 if (list_empty(&pcdev->active_bufs)) {
1594 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1595 __func__);
1596
1597 if (!status) {
1598 spin_unlock(&pcdev->lock);
1599 return IRQ_NONE;
1600 }
1601 }
1602
1603 if (status & (1 << 7)) { /* overflow */
1604 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1605 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1606 pcdev->base_emma + PRP_CNTL);
1607 writel(cntl, pcdev->base_emma + PRP_CNTL);
1608
1609 ibuf = list_first_entry(&pcdev->active_bufs,
1610 struct mx2_buf_internal, queue);
1611 mx27_camera_frame_done_emma(pcdev,
1612 ibuf->bufnum, true);
1613
1614 status &= ~(1 << 7);
1615 } else if (((status & (3 << 5)) == (3 << 5)) ||
1616 ((status & (3 << 3)) == (3 << 3))) {
1617 /*
1618 * Both buffers have triggered, process the one we're expecting
1619 * to first
1620 */
1621 ibuf = list_first_entry(&pcdev->active_bufs,
1622 struct mx2_buf_internal, queue);
1623 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1624 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1625 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1626 mx27_camera_frame_done_emma(pcdev, 0, false);
1627 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1628 mx27_camera_frame_done_emma(pcdev, 1, false);
1629 }
1630
1631 spin_unlock(&pcdev->lock);
1632 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1633
1634 return IRQ_HANDLED;
1635 }
1636
1637 static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1638 {
1639 struct resource *res_emma = pcdev->res_emma;
1640 int err = 0;
1641
1642 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1643 MX2_CAM_DRV_NAME)) {
1644 err = -EBUSY;
1645 goto out;
1646 }
1647
1648 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1649 if (!pcdev->base_emma) {
1650 err = -ENOMEM;
1651 goto exit_release;
1652 }
1653
1654 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1655 MX2_CAM_DRV_NAME, pcdev);
1656 if (err) {
1657 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1658 goto exit_iounmap;
1659 }
1660
1661 pcdev->clk_emma = clk_get(NULL, "emma");
1662 if (IS_ERR(pcdev->clk_emma)) {
1663 err = PTR_ERR(pcdev->clk_emma);
1664 goto exit_free_irq;
1665 }
1666
1667 clk_enable(pcdev->clk_emma);
1668
1669 err = mx27_camera_emma_prp_reset(pcdev);
1670 if (err)
1671 goto exit_clk_emma_put;
1672
1673 return err;
1674
1675 exit_clk_emma_put:
1676 clk_disable(pcdev->clk_emma);
1677 clk_put(pcdev->clk_emma);
1678 exit_free_irq:
1679 free_irq(pcdev->irq_emma, pcdev);
1680 exit_iounmap:
1681 iounmap(pcdev->base_emma);
1682 exit_release:
1683 release_mem_region(res_emma->start, resource_size(res_emma));
1684 out:
1685 return err;
1686 }
1687
1688 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1689 {
1690 struct mx2_camera_dev *pcdev;
1691 struct resource *res_csi, *res_emma;
1692 void __iomem *base_csi;
1693 int irq_csi, irq_emma;
1694 int err = 0;
1695
1696 dev_dbg(&pdev->dev, "initialising\n");
1697
1698 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1699 irq_csi = platform_get_irq(pdev, 0);
1700 if (res_csi == NULL || irq_csi < 0) {
1701 dev_err(&pdev->dev, "Missing platform resources data\n");
1702 err = -ENODEV;
1703 goto exit;
1704 }
1705
1706 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1707 if (!pcdev) {
1708 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1709 err = -ENOMEM;
1710 goto exit;
1711 }
1712
1713 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1714 if (IS_ERR(pcdev->clk_csi)) {
1715 dev_err(&pdev->dev, "Could not get csi clock\n");
1716 err = PTR_ERR(pcdev->clk_csi);
1717 goto exit_kfree;
1718 }
1719
1720 pcdev->res_csi = res_csi;
1721 pcdev->pdata = pdev->dev.platform_data;
1722 if (pcdev->pdata) {
1723 long rate;
1724
1725 pcdev->platform_flags = pcdev->pdata->flags;
1726
1727 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1728 if (rate <= 0) {
1729 err = -ENODEV;
1730 goto exit_dma_free;
1731 }
1732 err = clk_set_rate(pcdev->clk_csi, rate);
1733 if (err < 0)
1734 goto exit_dma_free;
1735 }
1736
1737 INIT_LIST_HEAD(&pcdev->capture);
1738 INIT_LIST_HEAD(&pcdev->active_bufs);
1739 INIT_LIST_HEAD(&pcdev->discard);
1740 spin_lock_init(&pcdev->lock);
1741
1742 /*
1743 * Request the regions.
1744 */
1745 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1746 MX2_CAM_DRV_NAME)) {
1747 err = -EBUSY;
1748 goto exit_dma_free;
1749 }
1750
1751 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1752 if (!base_csi) {
1753 err = -ENOMEM;
1754 goto exit_release;
1755 }
1756 pcdev->irq_csi = irq_csi;
1757 pcdev->base_csi = base_csi;
1758 pcdev->base_dma = res_csi->start;
1759 pcdev->dev = &pdev->dev;
1760
1761 if (cpu_is_mx25()) {
1762 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0,
1763 MX2_CAM_DRV_NAME, pcdev);
1764 if (err) {
1765 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1766 goto exit_iounmap;
1767 }
1768 }
1769
1770 if (cpu_is_mx27()) {
1771 /* EMMA support */
1772 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1773 irq_emma = platform_get_irq(pdev, 1);
1774
1775 if (!res_emma || !irq_emma) {
1776 dev_err(&pdev->dev, "no EMMA resources\n");
1777 goto exit_free_irq;
1778 }
1779
1780 pcdev->res_emma = res_emma;
1781 pcdev->irq_emma = irq_emma;
1782 if (mx27_camera_emma_init(pcdev))
1783 goto exit_free_irq;
1784 }
1785
1786 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1787 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1788 pcdev->soc_host.priv = pcdev;
1789 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1790 pcdev->soc_host.nr = pdev->id;
1791 if (cpu_is_mx25())
1792 pcdev->soc_host.capabilities = SOCAM_HOST_CAP_STRIDE;
1793
1794 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1795 if (IS_ERR(pcdev->alloc_ctx)) {
1796 err = PTR_ERR(pcdev->alloc_ctx);
1797 goto eallocctx;
1798 }
1799 err = soc_camera_host_register(&pcdev->soc_host);
1800 if (err)
1801 goto exit_free_emma;
1802
1803 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1804 clk_get_rate(pcdev->clk_csi));
1805
1806 return 0;
1807
1808 exit_free_emma:
1809 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1810 eallocctx:
1811 if (cpu_is_mx27()) {
1812 free_irq(pcdev->irq_emma, pcdev);
1813 clk_disable(pcdev->clk_emma);
1814 clk_put(pcdev->clk_emma);
1815 iounmap(pcdev->base_emma);
1816 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma));
1817 }
1818 exit_free_irq:
1819 if (cpu_is_mx25())
1820 free_irq(pcdev->irq_csi, pcdev);
1821 exit_iounmap:
1822 iounmap(base_csi);
1823 exit_release:
1824 release_mem_region(res_csi->start, resource_size(res_csi));
1825 exit_dma_free:
1826 clk_put(pcdev->clk_csi);
1827 exit_kfree:
1828 kfree(pcdev);
1829 exit:
1830 return err;
1831 }
1832
1833 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1834 {
1835 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1836 struct mx2_camera_dev *pcdev = container_of(soc_host,
1837 struct mx2_camera_dev, soc_host);
1838 struct resource *res;
1839
1840 clk_put(pcdev->clk_csi);
1841 if (cpu_is_mx25())
1842 free_irq(pcdev->irq_csi, pcdev);
1843 if (cpu_is_mx27())
1844 free_irq(pcdev->irq_emma, pcdev);
1845
1846 soc_camera_host_unregister(&pcdev->soc_host);
1847
1848 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1849
1850 iounmap(pcdev->base_csi);
1851
1852 if (cpu_is_mx27()) {
1853 clk_disable(pcdev->clk_emma);
1854 clk_put(pcdev->clk_emma);
1855 iounmap(pcdev->base_emma);
1856 res = pcdev->res_emma;
1857 release_mem_region(res->start, resource_size(res));
1858 }
1859
1860 res = pcdev->res_csi;
1861 release_mem_region(res->start, resource_size(res));
1862
1863 kfree(pcdev);
1864
1865 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1866
1867 return 0;
1868 }
1869
1870 static struct platform_driver mx2_camera_driver = {
1871 .driver = {
1872 .name = MX2_CAM_DRV_NAME,
1873 },
1874 .remove = __devexit_p(mx2_camera_remove),
1875 };
1876
1877
1878 static int __init mx2_camera_init(void)
1879 {
1880 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1881 }
1882
1883 static void __exit mx2_camera_exit(void)
1884 {
1885 return platform_driver_unregister(&mx2_camera_driver);
1886 }
1887
1888 module_init(mx2_camera_init);
1889 module_exit(mx2_camera_exit);
1890
1891 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1892 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1893 MODULE_LICENSE("GPL");
1894 MODULE_VERSION(MX2_CAM_VERSION);
Linux kernel - Deliverables
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