projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
V4L/DVB: ov7670: Avoid reading clkrc
[deliverable/linux.git] / drivers / media / video / ov7670.c
1 /*
2 * A V4L2 driver for OmniVision OV7670 cameras.
3 *
4 * Copyright 2006 One Laptop Per Child Association, Inc. Written
5 * by Jonathan Corbet with substantial inspiration from Mark
6 * McClelland's ovcamchip code.
7 *
8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
9 *
10 * This file may be distributed under the terms of the GNU General
11 * Public License, version 2.
12 */
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/delay.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-chip-ident.h>
21 #include <media/v4l2-i2c-drv.h>
22
23
24 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
25 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
26 MODULE_LICENSE("GPL");
27
28 static int debug;
29 module_param(debug, bool, 0644);
30 MODULE_PARM_DESC(debug, "Debug level (0-1)");
31
32 /*
33 * Basic window sizes. These probably belong somewhere more globally
34 * useful.
35 */
36 #define VGA_WIDTH 640
37 #define VGA_HEIGHT 480
38 #define QVGA_WIDTH 320
39 #define QVGA_HEIGHT 240
40 #define CIF_WIDTH 352
41 #define CIF_HEIGHT 288
42 #define QCIF_WIDTH 176
43 #define QCIF_HEIGHT 144
44
45 /*
46 * Our nominal (default) frame rate.
47 */
48 #define OV7670_FRAME_RATE 30
49
50 /*
51 * The 7670 sits on i2c with ID 0x42
52 */
53 #define OV7670_I2C_ADDR 0x42
54
55 /* Registers */
56 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
57 #define REG_BLUE 0x01 /* blue gain */
58 #define REG_RED 0x02 /* red gain */
59 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
60 #define REG_COM1 0x04 /* Control 1 */
61 #define COM1_CCIR656 0x40 /* CCIR656 enable */
62 #define REG_BAVE 0x05 /* U/B Average level */
63 #define REG_GbAVE 0x06 /* Y/Gb Average level */
64 #define REG_AECHH 0x07 /* AEC MS 5 bits */
65 #define REG_RAVE 0x08 /* V/R Average level */
66 #define REG_COM2 0x09 /* Control 2 */
67 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
68 #define REG_PID 0x0a /* Product ID MSB */
69 #define REG_VER 0x0b /* Product ID LSB */
70 #define REG_COM3 0x0c /* Control 3 */
71 #define COM3_SWAP 0x40 /* Byte swap */
72 #define COM3_SCALEEN 0x08 /* Enable scaling */
73 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
74 #define REG_COM4 0x0d /* Control 4 */
75 #define REG_COM5 0x0e /* All "reserved" */
76 #define REG_COM6 0x0f /* Control 6 */
77 #define REG_AECH 0x10 /* More bits of AEC value */
78 #define REG_CLKRC 0x11 /* Clocl control */
79 #define CLK_EXT 0x40 /* Use external clock directly */
80 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
81 #define REG_COM7 0x12 /* Control 7 */
82 #define COM7_RESET 0x80 /* Register reset */
83 #define COM7_FMT_MASK 0x38
84 #define COM7_FMT_VGA 0x00
85 #define COM7_FMT_CIF 0x20 /* CIF format */
86 #define COM7_FMT_QVGA 0x10 /* QVGA format */
87 #define COM7_FMT_QCIF 0x08 /* QCIF format */
88 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
89 #define COM7_YUV 0x00 /* YUV */
90 #define COM7_BAYER 0x01 /* Bayer format */
91 #define COM7_PBAYER 0x05 /* "Processed bayer" */
92 #define REG_COM8 0x13 /* Control 8 */
93 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
94 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
95 #define COM8_BFILT 0x20 /* Band filter enable */
96 #define COM8_AGC 0x04 /* Auto gain enable */
97 #define COM8_AWB 0x02 /* White balance enable */
98 #define COM8_AEC 0x01 /* Auto exposure enable */
99 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
100 #define REG_COM10 0x15 /* Control 10 */
101 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
102 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
103 #define COM10_HREF_REV 0x08 /* Reverse HREF */
104 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
105 #define COM10_VS_NEG 0x02 /* VSYNC negative */
106 #define COM10_HS_NEG 0x01 /* HSYNC negative */
107 #define REG_HSTART 0x17 /* Horiz start high bits */
108 #define REG_HSTOP 0x18 /* Horiz stop high bits */
109 #define REG_VSTART 0x19 /* Vert start high bits */
110 #define REG_VSTOP 0x1a /* Vert stop high bits */
111 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
112 #define REG_MIDH 0x1c /* Manuf. ID high */
113 #define REG_MIDL 0x1d /* Manuf. ID low */
114 #define REG_MVFP 0x1e /* Mirror / vflip */
115 #define MVFP_MIRROR 0x20 /* Mirror image */
116 #define MVFP_FLIP 0x10 /* Vertical flip */
117
118 #define REG_AEW 0x24 /* AGC upper limit */
119 #define REG_AEB 0x25 /* AGC lower limit */
120 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
121 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
122 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
123 #define REG_HREF 0x32 /* HREF pieces */
124 #define REG_TSLB 0x3a /* lots of stuff */
125 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
126 #define REG_COM11 0x3b /* Control 11 */
127 #define COM11_NIGHT 0x80 /* NIght mode enable */
128 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
129 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
130 #define COM11_50HZ 0x08 /* Manual 50Hz select */
131 #define COM11_EXP 0x02
132 #define REG_COM12 0x3c /* Control 12 */
133 #define COM12_HREF 0x80 /* HREF always */
134 #define REG_COM13 0x3d /* Control 13 */
135 #define COM13_GAMMA 0x80 /* Gamma enable */
136 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
137 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
138 #define REG_COM14 0x3e /* Control 14 */
139 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
140 #define REG_EDGE 0x3f /* Edge enhancement factor */
141 #define REG_COM15 0x40 /* Control 15 */
142 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
143 #define COM15_R01FE 0x80 /* 01 to FE */
144 #define COM15_R00FF 0xc0 /* 00 to FF */
145 #define COM15_RGB565 0x10 /* RGB565 output */
146 #define COM15_RGB555 0x30 /* RGB555 output */
147 #define REG_COM16 0x41 /* Control 16 */
148 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
149 #define REG_COM17 0x42 /* Control 17 */
150 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
151 #define COM17_CBAR 0x08 /* DSP Color bar */
152
153 /*
154 * This matrix defines how the colors are generated, must be
155 * tweaked to adjust hue and saturation.
156 *
157 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
158 *
159 * They are nine-bit signed quantities, with the sign bit
160 * stored in 0x58. Sign for v-red is bit 0, and up from there.
161 */
162 #define REG_CMATRIX_BASE 0x4f
163 #define CMATRIX_LEN 6
164 #define REG_CMATRIX_SIGN 0x58
165
166
167 #define REG_BRIGHT 0x55 /* Brightness */
168 #define REG_CONTRAS 0x56 /* Contrast control */
169
170 #define REG_GFIX 0x69 /* Fix gain control */
171
172 #define REG_REG76 0x76 /* OV's name */
173 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
174 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
175
176 #define REG_RGB444 0x8c /* RGB 444 control */
177 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
178 #define R444_RGBX 0x01 /* Empty nibble at end */
179
180 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
181 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
182
183 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
184 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
185 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
186 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
187 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
188 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
189 #define REG_BD60MAX 0xab /* 60hz banding step limit */
190
191
192 /*
193 * Information we maintain about a known sensor.
194 */
195 struct ov7670_format_struct; /* coming later */
196 struct ov7670_info {
197 struct v4l2_subdev sd;
198 struct ov7670_format_struct *fmt; /* Current format */
199 unsigned char sat; /* Saturation value */
200 int hue; /* Hue value */
201 u8 clkrc; /* Clock divider value */
202 };
203
204 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
205 {
206 return container_of(sd, struct ov7670_info, sd);
207 }
208
209
210
211 /*
212 * The default register settings, as obtained from OmniVision. There
213 * is really no making sense of most of these - lots of "reserved" values
214 * and such.
215 *
216 * These settings give VGA YUYV.
217 */
218
219 struct regval_list {
220 unsigned char reg_num;
221 unsigned char value;
222 };
223
224 static struct regval_list ov7670_default_regs[] = {
225 { REG_COM7, COM7_RESET },
226 /*
227 * Clock scale: 3 = 15fps
228 * 2 = 20fps
229 * 1 = 30fps
230 */
231 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
232 { REG_TSLB, 0x04 }, /* OV */
233 { REG_COM7, 0 }, /* VGA */
234 /*
235 * Set the hardware window. These values from OV don't entirely
236 * make sense - hstop is less than hstart. But they work...
237 */
238 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
239 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
240 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
241
242 { REG_COM3, 0 }, { REG_COM14, 0 },
243 /* Mystery scaling numbers */
244 { 0x70, 0x3a }, { 0x71, 0x35 },
245 { 0x72, 0x11 }, { 0x73, 0xf0 },
246 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
247
248 /* Gamma curve values */
249 { 0x7a, 0x20 }, { 0x7b, 0x10 },
250 { 0x7c, 0x1e }, { 0x7d, 0x35 },
251 { 0x7e, 0x5a }, { 0x7f, 0x69 },
252 { 0x80, 0x76 }, { 0x81, 0x80 },
253 { 0x82, 0x88 }, { 0x83, 0x8f },
254 { 0x84, 0x96 }, { 0x85, 0xa3 },
255 { 0x86, 0xaf }, { 0x87, 0xc4 },
256 { 0x88, 0xd7 }, { 0x89, 0xe8 },
257
258 /* AGC and AEC parameters. Note we start by disabling those features,
259 then turn them only after tweaking the values. */
260 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
261 { REG_GAIN, 0 }, { REG_AECH, 0 },
262 { REG_COM4, 0x40 }, /* magic reserved bit */
263 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
264 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
265 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
266 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
267 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
268 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
269 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
270 { REG_HAECC7, 0x94 },
271 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
272
273 /* Almost all of these are magic "reserved" values. */
274 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
275 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
276 { 0x21, 0x02 }, { 0x22, 0x91 },
277 { 0x29, 0x07 }, { 0x33, 0x0b },
278 { 0x35, 0x0b }, { 0x37, 0x1d },
279 { 0x38, 0x71 }, { 0x39, 0x2a },
280 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
281 { 0x4e, 0x20 }, { REG_GFIX, 0 },
282 { 0x6b, 0x4a }, { 0x74, 0x10 },
283 { 0x8d, 0x4f }, { 0x8e, 0 },
284 { 0x8f, 0 }, { 0x90, 0 },
285 { 0x91, 0 }, { 0x96, 0 },
286 { 0x9a, 0 }, { 0xb0, 0x84 },
287 { 0xb1, 0x0c }, { 0xb2, 0x0e },
288 { 0xb3, 0x82 }, { 0xb8, 0x0a },
289
290 /* More reserved magic, some of which tweaks white balance */
291 { 0x43, 0x0a }, { 0x44, 0xf0 },
292 { 0x45, 0x34 }, { 0x46, 0x58 },
293 { 0x47, 0x28 }, { 0x48, 0x3a },
294 { 0x59, 0x88 }, { 0x5a, 0x88 },
295 { 0x5b, 0x44 }, { 0x5c, 0x67 },
296 { 0x5d, 0x49 }, { 0x5e, 0x0e },
297 { 0x6c, 0x0a }, { 0x6d, 0x55 },
298 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
299 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
300 { REG_RED, 0x60 },
301 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
302
303 /* Matrix coefficients */
304 { 0x4f, 0x80 }, { 0x50, 0x80 },
305 { 0x51, 0 }, { 0x52, 0x22 },
306 { 0x53, 0x5e }, { 0x54, 0x80 },
307 { 0x58, 0x9e },
308
309 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
310 { 0x75, 0x05 }, { 0x76, 0xe1 },
311 { 0x4c, 0 }, { 0x77, 0x01 },
312 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
313 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
314 { 0x56, 0x40 },
315
316 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
317 { 0xa4, 0x88 }, { 0x96, 0 },
318 { 0x97, 0x30 }, { 0x98, 0x20 },
319 { 0x99, 0x30 }, { 0x9a, 0x84 },
320 { 0x9b, 0x29 }, { 0x9c, 0x03 },
321 { 0x9d, 0x4c }, { 0x9e, 0x3f },
322 { 0x78, 0x04 },
323
324 /* Extra-weird stuff. Some sort of multiplexor register */
325 { 0x79, 0x01 }, { 0xc8, 0xf0 },
326 { 0x79, 0x0f }, { 0xc8, 0x00 },
327 { 0x79, 0x10 }, { 0xc8, 0x7e },
328 { 0x79, 0x0a }, { 0xc8, 0x80 },
329 { 0x79, 0x0b }, { 0xc8, 0x01 },
330 { 0x79, 0x0c }, { 0xc8, 0x0f },
331 { 0x79, 0x0d }, { 0xc8, 0x20 },
332 { 0x79, 0x09 }, { 0xc8, 0x80 },
333 { 0x79, 0x02 }, { 0xc8, 0xc0 },
334 { 0x79, 0x03 }, { 0xc8, 0x40 },
335 { 0x79, 0x05 }, { 0xc8, 0x30 },
336 { 0x79, 0x26 },
337
338 { 0xff, 0xff }, /* END MARKER */
339 };
340
341
342 /*
343 * Here we'll try to encapsulate the changes for just the output
344 * video format.
345 *
346 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
347 *
348 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
349 */
350
351
352 static struct regval_list ov7670_fmt_yuv422[] = {
353 { REG_COM7, 0x0 }, /* Selects YUV mode */
354 { REG_RGB444, 0 }, /* No RGB444 please */
355 { REG_COM1, 0 }, /* CCIR601 */
356 { REG_COM15, COM15_R00FF },
357 { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */
358 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
359 { 0x50, 0x80 }, /* "matrix coefficient 2" */
360 { 0x51, 0 }, /* vb */
361 { 0x52, 0x22 }, /* "matrix coefficient 4" */
362 { 0x53, 0x5e }, /* "matrix coefficient 5" */
363 { 0x54, 0x80 }, /* "matrix coefficient 6" */
364 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
365 { 0xff, 0xff },
366 };
367
368 static struct regval_list ov7670_fmt_rgb565[] = {
369 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
370 { REG_RGB444, 0 }, /* No RGB444 please */
371 { REG_COM1, 0x0 }, /* CCIR601 */
372 { REG_COM15, COM15_RGB565 },
373 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
374 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
375 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
376 { 0x51, 0 }, /* vb */
377 { 0x52, 0x3d }, /* "matrix coefficient 4" */
378 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
379 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
380 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
381 { 0xff, 0xff },
382 };
383
384 static struct regval_list ov7670_fmt_rgb444[] = {
385 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
386 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
387 { REG_COM1, 0x0 }, /* CCIR601 */
388 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
389 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
390 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
391 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
392 { 0x51, 0 }, /* vb */
393 { 0x52, 0x3d }, /* "matrix coefficient 4" */
394 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
395 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
396 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
397 { 0xff, 0xff },
398 };
399
400 static struct regval_list ov7670_fmt_raw[] = {
401 { REG_COM7, COM7_BAYER },
402 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
403 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
404 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
405 { 0xff, 0xff },
406 };
407
408
409
410 /*
411 * Low-level register I/O.
412 */
413
414 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
415 unsigned char *value)
416 {
417 struct i2c_client *client = v4l2_get_subdevdata(sd);
418 int ret;
419
420 ret = i2c_smbus_read_byte_data(client, reg);
421 if (ret >= 0) {
422 *value = (unsigned char)ret;
423 ret = 0;
424 }
425 return ret;
426 }
427
428
429 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
430 unsigned char value)
431 {
432 struct i2c_client *client = v4l2_get_subdevdata(sd);
433 int ret = i2c_smbus_write_byte_data(client, reg, value);
434
435 if (reg == REG_COM7 && (value & COM7_RESET))
436 msleep(5); /* Wait for reset to run */
437 return ret;
438 }
439
440
441 /*
442 * Write a list of register settings; ff/ff stops the process.
443 */
444 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
445 {
446 while (vals->reg_num != 0xff || vals->value != 0xff) {
447 int ret = ov7670_write(sd, vals->reg_num, vals->value);
448 if (ret < 0)
449 return ret;
450 vals++;
451 }
452 return 0;
453 }
454
455
456 /*
457 * Stuff that knows about the sensor.
458 */
459 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
460 {
461 ov7670_write(sd, REG_COM7, COM7_RESET);
462 msleep(1);
463 return 0;
464 }
465
466
467 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
468 {
469 return ov7670_write_array(sd, ov7670_default_regs);
470 }
471
472
473
474 static int ov7670_detect(struct v4l2_subdev *sd)
475 {
476 unsigned char v;
477 int ret;
478
479 ret = ov7670_init(sd, 0);
480 if (ret < 0)
481 return ret;
482 ret = ov7670_read(sd, REG_MIDH, &v);
483 if (ret < 0)
484 return ret;
485 if (v != 0x7f) /* OV manuf. id. */
486 return -ENODEV;
487 ret = ov7670_read(sd, REG_MIDL, &v);
488 if (ret < 0)
489 return ret;
490 if (v != 0xa2)
491 return -ENODEV;
492 /*
493 * OK, we know we have an OmniVision chip...but which one?
494 */
495 ret = ov7670_read(sd, REG_PID, &v);
496 if (ret < 0)
497 return ret;
498 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
499 return -ENODEV;
500 ret = ov7670_read(sd, REG_VER, &v);
501 if (ret < 0)
502 return ret;
503 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
504 return -ENODEV;
505 return 0;
506 }
507
508
509 /*
510 * Store information about the video data format. The color matrix
511 * is deeply tied into the format, so keep the relevant values here.
512 * The magic matrix nubmers come from OmniVision.
513 */
514 static struct ov7670_format_struct {
515 __u8 *desc;
516 __u32 pixelformat;
517 struct regval_list *regs;
518 int cmatrix[CMATRIX_LEN];
519 int bpp; /* Bytes per pixel */
520 } ov7670_formats[] = {
521 {
522 .desc = "YUYV 4:2:2",
523 .pixelformat = V4L2_PIX_FMT_YUYV,
524 .regs = ov7670_fmt_yuv422,
525 .cmatrix = { 128, -128, 0, -34, -94, 128 },
526 .bpp = 2,
527 },
528 {
529 .desc = "RGB 444",
530 .pixelformat = V4L2_PIX_FMT_RGB444,
531 .regs = ov7670_fmt_rgb444,
532 .cmatrix = { 179, -179, 0, -61, -176, 228 },
533 .bpp = 2,
534 },
535 {
536 .desc = "RGB 565",
537 .pixelformat = V4L2_PIX_FMT_RGB565,
538 .regs = ov7670_fmt_rgb565,
539 .cmatrix = { 179, -179, 0, -61, -176, 228 },
540 .bpp = 2,
541 },
542 {
543 .desc = "Raw RGB Bayer",
544 .pixelformat = V4L2_PIX_FMT_SBGGR8,
545 .regs = ov7670_fmt_raw,
546 .cmatrix = { 0, 0, 0, 0, 0, 0 },
547 .bpp = 1
548 },
549 };
550 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
551
552
553 /*
554 * Then there is the issue of window sizes. Try to capture the info here.
555 */
556
557 /*
558 * QCIF mode is done (by OV) in a very strange way - it actually looks like
559 * VGA with weird scaling options - they do *not* use the canned QCIF mode
560 * which is allegedly provided by the sensor. So here's the weird register
561 * settings.
562 */
563 static struct regval_list ov7670_qcif_regs[] = {
564 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
565 { REG_COM3, COM3_DCWEN },
566 { REG_COM14, COM14_DCWEN | 0x01},
567 { 0x73, 0xf1 },
568 { 0xa2, 0x52 },
569 { 0x7b, 0x1c },
570 { 0x7c, 0x28 },
571 { 0x7d, 0x3c },
572 { 0x7f, 0x69 },
573 { REG_COM9, 0x38 },
574 { 0xa1, 0x0b },
575 { 0x74, 0x19 },
576 { 0x9a, 0x80 },
577 { 0x43, 0x14 },
578 { REG_COM13, 0xc0 },
579 { 0xff, 0xff },
580 };
581
582 static struct ov7670_win_size {
583 int width;
584 int height;
585 unsigned char com7_bit;
586 int hstart; /* Start/stop values for the camera. Note */
587 int hstop; /* that they do not always make complete */
588 int vstart; /* sense to humans, but evidently the sensor */
589 int vstop; /* will do the right thing... */
590 struct regval_list *regs; /* Regs to tweak */
591 /* h/vref stuff */
592 } ov7670_win_sizes[] = {
593 /* VGA */
594 {
595 .width = VGA_WIDTH,
596 .height = VGA_HEIGHT,
597 .com7_bit = COM7_FMT_VGA,
598 .hstart = 158, /* These values from */
599 .hstop = 14, /* Omnivision */
600 .vstart = 10,
601 .vstop = 490,
602 .regs = NULL,
603 },
604 /* CIF */
605 {
606 .width = CIF_WIDTH,
607 .height = CIF_HEIGHT,
608 .com7_bit = COM7_FMT_CIF,
609 .hstart = 170, /* Empirically determined */
610 .hstop = 90,
611 .vstart = 14,
612 .vstop = 494,
613 .regs = NULL,
614 },
615 /* QVGA */
616 {
617 .width = QVGA_WIDTH,
618 .height = QVGA_HEIGHT,
619 .com7_bit = COM7_FMT_QVGA,
620 .hstart = 164, /* Empirically determined */
621 .hstop = 20,
622 .vstart = 14,
623 .vstop = 494,
624 .regs = NULL,
625 },
626 /* QCIF */
627 {
628 .width = QCIF_WIDTH,
629 .height = QCIF_HEIGHT,
630 .com7_bit = COM7_FMT_VGA, /* see comment above */
631 .hstart = 456, /* Empirically determined */
632 .hstop = 24,
633 .vstart = 14,
634 .vstop = 494,
635 .regs = ov7670_qcif_regs,
636 },
637 };
638
639 #define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes))
640
641
642 /*
643 * Store a set of start/stop values into the camera.
644 */
645 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
646 int vstart, int vstop)
647 {
648 int ret;
649 unsigned char v;
650 /*
651 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
652 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
653 * a mystery "edge offset" value in the top two bits of href.
654 */
655 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
656 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
657 ret += ov7670_read(sd, REG_HREF, &v);
658 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
659 msleep(10);
660 ret += ov7670_write(sd, REG_HREF, v);
661 /*
662 * Vertical: similar arrangement, but only 10 bits.
663 */
664 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
665 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
666 ret += ov7670_read(sd, REG_VREF, &v);
667 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
668 msleep(10);
669 ret += ov7670_write(sd, REG_VREF, v);
670 return ret;
671 }
672
673
674 static int ov7670_enum_fmt(struct v4l2_subdev *sd, struct v4l2_fmtdesc *fmt)
675 {
676 struct ov7670_format_struct *ofmt;
677
678 if (fmt->index >= N_OV7670_FMTS)
679 return -EINVAL;
680
681 ofmt = ov7670_formats + fmt->index;
682 fmt->flags = 0;
683 strcpy(fmt->description, ofmt->desc);
684 fmt->pixelformat = ofmt->pixelformat;
685 return 0;
686 }
687
688
689 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
690 struct v4l2_format *fmt,
691 struct ov7670_format_struct **ret_fmt,
692 struct ov7670_win_size **ret_wsize)
693 {
694 int index;
695 struct ov7670_win_size *wsize;
696 struct v4l2_pix_format *pix = &fmt->fmt.pix;
697
698 for (index = 0; index < N_OV7670_FMTS; index++)
699 if (ov7670_formats[index].pixelformat == pix->pixelformat)
700 break;
701 if (index >= N_OV7670_FMTS) {
702 /* default to first format */
703 index = 0;
704 pix->pixelformat = ov7670_formats[0].pixelformat;
705 }
706 if (ret_fmt != NULL)
707 *ret_fmt = ov7670_formats + index;
708 /*
709 * Fields: the OV devices claim to be progressive.
710 */
711 pix->field = V4L2_FIELD_NONE;
712 /*
713 * Round requested image size down to the nearest
714 * we support, but not below the smallest.
715 */
716 for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES;
717 wsize++)
718 if (pix->width >= wsize->width && pix->height >= wsize->height)
719 break;
720 if (wsize >= ov7670_win_sizes + N_WIN_SIZES)
721 wsize--; /* Take the smallest one */
722 if (ret_wsize != NULL)
723 *ret_wsize = wsize;
724 /*
725 * Note the size we'll actually handle.
726 */
727 pix->width = wsize->width;
728 pix->height = wsize->height;
729 pix->bytesperline = pix->width*ov7670_formats[index].bpp;
730 pix->sizeimage = pix->height*pix->bytesperline;
731 return 0;
732 }
733
734 static int ov7670_try_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
735 {
736 return ov7670_try_fmt_internal(sd, fmt, NULL, NULL);
737 }
738
739 /*
740 * Set a format.
741 */
742 static int ov7670_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
743 {
744 int ret;
745 struct ov7670_format_struct *ovfmt;
746 struct ov7670_win_size *wsize;
747 struct ov7670_info *info = to_state(sd);
748 unsigned char com7;
749
750 ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize);
751 if (ret)
752 return ret;
753 /*
754 * COM7 is a pain in the ass, it doesn't like to be read then
755 * quickly written afterward. But we have everything we need
756 * to set it absolutely here, as long as the format-specific
757 * register sets list it first.
758 */
759 com7 = ovfmt->regs[0].value;
760 com7 |= wsize->com7_bit;
761 ov7670_write(sd, REG_COM7, com7);
762 /*
763 * Now write the rest of the array. Also store start/stops
764 */
765 ov7670_write_array(sd, ovfmt->regs + 1);
766 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
767 wsize->vstop);
768 ret = 0;
769 if (wsize->regs)
770 ret = ov7670_write_array(sd, wsize->regs);
771 info->fmt = ovfmt;
772
773 /*
774 * If we're running RGB565, we must rewrite clkrc after setting
775 * the other parameters or the image looks poor. If we're *not*
776 * doing RGB565, we must not rewrite clkrc or the image looks
777 * *really* poor.
778 */
779 if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565 && ret == 0)
780 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
781 return ret;
782 }
783
784 /*
785 * Implement G/S_PARM. There is a "high quality" mode we could try
786 * to do someday; for now, we just do the frame rate tweak.
787 */
788 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
789 {
790 struct v4l2_captureparm *cp = &parms->parm.capture;
791 struct ov7670_info *info = to_state(sd);
792
793 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
794 return -EINVAL;
795
796 memset(cp, 0, sizeof(struct v4l2_captureparm));
797 cp->capability = V4L2_CAP_TIMEPERFRAME;
798 cp->timeperframe.numerator = 1;
799 cp->timeperframe.denominator = OV7670_FRAME_RATE;
800 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
801 cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE);
802 return 0;
803 }
804
805 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
806 {
807 struct v4l2_captureparm *cp = &parms->parm.capture;
808 struct v4l2_fract *tpf = &cp->timeperframe;
809 struct ov7670_info *info = to_state(sd);
810 unsigned char clkrc;
811 int ret, div;
812
813 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
814 return -EINVAL;
815 if (cp->extendedmode != 0)
816 return -EINVAL;
817
818 if (tpf->numerator == 0 || tpf->denominator == 0)
819 div = 1; /* Reset to full rate */
820 else
821 div = (tpf->numerator*OV7670_FRAME_RATE)/tpf->denominator;
822 if (div == 0)
823 div = 1;
824 else if (div > CLK_SCALE)
825 div = CLK_SCALE;
826 info->clkrc = (info->clkrc & 0x80) | div;
827 tpf->numerator = 1;
828 tpf->denominator = OV7670_FRAME_RATE/div;
829 return ov7670_write(sd, REG_CLKRC, info->clkrc);
830 }
831
832
833
834 /*
835 * Code for dealing with controls.
836 */
837
838
839
840
841
842 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
843 int matrix[CMATRIX_LEN])
844 {
845 int i, ret;
846 unsigned char signbits = 0;
847
848 /*
849 * Weird crap seems to exist in the upper part of
850 * the sign bits register, so let's preserve it.
851 */
852 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
853 signbits &= 0xc0;
854
855 for (i = 0; i < CMATRIX_LEN; i++) {
856 unsigned char raw;
857
858 if (matrix[i] < 0) {
859 signbits |= (1 << i);
860 if (matrix[i] < -255)
861 raw = 0xff;
862 else
863 raw = (-1 * matrix[i]) & 0xff;
864 }
865 else {
866 if (matrix[i] > 255)
867 raw = 0xff;
868 else
869 raw = matrix[i] & 0xff;
870 }
871 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
872 }
873 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
874 return ret;
875 }
876
877
878 /*
879 * Hue also requires messing with the color matrix. It also requires
880 * trig functions, which tend not to be well supported in the kernel.
881 * So here is a simple table of sine values, 0-90 degrees, in steps
882 * of five degrees. Values are multiplied by 1000.
883 *
884 * The following naive approximate trig functions require an argument
885 * carefully limited to -180 <= theta <= 180.
886 */
887 #define SIN_STEP 5
888 static const int ov7670_sin_table[] = {
889 0, 87, 173, 258, 342, 422,
890 499, 573, 642, 707, 766, 819,
891 866, 906, 939, 965, 984, 996,
892 1000
893 };
894
895 static int ov7670_sine(int theta)
896 {
897 int chs = 1;
898 int sine;
899
900 if (theta < 0) {
901 theta = -theta;
902 chs = -1;
903 }
904 if (theta <= 90)
905 sine = ov7670_sin_table[theta/SIN_STEP];
906 else {
907 theta -= 90;
908 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
909 }
910 return sine*chs;
911 }
912
913 static int ov7670_cosine(int theta)
914 {
915 theta = 90 - theta;
916 if (theta > 180)
917 theta -= 360;
918 else if (theta < -180)
919 theta += 360;
920 return ov7670_sine(theta);
921 }
922
923
924
925
926 static void ov7670_calc_cmatrix(struct ov7670_info *info,
927 int matrix[CMATRIX_LEN])
928 {
929 int i;
930 /*
931 * Apply the current saturation setting first.
932 */
933 for (i = 0; i < CMATRIX_LEN; i++)
934 matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7;
935 /*
936 * Then, if need be, rotate the hue value.
937 */
938 if (info->hue != 0) {
939 int sinth, costh, tmpmatrix[CMATRIX_LEN];
940
941 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
942 sinth = ov7670_sine(info->hue);
943 costh = ov7670_cosine(info->hue);
944
945 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
946 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
947 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
948 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
949 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
950 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
951 }
952 }
953
954
955
956 static int ov7670_s_sat(struct v4l2_subdev *sd, int value)
957 {
958 struct ov7670_info *info = to_state(sd);
959 int matrix[CMATRIX_LEN];
960 int ret;
961
962 info->sat = value;
963 ov7670_calc_cmatrix(info, matrix);
964 ret = ov7670_store_cmatrix(sd, matrix);
965 return ret;
966 }
967
968 static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value)
969 {
970 struct ov7670_info *info = to_state(sd);
971
972 *value = info->sat;
973 return 0;
974 }
975
976 static int ov7670_s_hue(struct v4l2_subdev *sd, int value)
977 {
978 struct ov7670_info *info = to_state(sd);
979 int matrix[CMATRIX_LEN];
980 int ret;
981
982 if (value < -180 || value > 180)
983 return -EINVAL;
984 info->hue = value;
985 ov7670_calc_cmatrix(info, matrix);
986 ret = ov7670_store_cmatrix(sd, matrix);
987 return ret;
988 }
989
990
991 static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value)
992 {
993 struct ov7670_info *info = to_state(sd);
994
995 *value = info->hue;
996 return 0;
997 }
998
999
1000 /*
1001 * Some weird registers seem to store values in a sign/magnitude format!
1002 */
1003 static unsigned char ov7670_sm_to_abs(unsigned char v)
1004 {
1005 if ((v & 0x80) == 0)
1006 return v + 128;
1007 return 128 - (v & 0x7f);
1008 }
1009
1010
1011 static unsigned char ov7670_abs_to_sm(unsigned char v)
1012 {
1013 if (v > 127)
1014 return v & 0x7f;
1015 return (128 - v) | 0x80;
1016 }
1017
1018 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1019 {
1020 unsigned char com8 = 0, v;
1021 int ret;
1022
1023 ov7670_read(sd, REG_COM8, &com8);
1024 com8 &= ~COM8_AEC;
1025 ov7670_write(sd, REG_COM8, com8);
1026 v = ov7670_abs_to_sm(value);
1027 ret = ov7670_write(sd, REG_BRIGHT, v);
1028 return ret;
1029 }
1030
1031 static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value)
1032 {
1033 unsigned char v = 0;
1034 int ret = ov7670_read(sd, REG_BRIGHT, &v);
1035
1036 *value = ov7670_sm_to_abs(v);
1037 return ret;
1038 }
1039
1040 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1041 {
1042 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1043 }
1044
1045 static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value)
1046 {
1047 unsigned char v = 0;
1048 int ret = ov7670_read(sd, REG_CONTRAS, &v);
1049
1050 *value = v;
1051 return ret;
1052 }
1053
1054 static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value)
1055 {
1056 int ret;
1057 unsigned char v = 0;
1058
1059 ret = ov7670_read(sd, REG_MVFP, &v);
1060 *value = (v & MVFP_MIRROR) == MVFP_MIRROR;
1061 return ret;
1062 }
1063
1064
1065 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1066 {
1067 unsigned char v = 0;
1068 int ret;
1069
1070 ret = ov7670_read(sd, REG_MVFP, &v);
1071 if (value)
1072 v |= MVFP_MIRROR;
1073 else
1074 v &= ~MVFP_MIRROR;
1075 msleep(10); /* FIXME */
1076 ret += ov7670_write(sd, REG_MVFP, v);
1077 return ret;
1078 }
1079
1080
1081
1082 static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value)
1083 {
1084 int ret;
1085 unsigned char v = 0;
1086
1087 ret = ov7670_read(sd, REG_MVFP, &v);
1088 *value = (v & MVFP_FLIP) == MVFP_FLIP;
1089 return ret;
1090 }
1091
1092
1093 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1094 {
1095 unsigned char v = 0;
1096 int ret;
1097
1098 ret = ov7670_read(sd, REG_MVFP, &v);
1099 if (value)
1100 v |= MVFP_FLIP;
1101 else
1102 v &= ~MVFP_FLIP;
1103 msleep(10); /* FIXME */
1104 ret += ov7670_write(sd, REG_MVFP, v);
1105 return ret;
1106 }
1107
1108 static int ov7670_queryctrl(struct v4l2_subdev *sd,
1109 struct v4l2_queryctrl *qc)
1110 {
1111 /* Fill in min, max, step and default value for these controls. */
1112 switch (qc->id) {
1113 case V4L2_CID_BRIGHTNESS:
1114 return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128);
1115 case V4L2_CID_CONTRAST:
1116 return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64);
1117 case V4L2_CID_VFLIP:
1118 case V4L2_CID_HFLIP:
1119 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1120 case V4L2_CID_SATURATION:
1121 return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128);
1122 case V4L2_CID_HUE:
1123 return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0);
1124 }
1125 return -EINVAL;
1126 }
1127
1128 static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1129 {
1130 switch (ctrl->id) {
1131 case V4L2_CID_BRIGHTNESS:
1132 return ov7670_g_brightness(sd, &ctrl->value);
1133 case V4L2_CID_CONTRAST:
1134 return ov7670_g_contrast(sd, &ctrl->value);
1135 case V4L2_CID_SATURATION:
1136 return ov7670_g_sat(sd, &ctrl->value);
1137 case V4L2_CID_HUE:
1138 return ov7670_g_hue(sd, &ctrl->value);
1139 case V4L2_CID_VFLIP:
1140 return ov7670_g_vflip(sd, &ctrl->value);
1141 case V4L2_CID_HFLIP:
1142 return ov7670_g_hflip(sd, &ctrl->value);
1143 }
1144 return -EINVAL;
1145 }
1146
1147 static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
1148 {
1149 switch (ctrl->id) {
1150 case V4L2_CID_BRIGHTNESS:
1151 return ov7670_s_brightness(sd, ctrl->value);
1152 case V4L2_CID_CONTRAST:
1153 return ov7670_s_contrast(sd, ctrl->value);
1154 case V4L2_CID_SATURATION:
1155 return ov7670_s_sat(sd, ctrl->value);
1156 case V4L2_CID_HUE:
1157 return ov7670_s_hue(sd, ctrl->value);
1158 case V4L2_CID_VFLIP:
1159 return ov7670_s_vflip(sd, ctrl->value);
1160 case V4L2_CID_HFLIP:
1161 return ov7670_s_hflip(sd, ctrl->value);
1162 }
1163 return -EINVAL;
1164 }
1165
1166 static int ov7670_g_chip_ident(struct v4l2_subdev *sd,
1167 struct v4l2_dbg_chip_ident *chip)
1168 {
1169 struct i2c_client *client = v4l2_get_subdevdata(sd);
1170
1171 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0);
1172 }
1173
1174 #ifdef CONFIG_VIDEO_ADV_DEBUG
1175 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1176 {
1177 struct i2c_client *client = v4l2_get_subdevdata(sd);
1178 unsigned char val = 0;
1179 int ret;
1180
1181 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1182 return -EINVAL;
1183 if (!capable(CAP_SYS_ADMIN))
1184 return -EPERM;
1185 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1186 reg->val = val;
1187 reg->size = 1;
1188 return ret;
1189 }
1190
1191 static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1192 {
1193 struct i2c_client *client = v4l2_get_subdevdata(sd);
1194
1195 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1196 return -EINVAL;
1197 if (!capable(CAP_SYS_ADMIN))
1198 return -EPERM;
1199 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1200 return 0;
1201 }
1202 #endif
1203
1204 /* ----------------------------------------------------------------------- */
1205
1206 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1207 .g_chip_ident = ov7670_g_chip_ident,
1208 .g_ctrl = ov7670_g_ctrl,
1209 .s_ctrl = ov7670_s_ctrl,
1210 .queryctrl = ov7670_queryctrl,
1211 .reset = ov7670_reset,
1212 .init = ov7670_init,
1213 #ifdef CONFIG_VIDEO_ADV_DEBUG
1214 .g_register = ov7670_g_register,
1215 .s_register = ov7670_s_register,
1216 #endif
1217 };
1218
1219 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1220 .enum_fmt = ov7670_enum_fmt,
1221 .try_fmt = ov7670_try_fmt,
1222 .s_fmt = ov7670_s_fmt,
1223 .s_parm = ov7670_s_parm,
1224 .g_parm = ov7670_g_parm,
1225 };
1226
1227 static const struct v4l2_subdev_ops ov7670_ops = {
1228 .core = &ov7670_core_ops,
1229 .video = &ov7670_video_ops,
1230 };
1231
1232 /* ----------------------------------------------------------------------- */
1233
1234 static int ov7670_probe(struct i2c_client *client,
1235 const struct i2c_device_id *id)
1236 {
1237 struct v4l2_subdev *sd;
1238 struct ov7670_info *info;
1239 int ret;
1240
1241 info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL);
1242 if (info == NULL)
1243 return -ENOMEM;
1244 sd = &info->sd;
1245 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1246
1247 /* Make sure it's an ov7670 */
1248 ret = ov7670_detect(sd);
1249 if (ret) {
1250 v4l_dbg(1, debug, client,
1251 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1252 client->addr << 1, client->adapter->name);
1253 kfree(info);
1254 return ret;
1255 }
1256 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1257 client->addr << 1, client->adapter->name);
1258
1259 info->fmt = &ov7670_formats[0];
1260 info->sat = 128; /* Review this */
1261 info->clkrc = 1; /* 30fps */
1262
1263 return 0;
1264 }
1265
1266
1267 static int ov7670_remove(struct i2c_client *client)
1268 {
1269 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1270
1271 v4l2_device_unregister_subdev(sd);
1272 kfree(to_state(sd));
1273 return 0;
1274 }
1275
1276 static const struct i2c_device_id ov7670_id[] = {
1277 { "ov7670", 0 },
1278 { }
1279 };
1280 MODULE_DEVICE_TABLE(i2c, ov7670_id);
1281
1282 static struct v4l2_i2c_driver_data v4l2_i2c_data = {
1283 .name = "ov7670",
1284 .probe = ov7670_probe,
1285 .remove = ov7670_remove,
1286 .id_table = ov7670_id,
1287 };
Linux kernel - Deliverables
This page took 0.072597 seconds and 5 git commands to generate.