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Merge branch 'x86/urgent' into x86/pat
[deliverable/linux.git] / drivers / media / video / pxa_camera.c
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/camera.h>
39
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
42
43 /* Camera Interface */
44 #define CICR0 0x0000
45 #define CICR1 0x0004
46 #define CICR2 0x0008
47 #define CICR3 0x000C
48 #define CICR4 0x0010
49 #define CISR 0x0014
50 #define CIFR 0x0018
51 #define CITOR 0x001C
52 #define CIBR0 0x0028
53 #define CIBR1 0x0030
54 #define CIBR2 0x0038
55
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
72
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
83
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
85 wait count mask */
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
87 wait count mask */
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
90 wait count mask */
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
92 wait count mask */
93
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
95 wait count mask */
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
97 wait count mask */
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
102
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
111
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
128
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
137
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
143
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
149
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
155
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
160
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
164
165 /*
166 * Structures
167 */
168 enum pxa_camera_active_dma {
169 DMA_Y = 0x1,
170 DMA_U = 0x2,
171 DMA_V = 0x4,
172 };
173
174 /* descriptor needed for the PXA DMA engine */
175 struct pxa_cam_dma {
176 dma_addr_t sg_dma;
177 struct pxa_dma_desc *sg_cpu;
178 size_t sg_size;
179 int sglen;
180 };
181
182 /* buffer for one video frame */
183 struct pxa_buffer {
184 /* common v4l buffer stuff -- must be first */
185 struct videobuf_buffer vb;
186
187 const struct soc_camera_data_format *fmt;
188
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
191
192 int inwork;
193
194 enum pxa_camera_active_dma active_dma;
195 };
196
197 struct pxa_camera_dev {
198 struct soc_camera_host soc_host;
199 /* PXA27x is only supposed to handle one camera on its Quick Capture
200 * interface. If anyone ever builds hardware to enable more than
201 * one camera, they will have to modify this driver too */
202 struct soc_camera_device *icd;
203 struct clk *clk;
204
205 unsigned int irq;
206 void __iomem *base;
207
208 int channels;
209 unsigned int dma_chans[3];
210
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
214 unsigned long ciclk;
215 unsigned long mclk;
216 u32 mclk_divisor;
217
218 struct list_head capture;
219
220 spinlock_t lock;
221
222 struct pxa_buffer *active;
223 struct pxa_dma_desc *sg_tail[3];
224
225 u32 save_cicr[5];
226 };
227
228 static const char *pxa_cam_driver_description = "PXA_Camera";
229
230 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
231
232 /*
233 * Videobuf operations
234 */
235 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
236 unsigned int *size)
237 {
238 struct soc_camera_device *icd = vq->priv_data;
239
240 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
241
242 *size = roundup(icd->width * icd->height *
243 ((icd->current_fmt->depth + 7) >> 3), 8);
244
245 if (0 == *count)
246 *count = 32;
247 while (*size * *count > vid_limit * 1024 * 1024)
248 (*count)--;
249
250 return 0;
251 }
252
253 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
254 {
255 struct soc_camera_device *icd = vq->priv_data;
256 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
257 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
258 int i;
259
260 BUG_ON(in_interrupt());
261
262 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
263 &buf->vb, buf->vb.baddr, buf->vb.bsize);
264
265 /* This waits until this buffer is out of danger, i.e., until it is no
266 * longer in STATE_QUEUED or STATE_ACTIVE */
267 videobuf_waiton(&buf->vb, 0, 0);
268 videobuf_dma_unmap(vq, dma);
269 videobuf_dma_free(dma);
270
271 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
272 if (buf->dmas[i].sg_cpu)
273 dma_free_coherent(ici->dev, buf->dmas[i].sg_size,
274 buf->dmas[i].sg_cpu,
275 buf->dmas[i].sg_dma);
276 buf->dmas[i].sg_cpu = NULL;
277 }
278
279 buf->vb.state = VIDEOBUF_NEEDS_INIT;
280 }
281
282 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
283 int sg_first_ofs, int size)
284 {
285 int i, offset, dma_len, xfer_len;
286 struct scatterlist *sg;
287
288 offset = sg_first_ofs;
289 for_each_sg(sglist, sg, sglen, i) {
290 dma_len = sg_dma_len(sg);
291
292 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
293 xfer_len = roundup(min(dma_len - offset, size), 8);
294
295 size = max(0, size - xfer_len);
296 offset = 0;
297 if (size == 0)
298 break;
299 }
300
301 BUG_ON(size != 0);
302 return i + 1;
303 }
304
305 /**
306 * pxa_init_dma_channel - init dma descriptors
307 * @pcdev: pxa camera device
308 * @buf: pxa buffer to find pxa dma channel
309 * @dma: dma video buffer
310 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
311 * @cibr: camera Receive Buffer Register
312 * @size: bytes to transfer
313 * @sg_first: first element of sg_list
314 * @sg_first_ofs: offset in first element of sg_list
315 *
316 * Prepares the pxa dma descriptors to transfer one camera channel.
317 * Beware sg_first and sg_first_ofs are both input and output parameters.
318 *
319 * Returns 0 or -ENOMEM if no coherent memory is available
320 */
321 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
322 struct pxa_buffer *buf,
323 struct videobuf_dmabuf *dma, int channel,
324 int cibr, int size,
325 struct scatterlist **sg_first, int *sg_first_ofs)
326 {
327 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
328 struct scatterlist *sg;
329 int i, offset, sglen;
330 int dma_len = 0, xfer_len = 0;
331
332 if (pxa_dma->sg_cpu)
333 dma_free_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
334 pxa_dma->sg_cpu, pxa_dma->sg_dma);
335
336 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
337 *sg_first_ofs, size);
338
339 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
340 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
341 &pxa_dma->sg_dma, GFP_KERNEL);
342 if (!pxa_dma->sg_cpu)
343 return -ENOMEM;
344
345 pxa_dma->sglen = sglen;
346 offset = *sg_first_ofs;
347
348 dev_dbg(pcdev->soc_host.dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
349 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
350
351
352 for_each_sg(*sg_first, sg, sglen, i) {
353 dma_len = sg_dma_len(sg);
354
355 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
356 xfer_len = roundup(min(dma_len - offset, size), 8);
357
358 size = max(0, size - xfer_len);
359
360 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
361 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
362 pxa_dma->sg_cpu[i].dcmd =
363 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
364 #ifdef DEBUG
365 if (!i)
366 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
367 #endif
368 pxa_dma->sg_cpu[i].ddadr =
369 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
370
371 dev_vdbg(pcdev->soc_host.dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
372 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
373 sg_dma_address(sg) + offset, xfer_len);
374 offset = 0;
375
376 if (size == 0)
377 break;
378 }
379
380 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
381 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
382
383 /*
384 * Handle 1 special case :
385 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
386 * to dma_len (end on PAGE boundary). In this case, the sg element
387 * for next plane should be the next after the last used to store the
388 * last scatter gather RAM page
389 */
390 if (xfer_len >= dma_len) {
391 *sg_first_ofs = xfer_len - dma_len;
392 *sg_first = sg_next(sg);
393 } else {
394 *sg_first_ofs = xfer_len;
395 *sg_first = sg;
396 }
397
398 return 0;
399 }
400
401 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
402 struct pxa_buffer *buf)
403 {
404 buf->active_dma = DMA_Y;
405 if (pcdev->channels == 3)
406 buf->active_dma |= DMA_U | DMA_V;
407 }
408
409 /*
410 * Please check the DMA prepared buffer structure in :
411 * Documentation/video4linux/pxa_camera.txt
412 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
413 * modification while DMA chain is running will work anyway.
414 */
415 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
416 struct videobuf_buffer *vb, enum v4l2_field field)
417 {
418 struct soc_camera_device *icd = vq->priv_data;
419 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
420 struct pxa_camera_dev *pcdev = ici->priv;
421 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
422 int ret;
423 int size_y, size_u = 0, size_v = 0;
424
425 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
426 vb, vb->baddr, vb->bsize);
427
428 /* Added list head initialization on alloc */
429 WARN_ON(!list_empty(&vb->queue));
430
431 #ifdef DEBUG
432 /* This can be useful if you want to see if we actually fill
433 * the buffer with something */
434 memset((void *)vb->baddr, 0xaa, vb->bsize);
435 #endif
436
437 BUG_ON(NULL == icd->current_fmt);
438
439 /* I think, in buf_prepare you only have to protect global data,
440 * the actual buffer is yours */
441 buf->inwork = 1;
442
443 if (buf->fmt != icd->current_fmt ||
444 vb->width != icd->width ||
445 vb->height != icd->height ||
446 vb->field != field) {
447 buf->fmt = icd->current_fmt;
448 vb->width = icd->width;
449 vb->height = icd->height;
450 vb->field = field;
451 vb->state = VIDEOBUF_NEEDS_INIT;
452 }
453
454 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
455 if (0 != vb->baddr && vb->bsize < vb->size) {
456 ret = -EINVAL;
457 goto out;
458 }
459
460 if (vb->state == VIDEOBUF_NEEDS_INIT) {
461 int size = vb->size;
462 int next_ofs = 0;
463 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
464 struct scatterlist *sg;
465
466 ret = videobuf_iolock(vq, vb, NULL);
467 if (ret)
468 goto fail;
469
470 if (pcdev->channels == 3) {
471 size_y = size / 2;
472 size_u = size_v = size / 4;
473 } else {
474 size_y = size;
475 }
476
477 sg = dma->sglist;
478
479 /* init DMA for Y channel */
480 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
481 &sg, &next_ofs);
482 if (ret) {
483 dev_err(pcdev->soc_host.dev,
484 "DMA initialization for Y/RGB failed\n");
485 goto fail;
486 }
487
488 /* init DMA for U channel */
489 if (size_u)
490 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
491 size_u, &sg, &next_ofs);
492 if (ret) {
493 dev_err(pcdev->soc_host.dev,
494 "DMA initialization for U failed\n");
495 goto fail_u;
496 }
497
498 /* init DMA for V channel */
499 if (size_v)
500 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
501 size_v, &sg, &next_ofs);
502 if (ret) {
503 dev_err(pcdev->soc_host.dev,
504 "DMA initialization for V failed\n");
505 goto fail_v;
506 }
507
508 vb->state = VIDEOBUF_PREPARED;
509 }
510
511 buf->inwork = 0;
512 pxa_videobuf_set_actdma(pcdev, buf);
513
514 return 0;
515
516 fail_v:
517 dma_free_coherent(pcdev->soc_host.dev, buf->dmas[1].sg_size,
518 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
519 fail_u:
520 dma_free_coherent(pcdev->soc_host.dev, buf->dmas[0].sg_size,
521 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
522 fail:
523 free_buffer(vq, buf);
524 out:
525 buf->inwork = 0;
526 return ret;
527 }
528
529 /**
530 * pxa_dma_start_channels - start DMA channel for active buffer
531 * @pcdev: pxa camera device
532 *
533 * Initialize DMA channels to the beginning of the active video buffer, and
534 * start these channels.
535 */
536 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
537 {
538 int i;
539 struct pxa_buffer *active;
540
541 active = pcdev->active;
542
543 for (i = 0; i < pcdev->channels; i++) {
544 dev_dbg(pcdev->soc_host.dev, "%s (channel=%d) ddadr=%08x\n", __func__,
545 i, active->dmas[i].sg_dma);
546 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
547 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
548 }
549 }
550
551 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
552 {
553 int i;
554
555 for (i = 0; i < pcdev->channels; i++) {
556 dev_dbg(pcdev->soc_host.dev, "%s (channel=%d)\n", __func__, i);
557 DCSR(pcdev->dma_chans[i]) = 0;
558 }
559 }
560
561 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
562 struct pxa_buffer *buf)
563 {
564 int i;
565 struct pxa_dma_desc *buf_last_desc;
566
567 for (i = 0; i < pcdev->channels; i++) {
568 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
569 buf_last_desc->ddadr = DDADR_STOP;
570
571 if (pcdev->sg_tail[i])
572 /* Link the new buffer to the old tail */
573 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
574
575 /* Update the channel tail */
576 pcdev->sg_tail[i] = buf_last_desc;
577 }
578 }
579
580 /**
581 * pxa_camera_start_capture - start video capturing
582 * @pcdev: camera device
583 *
584 * Launch capturing. DMA channels should not be active yet. They should get
585 * activated at the end of frame interrupt, to capture only whole frames, and
586 * never begin the capture of a partial frame.
587 */
588 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
589 {
590 unsigned long cicr0, cifr;
591
592 dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
593 /* Reset the FIFOs */
594 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
595 __raw_writel(cifr, pcdev->base + CIFR);
596 /* Enable End-Of-Frame Interrupt */
597 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
598 cicr0 &= ~CICR0_EOFM;
599 __raw_writel(cicr0, pcdev->base + CICR0);
600 }
601
602 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
603 {
604 unsigned long cicr0;
605
606 pxa_dma_stop_channels(pcdev);
607
608 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
609 __raw_writel(cicr0, pcdev->base + CICR0);
610
611 pcdev->active = NULL;
612 dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
613 }
614
615 static void pxa_videobuf_queue(struct videobuf_queue *vq,
616 struct videobuf_buffer *vb)
617 {
618 struct soc_camera_device *icd = vq->priv_data;
619 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
620 struct pxa_camera_dev *pcdev = ici->priv;
621 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
622 unsigned long flags;
623
624 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__,
625 vb, vb->baddr, vb->bsize, pcdev->active);
626
627 spin_lock_irqsave(&pcdev->lock, flags);
628
629 list_add_tail(&vb->queue, &pcdev->capture);
630
631 vb->state = VIDEOBUF_ACTIVE;
632 pxa_dma_add_tail_buf(pcdev, buf);
633
634 if (!pcdev->active)
635 pxa_camera_start_capture(pcdev);
636
637 spin_unlock_irqrestore(&pcdev->lock, flags);
638 }
639
640 static void pxa_videobuf_release(struct videobuf_queue *vq,
641 struct videobuf_buffer *vb)
642 {
643 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
644 #ifdef DEBUG
645 struct soc_camera_device *icd = vq->priv_data;
646
647 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
648 vb, vb->baddr, vb->bsize);
649
650 switch (vb->state) {
651 case VIDEOBUF_ACTIVE:
652 dev_dbg(&icd->dev, "%s (active)\n", __func__);
653 break;
654 case VIDEOBUF_QUEUED:
655 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
656 break;
657 case VIDEOBUF_PREPARED:
658 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
659 break;
660 default:
661 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
662 break;
663 }
664 #endif
665
666 free_buffer(vq, buf);
667 }
668
669 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
670 struct videobuf_buffer *vb,
671 struct pxa_buffer *buf)
672 {
673 int i;
674
675 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
676 list_del_init(&vb->queue);
677 vb->state = VIDEOBUF_DONE;
678 do_gettimeofday(&vb->ts);
679 vb->field_count++;
680 wake_up(&vb->done);
681 dev_dbg(pcdev->soc_host.dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
682
683 if (list_empty(&pcdev->capture)) {
684 pxa_camera_stop_capture(pcdev);
685 for (i = 0; i < pcdev->channels; i++)
686 pcdev->sg_tail[i] = NULL;
687 return;
688 }
689
690 pcdev->active = list_entry(pcdev->capture.next,
691 struct pxa_buffer, vb.queue);
692 }
693
694 /**
695 * pxa_camera_check_link_miss - check missed DMA linking
696 * @pcdev: camera device
697 *
698 * The DMA chaining is done with DMA running. This means a tiny temporal window
699 * remains, where a buffer is queued on the chain, while the chain is already
700 * stopped. This means the tailed buffer would never be transfered by DMA.
701 * This function restarts the capture for this corner case, where :
702 * - DADR() == DADDR_STOP
703 * - a videobuffer is queued on the pcdev->capture list
704 *
705 * Please check the "DMA hot chaining timeslice issue" in
706 * Documentation/video4linux/pxa_camera.txt
707 *
708 * Context: should only be called within the dma irq handler
709 */
710 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
711 {
712 int i, is_dma_stopped = 1;
713
714 for (i = 0; i < pcdev->channels; i++)
715 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
716 is_dma_stopped = 0;
717 dev_dbg(pcdev->soc_host.dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
718 __func__, pcdev->active, is_dma_stopped);
719 if (pcdev->active && is_dma_stopped)
720 pxa_camera_start_capture(pcdev);
721 }
722
723 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
724 enum pxa_camera_active_dma act_dma)
725 {
726 struct pxa_buffer *buf;
727 unsigned long flags;
728 u32 status, camera_status, overrun;
729 struct videobuf_buffer *vb;
730
731 spin_lock_irqsave(&pcdev->lock, flags);
732
733 status = DCSR(channel);
734 DCSR(channel) = status;
735
736 camera_status = __raw_readl(pcdev->base + CISR);
737 overrun = CISR_IFO_0;
738 if (pcdev->channels == 3)
739 overrun |= CISR_IFO_1 | CISR_IFO_2;
740
741 if (status & DCSR_BUSERR) {
742 dev_err(pcdev->soc_host.dev, "DMA Bus Error IRQ!\n");
743 goto out;
744 }
745
746 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
747 dev_err(pcdev->soc_host.dev, "Unknown DMA IRQ source, "
748 "status: 0x%08x\n", status);
749 goto out;
750 }
751
752 /*
753 * pcdev->active should not be NULL in DMA irq handler.
754 *
755 * But there is one corner case : if capture was stopped due to an
756 * overrun of channel 1, and at that same channel 2 was completed.
757 *
758 * When handling the overrun in DMA irq for channel 1, we'll stop the
759 * capture and restart it (and thus set pcdev->active to NULL). But the
760 * DMA irq handler will already be pending for channel 2. So on entering
761 * the DMA irq handler for channel 2 there will be no active buffer, yet
762 * that is normal.
763 */
764 if (!pcdev->active)
765 goto out;
766
767 vb = &pcdev->active->vb;
768 buf = container_of(vb, struct pxa_buffer, vb);
769 WARN_ON(buf->inwork || list_empty(&vb->queue));
770
771 dev_dbg(pcdev->soc_host.dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
772 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
773 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
774
775 if (status & DCSR_ENDINTR) {
776 /*
777 * It's normal if the last frame creates an overrun, as there
778 * are no more DMA descriptors to fetch from QCI fifos
779 */
780 if (camera_status & overrun &&
781 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
782 dev_dbg(pcdev->soc_host.dev, "FIFO overrun! CISR: %x\n",
783 camera_status);
784 pxa_camera_stop_capture(pcdev);
785 pxa_camera_start_capture(pcdev);
786 goto out;
787 }
788 buf->active_dma &= ~act_dma;
789 if (!buf->active_dma) {
790 pxa_camera_wakeup(pcdev, vb, buf);
791 pxa_camera_check_link_miss(pcdev);
792 }
793 }
794
795 out:
796 spin_unlock_irqrestore(&pcdev->lock, flags);
797 }
798
799 static void pxa_camera_dma_irq_y(int channel, void *data)
800 {
801 struct pxa_camera_dev *pcdev = data;
802 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
803 }
804
805 static void pxa_camera_dma_irq_u(int channel, void *data)
806 {
807 struct pxa_camera_dev *pcdev = data;
808 pxa_camera_dma_irq(channel, pcdev, DMA_U);
809 }
810
811 static void pxa_camera_dma_irq_v(int channel, void *data)
812 {
813 struct pxa_camera_dev *pcdev = data;
814 pxa_camera_dma_irq(channel, pcdev, DMA_V);
815 }
816
817 static struct videobuf_queue_ops pxa_videobuf_ops = {
818 .buf_setup = pxa_videobuf_setup,
819 .buf_prepare = pxa_videobuf_prepare,
820 .buf_queue = pxa_videobuf_queue,
821 .buf_release = pxa_videobuf_release,
822 };
823
824 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
825 struct soc_camera_device *icd)
826 {
827 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
828 struct pxa_camera_dev *pcdev = ici->priv;
829
830 /* We must pass NULL as dev pointer, then all pci_* dma operations
831 * transform to normal dma_* ones. */
832 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
833 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
834 sizeof(struct pxa_buffer), icd);
835 }
836
837 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
838 {
839 unsigned long mclk = pcdev->mclk;
840 u32 div;
841 unsigned long lcdclk;
842
843 lcdclk = clk_get_rate(pcdev->clk);
844 pcdev->ciclk = lcdclk;
845
846 /* mclk <= ciclk / 4 (27.4.2) */
847 if (mclk > lcdclk / 4) {
848 mclk = lcdclk / 4;
849 dev_warn(pcdev->soc_host.dev, "Limiting master clock to %lu\n", mclk);
850 }
851
852 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
853 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
854
855 /* If we're not supplying MCLK, leave it at 0 */
856 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
857 pcdev->mclk = lcdclk / (2 * (div + 1));
858
859 dev_dbg(pcdev->soc_host.dev, "LCD clock %luHz, target freq %luHz, "
860 "divisor %u\n", lcdclk, mclk, div);
861
862 return div;
863 }
864
865 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
866 unsigned long pclk)
867 {
868 /* We want a timeout > 1 pixel time, not ">=" */
869 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
870
871 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
872 }
873
874 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
875 {
876 struct pxacamera_platform_data *pdata = pcdev->pdata;
877 u32 cicr4 = 0;
878
879 dev_dbg(pcdev->soc_host.dev, "Registered platform device at %p data %p\n",
880 pcdev, pdata);
881
882 if (pdata && pdata->init) {
883 dev_dbg(pcdev->soc_host.dev, "%s: Init gpios\n", __func__);
884 pdata->init(pcdev->soc_host.dev);
885 }
886
887 /* disable all interrupts */
888 __raw_writel(0x3ff, pcdev->base + CICR0);
889
890 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
891 cicr4 |= CICR4_PCLK_EN;
892 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
893 cicr4 |= CICR4_MCLK_EN;
894 if (pcdev->platform_flags & PXA_CAMERA_PCP)
895 cicr4 |= CICR4_PCP;
896 if (pcdev->platform_flags & PXA_CAMERA_HSP)
897 cicr4 |= CICR4_HSP;
898 if (pcdev->platform_flags & PXA_CAMERA_VSP)
899 cicr4 |= CICR4_VSP;
900
901 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
902
903 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
904 /* Initialise the timeout under the assumption pclk = mclk */
905 recalculate_fifo_timeout(pcdev, pcdev->mclk);
906 else
907 /* "Safe default" - 13MHz */
908 recalculate_fifo_timeout(pcdev, 13000000);
909
910 clk_enable(pcdev->clk);
911 }
912
913 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
914 {
915 clk_disable(pcdev->clk);
916 }
917
918 static irqreturn_t pxa_camera_irq(int irq, void *data)
919 {
920 struct pxa_camera_dev *pcdev = data;
921 unsigned long status, cicr0;
922 struct pxa_buffer *buf;
923 struct videobuf_buffer *vb;
924
925 status = __raw_readl(pcdev->base + CISR);
926 dev_dbg(pcdev->soc_host.dev, "Camera interrupt status 0x%lx\n", status);
927
928 if (!status)
929 return IRQ_NONE;
930
931 __raw_writel(status, pcdev->base + CISR);
932
933 if (status & CISR_EOF) {
934 pcdev->active = list_first_entry(&pcdev->capture,
935 struct pxa_buffer, vb.queue);
936 vb = &pcdev->active->vb;
937 buf = container_of(vb, struct pxa_buffer, vb);
938 pxa_videobuf_set_actdma(pcdev, buf);
939
940 pxa_dma_start_channels(pcdev);
941
942 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
943 __raw_writel(cicr0, pcdev->base + CICR0);
944 }
945
946 return IRQ_HANDLED;
947 }
948
949 /*
950 * The following two functions absolutely depend on the fact, that
951 * there can be only one camera on PXA quick capture interface
952 * Called with .video_lock held
953 */
954 static int pxa_camera_add_device(struct soc_camera_device *icd)
955 {
956 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
957 struct pxa_camera_dev *pcdev = ici->priv;
958 int ret;
959
960 if (pcdev->icd) {
961 ret = -EBUSY;
962 goto ebusy;
963 }
964
965 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
966 icd->devnum);
967
968 pxa_camera_activate(pcdev);
969 ret = icd->ops->init(icd);
970
971 if (!ret)
972 pcdev->icd = icd;
973
974 ebusy:
975 return ret;
976 }
977
978 /* Called with .video_lock held */
979 static void pxa_camera_remove_device(struct soc_camera_device *icd)
980 {
981 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
982 struct pxa_camera_dev *pcdev = ici->priv;
983
984 BUG_ON(icd != pcdev->icd);
985
986 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
987 icd->devnum);
988
989 /* disable capture, disable interrupts */
990 __raw_writel(0x3ff, pcdev->base + CICR0);
991
992 /* Stop DMA engine */
993 DCSR(pcdev->dma_chans[0]) = 0;
994 DCSR(pcdev->dma_chans[1]) = 0;
995 DCSR(pcdev->dma_chans[2]) = 0;
996
997 icd->ops->release(icd);
998
999 pxa_camera_deactivate(pcdev);
1000
1001 pcdev->icd = NULL;
1002 }
1003
1004 static int test_platform_param(struct pxa_camera_dev *pcdev,
1005 unsigned char buswidth, unsigned long *flags)
1006 {
1007 /*
1008 * Platform specified synchronization and pixel clock polarities are
1009 * only a recommendation and are only used during probing. The PXA270
1010 * quick capture interface supports both.
1011 */
1012 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1013 SOCAM_MASTER : SOCAM_SLAVE) |
1014 SOCAM_HSYNC_ACTIVE_HIGH |
1015 SOCAM_HSYNC_ACTIVE_LOW |
1016 SOCAM_VSYNC_ACTIVE_HIGH |
1017 SOCAM_VSYNC_ACTIVE_LOW |
1018 SOCAM_DATA_ACTIVE_HIGH |
1019 SOCAM_PCLK_SAMPLE_RISING |
1020 SOCAM_PCLK_SAMPLE_FALLING;
1021
1022 /* If requested data width is supported by the platform, use it */
1023 switch (buswidth) {
1024 case 10:
1025 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1026 return -EINVAL;
1027 *flags |= SOCAM_DATAWIDTH_10;
1028 break;
1029 case 9:
1030 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1031 return -EINVAL;
1032 *flags |= SOCAM_DATAWIDTH_9;
1033 break;
1034 case 8:
1035 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1036 return -EINVAL;
1037 *flags |= SOCAM_DATAWIDTH_8;
1038 break;
1039 default:
1040 return -EINVAL;
1041 }
1042
1043 return 0;
1044 }
1045
1046 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1047 {
1048 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1049 struct pxa_camera_dev *pcdev = ici->priv;
1050 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1051 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1052 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1053
1054 if (ret < 0)
1055 return ret;
1056
1057 camera_flags = icd->ops->query_bus_param(icd);
1058
1059 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1060 if (!common_flags)
1061 return -EINVAL;
1062
1063 pcdev->channels = 1;
1064
1065 /* Make choises, based on platform preferences */
1066 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1067 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1068 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1069 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1070 else
1071 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1072 }
1073
1074 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1075 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1076 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1077 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1078 else
1079 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1080 }
1081
1082 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1083 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1084 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1085 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1086 else
1087 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1088 }
1089
1090 ret = icd->ops->set_bus_param(icd, common_flags);
1091 if (ret < 0)
1092 return ret;
1093
1094 /* Datawidth is now guaranteed to be equal to one of the three values.
1095 * We fix bit-per-pixel equal to data-width... */
1096 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1097 case SOCAM_DATAWIDTH_10:
1098 dw = 4;
1099 bpp = 0x40;
1100 break;
1101 case SOCAM_DATAWIDTH_9:
1102 dw = 3;
1103 bpp = 0x20;
1104 break;
1105 default:
1106 /* Actually it can only be 8 now,
1107 * default is just to silence compiler warnings */
1108 case SOCAM_DATAWIDTH_8:
1109 dw = 2;
1110 bpp = 0;
1111 }
1112
1113 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1114 cicr4 |= CICR4_PCLK_EN;
1115 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1116 cicr4 |= CICR4_MCLK_EN;
1117 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1118 cicr4 |= CICR4_PCP;
1119 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1120 cicr4 |= CICR4_HSP;
1121 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1122 cicr4 |= CICR4_VSP;
1123
1124 cicr0 = __raw_readl(pcdev->base + CICR0);
1125 if (cicr0 & CICR0_ENB)
1126 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1127
1128 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1129
1130 switch (pixfmt) {
1131 case V4L2_PIX_FMT_YUV422P:
1132 pcdev->channels = 3;
1133 cicr1 |= CICR1_YCBCR_F;
1134 /*
1135 * Normally, pxa bus wants as input UYVY format. We allow all
1136 * reorderings of the YUV422 format, as no processing is done,
1137 * and the YUV stream is just passed through without any
1138 * transformation. Note that UYVY is the only format that
1139 * should be used if pxa framebuffer Overlay2 is used.
1140 */
1141 case V4L2_PIX_FMT_UYVY:
1142 case V4L2_PIX_FMT_VYUY:
1143 case V4L2_PIX_FMT_YUYV:
1144 case V4L2_PIX_FMT_YVYU:
1145 cicr1 |= CICR1_COLOR_SP_VAL(2);
1146 break;
1147 case V4L2_PIX_FMT_RGB555:
1148 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1149 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1150 break;
1151 case V4L2_PIX_FMT_RGB565:
1152 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1153 break;
1154 }
1155
1156 cicr2 = 0;
1157 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1158 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1159 cicr4 |= pcdev->mclk_divisor;
1160
1161 __raw_writel(cicr1, pcdev->base + CICR1);
1162 __raw_writel(cicr2, pcdev->base + CICR2);
1163 __raw_writel(cicr3, pcdev->base + CICR3);
1164 __raw_writel(cicr4, pcdev->base + CICR4);
1165
1166 /* CIF interrupts are not used, only DMA */
1167 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1168 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1169 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1170 __raw_writel(cicr0, pcdev->base + CICR0);
1171
1172 return 0;
1173 }
1174
1175 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1176 unsigned char buswidth)
1177 {
1178 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1179 struct pxa_camera_dev *pcdev = ici->priv;
1180 unsigned long bus_flags, camera_flags;
1181 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1182
1183 if (ret < 0)
1184 return ret;
1185
1186 camera_flags = icd->ops->query_bus_param(icd);
1187
1188 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1189 }
1190
1191 static const struct soc_camera_data_format pxa_camera_formats[] = {
1192 {
1193 .name = "Planar YUV422 16 bit",
1194 .depth = 16,
1195 .fourcc = V4L2_PIX_FMT_YUV422P,
1196 .colorspace = V4L2_COLORSPACE_JPEG,
1197 },
1198 };
1199
1200 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1201 {
1202 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1203 struct pxa_camera_dev *pcdev = ici->priv;
1204
1205 switch (depth) {
1206 case 8:
1207 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1208 case 9:
1209 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1210 case 10:
1211 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1212 }
1213 return false;
1214 }
1215
1216 static int required_buswidth(const struct soc_camera_data_format *fmt)
1217 {
1218 switch (fmt->fourcc) {
1219 case V4L2_PIX_FMT_UYVY:
1220 case V4L2_PIX_FMT_VYUY:
1221 case V4L2_PIX_FMT_YUYV:
1222 case V4L2_PIX_FMT_YVYU:
1223 case V4L2_PIX_FMT_RGB565:
1224 case V4L2_PIX_FMT_RGB555:
1225 return 8;
1226 default:
1227 return fmt->depth;
1228 }
1229 }
1230
1231 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1232 struct soc_camera_format_xlate *xlate)
1233 {
1234 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1235 int formats = 0, buswidth, ret;
1236
1237 buswidth = required_buswidth(icd->formats + idx);
1238
1239 if (!buswidth_supported(icd, buswidth))
1240 return 0;
1241
1242 ret = pxa_camera_try_bus_param(icd, buswidth);
1243 if (ret < 0)
1244 return 0;
1245
1246 switch (icd->formats[idx].fourcc) {
1247 case V4L2_PIX_FMT_UYVY:
1248 formats++;
1249 if (xlate) {
1250 xlate->host_fmt = &pxa_camera_formats[0];
1251 xlate->cam_fmt = icd->formats + idx;
1252 xlate->buswidth = buswidth;
1253 xlate++;
1254 dev_dbg(ici->dev, "Providing format %s using %s\n",
1255 pxa_camera_formats[0].name,
1256 icd->formats[idx].name);
1257 }
1258 case V4L2_PIX_FMT_VYUY:
1259 case V4L2_PIX_FMT_YUYV:
1260 case V4L2_PIX_FMT_YVYU:
1261 case V4L2_PIX_FMT_RGB565:
1262 case V4L2_PIX_FMT_RGB555:
1263 formats++;
1264 if (xlate) {
1265 xlate->host_fmt = icd->formats + idx;
1266 xlate->cam_fmt = icd->formats + idx;
1267 xlate->buswidth = buswidth;
1268 xlate++;
1269 dev_dbg(ici->dev, "Providing format %s packed\n",
1270 icd->formats[idx].name);
1271 }
1272 break;
1273 default:
1274 /* Generic pass-through */
1275 formats++;
1276 if (xlate) {
1277 xlate->host_fmt = icd->formats + idx;
1278 xlate->cam_fmt = icd->formats + idx;
1279 xlate->buswidth = icd->formats[idx].depth;
1280 xlate++;
1281 dev_dbg(ici->dev,
1282 "Providing format %s in pass-through mode\n",
1283 icd->formats[idx].name);
1284 }
1285 }
1286
1287 return formats;
1288 }
1289
1290 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1291 struct v4l2_rect *rect)
1292 {
1293 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1294 struct pxa_camera_dev *pcdev = ici->priv;
1295 struct soc_camera_sense sense = {
1296 .master_clock = pcdev->mclk,
1297 .pixel_clock_max = pcdev->ciclk / 4,
1298 };
1299 int ret;
1300
1301 /* If PCLK is used to latch data from the sensor, check sense */
1302 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1303 icd->sense = &sense;
1304
1305 ret = icd->ops->set_crop(icd, rect);
1306
1307 icd->sense = NULL;
1308
1309 if (ret < 0) {
1310 dev_warn(ici->dev, "Failed to crop to %ux%u@%u:%u\n",
1311 rect->width, rect->height, rect->left, rect->top);
1312 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1313 if (sense.pixel_clock > sense.pixel_clock_max) {
1314 dev_err(ici->dev,
1315 "pixel clock %lu set by the camera too high!",
1316 sense.pixel_clock);
1317 return -EIO;
1318 }
1319 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1320 }
1321
1322 return ret;
1323 }
1324
1325 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1326 struct v4l2_format *f)
1327 {
1328 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1329 struct pxa_camera_dev *pcdev = ici->priv;
1330 const struct soc_camera_data_format *cam_fmt = NULL;
1331 const struct soc_camera_format_xlate *xlate = NULL;
1332 struct soc_camera_sense sense = {
1333 .master_clock = pcdev->mclk,
1334 .pixel_clock_max = pcdev->ciclk / 4,
1335 };
1336 struct v4l2_pix_format *pix = &f->fmt.pix;
1337 struct v4l2_format cam_f = *f;
1338 int ret;
1339
1340 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1341 if (!xlate) {
1342 dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat);
1343 return -EINVAL;
1344 }
1345
1346 cam_fmt = xlate->cam_fmt;
1347
1348 /* If PCLK is used to latch data from the sensor, check sense */
1349 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1350 icd->sense = &sense;
1351
1352 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1353 ret = icd->ops->set_fmt(icd, &cam_f);
1354
1355 icd->sense = NULL;
1356
1357 if (ret < 0) {
1358 dev_warn(ici->dev, "Failed to configure for format %x\n",
1359 pix->pixelformat);
1360 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1361 if (sense.pixel_clock > sense.pixel_clock_max) {
1362 dev_err(ici->dev,
1363 "pixel clock %lu set by the camera too high!",
1364 sense.pixel_clock);
1365 return -EIO;
1366 }
1367 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1368 }
1369
1370 if (!ret) {
1371 icd->buswidth = xlate->buswidth;
1372 icd->current_fmt = xlate->host_fmt;
1373 }
1374
1375 return ret;
1376 }
1377
1378 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1379 struct v4l2_format *f)
1380 {
1381 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1382 const struct soc_camera_format_xlate *xlate;
1383 struct v4l2_pix_format *pix = &f->fmt.pix;
1384 __u32 pixfmt = pix->pixelformat;
1385 enum v4l2_field field;
1386 int ret;
1387
1388 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1389 if (!xlate) {
1390 dev_warn(ici->dev, "Format %x not found\n", pixfmt);
1391 return -EINVAL;
1392 }
1393
1394 /*
1395 * Limit to pxa hardware capabilities. YUV422P planar format requires
1396 * images size to be a multiple of 16 bytes. If not, zeros will be
1397 * inserted between Y and U planes, and U and V planes, which violates
1398 * the YUV422P standard.
1399 */
1400 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1401 &pix->height, 32, 2048, 0,
1402 xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1403
1404 pix->bytesperline = pix->width *
1405 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1406 pix->sizeimage = pix->height * pix->bytesperline;
1407
1408 /* camera has to see its format, but the user the original one */
1409 pix->pixelformat = xlate->cam_fmt->fourcc;
1410 /* limit to sensor capabilities */
1411 ret = icd->ops->try_fmt(icd, f);
1412 pix->pixelformat = xlate->host_fmt->fourcc;
1413
1414 field = pix->field;
1415
1416 if (field == V4L2_FIELD_ANY) {
1417 pix->field = V4L2_FIELD_NONE;
1418 } else if (field != V4L2_FIELD_NONE) {
1419 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1420 return -EINVAL;
1421 }
1422
1423 return ret;
1424 }
1425
1426 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1427 struct v4l2_requestbuffers *p)
1428 {
1429 int i;
1430
1431 /* This is for locking debugging only. I removed spinlocks and now I
1432 * check whether .prepare is ever called on a linked buffer, or whether
1433 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1434 * it hadn't triggered */
1435 for (i = 0; i < p->count; i++) {
1436 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1437 struct pxa_buffer, vb);
1438 buf->inwork = 0;
1439 INIT_LIST_HEAD(&buf->vb.queue);
1440 }
1441
1442 return 0;
1443 }
1444
1445 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1446 {
1447 struct soc_camera_file *icf = file->private_data;
1448 struct pxa_buffer *buf;
1449
1450 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1451 vb.stream);
1452
1453 poll_wait(file, &buf->vb.done, pt);
1454
1455 if (buf->vb.state == VIDEOBUF_DONE ||
1456 buf->vb.state == VIDEOBUF_ERROR)
1457 return POLLIN|POLLRDNORM;
1458
1459 return 0;
1460 }
1461
1462 static int pxa_camera_querycap(struct soc_camera_host *ici,
1463 struct v4l2_capability *cap)
1464 {
1465 /* cap->name is set by the firendly caller:-> */
1466 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1467 cap->version = PXA_CAM_VERSION_CODE;
1468 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1469
1470 return 0;
1471 }
1472
1473 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1474 {
1475 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1476 struct pxa_camera_dev *pcdev = ici->priv;
1477 int i = 0, ret = 0;
1478
1479 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1480 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1481 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1482 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1483 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1484
1485 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1486 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1487
1488 return ret;
1489 }
1490
1491 static int pxa_camera_resume(struct soc_camera_device *icd)
1492 {
1493 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1494 struct pxa_camera_dev *pcdev = ici->priv;
1495 int i = 0, ret = 0;
1496
1497 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1498 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1499 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1500
1501 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1502 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1503 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1504 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1505 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1506
1507 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1508 ret = pcdev->icd->ops->resume(pcdev->icd);
1509
1510 /* Restart frame capture if active buffer exists */
1511 if (!ret && pcdev->active)
1512 pxa_camera_start_capture(pcdev);
1513
1514 return ret;
1515 }
1516
1517 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1518 .owner = THIS_MODULE,
1519 .add = pxa_camera_add_device,
1520 .remove = pxa_camera_remove_device,
1521 .suspend = pxa_camera_suspend,
1522 .resume = pxa_camera_resume,
1523 .set_crop = pxa_camera_set_crop,
1524 .get_formats = pxa_camera_get_formats,
1525 .set_fmt = pxa_camera_set_fmt,
1526 .try_fmt = pxa_camera_try_fmt,
1527 .init_videobuf = pxa_camera_init_videobuf,
1528 .reqbufs = pxa_camera_reqbufs,
1529 .poll = pxa_camera_poll,
1530 .querycap = pxa_camera_querycap,
1531 .set_bus_param = pxa_camera_set_bus_param,
1532 };
1533
1534 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1535 {
1536 struct pxa_camera_dev *pcdev;
1537 struct resource *res;
1538 void __iomem *base;
1539 int irq;
1540 int err = 0;
1541
1542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1543 irq = platform_get_irq(pdev, 0);
1544 if (!res || irq < 0) {
1545 err = -ENODEV;
1546 goto exit;
1547 }
1548
1549 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1550 if (!pcdev) {
1551 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1552 err = -ENOMEM;
1553 goto exit;
1554 }
1555
1556 pcdev->clk = clk_get(&pdev->dev, NULL);
1557 if (IS_ERR(pcdev->clk)) {
1558 err = PTR_ERR(pcdev->clk);
1559 goto exit_kfree;
1560 }
1561
1562 pcdev->res = res;
1563
1564 pcdev->pdata = pdev->dev.platform_data;
1565 pcdev->platform_flags = pcdev->pdata->flags;
1566 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1567 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1568 /* Platform hasn't set available data widths. This is bad.
1569 * Warn and use a default. */
1570 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1571 "data widths, using default 10 bit\n");
1572 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1573 }
1574 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1575 if (!pcdev->mclk) {
1576 dev_warn(&pdev->dev,
1577 "mclk == 0! Please, fix your platform data. "
1578 "Using default 20MHz\n");
1579 pcdev->mclk = 20000000;
1580 }
1581
1582 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1583
1584 INIT_LIST_HEAD(&pcdev->capture);
1585 spin_lock_init(&pcdev->lock);
1586
1587 /*
1588 * Request the regions.
1589 */
1590 if (!request_mem_region(res->start, resource_size(res),
1591 PXA_CAM_DRV_NAME)) {
1592 err = -EBUSY;
1593 goto exit_clk;
1594 }
1595
1596 base = ioremap(res->start, resource_size(res));
1597 if (!base) {
1598 err = -ENOMEM;
1599 goto exit_release;
1600 }
1601 pcdev->irq = irq;
1602 pcdev->base = base;
1603
1604 /* request dma */
1605 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1606 pxa_camera_dma_irq_y, pcdev);
1607 if (err < 0) {
1608 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1609 goto exit_iounmap;
1610 }
1611 pcdev->dma_chans[0] = err;
1612 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1613
1614 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1615 pxa_camera_dma_irq_u, pcdev);
1616 if (err < 0) {
1617 dev_err(&pdev->dev, "Can't request DMA for U\n");
1618 goto exit_free_dma_y;
1619 }
1620 pcdev->dma_chans[1] = err;
1621 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1622
1623 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1624 pxa_camera_dma_irq_v, pcdev);
1625 if (err < 0) {
1626 dev_err(&pdev->dev, "Can't request DMA for V\n");
1627 goto exit_free_dma_u;
1628 }
1629 pcdev->dma_chans[2] = err;
1630 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1631
1632 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1633 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1634 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1635
1636 /* request irq */
1637 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1638 pcdev);
1639 if (err) {
1640 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1641 goto exit_free_dma;
1642 }
1643
1644 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1645 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1646 pcdev->soc_host.priv = pcdev;
1647 pcdev->soc_host.dev = &pdev->dev;
1648 pcdev->soc_host.nr = pdev->id;
1649
1650 err = soc_camera_host_register(&pcdev->soc_host);
1651 if (err)
1652 goto exit_free_irq;
1653
1654 return 0;
1655
1656 exit_free_irq:
1657 free_irq(pcdev->irq, pcdev);
1658 exit_free_dma:
1659 pxa_free_dma(pcdev->dma_chans[2]);
1660 exit_free_dma_u:
1661 pxa_free_dma(pcdev->dma_chans[1]);
1662 exit_free_dma_y:
1663 pxa_free_dma(pcdev->dma_chans[0]);
1664 exit_iounmap:
1665 iounmap(base);
1666 exit_release:
1667 release_mem_region(res->start, resource_size(res));
1668 exit_clk:
1669 clk_put(pcdev->clk);
1670 exit_kfree:
1671 kfree(pcdev);
1672 exit:
1673 return err;
1674 }
1675
1676 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1677 {
1678 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1679 struct pxa_camera_dev *pcdev = container_of(soc_host,
1680 struct pxa_camera_dev, soc_host);
1681 struct resource *res;
1682
1683 clk_put(pcdev->clk);
1684
1685 pxa_free_dma(pcdev->dma_chans[0]);
1686 pxa_free_dma(pcdev->dma_chans[1]);
1687 pxa_free_dma(pcdev->dma_chans[2]);
1688 free_irq(pcdev->irq, pcdev);
1689
1690 soc_camera_host_unregister(soc_host);
1691
1692 iounmap(pcdev->base);
1693
1694 res = pcdev->res;
1695 release_mem_region(res->start, resource_size(res));
1696
1697 kfree(pcdev);
1698
1699 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1700
1701 return 0;
1702 }
1703
1704 static struct platform_driver pxa_camera_driver = {
1705 .driver = {
1706 .name = PXA_CAM_DRV_NAME,
1707 },
1708 .probe = pxa_camera_probe,
1709 .remove = __devexit_p(pxa_camera_remove),
1710 };
1711
1712
1713 static int __init pxa_camera_init(void)
1714 {
1715 return platform_driver_register(&pxa_camera_driver);
1716 }
1717
1718 static void __exit pxa_camera_exit(void)
1719 {
1720 platform_driver_unregister(&pxa_camera_driver);
1721 }
1722
1723 module_init(pxa_camera_init);
1724 module_exit(pxa_camera_exit);
1725
1726 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1727 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1728 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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