2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/camera.h>
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43 /* Camera Interface */
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
168 enum pxa_camera_active_dma
{
174 /* descriptor needed for the PXA DMA engine */
177 struct pxa_dma_desc
*sg_cpu
;
182 /* buffer for one video frame */
184 /* common v4l buffer stuff -- must be first */
185 struct videobuf_buffer vb
;
187 const struct soc_camera_data_format
*fmt
;
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas
[3];
194 enum pxa_camera_active_dma active_dma
;
197 struct pxa_camera_dev
{
198 struct soc_camera_host soc_host
;
199 /* PXA27x is only supposed to handle one camera on its Quick Capture
200 * interface. If anyone ever builds hardware to enable more than
201 * one camera, they will have to modify this driver too */
202 struct soc_camera_device
*icd
;
209 unsigned int dma_chans
[3];
211 struct pxacamera_platform_data
*pdata
;
212 struct resource
*res
;
213 unsigned long platform_flags
;
218 struct list_head capture
;
222 struct pxa_buffer
*active
;
223 struct pxa_dma_desc
*sg_tail
[3];
228 static const char *pxa_cam_driver_description
= "PXA_Camera";
230 static unsigned int vid_limit
= 16; /* Video memory limit, in Mb */
233 * Videobuf operations
235 static int pxa_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
238 struct soc_camera_device
*icd
= vq
->priv_data
;
240 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
242 *size
= roundup(icd
->width
* icd
->height
*
243 ((icd
->current_fmt
->depth
+ 7) >> 3), 8);
247 while (*size
* *count
> vid_limit
* 1024 * 1024)
253 static void free_buffer(struct videobuf_queue
*vq
, struct pxa_buffer
*buf
)
255 struct soc_camera_device
*icd
= vq
->priv_data
;
256 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
257 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
260 BUG_ON(in_interrupt());
262 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
263 &buf
->vb
, buf
->vb
.baddr
, buf
->vb
.bsize
);
265 /* This waits until this buffer is out of danger, i.e., until it is no
266 * longer in STATE_QUEUED or STATE_ACTIVE */
267 videobuf_waiton(&buf
->vb
, 0, 0);
268 videobuf_dma_unmap(vq
, dma
);
269 videobuf_dma_free(dma
);
271 for (i
= 0; i
< ARRAY_SIZE(buf
->dmas
); i
++) {
272 if (buf
->dmas
[i
].sg_cpu
)
273 dma_free_coherent(ici
->dev
, buf
->dmas
[i
].sg_size
,
275 buf
->dmas
[i
].sg_dma
);
276 buf
->dmas
[i
].sg_cpu
= NULL
;
279 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
282 static int calculate_dma_sglen(struct scatterlist
*sglist
, int sglen
,
283 int sg_first_ofs
, int size
)
285 int i
, offset
, dma_len
, xfer_len
;
286 struct scatterlist
*sg
;
288 offset
= sg_first_ofs
;
289 for_each_sg(sglist
, sg
, sglen
, i
) {
290 dma_len
= sg_dma_len(sg
);
292 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
293 xfer_len
= roundup(min(dma_len
- offset
, size
), 8);
295 size
= max(0, size
- xfer_len
);
306 * pxa_init_dma_channel - init dma descriptors
307 * @pcdev: pxa camera device
308 * @buf: pxa buffer to find pxa dma channel
309 * @dma: dma video buffer
310 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
311 * @cibr: camera Receive Buffer Register
312 * @size: bytes to transfer
313 * @sg_first: first element of sg_list
314 * @sg_first_ofs: offset in first element of sg_list
316 * Prepares the pxa dma descriptors to transfer one camera channel.
317 * Beware sg_first and sg_first_ofs are both input and output parameters.
319 * Returns 0 or -ENOMEM if no coherent memory is available
321 static int pxa_init_dma_channel(struct pxa_camera_dev
*pcdev
,
322 struct pxa_buffer
*buf
,
323 struct videobuf_dmabuf
*dma
, int channel
,
325 struct scatterlist
**sg_first
, int *sg_first_ofs
)
327 struct pxa_cam_dma
*pxa_dma
= &buf
->dmas
[channel
];
328 struct scatterlist
*sg
;
329 int i
, offset
, sglen
;
330 int dma_len
= 0, xfer_len
= 0;
333 dma_free_coherent(pcdev
->soc_host
.dev
, pxa_dma
->sg_size
,
334 pxa_dma
->sg_cpu
, pxa_dma
->sg_dma
);
336 sglen
= calculate_dma_sglen(*sg_first
, dma
->sglen
,
337 *sg_first_ofs
, size
);
339 pxa_dma
->sg_size
= (sglen
+ 1) * sizeof(struct pxa_dma_desc
);
340 pxa_dma
->sg_cpu
= dma_alloc_coherent(pcdev
->soc_host
.dev
, pxa_dma
->sg_size
,
341 &pxa_dma
->sg_dma
, GFP_KERNEL
);
342 if (!pxa_dma
->sg_cpu
)
345 pxa_dma
->sglen
= sglen
;
346 offset
= *sg_first_ofs
;
348 dev_dbg(pcdev
->soc_host
.dev
, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
349 *sg_first
, sglen
, *sg_first_ofs
, pxa_dma
->sg_dma
);
352 for_each_sg(*sg_first
, sg
, sglen
, i
) {
353 dma_len
= sg_dma_len(sg
);
355 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
356 xfer_len
= roundup(min(dma_len
- offset
, size
), 8);
358 size
= max(0, size
- xfer_len
);
360 pxa_dma
->sg_cpu
[i
].dsadr
= pcdev
->res
->start
+ cibr
;
361 pxa_dma
->sg_cpu
[i
].dtadr
= sg_dma_address(sg
) + offset
;
362 pxa_dma
->sg_cpu
[i
].dcmd
=
363 DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_INCTRGADDR
| xfer_len
;
366 pxa_dma
->sg_cpu
[i
].dcmd
|= DCMD_STARTIRQEN
;
368 pxa_dma
->sg_cpu
[i
].ddadr
=
369 pxa_dma
->sg_dma
+ (i
+ 1) * sizeof(struct pxa_dma_desc
);
371 dev_vdbg(pcdev
->soc_host
.dev
, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
372 pxa_dma
->sg_dma
+ i
* sizeof(struct pxa_dma_desc
),
373 sg_dma_address(sg
) + offset
, xfer_len
);
380 pxa_dma
->sg_cpu
[sglen
].ddadr
= DDADR_STOP
;
381 pxa_dma
->sg_cpu
[sglen
].dcmd
= DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_ENDIRQEN
;
384 * Handle 1 special case :
385 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
386 * to dma_len (end on PAGE boundary). In this case, the sg element
387 * for next plane should be the next after the last used to store the
388 * last scatter gather RAM page
390 if (xfer_len
>= dma_len
) {
391 *sg_first_ofs
= xfer_len
- dma_len
;
392 *sg_first
= sg_next(sg
);
394 *sg_first_ofs
= xfer_len
;
401 static void pxa_videobuf_set_actdma(struct pxa_camera_dev
*pcdev
,
402 struct pxa_buffer
*buf
)
404 buf
->active_dma
= DMA_Y
;
405 if (pcdev
->channels
== 3)
406 buf
->active_dma
|= DMA_U
| DMA_V
;
410 * Please check the DMA prepared buffer structure in :
411 * Documentation/video4linux/pxa_camera.txt
412 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
413 * modification while DMA chain is running will work anyway.
415 static int pxa_videobuf_prepare(struct videobuf_queue
*vq
,
416 struct videobuf_buffer
*vb
, enum v4l2_field field
)
418 struct soc_camera_device
*icd
= vq
->priv_data
;
419 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
420 struct pxa_camera_dev
*pcdev
= ici
->priv
;
421 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
423 int size_y
, size_u
= 0, size_v
= 0;
425 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
426 vb
, vb
->baddr
, vb
->bsize
);
428 /* Added list head initialization on alloc */
429 WARN_ON(!list_empty(&vb
->queue
));
432 /* This can be useful if you want to see if we actually fill
433 * the buffer with something */
434 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
437 BUG_ON(NULL
== icd
->current_fmt
);
439 /* I think, in buf_prepare you only have to protect global data,
440 * the actual buffer is yours */
443 if (buf
->fmt
!= icd
->current_fmt
||
444 vb
->width
!= icd
->width
||
445 vb
->height
!= icd
->height
||
446 vb
->field
!= field
) {
447 buf
->fmt
= icd
->current_fmt
;
448 vb
->width
= icd
->width
;
449 vb
->height
= icd
->height
;
451 vb
->state
= VIDEOBUF_NEEDS_INIT
;
454 vb
->size
= vb
->width
* vb
->height
* ((buf
->fmt
->depth
+ 7) >> 3);
455 if (0 != vb
->baddr
&& vb
->bsize
< vb
->size
) {
460 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
463 struct videobuf_dmabuf
*dma
= videobuf_to_dma(vb
);
464 struct scatterlist
*sg
;
466 ret
= videobuf_iolock(vq
, vb
, NULL
);
470 if (pcdev
->channels
== 3) {
472 size_u
= size_v
= size
/ 4;
479 /* init DMA for Y channel */
480 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 0, CIBR0
, size_y
,
483 dev_err(pcdev
->soc_host
.dev
,
484 "DMA initialization for Y/RGB failed\n");
488 /* init DMA for U channel */
490 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 1, CIBR1
,
491 size_u
, &sg
, &next_ofs
);
493 dev_err(pcdev
->soc_host
.dev
,
494 "DMA initialization for U failed\n");
498 /* init DMA for V channel */
500 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 2, CIBR2
,
501 size_v
, &sg
, &next_ofs
);
503 dev_err(pcdev
->soc_host
.dev
,
504 "DMA initialization for V failed\n");
508 vb
->state
= VIDEOBUF_PREPARED
;
512 pxa_videobuf_set_actdma(pcdev
, buf
);
517 dma_free_coherent(pcdev
->soc_host
.dev
, buf
->dmas
[1].sg_size
,
518 buf
->dmas
[1].sg_cpu
, buf
->dmas
[1].sg_dma
);
520 dma_free_coherent(pcdev
->soc_host
.dev
, buf
->dmas
[0].sg_size
,
521 buf
->dmas
[0].sg_cpu
, buf
->dmas
[0].sg_dma
);
523 free_buffer(vq
, buf
);
530 * pxa_dma_start_channels - start DMA channel for active buffer
531 * @pcdev: pxa camera device
533 * Initialize DMA channels to the beginning of the active video buffer, and
534 * start these channels.
536 static void pxa_dma_start_channels(struct pxa_camera_dev
*pcdev
)
539 struct pxa_buffer
*active
;
541 active
= pcdev
->active
;
543 for (i
= 0; i
< pcdev
->channels
; i
++) {
544 dev_dbg(pcdev
->soc_host
.dev
, "%s (channel=%d) ddadr=%08x\n", __func__
,
545 i
, active
->dmas
[i
].sg_dma
);
546 DDADR(pcdev
->dma_chans
[i
]) = active
->dmas
[i
].sg_dma
;
547 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
551 static void pxa_dma_stop_channels(struct pxa_camera_dev
*pcdev
)
555 for (i
= 0; i
< pcdev
->channels
; i
++) {
556 dev_dbg(pcdev
->soc_host
.dev
, "%s (channel=%d)\n", __func__
, i
);
557 DCSR(pcdev
->dma_chans
[i
]) = 0;
561 static void pxa_dma_add_tail_buf(struct pxa_camera_dev
*pcdev
,
562 struct pxa_buffer
*buf
)
565 struct pxa_dma_desc
*buf_last_desc
;
567 for (i
= 0; i
< pcdev
->channels
; i
++) {
568 buf_last_desc
= buf
->dmas
[i
].sg_cpu
+ buf
->dmas
[i
].sglen
;
569 buf_last_desc
->ddadr
= DDADR_STOP
;
571 if (pcdev
->sg_tail
[i
])
572 /* Link the new buffer to the old tail */
573 pcdev
->sg_tail
[i
]->ddadr
= buf
->dmas
[i
].sg_dma
;
575 /* Update the channel tail */
576 pcdev
->sg_tail
[i
] = buf_last_desc
;
581 * pxa_camera_start_capture - start video capturing
582 * @pcdev: camera device
584 * Launch capturing. DMA channels should not be active yet. They should get
585 * activated at the end of frame interrupt, to capture only whole frames, and
586 * never begin the capture of a partial frame.
588 static void pxa_camera_start_capture(struct pxa_camera_dev
*pcdev
)
590 unsigned long cicr0
, cifr
;
592 dev_dbg(pcdev
->soc_host
.dev
, "%s\n", __func__
);
593 /* Reset the FIFOs */
594 cifr
= __raw_readl(pcdev
->base
+ CIFR
) | CIFR_RESET_F
;
595 __raw_writel(cifr
, pcdev
->base
+ CIFR
);
596 /* Enable End-Of-Frame Interrupt */
597 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) | CICR0_ENB
;
598 cicr0
&= ~CICR0_EOFM
;
599 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
602 static void pxa_camera_stop_capture(struct pxa_camera_dev
*pcdev
)
606 pxa_dma_stop_channels(pcdev
);
608 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) & ~CICR0_ENB
;
609 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
611 pcdev
->active
= NULL
;
612 dev_dbg(pcdev
->soc_host
.dev
, "%s\n", __func__
);
615 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
616 static void pxa_videobuf_queue(struct videobuf_queue
*vq
,
617 struct videobuf_buffer
*vb
)
619 struct soc_camera_device
*icd
= vq
->priv_data
;
620 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
621 struct pxa_camera_dev
*pcdev
= ici
->priv
;
622 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
624 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d active=%p\n", __func__
,
625 vb
, vb
->baddr
, vb
->bsize
, pcdev
->active
);
627 list_add_tail(&vb
->queue
, &pcdev
->capture
);
629 vb
->state
= VIDEOBUF_ACTIVE
;
630 pxa_dma_add_tail_buf(pcdev
, buf
);
633 pxa_camera_start_capture(pcdev
);
636 static void pxa_videobuf_release(struct videobuf_queue
*vq
,
637 struct videobuf_buffer
*vb
)
639 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
641 struct soc_camera_device
*icd
= vq
->priv_data
;
643 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
644 vb
, vb
->baddr
, vb
->bsize
);
647 case VIDEOBUF_ACTIVE
:
648 dev_dbg(&icd
->dev
, "%s (active)\n", __func__
);
650 case VIDEOBUF_QUEUED
:
651 dev_dbg(&icd
->dev
, "%s (queued)\n", __func__
);
653 case VIDEOBUF_PREPARED
:
654 dev_dbg(&icd
->dev
, "%s (prepared)\n", __func__
);
657 dev_dbg(&icd
->dev
, "%s (unknown)\n", __func__
);
662 free_buffer(vq
, buf
);
665 static void pxa_camera_wakeup(struct pxa_camera_dev
*pcdev
,
666 struct videobuf_buffer
*vb
,
667 struct pxa_buffer
*buf
)
671 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
672 list_del_init(&vb
->queue
);
673 vb
->state
= VIDEOBUF_DONE
;
674 do_gettimeofday(&vb
->ts
);
677 dev_dbg(pcdev
->soc_host
.dev
, "%s dequeud buffer (vb=0x%p)\n", __func__
, vb
);
679 if (list_empty(&pcdev
->capture
)) {
680 pxa_camera_stop_capture(pcdev
);
681 for (i
= 0; i
< pcdev
->channels
; i
++)
682 pcdev
->sg_tail
[i
] = NULL
;
686 pcdev
->active
= list_entry(pcdev
->capture
.next
,
687 struct pxa_buffer
, vb
.queue
);
691 * pxa_camera_check_link_miss - check missed DMA linking
692 * @pcdev: camera device
694 * The DMA chaining is done with DMA running. This means a tiny temporal window
695 * remains, where a buffer is queued on the chain, while the chain is already
696 * stopped. This means the tailed buffer would never be transfered by DMA.
697 * This function restarts the capture for this corner case, where :
698 * - DADR() == DADDR_STOP
699 * - a videobuffer is queued on the pcdev->capture list
701 * Please check the "DMA hot chaining timeslice issue" in
702 * Documentation/video4linux/pxa_camera.txt
704 * Context: should only be called within the dma irq handler
706 static void pxa_camera_check_link_miss(struct pxa_camera_dev
*pcdev
)
708 int i
, is_dma_stopped
= 1;
710 for (i
= 0; i
< pcdev
->channels
; i
++)
711 if (DDADR(pcdev
->dma_chans
[i
]) != DDADR_STOP
)
713 dev_dbg(pcdev
->soc_host
.dev
, "%s : top queued buffer=%p, dma_stopped=%d\n",
714 __func__
, pcdev
->active
, is_dma_stopped
);
715 if (pcdev
->active
&& is_dma_stopped
)
716 pxa_camera_start_capture(pcdev
);
719 static void pxa_camera_dma_irq(int channel
, struct pxa_camera_dev
*pcdev
,
720 enum pxa_camera_active_dma act_dma
)
722 struct pxa_buffer
*buf
;
724 u32 status
, camera_status
, overrun
;
725 struct videobuf_buffer
*vb
;
727 spin_lock_irqsave(&pcdev
->lock
, flags
);
729 status
= DCSR(channel
);
730 DCSR(channel
) = status
;
732 camera_status
= __raw_readl(pcdev
->base
+ CISR
);
733 overrun
= CISR_IFO_0
;
734 if (pcdev
->channels
== 3)
735 overrun
|= CISR_IFO_1
| CISR_IFO_2
;
737 if (status
& DCSR_BUSERR
) {
738 dev_err(pcdev
->soc_host
.dev
, "DMA Bus Error IRQ!\n");
742 if (!(status
& (DCSR_ENDINTR
| DCSR_STARTINTR
))) {
743 dev_err(pcdev
->soc_host
.dev
, "Unknown DMA IRQ source, "
744 "status: 0x%08x\n", status
);
749 * pcdev->active should not be NULL in DMA irq handler.
751 * But there is one corner case : if capture was stopped due to an
752 * overrun of channel 1, and at that same channel 2 was completed.
754 * When handling the overrun in DMA irq for channel 1, we'll stop the
755 * capture and restart it (and thus set pcdev->active to NULL). But the
756 * DMA irq handler will already be pending for channel 2. So on entering
757 * the DMA irq handler for channel 2 there will be no active buffer, yet
763 vb
= &pcdev
->active
->vb
;
764 buf
= container_of(vb
, struct pxa_buffer
, vb
);
765 WARN_ON(buf
->inwork
|| list_empty(&vb
->queue
));
767 dev_dbg(pcdev
->soc_host
.dev
, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
768 __func__
, channel
, status
& DCSR_STARTINTR
? "SOF " : "",
769 status
& DCSR_ENDINTR
? "EOF " : "", vb
, DDADR(channel
));
771 if (status
& DCSR_ENDINTR
) {
773 * It's normal if the last frame creates an overrun, as there
774 * are no more DMA descriptors to fetch from QCI fifos
776 if (camera_status
& overrun
&&
777 !list_is_last(pcdev
->capture
.next
, &pcdev
->capture
)) {
778 dev_dbg(pcdev
->soc_host
.dev
, "FIFO overrun! CISR: %x\n",
780 pxa_camera_stop_capture(pcdev
);
781 pxa_camera_start_capture(pcdev
);
784 buf
->active_dma
&= ~act_dma
;
785 if (!buf
->active_dma
) {
786 pxa_camera_wakeup(pcdev
, vb
, buf
);
787 pxa_camera_check_link_miss(pcdev
);
792 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
795 static void pxa_camera_dma_irq_y(int channel
, void *data
)
797 struct pxa_camera_dev
*pcdev
= data
;
798 pxa_camera_dma_irq(channel
, pcdev
, DMA_Y
);
801 static void pxa_camera_dma_irq_u(int channel
, void *data
)
803 struct pxa_camera_dev
*pcdev
= data
;
804 pxa_camera_dma_irq(channel
, pcdev
, DMA_U
);
807 static void pxa_camera_dma_irq_v(int channel
, void *data
)
809 struct pxa_camera_dev
*pcdev
= data
;
810 pxa_camera_dma_irq(channel
, pcdev
, DMA_V
);
813 static struct videobuf_queue_ops pxa_videobuf_ops
= {
814 .buf_setup
= pxa_videobuf_setup
,
815 .buf_prepare
= pxa_videobuf_prepare
,
816 .buf_queue
= pxa_videobuf_queue
,
817 .buf_release
= pxa_videobuf_release
,
820 static void pxa_camera_init_videobuf(struct videobuf_queue
*q
,
821 struct soc_camera_device
*icd
)
823 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
824 struct pxa_camera_dev
*pcdev
= ici
->priv
;
826 /* We must pass NULL as dev pointer, then all pci_* dma operations
827 * transform to normal dma_* ones. */
828 videobuf_queue_sg_init(q
, &pxa_videobuf_ops
, NULL
, &pcdev
->lock
,
829 V4L2_BUF_TYPE_VIDEO_CAPTURE
, V4L2_FIELD_NONE
,
830 sizeof(struct pxa_buffer
), icd
);
833 static u32
mclk_get_divisor(struct platform_device
*pdev
,
834 struct pxa_camera_dev
*pcdev
)
836 unsigned long mclk
= pcdev
->mclk
;
838 unsigned long lcdclk
;
840 lcdclk
= clk_get_rate(pcdev
->clk
);
841 pcdev
->ciclk
= lcdclk
;
843 /* mclk <= ciclk / 4 (27.4.2) */
844 if (mclk
> lcdclk
/ 4) {
846 dev_warn(&pdev
->dev
, "Limiting master clock to %lu\n", mclk
);
849 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
850 div
= (lcdclk
+ 2 * mclk
- 1) / (2 * mclk
) - 1;
852 /* If we're not supplying MCLK, leave it at 0 */
853 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
854 pcdev
->mclk
= lcdclk
/ (2 * (div
+ 1));
856 dev_dbg(&pdev
->dev
, "LCD clock %luHz, target freq %luHz, divisor %u\n",
862 static void recalculate_fifo_timeout(struct pxa_camera_dev
*pcdev
,
865 /* We want a timeout > 1 pixel time, not ">=" */
866 u32 ciclk_per_pixel
= pcdev
->ciclk
/ pclk
+ 1;
868 __raw_writel(ciclk_per_pixel
, pcdev
->base
+ CITOR
);
871 static void pxa_camera_activate(struct pxa_camera_dev
*pcdev
)
873 struct pxacamera_platform_data
*pdata
= pcdev
->pdata
;
876 dev_dbg(pcdev
->soc_host
.dev
, "Registered platform device at %p data %p\n",
879 if (pdata
&& pdata
->init
) {
880 dev_dbg(pcdev
->soc_host
.dev
, "%s: Init gpios\n", __func__
);
881 pdata
->init(pcdev
->soc_host
.dev
);
884 /* disable all interrupts */
885 __raw_writel(0x3ff, pcdev
->base
+ CICR0
);
887 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
888 cicr4
|= CICR4_PCLK_EN
;
889 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
890 cicr4
|= CICR4_MCLK_EN
;
891 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
893 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
895 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
898 __raw_writel(pcdev
->mclk_divisor
| cicr4
, pcdev
->base
+ CICR4
);
900 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
901 /* Initialise the timeout under the assumption pclk = mclk */
902 recalculate_fifo_timeout(pcdev
, pcdev
->mclk
);
904 /* "Safe default" - 13MHz */
905 recalculate_fifo_timeout(pcdev
, 13000000);
907 clk_enable(pcdev
->clk
);
910 static void pxa_camera_deactivate(struct pxa_camera_dev
*pcdev
)
912 clk_disable(pcdev
->clk
);
915 static irqreturn_t
pxa_camera_irq(int irq
, void *data
)
917 struct pxa_camera_dev
*pcdev
= data
;
918 unsigned long status
, cicr0
;
919 struct pxa_buffer
*buf
;
920 struct videobuf_buffer
*vb
;
922 status
= __raw_readl(pcdev
->base
+ CISR
);
923 dev_dbg(pcdev
->soc_host
.dev
, "Camera interrupt status 0x%lx\n", status
);
928 __raw_writel(status
, pcdev
->base
+ CISR
);
930 if (status
& CISR_EOF
) {
931 pcdev
->active
= list_first_entry(&pcdev
->capture
,
932 struct pxa_buffer
, vb
.queue
);
933 vb
= &pcdev
->active
->vb
;
934 buf
= container_of(vb
, struct pxa_buffer
, vb
);
935 pxa_videobuf_set_actdma(pcdev
, buf
);
937 pxa_dma_start_channels(pcdev
);
939 cicr0
= __raw_readl(pcdev
->base
+ CICR0
) | CICR0_EOFM
;
940 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
947 * The following two functions absolutely depend on the fact, that
948 * there can be only one camera on PXA quick capture interface
949 * Called with .video_lock held
951 static int pxa_camera_add_device(struct soc_camera_device
*icd
)
953 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
954 struct pxa_camera_dev
*pcdev
= ici
->priv
;
962 pxa_camera_activate(pcdev
);
963 ret
= icd
->ops
->init(icd
);
969 dev_info(&icd
->dev
, "PXA Camera driver attached to camera %d\n",
975 pxa_camera_deactivate(pcdev
);
980 /* Called with .video_lock held */
981 static void pxa_camera_remove_device(struct soc_camera_device
*icd
)
983 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
984 struct pxa_camera_dev
*pcdev
= ici
->priv
;
986 BUG_ON(icd
!= pcdev
->icd
);
988 dev_info(&icd
->dev
, "PXA Camera driver detached from camera %d\n",
991 /* disable capture, disable interrupts */
992 __raw_writel(0x3ff, pcdev
->base
+ CICR0
);
994 /* Stop DMA engine */
995 DCSR(pcdev
->dma_chans
[0]) = 0;
996 DCSR(pcdev
->dma_chans
[1]) = 0;
997 DCSR(pcdev
->dma_chans
[2]) = 0;
999 icd
->ops
->release(icd
);
1001 pxa_camera_deactivate(pcdev
);
1006 static int test_platform_param(struct pxa_camera_dev
*pcdev
,
1007 unsigned char buswidth
, unsigned long *flags
)
1010 * Platform specified synchronization and pixel clock polarities are
1011 * only a recommendation and are only used during probing. The PXA270
1012 * quick capture interface supports both.
1014 *flags
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
1015 SOCAM_MASTER
: SOCAM_SLAVE
) |
1016 SOCAM_HSYNC_ACTIVE_HIGH
|
1017 SOCAM_HSYNC_ACTIVE_LOW
|
1018 SOCAM_VSYNC_ACTIVE_HIGH
|
1019 SOCAM_VSYNC_ACTIVE_LOW
|
1020 SOCAM_DATA_ACTIVE_HIGH
|
1021 SOCAM_PCLK_SAMPLE_RISING
|
1022 SOCAM_PCLK_SAMPLE_FALLING
;
1024 /* If requested data width is supported by the platform, use it */
1027 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
))
1029 *flags
|= SOCAM_DATAWIDTH_10
;
1032 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
))
1034 *flags
|= SOCAM_DATAWIDTH_9
;
1037 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
))
1039 *flags
|= SOCAM_DATAWIDTH_8
;
1048 static int pxa_camera_set_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
1050 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1051 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1052 unsigned long dw
, bpp
, bus_flags
, camera_flags
, common_flags
;
1053 u32 cicr0
, cicr1
, cicr2
, cicr3
, cicr4
= 0;
1054 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
1059 camera_flags
= icd
->ops
->query_bus_param(icd
);
1061 common_flags
= soc_camera_bus_param_compatible(camera_flags
, bus_flags
);
1065 pcdev
->channels
= 1;
1067 /* Make choises, based on platform preferences */
1068 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
1069 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
1070 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
1071 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
1073 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
1076 if ((common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
) &&
1077 (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)) {
1078 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
1079 common_flags
&= ~SOCAM_VSYNC_ACTIVE_HIGH
;
1081 common_flags
&= ~SOCAM_VSYNC_ACTIVE_LOW
;
1084 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
1085 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
1086 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
1087 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
1089 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
1092 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
1096 /* Datawidth is now guaranteed to be equal to one of the three values.
1097 * We fix bit-per-pixel equal to data-width... */
1098 switch (common_flags
& SOCAM_DATAWIDTH_MASK
) {
1099 case SOCAM_DATAWIDTH_10
:
1103 case SOCAM_DATAWIDTH_9
:
1108 /* Actually it can only be 8 now,
1109 * default is just to silence compiler warnings */
1110 case SOCAM_DATAWIDTH_8
:
1115 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
1116 cicr4
|= CICR4_PCLK_EN
;
1117 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
1118 cicr4
|= CICR4_MCLK_EN
;
1119 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
1121 if (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)
1123 if (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)
1126 cicr0
= __raw_readl(pcdev
->base
+ CICR0
);
1127 if (cicr0
& CICR0_ENB
)
1128 __raw_writel(cicr0
& ~CICR0_ENB
, pcdev
->base
+ CICR0
);
1130 cicr1
= CICR1_PPL_VAL(icd
->width
- 1) | bpp
| dw
;
1133 case V4L2_PIX_FMT_YUV422P
:
1134 pcdev
->channels
= 3;
1135 cicr1
|= CICR1_YCBCR_F
;
1137 * Normally, pxa bus wants as input UYVY format. We allow all
1138 * reorderings of the YUV422 format, as no processing is done,
1139 * and the YUV stream is just passed through without any
1140 * transformation. Note that UYVY is the only format that
1141 * should be used if pxa framebuffer Overlay2 is used.
1143 case V4L2_PIX_FMT_UYVY
:
1144 case V4L2_PIX_FMT_VYUY
:
1145 case V4L2_PIX_FMT_YUYV
:
1146 case V4L2_PIX_FMT_YVYU
:
1147 cicr1
|= CICR1_COLOR_SP_VAL(2);
1149 case V4L2_PIX_FMT_RGB555
:
1150 cicr1
|= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1151 CICR1_TBIT
| CICR1_COLOR_SP_VAL(1);
1153 case V4L2_PIX_FMT_RGB565
:
1154 cicr1
|= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1159 cicr3
= CICR3_LPF_VAL(icd
->height
- 1) |
1160 CICR3_BFW_VAL(min((unsigned short)255, icd
->y_skip_top
));
1161 cicr4
|= pcdev
->mclk_divisor
;
1163 __raw_writel(cicr1
, pcdev
->base
+ CICR1
);
1164 __raw_writel(cicr2
, pcdev
->base
+ CICR2
);
1165 __raw_writel(cicr3
, pcdev
->base
+ CICR3
);
1166 __raw_writel(cicr4
, pcdev
->base
+ CICR4
);
1168 /* CIF interrupts are not used, only DMA */
1169 cicr0
= (cicr0
& CICR0_ENB
) | (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
1170 CICR0_SIM_MP
: (CICR0_SL_CAP_EN
| CICR0_SIM_SP
));
1171 cicr0
|= CICR0_DMAEN
| CICR0_IRQ_MASK
;
1172 __raw_writel(cicr0
, pcdev
->base
+ CICR0
);
1177 static int pxa_camera_try_bus_param(struct soc_camera_device
*icd
,
1178 unsigned char buswidth
)
1180 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1181 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1182 unsigned long bus_flags
, camera_flags
;
1183 int ret
= test_platform_param(pcdev
, buswidth
, &bus_flags
);
1188 camera_flags
= icd
->ops
->query_bus_param(icd
);
1190 return soc_camera_bus_param_compatible(camera_flags
, bus_flags
) ? 0 : -EINVAL
;
1193 static const struct soc_camera_data_format pxa_camera_formats
[] = {
1195 .name
= "Planar YUV422 16 bit",
1197 .fourcc
= V4L2_PIX_FMT_YUV422P
,
1198 .colorspace
= V4L2_COLORSPACE_JPEG
,
1202 static bool buswidth_supported(struct soc_camera_device
*icd
, int depth
)
1204 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1205 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1209 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
);
1211 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
);
1213 return !!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
);
1218 static int required_buswidth(const struct soc_camera_data_format
*fmt
)
1220 switch (fmt
->fourcc
) {
1221 case V4L2_PIX_FMT_UYVY
:
1222 case V4L2_PIX_FMT_VYUY
:
1223 case V4L2_PIX_FMT_YUYV
:
1224 case V4L2_PIX_FMT_YVYU
:
1225 case V4L2_PIX_FMT_RGB565
:
1226 case V4L2_PIX_FMT_RGB555
:
1233 static int pxa_camera_get_formats(struct soc_camera_device
*icd
, int idx
,
1234 struct soc_camera_format_xlate
*xlate
)
1236 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1237 int formats
= 0, buswidth
, ret
;
1239 buswidth
= required_buswidth(icd
->formats
+ idx
);
1241 if (!buswidth_supported(icd
, buswidth
))
1244 ret
= pxa_camera_try_bus_param(icd
, buswidth
);
1248 switch (icd
->formats
[idx
].fourcc
) {
1249 case V4L2_PIX_FMT_UYVY
:
1252 xlate
->host_fmt
= &pxa_camera_formats
[0];
1253 xlate
->cam_fmt
= icd
->formats
+ idx
;
1254 xlate
->buswidth
= buswidth
;
1256 dev_dbg(ici
->dev
, "Providing format %s using %s\n",
1257 pxa_camera_formats
[0].name
,
1258 icd
->formats
[idx
].name
);
1260 case V4L2_PIX_FMT_VYUY
:
1261 case V4L2_PIX_FMT_YUYV
:
1262 case V4L2_PIX_FMT_YVYU
:
1263 case V4L2_PIX_FMT_RGB565
:
1264 case V4L2_PIX_FMT_RGB555
:
1267 xlate
->host_fmt
= icd
->formats
+ idx
;
1268 xlate
->cam_fmt
= icd
->formats
+ idx
;
1269 xlate
->buswidth
= buswidth
;
1271 dev_dbg(ici
->dev
, "Providing format %s packed\n",
1272 icd
->formats
[idx
].name
);
1276 /* Generic pass-through */
1279 xlate
->host_fmt
= icd
->formats
+ idx
;
1280 xlate
->cam_fmt
= icd
->formats
+ idx
;
1281 xlate
->buswidth
= icd
->formats
[idx
].depth
;
1284 "Providing format %s in pass-through mode\n",
1285 icd
->formats
[idx
].name
);
1292 static int pxa_camera_set_crop(struct soc_camera_device
*icd
,
1293 struct v4l2_rect
*rect
)
1295 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1296 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1297 struct soc_camera_sense sense
= {
1298 .master_clock
= pcdev
->mclk
,
1299 .pixel_clock_max
= pcdev
->ciclk
/ 4,
1303 /* If PCLK is used to latch data from the sensor, check sense */
1304 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
1305 icd
->sense
= &sense
;
1307 ret
= icd
->ops
->set_crop(icd
, rect
);
1312 dev_warn(ici
->dev
, "Failed to crop to %ux%u@%u:%u\n",
1313 rect
->width
, rect
->height
, rect
->left
, rect
->top
);
1314 } else if (sense
.flags
& SOCAM_SENSE_PCLK_CHANGED
) {
1315 if (sense
.pixel_clock
> sense
.pixel_clock_max
) {
1317 "pixel clock %lu set by the camera too high!",
1321 recalculate_fifo_timeout(pcdev
, sense
.pixel_clock
);
1327 static int pxa_camera_set_fmt(struct soc_camera_device
*icd
,
1328 struct v4l2_format
*f
)
1330 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1331 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1332 const struct soc_camera_data_format
*cam_fmt
= NULL
;
1333 const struct soc_camera_format_xlate
*xlate
= NULL
;
1334 struct soc_camera_sense sense
= {
1335 .master_clock
= pcdev
->mclk
,
1336 .pixel_clock_max
= pcdev
->ciclk
/ 4,
1338 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1339 struct v4l2_format cam_f
= *f
;
1342 xlate
= soc_camera_xlate_by_fourcc(icd
, pix
->pixelformat
);
1344 dev_warn(ici
->dev
, "Format %x not found\n", pix
->pixelformat
);
1348 cam_fmt
= xlate
->cam_fmt
;
1350 /* If PCLK is used to latch data from the sensor, check sense */
1351 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
1352 icd
->sense
= &sense
;
1354 cam_f
.fmt
.pix
.pixelformat
= cam_fmt
->fourcc
;
1355 ret
= icd
->ops
->set_fmt(icd
, &cam_f
);
1360 dev_warn(ici
->dev
, "Failed to configure for format %x\n",
1362 } else if (sense
.flags
& SOCAM_SENSE_PCLK_CHANGED
) {
1363 if (sense
.pixel_clock
> sense
.pixel_clock_max
) {
1365 "pixel clock %lu set by the camera too high!",
1369 recalculate_fifo_timeout(pcdev
, sense
.pixel_clock
);
1373 icd
->buswidth
= xlate
->buswidth
;
1374 icd
->current_fmt
= xlate
->host_fmt
;
1380 static int pxa_camera_try_fmt(struct soc_camera_device
*icd
,
1381 struct v4l2_format
*f
)
1383 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1384 const struct soc_camera_format_xlate
*xlate
;
1385 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1386 __u32 pixfmt
= pix
->pixelformat
;
1387 enum v4l2_field field
;
1390 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1392 dev_warn(ici
->dev
, "Format %x not found\n", pixfmt
);
1397 * Limit to pxa hardware capabilities. YUV422P planar format requires
1398 * images size to be a multiple of 16 bytes. If not, zeros will be
1399 * inserted between Y and U planes, and U and V planes, which violates
1400 * the YUV422P standard.
1402 v4l_bound_align_image(&pix
->width
, 48, 2048, 1,
1403 &pix
->height
, 32, 2048, 0,
1404 xlate
->host_fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
? 4 : 0);
1406 pix
->bytesperline
= pix
->width
*
1407 DIV_ROUND_UP(xlate
->host_fmt
->depth
, 8);
1408 pix
->sizeimage
= pix
->height
* pix
->bytesperline
;
1410 /* camera has to see its format, but the user the original one */
1411 pix
->pixelformat
= xlate
->cam_fmt
->fourcc
;
1412 /* limit to sensor capabilities */
1413 ret
= icd
->ops
->try_fmt(icd
, f
);
1414 pix
->pixelformat
= xlate
->host_fmt
->fourcc
;
1418 if (field
== V4L2_FIELD_ANY
) {
1419 pix
->field
= V4L2_FIELD_NONE
;
1420 } else if (field
!= V4L2_FIELD_NONE
) {
1421 dev_err(&icd
->dev
, "Field type %d unsupported.\n", field
);
1428 static int pxa_camera_reqbufs(struct soc_camera_file
*icf
,
1429 struct v4l2_requestbuffers
*p
)
1433 /* This is for locking debugging only. I removed spinlocks and now I
1434 * check whether .prepare is ever called on a linked buffer, or whether
1435 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1436 * it hadn't triggered */
1437 for (i
= 0; i
< p
->count
; i
++) {
1438 struct pxa_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
1439 struct pxa_buffer
, vb
);
1441 INIT_LIST_HEAD(&buf
->vb
.queue
);
1447 static unsigned int pxa_camera_poll(struct file
*file
, poll_table
*pt
)
1449 struct soc_camera_file
*icf
= file
->private_data
;
1450 struct pxa_buffer
*buf
;
1452 buf
= list_entry(icf
->vb_vidq
.stream
.next
, struct pxa_buffer
,
1455 poll_wait(file
, &buf
->vb
.done
, pt
);
1457 if (buf
->vb
.state
== VIDEOBUF_DONE
||
1458 buf
->vb
.state
== VIDEOBUF_ERROR
)
1459 return POLLIN
|POLLRDNORM
;
1464 static int pxa_camera_querycap(struct soc_camera_host
*ici
,
1465 struct v4l2_capability
*cap
)
1467 /* cap->name is set by the firendly caller:-> */
1468 strlcpy(cap
->card
, pxa_cam_driver_description
, sizeof(cap
->card
));
1469 cap
->version
= PXA_CAM_VERSION_CODE
;
1470 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
1475 static int pxa_camera_suspend(struct soc_camera_device
*icd
, pm_message_t state
)
1477 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1478 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1481 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR0
);
1482 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR1
);
1483 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR2
);
1484 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR3
);
1485 pcdev
->save_cicr
[i
++] = __raw_readl(pcdev
->base
+ CICR4
);
1487 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->suspend
))
1488 ret
= pcdev
->icd
->ops
->suspend(pcdev
->icd
, state
);
1493 static int pxa_camera_resume(struct soc_camera_device
*icd
)
1495 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
1496 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1499 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1500 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1501 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1503 __raw_writel(pcdev
->save_cicr
[i
++] & ~CICR0_ENB
, pcdev
->base
+ CICR0
);
1504 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR1
);
1505 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR2
);
1506 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR3
);
1507 __raw_writel(pcdev
->save_cicr
[i
++], pcdev
->base
+ CICR4
);
1509 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->resume
))
1510 ret
= pcdev
->icd
->ops
->resume(pcdev
->icd
);
1512 /* Restart frame capture if active buffer exists */
1513 if (!ret
&& pcdev
->active
)
1514 pxa_camera_start_capture(pcdev
);
1519 static struct soc_camera_host_ops pxa_soc_camera_host_ops
= {
1520 .owner
= THIS_MODULE
,
1521 .add
= pxa_camera_add_device
,
1522 .remove
= pxa_camera_remove_device
,
1523 .suspend
= pxa_camera_suspend
,
1524 .resume
= pxa_camera_resume
,
1525 .set_crop
= pxa_camera_set_crop
,
1526 .get_formats
= pxa_camera_get_formats
,
1527 .set_fmt
= pxa_camera_set_fmt
,
1528 .try_fmt
= pxa_camera_try_fmt
,
1529 .init_videobuf
= pxa_camera_init_videobuf
,
1530 .reqbufs
= pxa_camera_reqbufs
,
1531 .poll
= pxa_camera_poll
,
1532 .querycap
= pxa_camera_querycap
,
1533 .set_bus_param
= pxa_camera_set_bus_param
,
1536 static int __devinit
pxa_camera_probe(struct platform_device
*pdev
)
1538 struct pxa_camera_dev
*pcdev
;
1539 struct resource
*res
;
1544 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1545 irq
= platform_get_irq(pdev
, 0);
1546 if (!res
|| irq
< 0) {
1551 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1553 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1558 pcdev
->clk
= clk_get(&pdev
->dev
, NULL
);
1559 if (IS_ERR(pcdev
->clk
)) {
1560 err
= PTR_ERR(pcdev
->clk
);
1566 pcdev
->pdata
= pdev
->dev
.platform_data
;
1567 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1568 if (!(pcdev
->platform_flags
& (PXA_CAMERA_DATAWIDTH_8
|
1569 PXA_CAMERA_DATAWIDTH_9
| PXA_CAMERA_DATAWIDTH_10
))) {
1570 /* Platform hasn't set available data widths. This is bad.
1571 * Warn and use a default. */
1572 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1573 "data widths, using default 10 bit\n");
1574 pcdev
->platform_flags
|= PXA_CAMERA_DATAWIDTH_10
;
1576 pcdev
->mclk
= pcdev
->pdata
->mclk_10khz
* 10000;
1578 dev_warn(&pdev
->dev
,
1579 "mclk == 0! Please, fix your platform data. "
1580 "Using default 20MHz\n");
1581 pcdev
->mclk
= 20000000;
1584 pcdev
->mclk_divisor
= mclk_get_divisor(pdev
, pcdev
);
1586 INIT_LIST_HEAD(&pcdev
->capture
);
1587 spin_lock_init(&pcdev
->lock
);
1590 * Request the regions.
1592 if (!request_mem_region(res
->start
, resource_size(res
),
1593 PXA_CAM_DRV_NAME
)) {
1598 base
= ioremap(res
->start
, resource_size(res
));
1607 err
= pxa_request_dma("CI_Y", DMA_PRIO_HIGH
,
1608 pxa_camera_dma_irq_y
, pcdev
);
1610 dev_err(&pdev
->dev
, "Can't request DMA for Y\n");
1613 pcdev
->dma_chans
[0] = err
;
1614 dev_dbg(&pdev
->dev
, "got DMA channel %d\n", pcdev
->dma_chans
[0]);
1616 err
= pxa_request_dma("CI_U", DMA_PRIO_HIGH
,
1617 pxa_camera_dma_irq_u
, pcdev
);
1619 dev_err(&pdev
->dev
, "Can't request DMA for U\n");
1620 goto exit_free_dma_y
;
1622 pcdev
->dma_chans
[1] = err
;
1623 dev_dbg(&pdev
->dev
, "got DMA channel (U) %d\n", pcdev
->dma_chans
[1]);
1625 err
= pxa_request_dma("CI_V", DMA_PRIO_HIGH
,
1626 pxa_camera_dma_irq_v
, pcdev
);
1628 dev_err(&pdev
->dev
, "Can't request DMA for V\n");
1629 goto exit_free_dma_u
;
1631 pcdev
->dma_chans
[2] = err
;
1632 dev_dbg(&pdev
->dev
, "got DMA channel (V) %d\n", pcdev
->dma_chans
[2]);
1634 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1635 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1636 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1639 err
= request_irq(pcdev
->irq
, pxa_camera_irq
, 0, PXA_CAM_DRV_NAME
,
1642 dev_err(&pdev
->dev
, "Camera interrupt register failed \n");
1646 pcdev
->soc_host
.drv_name
= PXA_CAM_DRV_NAME
;
1647 pcdev
->soc_host
.ops
= &pxa_soc_camera_host_ops
;
1648 pcdev
->soc_host
.priv
= pcdev
;
1649 pcdev
->soc_host
.dev
= &pdev
->dev
;
1650 pcdev
->soc_host
.nr
= pdev
->id
;
1652 err
= soc_camera_host_register(&pcdev
->soc_host
);
1659 free_irq(pcdev
->irq
, pcdev
);
1661 pxa_free_dma(pcdev
->dma_chans
[2]);
1663 pxa_free_dma(pcdev
->dma_chans
[1]);
1665 pxa_free_dma(pcdev
->dma_chans
[0]);
1669 release_mem_region(res
->start
, resource_size(res
));
1671 clk_put(pcdev
->clk
);
1678 static int __devexit
pxa_camera_remove(struct platform_device
*pdev
)
1680 struct soc_camera_host
*soc_host
= to_soc_camera_host(&pdev
->dev
);
1681 struct pxa_camera_dev
*pcdev
= container_of(soc_host
,
1682 struct pxa_camera_dev
, soc_host
);
1683 struct resource
*res
;
1685 clk_put(pcdev
->clk
);
1687 pxa_free_dma(pcdev
->dma_chans
[0]);
1688 pxa_free_dma(pcdev
->dma_chans
[1]);
1689 pxa_free_dma(pcdev
->dma_chans
[2]);
1690 free_irq(pcdev
->irq
, pcdev
);
1692 soc_camera_host_unregister(soc_host
);
1694 iounmap(pcdev
->base
);
1697 release_mem_region(res
->start
, resource_size(res
));
1701 dev_info(&pdev
->dev
, "PXA Camera driver unloaded\n");
1706 static struct platform_driver pxa_camera_driver
= {
1708 .name
= PXA_CAM_DRV_NAME
,
1710 .probe
= pxa_camera_probe
,
1711 .remove
= __devexit_p(pxa_camera_remove
),
1715 static int __init
pxa_camera_init(void)
1717 return platform_driver_register(&pxa_camera_driver
);
1720 static void __exit
pxa_camera_exit(void)
1722 platform_driver_unregister(&pxa_camera_driver
);
1725 module_init(pxa_camera_init
);
1726 module_exit(pxa_camera_exit
);
1728 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1729 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1730 MODULE_LICENSE("GPL");
1731 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME
);