2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/mutex.h>
29 #include <linux/clk.h>
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <asm/arch/pxa-regs.h>
39 #include <asm/arch/camera.h>
41 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44 #define CICR0_SIM_MP (0 << 24)
45 #define CICR0_SIM_SP (1 << 24)
46 #define CICR0_SIM_MS (2 << 24)
47 #define CICR0_SIM_EP (3 << 24)
48 #define CICR0_SIM_ES (4 << 24)
50 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
51 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
52 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
53 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
54 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
56 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
57 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
58 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
59 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
60 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
62 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
63 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
64 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
65 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
67 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
68 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
69 CICR0_EOFM | CICR0_FOM)
71 static DEFINE_MUTEX(camera_lock
);
76 enum pxa_camera_active_dma
{
82 /* descriptor needed for the PXA DMA engine */
85 struct pxa_dma_desc
*sg_cpu
;
90 /* buffer for one video frame */
92 /* common v4l buffer stuff -- must be first */
93 struct videobuf_buffer vb
;
95 const struct soc_camera_data_format
*fmt
;
97 /* our descriptor lists for Y, U and V channels */
98 struct pxa_cam_dma dmas
[3];
102 enum pxa_camera_active_dma active_dma
;
105 struct pxa_framebuffer_queue
{
106 dma_addr_t sg_last_dma
;
107 struct pxa_dma_desc
*sg_last_cpu
;
110 struct pxa_camera_dev
{
112 /* PXA27x is only supposed to handle one camera on its Quick Capture
113 * interface. If anyone ever builds hardware to enable more than
114 * one camera, they will have to modify this driver too */
115 struct soc_camera_device
*icd
;
121 unsigned int dma_chans
[3];
123 struct pxacamera_platform_data
*pdata
;
124 struct resource
*res
;
125 unsigned long platform_flags
;
126 unsigned long platform_mclk_10khz
;
128 struct list_head capture
;
132 struct pxa_buffer
*active
;
135 static const char *pxa_cam_driver_description
= "PXA_Camera";
137 static unsigned int vid_limit
= 16; /* Video memory limit, in Mb */
140 * Videobuf operations
142 static int pxa_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
145 struct soc_camera_device
*icd
= vq
->priv_data
;
147 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
149 /* planar capture requires Y, U and V buffers to be page aligned */
150 if (icd
->current_fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
151 *size
= PAGE_ALIGN(icd
->width
* icd
->height
); /* Y pages */
152 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* U pages */
153 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* V pages */
155 *size
= icd
->width
* icd
->height
*
156 ((icd
->current_fmt
->depth
+ 7) >> 3);
161 while (*size
* *count
> vid_limit
* 1024 * 1024)
167 static void free_buffer(struct videobuf_queue
*vq
, struct pxa_buffer
*buf
)
169 struct soc_camera_device
*icd
= vq
->priv_data
;
170 struct soc_camera_host
*ici
=
171 to_soc_camera_host(icd
->dev
.parent
);
172 struct pxa_camera_dev
*pcdev
= ici
->priv
;
173 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
176 BUG_ON(in_interrupt());
178 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
179 &buf
->vb
, buf
->vb
.baddr
, buf
->vb
.bsize
);
181 /* This waits until this buffer is out of danger, i.e., until it is no
182 * longer in STATE_QUEUED or STATE_ACTIVE */
183 videobuf_waiton(&buf
->vb
, 0, 0);
184 videobuf_dma_unmap(vq
, dma
);
185 videobuf_dma_free(dma
);
187 for (i
= 0; i
< ARRAY_SIZE(buf
->dmas
); i
++) {
188 if (buf
->dmas
[i
].sg_cpu
)
189 dma_free_coherent(pcdev
->dev
, buf
->dmas
[i
].sg_size
,
191 buf
->dmas
[i
].sg_dma
);
192 buf
->dmas
[i
].sg_cpu
= NULL
;
195 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
198 static int pxa_init_dma_channel(struct pxa_camera_dev
*pcdev
,
199 struct pxa_buffer
*buf
,
200 struct videobuf_dmabuf
*dma
, int channel
,
201 int sglen
, int sg_start
, int cibr
,
204 struct pxa_cam_dma
*pxa_dma
= &buf
->dmas
[channel
];
208 dma_free_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
209 pxa_dma
->sg_cpu
, pxa_dma
->sg_dma
);
211 pxa_dma
->sg_size
= (sglen
+ 1) * sizeof(struct pxa_dma_desc
);
212 pxa_dma
->sg_cpu
= dma_alloc_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
213 &pxa_dma
->sg_dma
, GFP_KERNEL
);
214 if (!pxa_dma
->sg_cpu
)
217 pxa_dma
->sglen
= sglen
;
219 for (i
= 0; i
< sglen
; i
++) {
220 int sg_i
= sg_start
+ i
;
221 struct scatterlist
*sg
= dma
->sglist
;
222 unsigned int dma_len
= sg_dma_len(&sg
[sg_i
]), xfer_len
;
224 pxa_dma
->sg_cpu
[i
].dsadr
= pcdev
->res
->start
+ cibr
;
225 pxa_dma
->sg_cpu
[i
].dtadr
= sg_dma_address(&sg
[sg_i
]);
227 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
228 xfer_len
= (min(dma_len
, size
) + 7) & ~7;
230 pxa_dma
->sg_cpu
[i
].dcmd
=
231 DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_INCTRGADDR
| xfer_len
;
233 pxa_dma
->sg_cpu
[i
].ddadr
=
234 pxa_dma
->sg_dma
+ (i
+ 1) * sizeof(struct pxa_dma_desc
);
237 pxa_dma
->sg_cpu
[sglen
- 1].ddadr
= DDADR_STOP
;
238 pxa_dma
->sg_cpu
[sglen
- 1].dcmd
|= DCMD_ENDIRQEN
;
243 static int pxa_videobuf_prepare(struct videobuf_queue
*vq
,
244 struct videobuf_buffer
*vb
, enum v4l2_field field
)
246 struct soc_camera_device
*icd
= vq
->priv_data
;
247 struct soc_camera_host
*ici
=
248 to_soc_camera_host(icd
->dev
.parent
);
249 struct pxa_camera_dev
*pcdev
= ici
->priv
;
250 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
252 int sglen_y
, sglen_yu
= 0, sglen_u
= 0, sglen_v
= 0;
253 int size_y
, size_u
= 0, size_v
= 0;
255 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
256 vb
, vb
->baddr
, vb
->bsize
);
258 /* Added list head initialization on alloc */
259 WARN_ON(!list_empty(&vb
->queue
));
262 /* This can be useful if you want to see if we actually fill
263 * the buffer with something */
264 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
267 BUG_ON(NULL
== icd
->current_fmt
);
269 /* I think, in buf_prepare you only have to protect global data,
270 * the actual buffer is yours */
273 if (buf
->fmt
!= icd
->current_fmt
||
274 vb
->width
!= icd
->width
||
275 vb
->height
!= icd
->height
||
276 vb
->field
!= field
) {
277 buf
->fmt
= icd
->current_fmt
;
278 vb
->width
= icd
->width
;
279 vb
->height
= icd
->height
;
281 vb
->state
= VIDEOBUF_NEEDS_INIT
;
284 vb
->size
= vb
->width
* vb
->height
* ((buf
->fmt
->depth
+ 7) >> 3);
285 if (0 != vb
->baddr
&& vb
->bsize
< vb
->size
) {
290 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
291 unsigned int size
= vb
->size
;
292 struct videobuf_dmabuf
*dma
= videobuf_to_dma(vb
);
294 ret
= videobuf_iolock(vq
, vb
, NULL
);
298 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
299 /* FIXME the calculations should be more precise */
300 sglen_y
= dma
->sglen
/ 2;
301 sglen_u
= sglen_v
= dma
->sglen
/ 4 + 1;
302 sglen_yu
= sglen_y
+ sglen_u
;
304 size_u
= size_v
= size
/ 4;
306 sglen_y
= dma
->sglen
;
310 /* init DMA for Y channel */
311 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 0, sglen_y
,
316 "DMA initialization for Y/RGB failed\n");
320 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
321 /* init DMA for U channel */
322 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 1, sglen_u
,
323 sglen_y
, 0x30, size_u
);
326 "DMA initialization for U failed\n");
330 /* init DMA for V channel */
331 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 2, sglen_v
,
332 sglen_yu
, 0x38, size_v
);
335 "DMA initialization for V failed\n");
340 vb
->state
= VIDEOBUF_PREPARED
;
344 buf
->active_dma
= DMA_Y
;
345 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
)
346 buf
->active_dma
|= DMA_U
| DMA_V
;
351 dma_free_coherent(pcdev
->dev
, buf
->dmas
[1].sg_size
,
352 buf
->dmas
[1].sg_cpu
, buf
->dmas
[1].sg_dma
);
354 dma_free_coherent(pcdev
->dev
, buf
->dmas
[0].sg_size
,
355 buf
->dmas
[0].sg_cpu
, buf
->dmas
[0].sg_dma
);
357 free_buffer(vq
, buf
);
363 static void pxa_videobuf_queue(struct videobuf_queue
*vq
,
364 struct videobuf_buffer
*vb
)
366 struct soc_camera_device
*icd
= vq
->priv_data
;
367 struct soc_camera_host
*ici
=
368 to_soc_camera_host(icd
->dev
.parent
);
369 struct pxa_camera_dev
*pcdev
= ici
->priv
;
370 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
371 struct pxa_buffer
*active
;
374 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
375 vb
, vb
->baddr
, vb
->bsize
);
376 spin_lock_irqsave(&pcdev
->lock
, flags
);
378 list_add_tail(&vb
->queue
, &pcdev
->capture
);
380 vb
->state
= VIDEOBUF_ACTIVE
;
381 active
= pcdev
->active
;
384 CIFR
|= CIFR_RESET_F
;
385 DDADR(pcdev
->dma_chans
[0]) = buf
->dmas
[0].sg_dma
;
386 DCSR(pcdev
->dma_chans
[0]) = DCSR_RUN
;
388 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
) {
389 DDADR(pcdev
->dma_chans
[1]) = buf
->dmas
[1].sg_dma
;
390 DCSR(pcdev
->dma_chans
[1]) = DCSR_RUN
;
392 DDADR(pcdev
->dma_chans
[2]) = buf
->dmas
[2].sg_dma
;
393 DCSR(pcdev
->dma_chans
[2]) = DCSR_RUN
;
399 struct pxa_cam_dma
*buf_dma
;
400 struct pxa_cam_dma
*act_dma
;
405 if (buf
->fmt
->fourcc
== V4L2_PIX_FMT_YUV422P
)
408 for (i
= 0; i
< channels
; i
++) {
409 buf_dma
= &buf
->dmas
[i
];
410 act_dma
= &active
->dmas
[i
];
411 nents
= buf_dma
->sglen
;
413 /* Stop DMA engine */
414 DCSR(pcdev
->dma_chans
[i
]) = 0;
416 /* Add the descriptors we just initialized to
417 the currently running chain */
418 act_dma
->sg_cpu
[act_dma
->sglen
- 1].ddadr
=
421 /* Setup a dummy descriptor with the DMA engines current
424 buf_dma
->sg_cpu
[nents
].dsadr
=
425 pcdev
->res
->start
+ 0x28 + i
*8; /* CIBRx */
426 buf_dma
->sg_cpu
[nents
].dtadr
=
427 DTADR(pcdev
->dma_chans
[i
]);
428 buf_dma
->sg_cpu
[nents
].dcmd
=
429 DCMD(pcdev
->dma_chans
[i
]);
431 if (DDADR(pcdev
->dma_chans
[i
]) == DDADR_STOP
) {
432 /* The DMA engine is on the last
433 descriptor, set the next descriptors
434 address to the descriptors we just
436 buf_dma
->sg_cpu
[nents
].ddadr
= buf_dma
->sg_dma
;
438 buf_dma
->sg_cpu
[nents
].ddadr
=
439 DDADR(pcdev
->dma_chans
[i
]);
442 /* The next descriptor is the dummy descriptor */
443 DDADR(pcdev
->dma_chans
[i
]) = buf_dma
->sg_dma
+ nents
*
444 sizeof(struct pxa_dma_desc
);
446 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
449 if (CISR
& (CISR_IFO_0
| CISR_IFO_1
| CISR_IFO_2
)) {
450 dev_warn(pcdev
->dev
, "FIFO overrun\n");
451 for (i
= 0; i
< channels
; i
++)
452 DDADR(pcdev
->dma_chans
[i
]) =
453 pcdev
->active
->dmas
[i
].sg_dma
;
456 CIFR
|= CIFR_RESET_F
;
457 for (i
= 0; i
< channels
; i
++)
458 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
464 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
467 static void pxa_videobuf_release(struct videobuf_queue
*vq
,
468 struct videobuf_buffer
*vb
)
470 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
472 struct soc_camera_device
*icd
= vq
->priv_data
;
474 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
475 vb
, vb
->baddr
, vb
->bsize
);
478 case VIDEOBUF_ACTIVE
:
479 dev_dbg(&icd
->dev
, "%s (active)\n", __func__
);
481 case VIDEOBUF_QUEUED
:
482 dev_dbg(&icd
->dev
, "%s (queued)\n", __func__
);
484 case VIDEOBUF_PREPARED
:
485 dev_dbg(&icd
->dev
, "%s (prepared)\n", __func__
);
488 dev_dbg(&icd
->dev
, "%s (unknown)\n", __func__
);
493 free_buffer(vq
, buf
);
496 static void pxa_camera_wakeup(struct pxa_camera_dev
*pcdev
,
497 struct videobuf_buffer
*vb
,
498 struct pxa_buffer
*buf
)
500 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
501 list_del_init(&vb
->queue
);
502 vb
->state
= VIDEOBUF_DONE
;
503 do_gettimeofday(&vb
->ts
);
507 if (list_empty(&pcdev
->capture
)) {
508 pcdev
->active
= NULL
;
509 DCSR(pcdev
->dma_chans
[0]) = 0;
510 DCSR(pcdev
->dma_chans
[1]) = 0;
511 DCSR(pcdev
->dma_chans
[2]) = 0;
516 pcdev
->active
= list_entry(pcdev
->capture
.next
,
517 struct pxa_buffer
, vb
.queue
);
520 static void pxa_camera_dma_irq(int channel
, struct pxa_camera_dev
*pcdev
,
521 enum pxa_camera_active_dma act_dma
)
523 struct pxa_buffer
*buf
;
526 struct videobuf_buffer
*vb
;
528 spin_lock_irqsave(&pcdev
->lock
, flags
);
530 status
= DCSR(channel
);
531 DCSR(channel
) = status
| DCSR_ENDINTR
;
533 if (status
& DCSR_BUSERR
) {
534 dev_err(pcdev
->dev
, "DMA Bus Error IRQ!\n");
538 if (!(status
& DCSR_ENDINTR
)) {
539 dev_err(pcdev
->dev
, "Unknown DMA IRQ source, "
540 "status: 0x%08x\n", status
);
544 if (!pcdev
->active
) {
545 dev_err(pcdev
->dev
, "DMA End IRQ with no active buffer!\n");
549 vb
= &pcdev
->active
->vb
;
550 buf
= container_of(vb
, struct pxa_buffer
, vb
);
551 WARN_ON(buf
->inwork
|| list_empty(&vb
->queue
));
552 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
553 vb
, vb
->baddr
, vb
->bsize
);
555 buf
->active_dma
&= ~act_dma
;
556 if (!buf
->active_dma
)
557 pxa_camera_wakeup(pcdev
, vb
, buf
);
560 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
563 static void pxa_camera_dma_irq_y(int channel
, void *data
)
565 struct pxa_camera_dev
*pcdev
= data
;
566 pxa_camera_dma_irq(channel
, pcdev
, DMA_Y
);
569 static void pxa_camera_dma_irq_u(int channel
, void *data
)
571 struct pxa_camera_dev
*pcdev
= data
;
572 pxa_camera_dma_irq(channel
, pcdev
, DMA_U
);
575 static void pxa_camera_dma_irq_v(int channel
, void *data
)
577 struct pxa_camera_dev
*pcdev
= data
;
578 pxa_camera_dma_irq(channel
, pcdev
, DMA_V
);
581 static struct videobuf_queue_ops pxa_videobuf_ops
= {
582 .buf_setup
= pxa_videobuf_setup
,
583 .buf_prepare
= pxa_videobuf_prepare
,
584 .buf_queue
= pxa_videobuf_queue
,
585 .buf_release
= pxa_videobuf_release
,
588 static int mclk_get_divisor(struct pxa_camera_dev
*pcdev
)
590 unsigned int mclk_10khz
= pcdev
->platform_mclk_10khz
;
592 unsigned long lcdclk
;
594 lcdclk
= clk_get_rate(pcdev
->clk
) / 10000;
596 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
597 * they get a nice Oops */
598 div
= (lcdclk
+ 2 * mclk_10khz
- 1) / (2 * mclk_10khz
) - 1;
600 dev_dbg(pcdev
->dev
, "LCD clock %lukHz, target freq %dkHz, "
601 "divisor %lu\n", lcdclk
* 10, mclk_10khz
* 10, div
);
606 static void pxa_camera_activate(struct pxa_camera_dev
*pcdev
)
608 struct pxacamera_platform_data
*pdata
= pcdev
->pdata
;
611 dev_dbg(pcdev
->dev
, "Registered platform device at %p data %p\n",
614 if (pdata
&& pdata
->init
) {
615 dev_dbg(pcdev
->dev
, "%s: Init gpios\n", __func__
);
616 pdata
->init(pcdev
->dev
);
619 if (pdata
&& pdata
->power
) {
620 dev_dbg(pcdev
->dev
, "%s: Power on camera\n", __func__
);
621 pdata
->power(pcdev
->dev
, 1);
624 if (pdata
&& pdata
->reset
) {
625 dev_dbg(pcdev
->dev
, "%s: Releasing camera reset\n",
627 pdata
->reset(pcdev
->dev
, 1);
630 CICR0
= 0x3FF; /* disable all interrupts */
632 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
633 cicr4
|= CICR4_PCLK_EN
;
634 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
635 cicr4
|= CICR4_MCLK_EN
;
636 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
638 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
640 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
643 CICR4
= mclk_get_divisor(pcdev
) | cicr4
;
645 clk_enable(pcdev
->clk
);
648 static void pxa_camera_deactivate(struct pxa_camera_dev
*pcdev
)
650 struct pxacamera_platform_data
*board
= pcdev
->pdata
;
652 clk_disable(pcdev
->clk
);
654 if (board
&& board
->reset
) {
655 dev_dbg(pcdev
->dev
, "%s: Asserting camera reset\n",
657 board
->reset(pcdev
->dev
, 0);
660 if (board
&& board
->power
) {
661 dev_dbg(pcdev
->dev
, "%s: Power off camera\n", __func__
);
662 board
->power(pcdev
->dev
, 0);
666 static irqreturn_t
pxa_camera_irq(int irq
, void *data
)
668 struct pxa_camera_dev
*pcdev
= data
;
669 unsigned int status
= CISR
;
671 dev_dbg(pcdev
->dev
, "Camera interrupt status 0x%x\n", status
);
677 /* The following two functions absolutely depend on the fact, that
678 * there can be only one camera on PXA quick capture interface */
679 static int pxa_camera_add_device(struct soc_camera_device
*icd
)
681 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
682 struct pxa_camera_dev
*pcdev
= ici
->priv
;
685 mutex_lock(&camera_lock
);
692 dev_info(&icd
->dev
, "PXA Camera driver attached to camera %d\n",
695 pxa_camera_activate(pcdev
);
696 ret
= icd
->ops
->init(icd
);
702 mutex_unlock(&camera_lock
);
707 static void pxa_camera_remove_device(struct soc_camera_device
*icd
)
709 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
710 struct pxa_camera_dev
*pcdev
= ici
->priv
;
712 BUG_ON(icd
!= pcdev
->icd
);
714 dev_info(&icd
->dev
, "PXA Camera driver detached from camera %d\n",
717 /* disable capture, disable interrupts */
720 /* Stop DMA engine */
721 DCSR(pcdev
->dma_chans
[0]) = 0;
722 DCSR(pcdev
->dma_chans
[1]) = 0;
723 DCSR(pcdev
->dma_chans
[2]) = 0;
725 icd
->ops
->release(icd
);
727 pxa_camera_deactivate(pcdev
);
732 static int test_platform_param(struct pxa_camera_dev
*pcdev
,
733 unsigned char buswidth
, unsigned long *flags
)
736 * Platform specified synchronization and pixel clock polarities are
737 * only a recommendation and are only used during probing. The PXA270
738 * quick capture interface supports both.
740 *flags
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
741 SOCAM_MASTER
: SOCAM_SLAVE
) |
742 SOCAM_HSYNC_ACTIVE_HIGH
|
743 SOCAM_HSYNC_ACTIVE_LOW
|
744 SOCAM_VSYNC_ACTIVE_HIGH
|
745 SOCAM_VSYNC_ACTIVE_LOW
|
746 SOCAM_PCLK_SAMPLE_RISING
|
747 SOCAM_PCLK_SAMPLE_FALLING
;
749 /* If requested data width is supported by the platform, use it */
752 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
))
754 *flags
|= SOCAM_DATAWIDTH_10
;
757 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
))
759 *flags
|= SOCAM_DATAWIDTH_9
;
762 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
))
764 *flags
|= SOCAM_DATAWIDTH_8
;
770 static int pxa_camera_set_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
772 struct soc_camera_host
*ici
=
773 to_soc_camera_host(icd
->dev
.parent
);
774 struct pxa_camera_dev
*pcdev
= ici
->priv
;
775 unsigned long dw
, bpp
, bus_flags
, camera_flags
, common_flags
;
776 u32 cicr0
, cicr1
, cicr4
= 0;
777 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
782 camera_flags
= icd
->ops
->query_bus_param(icd
);
784 common_flags
= soc_camera_bus_param_compatible(camera_flags
, bus_flags
);
788 /* Make choises, based on platform preferences */
789 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
790 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
791 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
792 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
794 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
797 if ((common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
) &&
798 (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)) {
799 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
800 common_flags
&= ~SOCAM_VSYNC_ACTIVE_HIGH
;
802 common_flags
&= ~SOCAM_VSYNC_ACTIVE_LOW
;
805 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
806 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
807 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
808 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
810 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
813 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
817 /* Datawidth is now guaranteed to be equal to one of the three values.
818 * We fix bit-per-pixel equal to data-width... */
819 switch (common_flags
& SOCAM_DATAWIDTH_MASK
) {
820 case SOCAM_DATAWIDTH_10
:
825 case SOCAM_DATAWIDTH_9
:
831 /* Actually it can only be 8 now,
832 * default is just to silence compiler warnings */
833 case SOCAM_DATAWIDTH_8
:
839 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
840 cicr4
|= CICR4_PCLK_EN
;
841 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
842 cicr4
|= CICR4_MCLK_EN
;
843 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
845 if (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)
847 if (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)
851 if (cicr0
& CICR0_ENB
)
852 CICR0
= cicr0
& ~CICR0_ENB
;
854 cicr1
= CICR1_PPL_VAL(icd
->width
- 1) | bpp
| dw
;
857 case V4L2_PIX_FMT_YUV422P
:
858 cicr1
|= CICR1_YCBCR_F
;
859 case V4L2_PIX_FMT_YUYV
:
860 cicr1
|= CICR1_COLOR_SP_VAL(2);
862 case V4L2_PIX_FMT_RGB555
:
863 cicr1
|= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
864 CICR1_TBIT
| CICR1_COLOR_SP_VAL(1);
866 case V4L2_PIX_FMT_RGB565
:
867 cicr1
|= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
873 CICR3
= CICR3_LPF_VAL(icd
->height
- 1) |
874 CICR3_BFW_VAL(min((unsigned short)255, icd
->y_skip_top
));
875 CICR4
= mclk_get_divisor(pcdev
) | cicr4
;
877 /* CIF interrupts are not used, only DMA */
878 CICR0
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
879 CICR0_SIM_MP
: (CICR0_SL_CAP_EN
| CICR0_SIM_SP
)) |
880 CICR0_DMAEN
| CICR0_IRQ_MASK
| (cicr0
& CICR0_ENB
);
885 static int pxa_camera_try_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
887 struct soc_camera_host
*ici
=
888 to_soc_camera_host(icd
->dev
.parent
);
889 struct pxa_camera_dev
*pcdev
= ici
->priv
;
890 unsigned long bus_flags
, camera_flags
;
891 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
896 camera_flags
= icd
->ops
->query_bus_param(icd
);
898 return soc_camera_bus_param_compatible(camera_flags
, bus_flags
) ? 0 : -EINVAL
;
901 static int pxa_camera_set_fmt_cap(struct soc_camera_device
*icd
,
902 __u32 pixfmt
, struct v4l2_rect
*rect
)
904 return icd
->ops
->set_fmt_cap(icd
, pixfmt
, rect
);
907 static int pxa_camera_try_fmt_cap(struct soc_camera_device
*icd
,
908 struct v4l2_format
*f
)
910 /* limit to pxa hardware capabilities */
911 if (f
->fmt
.pix
.height
< 32)
912 f
->fmt
.pix
.height
= 32;
913 if (f
->fmt
.pix
.height
> 2048)
914 f
->fmt
.pix
.height
= 2048;
915 if (f
->fmt
.pix
.width
< 48)
916 f
->fmt
.pix
.width
= 48;
917 if (f
->fmt
.pix
.width
> 2048)
918 f
->fmt
.pix
.width
= 2048;
919 f
->fmt
.pix
.width
&= ~0x01;
921 /* limit to sensor capabilities */
922 return icd
->ops
->try_fmt_cap(icd
, f
);
925 static int pxa_camera_reqbufs(struct soc_camera_file
*icf
,
926 struct v4l2_requestbuffers
*p
)
930 /* This is for locking debugging only. I removed spinlocks and now I
931 * check whether .prepare is ever called on a linked buffer, or whether
932 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
933 * it hadn't triggered */
934 for (i
= 0; i
< p
->count
; i
++) {
935 struct pxa_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
936 struct pxa_buffer
, vb
);
938 INIT_LIST_HEAD(&buf
->vb
.queue
);
944 static unsigned int pxa_camera_poll(struct file
*file
, poll_table
*pt
)
946 struct soc_camera_file
*icf
= file
->private_data
;
947 struct pxa_buffer
*buf
;
949 buf
= list_entry(icf
->vb_vidq
.stream
.next
, struct pxa_buffer
,
952 poll_wait(file
, &buf
->vb
.done
, pt
);
954 if (buf
->vb
.state
== VIDEOBUF_DONE
||
955 buf
->vb
.state
== VIDEOBUF_ERROR
)
956 return POLLIN
|POLLRDNORM
;
961 static int pxa_camera_querycap(struct soc_camera_host
*ici
,
962 struct v4l2_capability
*cap
)
964 /* cap->name is set by the firendly caller:-> */
965 strlcpy(cap
->card
, pxa_cam_driver_description
, sizeof(cap
->card
));
966 cap
->version
= PXA_CAM_VERSION_CODE
;
967 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
972 static spinlock_t
*pxa_camera_spinlock_alloc(struct soc_camera_file
*icf
)
974 struct soc_camera_host
*ici
=
975 to_soc_camera_host(icf
->icd
->dev
.parent
);
976 struct pxa_camera_dev
*pcdev
= ici
->priv
;
981 static struct soc_camera_host_ops pxa_soc_camera_host_ops
= {
982 .owner
= THIS_MODULE
,
983 .add
= pxa_camera_add_device
,
984 .remove
= pxa_camera_remove_device
,
985 .set_fmt_cap
= pxa_camera_set_fmt_cap
,
986 .try_fmt_cap
= pxa_camera_try_fmt_cap
,
987 .reqbufs
= pxa_camera_reqbufs
,
988 .poll
= pxa_camera_poll
,
989 .querycap
= pxa_camera_querycap
,
990 .try_bus_param
= pxa_camera_try_bus_param
,
991 .set_bus_param
= pxa_camera_set_bus_param
,
992 .spinlock_alloc
= pxa_camera_spinlock_alloc
,
995 /* Should be allocated dynamically too, but we have only one. */
996 static struct soc_camera_host pxa_soc_camera_host
= {
997 .drv_name
= PXA_CAM_DRV_NAME
,
998 .vbq_ops
= &pxa_videobuf_ops
,
999 .msize
= sizeof(struct pxa_buffer
),
1000 .ops
= &pxa_soc_camera_host_ops
,
1003 static int pxa_camera_probe(struct platform_device
*pdev
)
1005 struct pxa_camera_dev
*pcdev
;
1006 struct resource
*res
;
1011 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1012 irq
= platform_get_irq(pdev
, 0);
1018 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1020 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1025 pcdev
->clk
= clk_get(&pdev
->dev
, "CAMCLK");
1026 if (IS_ERR(pcdev
->clk
)) {
1027 err
= PTR_ERR(pcdev
->clk
);
1031 dev_set_drvdata(&pdev
->dev
, pcdev
);
1034 pcdev
->pdata
= pdev
->dev
.platform_data
;
1035 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1036 if (!(pcdev
->platform_flags
& (PXA_CAMERA_DATAWIDTH_8
|
1037 PXA_CAMERA_DATAWIDTH_9
| PXA_CAMERA_DATAWIDTH_10
))) {
1038 /* Platform hasn't set available data widths. This is bad.
1039 * Warn and use a default. */
1040 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1041 "data widths, using default 10 bit\n");
1042 pcdev
->platform_flags
|= PXA_CAMERA_DATAWIDTH_10
;
1044 pcdev
->platform_mclk_10khz
= pcdev
->pdata
->mclk_10khz
;
1045 if (!pcdev
->platform_mclk_10khz
) {
1046 dev_warn(&pdev
->dev
,
1047 "mclk_10khz == 0! Please, fix your platform data. "
1048 "Using default 20MHz\n");
1049 pcdev
->platform_mclk_10khz
= 2000;
1052 INIT_LIST_HEAD(&pcdev
->capture
);
1053 spin_lock_init(&pcdev
->lock
);
1056 * Request the regions.
1058 if (!request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
1059 PXA_CAM_DRV_NAME
)) {
1064 base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1071 pcdev
->dev
= &pdev
->dev
;
1074 pcdev
->dma_chans
[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH
,
1075 pxa_camera_dma_irq_y
, pcdev
);
1076 if (pcdev
->dma_chans
[0] < 0) {
1077 dev_err(pcdev
->dev
, "Can't request DMA for Y\n");
1081 dev_dbg(pcdev
->dev
, "got DMA channel %d\n", pcdev
->dma_chans
[0]);
1083 pcdev
->dma_chans
[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH
,
1084 pxa_camera_dma_irq_u
, pcdev
);
1085 if (pcdev
->dma_chans
[1] < 0) {
1086 dev_err(pcdev
->dev
, "Can't request DMA for U\n");
1088 goto exit_free_dma_y
;
1090 dev_dbg(pcdev
->dev
, "got DMA channel (U) %d\n", pcdev
->dma_chans
[1]);
1092 pcdev
->dma_chans
[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH
,
1093 pxa_camera_dma_irq_v
, pcdev
);
1094 if (pcdev
->dma_chans
[0] < 0) {
1095 dev_err(pcdev
->dev
, "Can't request DMA for V\n");
1097 goto exit_free_dma_u
;
1099 dev_dbg(pcdev
->dev
, "got DMA channel (V) %d\n", pcdev
->dma_chans
[2]);
1101 DRCMR68
= pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1102 DRCMR69
= pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1103 DRCMR70
= pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1106 err
= request_irq(pcdev
->irq
, pxa_camera_irq
, 0, PXA_CAM_DRV_NAME
,
1109 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1113 pxa_soc_camera_host
.priv
= pcdev
;
1114 pxa_soc_camera_host
.dev
.parent
= &pdev
->dev
;
1115 pxa_soc_camera_host
.nr
= pdev
->id
;
1116 err
= soc_camera_host_register(&pxa_soc_camera_host
);
1123 free_irq(pcdev
->irq
, pcdev
);
1125 pxa_free_dma(pcdev
->dma_chans
[2]);
1127 pxa_free_dma(pcdev
->dma_chans
[1]);
1129 pxa_free_dma(pcdev
->dma_chans
[0]);
1133 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1135 clk_put(pcdev
->clk
);
1142 static int __devexit
pxa_camera_remove(struct platform_device
*pdev
)
1144 struct pxa_camera_dev
*pcdev
= platform_get_drvdata(pdev
);
1145 struct resource
*res
;
1147 clk_put(pcdev
->clk
);
1149 pxa_free_dma(pcdev
->dma_chans
[0]);
1150 pxa_free_dma(pcdev
->dma_chans
[1]);
1151 pxa_free_dma(pcdev
->dma_chans
[2]);
1152 free_irq(pcdev
->irq
, pcdev
);
1154 soc_camera_host_unregister(&pxa_soc_camera_host
);
1156 iounmap(pcdev
->base
);
1159 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1163 dev_info(&pdev
->dev
, "PXA Camera driver unloaded\n");
1168 static struct platform_driver pxa_camera_driver
= {
1170 .name
= PXA_CAM_DRV_NAME
,
1172 .probe
= pxa_camera_probe
,
1173 .remove
= __exit_p(pxa_camera_remove
),
1177 static int __devinit
pxa_camera_init(void)
1179 return platform_driver_register(&pxa_camera_driver
);
1182 static void __exit
pxa_camera_exit(void)
1184 return platform_driver_unregister(&pxa_camera_driver
);
1187 module_init(pxa_camera_init
);
1188 module_exit(pxa_camera_exit
);
1190 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1191 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1192 MODULE_LICENSE("GPL");