2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/mutex.h>
29 #include <linux/clk.h>
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/videobuf-dma-sg.h>
34 #include <media/soc_camera.h>
36 #include <linux/videodev2.h>
39 #include <mach/pxa-regs.h>
40 #include <mach/camera.h>
42 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
43 #define PXA_CAM_DRV_NAME "pxa27x-camera"
45 #define CICR0_SIM_MP (0 << 24)
46 #define CICR0_SIM_SP (1 << 24)
47 #define CICR0_SIM_MS (2 << 24)
48 #define CICR0_SIM_EP (3 << 24)
49 #define CICR0_SIM_ES (4 << 24)
51 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
52 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
53 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
54 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
55 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
57 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
58 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
59 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
60 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
61 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
63 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
64 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
65 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
66 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
68 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
69 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
70 CICR0_EOFM | CICR0_FOM)
72 static DEFINE_MUTEX(camera_lock
);
77 enum pxa_camera_active_dma
{
83 /* descriptor needed for the PXA DMA engine */
86 struct pxa_dma_desc
*sg_cpu
;
91 /* buffer for one video frame */
93 /* common v4l buffer stuff -- must be first */
94 struct videobuf_buffer vb
;
96 const struct soc_camera_data_format
*fmt
;
98 /* our descriptor lists for Y, U and V channels */
99 struct pxa_cam_dma dmas
[3];
103 enum pxa_camera_active_dma active_dma
;
106 struct pxa_camera_dev
{
108 /* PXA27x is only supposed to handle one camera on its Quick Capture
109 * interface. If anyone ever builds hardware to enable more than
110 * one camera, they will have to modify this driver too */
111 struct soc_camera_device
*icd
;
118 unsigned int dma_chans
[3];
120 struct pxacamera_platform_data
*pdata
;
121 struct resource
*res
;
122 unsigned long platform_flags
;
123 unsigned long platform_mclk_10khz
;
125 struct list_head capture
;
129 struct pxa_buffer
*active
;
130 struct pxa_dma_desc
*sg_tail
[3];
135 static const char *pxa_cam_driver_description
= "PXA_Camera";
137 static unsigned int vid_limit
= 16; /* Video memory limit, in Mb */
140 * Videobuf operations
142 static int pxa_videobuf_setup(struct videobuf_queue
*vq
, unsigned int *count
,
145 struct soc_camera_device
*icd
= vq
->priv_data
;
146 struct soc_camera_host
*ici
=
147 to_soc_camera_host(icd
->dev
.parent
);
148 struct pxa_camera_dev
*pcdev
= ici
->priv
;
150 dev_dbg(&icd
->dev
, "count=%d, size=%d\n", *count
, *size
);
152 /* planar capture requires Y, U and V buffers to be page aligned */
153 if (pcdev
->channels
== 3) {
154 *size
= PAGE_ALIGN(icd
->width
* icd
->height
); /* Y pages */
155 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* U pages */
156 *size
+= PAGE_ALIGN(icd
->width
* icd
->height
/ 2); /* V pages */
158 *size
= icd
->width
* icd
->height
*
159 ((icd
->current_fmt
->depth
+ 7) >> 3);
164 while (*size
* *count
> vid_limit
* 1024 * 1024)
170 static void free_buffer(struct videobuf_queue
*vq
, struct pxa_buffer
*buf
)
172 struct soc_camera_device
*icd
= vq
->priv_data
;
173 struct soc_camera_host
*ici
=
174 to_soc_camera_host(icd
->dev
.parent
);
175 struct pxa_camera_dev
*pcdev
= ici
->priv
;
176 struct videobuf_dmabuf
*dma
= videobuf_to_dma(&buf
->vb
);
179 BUG_ON(in_interrupt());
181 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
182 &buf
->vb
, buf
->vb
.baddr
, buf
->vb
.bsize
);
184 /* This waits until this buffer is out of danger, i.e., until it is no
185 * longer in STATE_QUEUED or STATE_ACTIVE */
186 videobuf_waiton(&buf
->vb
, 0, 0);
187 videobuf_dma_unmap(vq
, dma
);
188 videobuf_dma_free(dma
);
190 for (i
= 0; i
< ARRAY_SIZE(buf
->dmas
); i
++) {
191 if (buf
->dmas
[i
].sg_cpu
)
192 dma_free_coherent(pcdev
->dev
, buf
->dmas
[i
].sg_size
,
194 buf
->dmas
[i
].sg_dma
);
195 buf
->dmas
[i
].sg_cpu
= NULL
;
198 buf
->vb
.state
= VIDEOBUF_NEEDS_INIT
;
201 static int pxa_init_dma_channel(struct pxa_camera_dev
*pcdev
,
202 struct pxa_buffer
*buf
,
203 struct videobuf_dmabuf
*dma
, int channel
,
204 int sglen
, int sg_start
, int cibr
,
207 struct pxa_cam_dma
*pxa_dma
= &buf
->dmas
[channel
];
211 dma_free_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
212 pxa_dma
->sg_cpu
, pxa_dma
->sg_dma
);
214 pxa_dma
->sg_size
= (sglen
+ 1) * sizeof(struct pxa_dma_desc
);
215 pxa_dma
->sg_cpu
= dma_alloc_coherent(pcdev
->dev
, pxa_dma
->sg_size
,
216 &pxa_dma
->sg_dma
, GFP_KERNEL
);
217 if (!pxa_dma
->sg_cpu
)
220 pxa_dma
->sglen
= sglen
;
222 for (i
= 0; i
< sglen
; i
++) {
223 int sg_i
= sg_start
+ i
;
224 struct scatterlist
*sg
= dma
->sglist
;
225 unsigned int dma_len
= sg_dma_len(&sg
[sg_i
]), xfer_len
;
227 pxa_dma
->sg_cpu
[i
].dsadr
= pcdev
->res
->start
+ cibr
;
228 pxa_dma
->sg_cpu
[i
].dtadr
= sg_dma_address(&sg
[sg_i
]);
230 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
231 xfer_len
= (min(dma_len
, size
) + 7) & ~7;
233 pxa_dma
->sg_cpu
[i
].dcmd
=
234 DCMD_FLOWSRC
| DCMD_BURST8
| DCMD_INCTRGADDR
| xfer_len
;
236 pxa_dma
->sg_cpu
[i
].ddadr
=
237 pxa_dma
->sg_dma
+ (i
+ 1) * sizeof(struct pxa_dma_desc
);
240 pxa_dma
->sg_cpu
[sglen
- 1].ddadr
= DDADR_STOP
;
241 pxa_dma
->sg_cpu
[sglen
- 1].dcmd
|= DCMD_ENDIRQEN
;
246 static int pxa_videobuf_prepare(struct videobuf_queue
*vq
,
247 struct videobuf_buffer
*vb
, enum v4l2_field field
)
249 struct soc_camera_device
*icd
= vq
->priv_data
;
250 struct soc_camera_host
*ici
=
251 to_soc_camera_host(icd
->dev
.parent
);
252 struct pxa_camera_dev
*pcdev
= ici
->priv
;
253 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
255 int sglen_y
, sglen_yu
= 0, sglen_u
= 0, sglen_v
= 0;
256 int size_y
, size_u
= 0, size_v
= 0;
258 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
259 vb
, vb
->baddr
, vb
->bsize
);
261 /* Added list head initialization on alloc */
262 WARN_ON(!list_empty(&vb
->queue
));
265 /* This can be useful if you want to see if we actually fill
266 * the buffer with something */
267 memset((void *)vb
->baddr
, 0xaa, vb
->bsize
);
270 BUG_ON(NULL
== icd
->current_fmt
);
272 /* I think, in buf_prepare you only have to protect global data,
273 * the actual buffer is yours */
276 if (buf
->fmt
!= icd
->current_fmt
||
277 vb
->width
!= icd
->width
||
278 vb
->height
!= icd
->height
||
279 vb
->field
!= field
) {
280 buf
->fmt
= icd
->current_fmt
;
281 vb
->width
= icd
->width
;
282 vb
->height
= icd
->height
;
284 vb
->state
= VIDEOBUF_NEEDS_INIT
;
287 vb
->size
= vb
->width
* vb
->height
* ((buf
->fmt
->depth
+ 7) >> 3);
288 if (0 != vb
->baddr
&& vb
->bsize
< vb
->size
) {
293 if (vb
->state
== VIDEOBUF_NEEDS_INIT
) {
294 unsigned int size
= vb
->size
;
295 struct videobuf_dmabuf
*dma
= videobuf_to_dma(vb
);
297 ret
= videobuf_iolock(vq
, vb
, NULL
);
301 if (pcdev
->channels
== 3) {
302 /* FIXME the calculations should be more precise */
303 sglen_y
= dma
->sglen
/ 2;
304 sglen_u
= sglen_v
= dma
->sglen
/ 4 + 1;
305 sglen_yu
= sglen_y
+ sglen_u
;
307 size_u
= size_v
= size
/ 4;
309 sglen_y
= dma
->sglen
;
313 /* init DMA for Y channel */
314 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 0, sglen_y
,
319 "DMA initialization for Y/RGB failed\n");
323 if (pcdev
->channels
== 3) {
324 /* init DMA for U channel */
325 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 1, sglen_u
,
326 sglen_y
, 0x30, size_u
);
329 "DMA initialization for U failed\n");
333 /* init DMA for V channel */
334 ret
= pxa_init_dma_channel(pcdev
, buf
, dma
, 2, sglen_v
,
335 sglen_yu
, 0x38, size_v
);
338 "DMA initialization for V failed\n");
343 vb
->state
= VIDEOBUF_PREPARED
;
347 buf
->active_dma
= DMA_Y
;
348 if (pcdev
->channels
== 3)
349 buf
->active_dma
|= DMA_U
| DMA_V
;
354 dma_free_coherent(pcdev
->dev
, buf
->dmas
[1].sg_size
,
355 buf
->dmas
[1].sg_cpu
, buf
->dmas
[1].sg_dma
);
357 dma_free_coherent(pcdev
->dev
, buf
->dmas
[0].sg_size
,
358 buf
->dmas
[0].sg_cpu
, buf
->dmas
[0].sg_dma
);
360 free_buffer(vq
, buf
);
366 static void pxa_videobuf_queue(struct videobuf_queue
*vq
,
367 struct videobuf_buffer
*vb
)
369 struct soc_camera_device
*icd
= vq
->priv_data
;
370 struct soc_camera_host
*ici
=
371 to_soc_camera_host(icd
->dev
.parent
);
372 struct pxa_camera_dev
*pcdev
= ici
->priv
;
373 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
374 struct pxa_buffer
*active
;
378 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
379 vb
, vb
->baddr
, vb
->bsize
);
380 spin_lock_irqsave(&pcdev
->lock
, flags
);
382 list_add_tail(&vb
->queue
, &pcdev
->capture
);
384 vb
->state
= VIDEOBUF_ACTIVE
;
385 active
= pcdev
->active
;
388 CIFR
|= CIFR_RESET_F
;
390 for (i
= 0; i
< pcdev
->channels
; i
++) {
391 DDADR(pcdev
->dma_chans
[i
]) = buf
->dmas
[i
].sg_dma
;
392 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
393 pcdev
->sg_tail
[i
] = buf
->dmas
[i
].sg_cpu
+ buf
->dmas
[i
].sglen
- 1;
399 struct pxa_cam_dma
*buf_dma
;
400 struct pxa_cam_dma
*act_dma
;
403 for (i
= 0; i
< pcdev
->channels
; i
++) {
404 buf_dma
= &buf
->dmas
[i
];
405 act_dma
= &active
->dmas
[i
];
406 nents
= buf_dma
->sglen
;
408 /* Stop DMA engine */
409 DCSR(pcdev
->dma_chans
[i
]) = 0;
411 /* Add the descriptors we just initialized to
412 the currently running chain */
413 pcdev
->sg_tail
[i
]->ddadr
= buf_dma
->sg_dma
;
414 pcdev
->sg_tail
[i
] = buf_dma
->sg_cpu
+ buf_dma
->sglen
- 1;
416 /* Setup a dummy descriptor with the DMA engines current
419 buf_dma
->sg_cpu
[nents
].dsadr
=
420 pcdev
->res
->start
+ 0x28 + i
*8; /* CIBRx */
421 buf_dma
->sg_cpu
[nents
].dtadr
=
422 DTADR(pcdev
->dma_chans
[i
]);
423 buf_dma
->sg_cpu
[nents
].dcmd
=
424 DCMD(pcdev
->dma_chans
[i
]);
426 if (DDADR(pcdev
->dma_chans
[i
]) == DDADR_STOP
) {
427 /* The DMA engine is on the last
428 descriptor, set the next descriptors
429 address to the descriptors we just
431 buf_dma
->sg_cpu
[nents
].ddadr
= buf_dma
->sg_dma
;
433 buf_dma
->sg_cpu
[nents
].ddadr
=
434 DDADR(pcdev
->dma_chans
[i
]);
437 /* The next descriptor is the dummy descriptor */
438 DDADR(pcdev
->dma_chans
[i
]) = buf_dma
->sg_dma
+ nents
*
439 sizeof(struct pxa_dma_desc
);
441 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
445 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
448 static void pxa_videobuf_release(struct videobuf_queue
*vq
,
449 struct videobuf_buffer
*vb
)
451 struct pxa_buffer
*buf
= container_of(vb
, struct pxa_buffer
, vb
);
453 struct soc_camera_device
*icd
= vq
->priv_data
;
455 dev_dbg(&icd
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
456 vb
, vb
->baddr
, vb
->bsize
);
459 case VIDEOBUF_ACTIVE
:
460 dev_dbg(&icd
->dev
, "%s (active)\n", __func__
);
462 case VIDEOBUF_QUEUED
:
463 dev_dbg(&icd
->dev
, "%s (queued)\n", __func__
);
465 case VIDEOBUF_PREPARED
:
466 dev_dbg(&icd
->dev
, "%s (prepared)\n", __func__
);
469 dev_dbg(&icd
->dev
, "%s (unknown)\n", __func__
);
474 free_buffer(vq
, buf
);
477 static void pxa_camera_wakeup(struct pxa_camera_dev
*pcdev
,
478 struct videobuf_buffer
*vb
,
479 struct pxa_buffer
*buf
)
481 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
482 list_del_init(&vb
->queue
);
483 vb
->state
= VIDEOBUF_DONE
;
484 do_gettimeofday(&vb
->ts
);
488 if (list_empty(&pcdev
->capture
)) {
489 pcdev
->active
= NULL
;
490 DCSR(pcdev
->dma_chans
[0]) = 0;
491 DCSR(pcdev
->dma_chans
[1]) = 0;
492 DCSR(pcdev
->dma_chans
[2]) = 0;
497 pcdev
->active
= list_entry(pcdev
->capture
.next
,
498 struct pxa_buffer
, vb
.queue
);
501 static void pxa_camera_dma_irq(int channel
, struct pxa_camera_dev
*pcdev
,
502 enum pxa_camera_active_dma act_dma
)
504 struct pxa_buffer
*buf
;
506 u32 status
, camera_status
, overrun
;
507 struct videobuf_buffer
*vb
;
509 spin_lock_irqsave(&pcdev
->lock
, flags
);
511 status
= DCSR(channel
);
512 DCSR(channel
) = status
| DCSR_ENDINTR
;
514 if (status
& DCSR_BUSERR
) {
515 dev_err(pcdev
->dev
, "DMA Bus Error IRQ!\n");
519 if (!(status
& DCSR_ENDINTR
)) {
520 dev_err(pcdev
->dev
, "Unknown DMA IRQ source, "
521 "status: 0x%08x\n", status
);
525 if (!pcdev
->active
) {
526 dev_err(pcdev
->dev
, "DMA End IRQ with no active buffer!\n");
530 camera_status
= CISR
;
531 overrun
= CISR_IFO_0
;
532 if (pcdev
->channels
== 3)
533 overrun
|= CISR_IFO_1
| CISR_IFO_2
;
534 if (camera_status
& overrun
) {
535 dev_dbg(pcdev
->dev
, "FIFO overrun! CISR: %x\n", camera_status
);
536 /* Stop the Capture Interface */
540 /* Reset the FIFOs */
541 CIFR
|= CIFR_RESET_F
;
542 /* Enable End-Of-Frame Interrupt */
543 CICR0
&= ~CICR0_EOFM
;
544 /* Restart the Capture Interface */
549 vb
= &pcdev
->active
->vb
;
550 buf
= container_of(vb
, struct pxa_buffer
, vb
);
551 WARN_ON(buf
->inwork
|| list_empty(&vb
->queue
));
552 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%08lx %d\n", __func__
,
553 vb
, vb
->baddr
, vb
->bsize
);
555 buf
->active_dma
&= ~act_dma
;
556 if (!buf
->active_dma
)
557 pxa_camera_wakeup(pcdev
, vb
, buf
);
560 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
563 static void pxa_camera_dma_irq_y(int channel
, void *data
)
565 struct pxa_camera_dev
*pcdev
= data
;
566 pxa_camera_dma_irq(channel
, pcdev
, DMA_Y
);
569 static void pxa_camera_dma_irq_u(int channel
, void *data
)
571 struct pxa_camera_dev
*pcdev
= data
;
572 pxa_camera_dma_irq(channel
, pcdev
, DMA_U
);
575 static void pxa_camera_dma_irq_v(int channel
, void *data
)
577 struct pxa_camera_dev
*pcdev
= data
;
578 pxa_camera_dma_irq(channel
, pcdev
, DMA_V
);
581 static struct videobuf_queue_ops pxa_videobuf_ops
= {
582 .buf_setup
= pxa_videobuf_setup
,
583 .buf_prepare
= pxa_videobuf_prepare
,
584 .buf_queue
= pxa_videobuf_queue
,
585 .buf_release
= pxa_videobuf_release
,
588 static void pxa_camera_init_videobuf(struct videobuf_queue
*q
,
589 struct soc_camera_device
*icd
)
591 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
592 struct pxa_camera_dev
*pcdev
= ici
->priv
;
594 /* We must pass NULL as dev pointer, then all pci_* dma operations
595 * transform to normal dma_* ones. */
596 videobuf_queue_sg_init(q
, &pxa_videobuf_ops
, NULL
, &pcdev
->lock
,
597 V4L2_BUF_TYPE_VIDEO_CAPTURE
, V4L2_FIELD_NONE
,
598 sizeof(struct pxa_buffer
), icd
);
601 static int mclk_get_divisor(struct pxa_camera_dev
*pcdev
)
603 unsigned int mclk_10khz
= pcdev
->platform_mclk_10khz
;
605 unsigned long lcdclk
;
607 lcdclk
= clk_get_rate(pcdev
->clk
) / 10000;
609 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
610 * they get a nice Oops */
611 div
= (lcdclk
+ 2 * mclk_10khz
- 1) / (2 * mclk_10khz
) - 1;
613 dev_dbg(pcdev
->dev
, "LCD clock %lukHz, target freq %dkHz, "
614 "divisor %lu\n", lcdclk
* 10, mclk_10khz
* 10, div
);
619 static void pxa_camera_activate(struct pxa_camera_dev
*pcdev
)
621 struct pxacamera_platform_data
*pdata
= pcdev
->pdata
;
624 dev_dbg(pcdev
->dev
, "Registered platform device at %p data %p\n",
627 if (pdata
&& pdata
->init
) {
628 dev_dbg(pcdev
->dev
, "%s: Init gpios\n", __func__
);
629 pdata
->init(pcdev
->dev
);
632 CICR0
= 0x3FF; /* disable all interrupts */
634 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
635 cicr4
|= CICR4_PCLK_EN
;
636 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
637 cicr4
|= CICR4_MCLK_EN
;
638 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
640 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
642 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
645 CICR4
= mclk_get_divisor(pcdev
) | cicr4
;
647 clk_enable(pcdev
->clk
);
650 static void pxa_camera_deactivate(struct pxa_camera_dev
*pcdev
)
652 clk_disable(pcdev
->clk
);
655 static irqreturn_t
pxa_camera_irq(int irq
, void *data
)
657 struct pxa_camera_dev
*pcdev
= data
;
658 unsigned int status
= CISR
;
660 dev_dbg(pcdev
->dev
, "Camera interrupt status 0x%x\n", status
);
667 if (status
& CISR_EOF
) {
669 for (i
= 0; i
< pcdev
->channels
; i
++) {
670 DDADR(pcdev
->dma_chans
[i
]) =
671 pcdev
->active
->dmas
[i
].sg_dma
;
672 DCSR(pcdev
->dma_chans
[i
]) = DCSR_RUN
;
680 /* The following two functions absolutely depend on the fact, that
681 * there can be only one camera on PXA quick capture interface */
682 static int pxa_camera_add_device(struct soc_camera_device
*icd
)
684 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
685 struct pxa_camera_dev
*pcdev
= ici
->priv
;
688 mutex_lock(&camera_lock
);
695 dev_info(&icd
->dev
, "PXA Camera driver attached to camera %d\n",
698 pxa_camera_activate(pcdev
);
699 ret
= icd
->ops
->init(icd
);
705 mutex_unlock(&camera_lock
);
710 static void pxa_camera_remove_device(struct soc_camera_device
*icd
)
712 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->dev
.parent
);
713 struct pxa_camera_dev
*pcdev
= ici
->priv
;
715 BUG_ON(icd
!= pcdev
->icd
);
717 dev_info(&icd
->dev
, "PXA Camera driver detached from camera %d\n",
720 /* disable capture, disable interrupts */
723 /* Stop DMA engine */
724 DCSR(pcdev
->dma_chans
[0]) = 0;
725 DCSR(pcdev
->dma_chans
[1]) = 0;
726 DCSR(pcdev
->dma_chans
[2]) = 0;
728 icd
->ops
->release(icd
);
730 pxa_camera_deactivate(pcdev
);
735 static int test_platform_param(struct pxa_camera_dev
*pcdev
,
736 unsigned char buswidth
, unsigned long *flags
)
739 * Platform specified synchronization and pixel clock polarities are
740 * only a recommendation and are only used during probing. The PXA270
741 * quick capture interface supports both.
743 *flags
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
744 SOCAM_MASTER
: SOCAM_SLAVE
) |
745 SOCAM_HSYNC_ACTIVE_HIGH
|
746 SOCAM_HSYNC_ACTIVE_LOW
|
747 SOCAM_VSYNC_ACTIVE_HIGH
|
748 SOCAM_VSYNC_ACTIVE_LOW
|
749 SOCAM_PCLK_SAMPLE_RISING
|
750 SOCAM_PCLK_SAMPLE_FALLING
;
752 /* If requested data width is supported by the platform, use it */
755 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_10
))
757 *flags
|= SOCAM_DATAWIDTH_10
;
760 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_9
))
762 *flags
|= SOCAM_DATAWIDTH_9
;
765 if (!(pcdev
->platform_flags
& PXA_CAMERA_DATAWIDTH_8
))
767 *flags
|= SOCAM_DATAWIDTH_8
;
773 static int pxa_camera_set_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
775 struct soc_camera_host
*ici
=
776 to_soc_camera_host(icd
->dev
.parent
);
777 struct pxa_camera_dev
*pcdev
= ici
->priv
;
778 unsigned long dw
, bpp
, bus_flags
, camera_flags
, common_flags
;
779 u32 cicr0
, cicr1
, cicr4
= 0;
780 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
785 camera_flags
= icd
->ops
->query_bus_param(icd
);
787 common_flags
= soc_camera_bus_param_compatible(camera_flags
, bus_flags
);
793 /* Make choises, based on platform preferences */
794 if ((common_flags
& SOCAM_HSYNC_ACTIVE_HIGH
) &&
795 (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)) {
796 if (pcdev
->platform_flags
& PXA_CAMERA_HSP
)
797 common_flags
&= ~SOCAM_HSYNC_ACTIVE_HIGH
;
799 common_flags
&= ~SOCAM_HSYNC_ACTIVE_LOW
;
802 if ((common_flags
& SOCAM_VSYNC_ACTIVE_HIGH
) &&
803 (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)) {
804 if (pcdev
->platform_flags
& PXA_CAMERA_VSP
)
805 common_flags
&= ~SOCAM_VSYNC_ACTIVE_HIGH
;
807 common_flags
&= ~SOCAM_VSYNC_ACTIVE_LOW
;
810 if ((common_flags
& SOCAM_PCLK_SAMPLE_RISING
) &&
811 (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)) {
812 if (pcdev
->platform_flags
& PXA_CAMERA_PCP
)
813 common_flags
&= ~SOCAM_PCLK_SAMPLE_RISING
;
815 common_flags
&= ~SOCAM_PCLK_SAMPLE_FALLING
;
818 ret
= icd
->ops
->set_bus_param(icd
, common_flags
);
822 /* Datawidth is now guaranteed to be equal to one of the three values.
823 * We fix bit-per-pixel equal to data-width... */
824 switch (common_flags
& SOCAM_DATAWIDTH_MASK
) {
825 case SOCAM_DATAWIDTH_10
:
830 case SOCAM_DATAWIDTH_9
:
836 /* Actually it can only be 8 now,
837 * default is just to silence compiler warnings */
838 case SOCAM_DATAWIDTH_8
:
844 if (pcdev
->platform_flags
& PXA_CAMERA_PCLK_EN
)
845 cicr4
|= CICR4_PCLK_EN
;
846 if (pcdev
->platform_flags
& PXA_CAMERA_MCLK_EN
)
847 cicr4
|= CICR4_MCLK_EN
;
848 if (common_flags
& SOCAM_PCLK_SAMPLE_FALLING
)
850 if (common_flags
& SOCAM_HSYNC_ACTIVE_LOW
)
852 if (common_flags
& SOCAM_VSYNC_ACTIVE_LOW
)
856 if (cicr0
& CICR0_ENB
)
857 CICR0
= cicr0
& ~CICR0_ENB
;
859 cicr1
= CICR1_PPL_VAL(icd
->width
- 1) | bpp
| dw
;
862 case V4L2_PIX_FMT_YUV422P
:
864 cicr1
|= CICR1_YCBCR_F
;
865 case V4L2_PIX_FMT_YUYV
:
866 cicr1
|= CICR1_COLOR_SP_VAL(2);
868 case V4L2_PIX_FMT_RGB555
:
869 cicr1
|= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
870 CICR1_TBIT
| CICR1_COLOR_SP_VAL(1);
872 case V4L2_PIX_FMT_RGB565
:
873 cicr1
|= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
879 CICR3
= CICR3_LPF_VAL(icd
->height
- 1) |
880 CICR3_BFW_VAL(min((unsigned short)255, icd
->y_skip_top
));
881 CICR4
= mclk_get_divisor(pcdev
) | cicr4
;
883 /* CIF interrupts are not used, only DMA */
884 CICR0
= (pcdev
->platform_flags
& PXA_CAMERA_MASTER
?
885 CICR0_SIM_MP
: (CICR0_SL_CAP_EN
| CICR0_SIM_SP
)) |
886 CICR0_DMAEN
| CICR0_IRQ_MASK
| (cicr0
& CICR0_ENB
);
891 static int pxa_camera_try_bus_param(struct soc_camera_device
*icd
, __u32 pixfmt
)
893 struct soc_camera_host
*ici
=
894 to_soc_camera_host(icd
->dev
.parent
);
895 struct pxa_camera_dev
*pcdev
= ici
->priv
;
896 unsigned long bus_flags
, camera_flags
;
897 int ret
= test_platform_param(pcdev
, icd
->buswidth
, &bus_flags
);
902 camera_flags
= icd
->ops
->query_bus_param(icd
);
904 return soc_camera_bus_param_compatible(camera_flags
, bus_flags
) ? 0 : -EINVAL
;
907 static int pxa_camera_set_fmt_cap(struct soc_camera_device
*icd
,
908 __u32 pixfmt
, struct v4l2_rect
*rect
)
910 return icd
->ops
->set_fmt_cap(icd
, pixfmt
, rect
);
913 static int pxa_camera_try_fmt_cap(struct soc_camera_device
*icd
,
914 struct v4l2_format
*f
)
916 /* limit to pxa hardware capabilities */
917 if (f
->fmt
.pix
.height
< 32)
918 f
->fmt
.pix
.height
= 32;
919 if (f
->fmt
.pix
.height
> 2048)
920 f
->fmt
.pix
.height
= 2048;
921 if (f
->fmt
.pix
.width
< 48)
922 f
->fmt
.pix
.width
= 48;
923 if (f
->fmt
.pix
.width
> 2048)
924 f
->fmt
.pix
.width
= 2048;
925 f
->fmt
.pix
.width
&= ~0x01;
927 /* limit to sensor capabilities */
928 return icd
->ops
->try_fmt_cap(icd
, f
);
931 static int pxa_camera_reqbufs(struct soc_camera_file
*icf
,
932 struct v4l2_requestbuffers
*p
)
936 /* This is for locking debugging only. I removed spinlocks and now I
937 * check whether .prepare is ever called on a linked buffer, or whether
938 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
939 * it hadn't triggered */
940 for (i
= 0; i
< p
->count
; i
++) {
941 struct pxa_buffer
*buf
= container_of(icf
->vb_vidq
.bufs
[i
],
942 struct pxa_buffer
, vb
);
944 INIT_LIST_HEAD(&buf
->vb
.queue
);
950 static unsigned int pxa_camera_poll(struct file
*file
, poll_table
*pt
)
952 struct soc_camera_file
*icf
= file
->private_data
;
953 struct pxa_buffer
*buf
;
955 buf
= list_entry(icf
->vb_vidq
.stream
.next
, struct pxa_buffer
,
958 poll_wait(file
, &buf
->vb
.done
, pt
);
960 if (buf
->vb
.state
== VIDEOBUF_DONE
||
961 buf
->vb
.state
== VIDEOBUF_ERROR
)
962 return POLLIN
|POLLRDNORM
;
967 static int pxa_camera_querycap(struct soc_camera_host
*ici
,
968 struct v4l2_capability
*cap
)
970 /* cap->name is set by the firendly caller:-> */
971 strlcpy(cap
->card
, pxa_cam_driver_description
, sizeof(cap
->card
));
972 cap
->version
= PXA_CAM_VERSION_CODE
;
973 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
978 static int pxa_camera_suspend(struct soc_camera_device
*icd
, pm_message_t state
)
980 struct soc_camera_host
*ici
=
981 to_soc_camera_host(icd
->dev
.parent
);
982 struct pxa_camera_dev
*pcdev
= ici
->priv
;
985 pcdev
->save_cicr
[i
++] = CICR0
;
986 pcdev
->save_cicr
[i
++] = CICR1
;
987 pcdev
->save_cicr
[i
++] = CICR2
;
988 pcdev
->save_cicr
[i
++] = CICR3
;
989 pcdev
->save_cicr
[i
++] = CICR4
;
991 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->suspend
))
992 ret
= pcdev
->icd
->ops
->suspend(pcdev
->icd
, state
);
997 static int pxa_camera_resume(struct soc_camera_device
*icd
)
999 struct soc_camera_host
*ici
=
1000 to_soc_camera_host(icd
->dev
.parent
);
1001 struct pxa_camera_dev
*pcdev
= ici
->priv
;
1004 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1005 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1006 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1008 CICR0
= pcdev
->save_cicr
[i
++] & ~CICR0_ENB
;
1009 CICR1
= pcdev
->save_cicr
[i
++];
1010 CICR2
= pcdev
->save_cicr
[i
++];
1011 CICR3
= pcdev
->save_cicr
[i
++];
1012 CICR4
= pcdev
->save_cicr
[i
++];
1014 if ((pcdev
->icd
) && (pcdev
->icd
->ops
->resume
))
1015 ret
= pcdev
->icd
->ops
->resume(pcdev
->icd
);
1017 /* Restart frame capture if active buffer exists */
1018 if (!ret
&& pcdev
->active
) {
1019 /* Reset the FIFOs */
1020 CIFR
|= CIFR_RESET_F
;
1021 /* Enable End-Of-Frame Interrupt */
1022 CICR0
&= ~CICR0_EOFM
;
1023 /* Restart the Capture Interface */
1030 static struct soc_camera_host_ops pxa_soc_camera_host_ops
= {
1031 .owner
= THIS_MODULE
,
1032 .add
= pxa_camera_add_device
,
1033 .remove
= pxa_camera_remove_device
,
1034 .suspend
= pxa_camera_suspend
,
1035 .resume
= pxa_camera_resume
,
1036 .set_fmt_cap
= pxa_camera_set_fmt_cap
,
1037 .try_fmt_cap
= pxa_camera_try_fmt_cap
,
1038 .init_videobuf
= pxa_camera_init_videobuf
,
1039 .reqbufs
= pxa_camera_reqbufs
,
1040 .poll
= pxa_camera_poll
,
1041 .querycap
= pxa_camera_querycap
,
1042 .try_bus_param
= pxa_camera_try_bus_param
,
1043 .set_bus_param
= pxa_camera_set_bus_param
,
1046 /* Should be allocated dynamically too, but we have only one. */
1047 static struct soc_camera_host pxa_soc_camera_host
= {
1048 .drv_name
= PXA_CAM_DRV_NAME
,
1049 .ops
= &pxa_soc_camera_host_ops
,
1052 static int pxa_camera_probe(struct platform_device
*pdev
)
1054 struct pxa_camera_dev
*pcdev
;
1055 struct resource
*res
;
1060 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1061 irq
= platform_get_irq(pdev
, 0);
1062 if (!res
|| irq
< 0) {
1067 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1069 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1074 pcdev
->clk
= clk_get(&pdev
->dev
, "CAMCLK");
1075 if (IS_ERR(pcdev
->clk
)) {
1076 err
= PTR_ERR(pcdev
->clk
);
1080 dev_set_drvdata(&pdev
->dev
, pcdev
);
1083 pcdev
->pdata
= pdev
->dev
.platform_data
;
1084 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1085 if (!(pcdev
->platform_flags
& (PXA_CAMERA_DATAWIDTH_8
|
1086 PXA_CAMERA_DATAWIDTH_9
| PXA_CAMERA_DATAWIDTH_10
))) {
1087 /* Platform hasn't set available data widths. This is bad.
1088 * Warn and use a default. */
1089 dev_warn(&pdev
->dev
, "WARNING! Platform hasn't set available "
1090 "data widths, using default 10 bit\n");
1091 pcdev
->platform_flags
|= PXA_CAMERA_DATAWIDTH_10
;
1093 pcdev
->platform_mclk_10khz
= pcdev
->pdata
->mclk_10khz
;
1094 if (!pcdev
->platform_mclk_10khz
) {
1095 dev_warn(&pdev
->dev
,
1096 "mclk_10khz == 0! Please, fix your platform data. "
1097 "Using default 20MHz\n");
1098 pcdev
->platform_mclk_10khz
= 2000;
1101 INIT_LIST_HEAD(&pcdev
->capture
);
1102 spin_lock_init(&pcdev
->lock
);
1105 * Request the regions.
1107 if (!request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
1108 PXA_CAM_DRV_NAME
)) {
1113 base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1120 pcdev
->dev
= &pdev
->dev
;
1123 err
= pxa_request_dma("CI_Y", DMA_PRIO_HIGH
,
1124 pxa_camera_dma_irq_y
, pcdev
);
1126 dev_err(pcdev
->dev
, "Can't request DMA for Y\n");
1129 pcdev
->dma_chans
[0] = err
;
1130 dev_dbg(pcdev
->dev
, "got DMA channel %d\n", pcdev
->dma_chans
[0]);
1132 err
= pxa_request_dma("CI_U", DMA_PRIO_HIGH
,
1133 pxa_camera_dma_irq_u
, pcdev
);
1135 dev_err(pcdev
->dev
, "Can't request DMA for U\n");
1136 goto exit_free_dma_y
;
1138 pcdev
->dma_chans
[1] = err
;
1139 dev_dbg(pcdev
->dev
, "got DMA channel (U) %d\n", pcdev
->dma_chans
[1]);
1141 err
= pxa_request_dma("CI_V", DMA_PRIO_HIGH
,
1142 pxa_camera_dma_irq_v
, pcdev
);
1144 dev_err(pcdev
->dev
, "Can't request DMA for V\n");
1145 goto exit_free_dma_u
;
1147 pcdev
->dma_chans
[2] = err
;
1148 dev_dbg(pcdev
->dev
, "got DMA channel (V) %d\n", pcdev
->dma_chans
[2]);
1150 DRCMR(68) = pcdev
->dma_chans
[0] | DRCMR_MAPVLD
;
1151 DRCMR(69) = pcdev
->dma_chans
[1] | DRCMR_MAPVLD
;
1152 DRCMR(70) = pcdev
->dma_chans
[2] | DRCMR_MAPVLD
;
1155 err
= request_irq(pcdev
->irq
, pxa_camera_irq
, 0, PXA_CAM_DRV_NAME
,
1158 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1162 pxa_soc_camera_host
.priv
= pcdev
;
1163 pxa_soc_camera_host
.dev
.parent
= &pdev
->dev
;
1164 pxa_soc_camera_host
.nr
= pdev
->id
;
1165 err
= soc_camera_host_register(&pxa_soc_camera_host
);
1172 free_irq(pcdev
->irq
, pcdev
);
1174 pxa_free_dma(pcdev
->dma_chans
[2]);
1176 pxa_free_dma(pcdev
->dma_chans
[1]);
1178 pxa_free_dma(pcdev
->dma_chans
[0]);
1182 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1184 clk_put(pcdev
->clk
);
1191 static int __devexit
pxa_camera_remove(struct platform_device
*pdev
)
1193 struct pxa_camera_dev
*pcdev
= platform_get_drvdata(pdev
);
1194 struct resource
*res
;
1196 clk_put(pcdev
->clk
);
1198 pxa_free_dma(pcdev
->dma_chans
[0]);
1199 pxa_free_dma(pcdev
->dma_chans
[1]);
1200 pxa_free_dma(pcdev
->dma_chans
[2]);
1201 free_irq(pcdev
->irq
, pcdev
);
1203 soc_camera_host_unregister(&pxa_soc_camera_host
);
1205 iounmap(pcdev
->base
);
1208 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
1212 dev_info(&pdev
->dev
, "PXA Camera driver unloaded\n");
1217 static struct platform_driver pxa_camera_driver
= {
1219 .name
= PXA_CAM_DRV_NAME
,
1221 .probe
= pxa_camera_probe
,
1222 .remove
= __exit_p(pxa_camera_remove
),
1226 static int __devinit
pxa_camera_init(void)
1228 return platform_driver_register(&pxa_camera_driver
);
1231 static void __exit
pxa_camera_exit(void)
1233 platform_driver_unregister(&pxa_camera_driver
);
1236 module_init(pxa_camera_init
);
1237 module_exit(pxa_camera_exit
);
1239 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1240 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1241 MODULE_LICENSE("GPL");