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Merge branch 'linus' into core/rcu
[deliverable/linux.git] / drivers / media / video / pxa_camera.c
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/mutex.h>
29 #include <linux/clk.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/videobuf-dma-sg.h>
34 #include <media/soc_camera.h>
35
36 #include <linux/videodev2.h>
37
38 #include <asm/dma.h>
39 #include <mach/pxa-regs.h>
40 #include <mach/camera.h>
41
42 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
43 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44
45 #define CICR0_SIM_MP (0 << 24)
46 #define CICR0_SIM_SP (1 << 24)
47 #define CICR0_SIM_MS (2 << 24)
48 #define CICR0_SIM_EP (3 << 24)
49 #define CICR0_SIM_ES (4 << 24)
50
51 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
52 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
53 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
54 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
55 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
56
57 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
58 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
59 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
60 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
61 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
62
63 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
64 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
65 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
66 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
67
68 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
69 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
70 CICR0_EOFM | CICR0_FOM)
71
72 static DEFINE_MUTEX(camera_lock);
73
74 /*
75 * Structures
76 */
77 enum pxa_camera_active_dma {
78 DMA_Y = 0x1,
79 DMA_U = 0x2,
80 DMA_V = 0x4,
81 };
82
83 /* descriptor needed for the PXA DMA engine */
84 struct pxa_cam_dma {
85 dma_addr_t sg_dma;
86 struct pxa_dma_desc *sg_cpu;
87 size_t sg_size;
88 int sglen;
89 };
90
91 /* buffer for one video frame */
92 struct pxa_buffer {
93 /* common v4l buffer stuff -- must be first */
94 struct videobuf_buffer vb;
95
96 const struct soc_camera_data_format *fmt;
97
98 /* our descriptor lists for Y, U and V channels */
99 struct pxa_cam_dma dmas[3];
100
101 int inwork;
102
103 enum pxa_camera_active_dma active_dma;
104 };
105
106 struct pxa_camera_dev {
107 struct device *dev;
108 /* PXA27x is only supposed to handle one camera on its Quick Capture
109 * interface. If anyone ever builds hardware to enable more than
110 * one camera, they will have to modify this driver too */
111 struct soc_camera_device *icd;
112 struct clk *clk;
113
114 unsigned int irq;
115 void __iomem *base;
116
117 int channels;
118 unsigned int dma_chans[3];
119
120 struct pxacamera_platform_data *pdata;
121 struct resource *res;
122 unsigned long platform_flags;
123 unsigned long platform_mclk_10khz;
124
125 struct list_head capture;
126
127 spinlock_t lock;
128
129 struct pxa_buffer *active;
130 struct pxa_dma_desc *sg_tail[3];
131
132 u32 save_cicr[5];
133 };
134
135 static const char *pxa_cam_driver_description = "PXA_Camera";
136
137 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
138
139 /*
140 * Videobuf operations
141 */
142 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
143 unsigned int *size)
144 {
145 struct soc_camera_device *icd = vq->priv_data;
146 struct soc_camera_host *ici =
147 to_soc_camera_host(icd->dev.parent);
148 struct pxa_camera_dev *pcdev = ici->priv;
149
150 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
151
152 /* planar capture requires Y, U and V buffers to be page aligned */
153 if (pcdev->channels == 3) {
154 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
155 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
156 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
157 } else {
158 *size = icd->width * icd->height *
159 ((icd->current_fmt->depth + 7) >> 3);
160 }
161
162 if (0 == *count)
163 *count = 32;
164 while (*size * *count > vid_limit * 1024 * 1024)
165 (*count)--;
166
167 return 0;
168 }
169
170 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
171 {
172 struct soc_camera_device *icd = vq->priv_data;
173 struct soc_camera_host *ici =
174 to_soc_camera_host(icd->dev.parent);
175 struct pxa_camera_dev *pcdev = ici->priv;
176 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
177 int i;
178
179 BUG_ON(in_interrupt());
180
181 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
182 &buf->vb, buf->vb.baddr, buf->vb.bsize);
183
184 /* This waits until this buffer is out of danger, i.e., until it is no
185 * longer in STATE_QUEUED or STATE_ACTIVE */
186 videobuf_waiton(&buf->vb, 0, 0);
187 videobuf_dma_unmap(vq, dma);
188 videobuf_dma_free(dma);
189
190 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
191 if (buf->dmas[i].sg_cpu)
192 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
193 buf->dmas[i].sg_cpu,
194 buf->dmas[i].sg_dma);
195 buf->dmas[i].sg_cpu = NULL;
196 }
197
198 buf->vb.state = VIDEOBUF_NEEDS_INIT;
199 }
200
201 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
202 struct pxa_buffer *buf,
203 struct videobuf_dmabuf *dma, int channel,
204 int sglen, int sg_start, int cibr,
205 unsigned int size)
206 {
207 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
208 int i;
209
210 if (pxa_dma->sg_cpu)
211 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
212 pxa_dma->sg_cpu, pxa_dma->sg_dma);
213
214 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
215 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
216 &pxa_dma->sg_dma, GFP_KERNEL);
217 if (!pxa_dma->sg_cpu)
218 return -ENOMEM;
219
220 pxa_dma->sglen = sglen;
221
222 for (i = 0; i < sglen; i++) {
223 int sg_i = sg_start + i;
224 struct scatterlist *sg = dma->sglist;
225 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
226
227 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
228 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
229
230 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
231 xfer_len = (min(dma_len, size) + 7) & ~7;
232
233 pxa_dma->sg_cpu[i].dcmd =
234 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
235 size -= dma_len;
236 pxa_dma->sg_cpu[i].ddadr =
237 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
238 }
239
240 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
241 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
242
243 return 0;
244 }
245
246 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
247 struct videobuf_buffer *vb, enum v4l2_field field)
248 {
249 struct soc_camera_device *icd = vq->priv_data;
250 struct soc_camera_host *ici =
251 to_soc_camera_host(icd->dev.parent);
252 struct pxa_camera_dev *pcdev = ici->priv;
253 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
254 int ret;
255 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
256 int size_y, size_u = 0, size_v = 0;
257
258 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
259 vb, vb->baddr, vb->bsize);
260
261 /* Added list head initialization on alloc */
262 WARN_ON(!list_empty(&vb->queue));
263
264 #ifdef DEBUG
265 /* This can be useful if you want to see if we actually fill
266 * the buffer with something */
267 memset((void *)vb->baddr, 0xaa, vb->bsize);
268 #endif
269
270 BUG_ON(NULL == icd->current_fmt);
271
272 /* I think, in buf_prepare you only have to protect global data,
273 * the actual buffer is yours */
274 buf->inwork = 1;
275
276 if (buf->fmt != icd->current_fmt ||
277 vb->width != icd->width ||
278 vb->height != icd->height ||
279 vb->field != field) {
280 buf->fmt = icd->current_fmt;
281 vb->width = icd->width;
282 vb->height = icd->height;
283 vb->field = field;
284 vb->state = VIDEOBUF_NEEDS_INIT;
285 }
286
287 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
288 if (0 != vb->baddr && vb->bsize < vb->size) {
289 ret = -EINVAL;
290 goto out;
291 }
292
293 if (vb->state == VIDEOBUF_NEEDS_INIT) {
294 unsigned int size = vb->size;
295 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
296
297 ret = videobuf_iolock(vq, vb, NULL);
298 if (ret)
299 goto fail;
300
301 if (pcdev->channels == 3) {
302 /* FIXME the calculations should be more precise */
303 sglen_y = dma->sglen / 2;
304 sglen_u = sglen_v = dma->sglen / 4 + 1;
305 sglen_yu = sglen_y + sglen_u;
306 size_y = size / 2;
307 size_u = size_v = size / 4;
308 } else {
309 sglen_y = dma->sglen;
310 size_y = size;
311 }
312
313 /* init DMA for Y channel */
314 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
315 0, 0x28, size_y);
316
317 if (ret) {
318 dev_err(pcdev->dev,
319 "DMA initialization for Y/RGB failed\n");
320 goto fail;
321 }
322
323 if (pcdev->channels == 3) {
324 /* init DMA for U channel */
325 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
326 sglen_y, 0x30, size_u);
327 if (ret) {
328 dev_err(pcdev->dev,
329 "DMA initialization for U failed\n");
330 goto fail_u;
331 }
332
333 /* init DMA for V channel */
334 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
335 sglen_yu, 0x38, size_v);
336 if (ret) {
337 dev_err(pcdev->dev,
338 "DMA initialization for V failed\n");
339 goto fail_v;
340 }
341 }
342
343 vb->state = VIDEOBUF_PREPARED;
344 }
345
346 buf->inwork = 0;
347 buf->active_dma = DMA_Y;
348 if (pcdev->channels == 3)
349 buf->active_dma |= DMA_U | DMA_V;
350
351 return 0;
352
353 fail_v:
354 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
355 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
356 fail_u:
357 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
358 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
359 fail:
360 free_buffer(vq, buf);
361 out:
362 buf->inwork = 0;
363 return ret;
364 }
365
366 static void pxa_videobuf_queue(struct videobuf_queue *vq,
367 struct videobuf_buffer *vb)
368 {
369 struct soc_camera_device *icd = vq->priv_data;
370 struct soc_camera_host *ici =
371 to_soc_camera_host(icd->dev.parent);
372 struct pxa_camera_dev *pcdev = ici->priv;
373 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
374 struct pxa_buffer *active;
375 unsigned long flags;
376 int i;
377
378 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
379 vb, vb->baddr, vb->bsize);
380 spin_lock_irqsave(&pcdev->lock, flags);
381
382 list_add_tail(&vb->queue, &pcdev->capture);
383
384 vb->state = VIDEOBUF_ACTIVE;
385 active = pcdev->active;
386
387 if (!active) {
388 CIFR |= CIFR_RESET_F;
389
390 for (i = 0; i < pcdev->channels; i++) {
391 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
392 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
393 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
394 }
395
396 pcdev->active = buf;
397 CICR0 |= CICR0_ENB;
398 } else {
399 struct pxa_cam_dma *buf_dma;
400 struct pxa_cam_dma *act_dma;
401 int nents;
402
403 for (i = 0; i < pcdev->channels; i++) {
404 buf_dma = &buf->dmas[i];
405 act_dma = &active->dmas[i];
406 nents = buf_dma->sglen;
407
408 /* Stop DMA engine */
409 DCSR(pcdev->dma_chans[i]) = 0;
410
411 /* Add the descriptors we just initialized to
412 the currently running chain */
413 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
414 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
415
416 /* Setup a dummy descriptor with the DMA engines current
417 * state
418 */
419 buf_dma->sg_cpu[nents].dsadr =
420 pcdev->res->start + 0x28 + i*8; /* CIBRx */
421 buf_dma->sg_cpu[nents].dtadr =
422 DTADR(pcdev->dma_chans[i]);
423 buf_dma->sg_cpu[nents].dcmd =
424 DCMD(pcdev->dma_chans[i]);
425
426 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
427 /* The DMA engine is on the last
428 descriptor, set the next descriptors
429 address to the descriptors we just
430 initialized */
431 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
432 } else {
433 buf_dma->sg_cpu[nents].ddadr =
434 DDADR(pcdev->dma_chans[i]);
435 }
436
437 /* The next descriptor is the dummy descriptor */
438 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
439 sizeof(struct pxa_dma_desc);
440
441 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
442 }
443 }
444
445 spin_unlock_irqrestore(&pcdev->lock, flags);
446 }
447
448 static void pxa_videobuf_release(struct videobuf_queue *vq,
449 struct videobuf_buffer *vb)
450 {
451 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
452 #ifdef DEBUG
453 struct soc_camera_device *icd = vq->priv_data;
454
455 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
456 vb, vb->baddr, vb->bsize);
457
458 switch (vb->state) {
459 case VIDEOBUF_ACTIVE:
460 dev_dbg(&icd->dev, "%s (active)\n", __func__);
461 break;
462 case VIDEOBUF_QUEUED:
463 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
464 break;
465 case VIDEOBUF_PREPARED:
466 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
467 break;
468 default:
469 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
470 break;
471 }
472 #endif
473
474 free_buffer(vq, buf);
475 }
476
477 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
478 struct videobuf_buffer *vb,
479 struct pxa_buffer *buf)
480 {
481 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
482 list_del_init(&vb->queue);
483 vb->state = VIDEOBUF_DONE;
484 do_gettimeofday(&vb->ts);
485 vb->field_count++;
486 wake_up(&vb->done);
487
488 if (list_empty(&pcdev->capture)) {
489 pcdev->active = NULL;
490 DCSR(pcdev->dma_chans[0]) = 0;
491 DCSR(pcdev->dma_chans[1]) = 0;
492 DCSR(pcdev->dma_chans[2]) = 0;
493 CICR0 &= ~CICR0_ENB;
494 return;
495 }
496
497 pcdev->active = list_entry(pcdev->capture.next,
498 struct pxa_buffer, vb.queue);
499 }
500
501 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
502 enum pxa_camera_active_dma act_dma)
503 {
504 struct pxa_buffer *buf;
505 unsigned long flags;
506 u32 status, camera_status, overrun;
507 struct videobuf_buffer *vb;
508
509 spin_lock_irqsave(&pcdev->lock, flags);
510
511 status = DCSR(channel);
512 DCSR(channel) = status | DCSR_ENDINTR;
513
514 if (status & DCSR_BUSERR) {
515 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
516 goto out;
517 }
518
519 if (!(status & DCSR_ENDINTR)) {
520 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
521 "status: 0x%08x\n", status);
522 goto out;
523 }
524
525 if (!pcdev->active) {
526 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
527 goto out;
528 }
529
530 camera_status = CISR;
531 overrun = CISR_IFO_0;
532 if (pcdev->channels == 3)
533 overrun |= CISR_IFO_1 | CISR_IFO_2;
534 if (camera_status & overrun) {
535 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
536 /* Stop the Capture Interface */
537 CICR0 &= ~CICR0_ENB;
538 /* Stop DMA */
539 DCSR(channel) = 0;
540 /* Reset the FIFOs */
541 CIFR |= CIFR_RESET_F;
542 /* Enable End-Of-Frame Interrupt */
543 CICR0 &= ~CICR0_EOFM;
544 /* Restart the Capture Interface */
545 CICR0 |= CICR0_ENB;
546 goto out;
547 }
548
549 vb = &pcdev->active->vb;
550 buf = container_of(vb, struct pxa_buffer, vb);
551 WARN_ON(buf->inwork || list_empty(&vb->queue));
552 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
553 vb, vb->baddr, vb->bsize);
554
555 buf->active_dma &= ~act_dma;
556 if (!buf->active_dma)
557 pxa_camera_wakeup(pcdev, vb, buf);
558
559 out:
560 spin_unlock_irqrestore(&pcdev->lock, flags);
561 }
562
563 static void pxa_camera_dma_irq_y(int channel, void *data)
564 {
565 struct pxa_camera_dev *pcdev = data;
566 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
567 }
568
569 static void pxa_camera_dma_irq_u(int channel, void *data)
570 {
571 struct pxa_camera_dev *pcdev = data;
572 pxa_camera_dma_irq(channel, pcdev, DMA_U);
573 }
574
575 static void pxa_camera_dma_irq_v(int channel, void *data)
576 {
577 struct pxa_camera_dev *pcdev = data;
578 pxa_camera_dma_irq(channel, pcdev, DMA_V);
579 }
580
581 static struct videobuf_queue_ops pxa_videobuf_ops = {
582 .buf_setup = pxa_videobuf_setup,
583 .buf_prepare = pxa_videobuf_prepare,
584 .buf_queue = pxa_videobuf_queue,
585 .buf_release = pxa_videobuf_release,
586 };
587
588 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
589 struct soc_camera_device *icd)
590 {
591 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
592 struct pxa_camera_dev *pcdev = ici->priv;
593
594 /* We must pass NULL as dev pointer, then all pci_* dma operations
595 * transform to normal dma_* ones. */
596 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
597 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
598 sizeof(struct pxa_buffer), icd);
599 }
600
601 static int mclk_get_divisor(struct pxa_camera_dev *pcdev)
602 {
603 unsigned int mclk_10khz = pcdev->platform_mclk_10khz;
604 unsigned long div;
605 unsigned long lcdclk;
606
607 lcdclk = clk_get_rate(pcdev->clk) / 10000;
608
609 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here
610 * they get a nice Oops */
611 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1;
612
613 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, "
614 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div);
615
616 return div;
617 }
618
619 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
620 {
621 struct pxacamera_platform_data *pdata = pcdev->pdata;
622 u32 cicr4 = 0;
623
624 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
625 pcdev, pdata);
626
627 if (pdata && pdata->init) {
628 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
629 pdata->init(pcdev->dev);
630 }
631
632 if (pdata && pdata->power) {
633 dev_dbg(pcdev->dev, "%s: Power on camera\n", __func__);
634 pdata->power(pcdev->dev, 1);
635 }
636
637 if (pdata && pdata->reset) {
638 dev_dbg(pcdev->dev, "%s: Releasing camera reset\n",
639 __func__);
640 pdata->reset(pcdev->dev, 1);
641 }
642
643 CICR0 = 0x3FF; /* disable all interrupts */
644
645 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
646 cicr4 |= CICR4_PCLK_EN;
647 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
648 cicr4 |= CICR4_MCLK_EN;
649 if (pcdev->platform_flags & PXA_CAMERA_PCP)
650 cicr4 |= CICR4_PCP;
651 if (pcdev->platform_flags & PXA_CAMERA_HSP)
652 cicr4 |= CICR4_HSP;
653 if (pcdev->platform_flags & PXA_CAMERA_VSP)
654 cicr4 |= CICR4_VSP;
655
656 CICR4 = mclk_get_divisor(pcdev) | cicr4;
657
658 clk_enable(pcdev->clk);
659 }
660
661 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
662 {
663 struct pxacamera_platform_data *board = pcdev->pdata;
664
665 clk_disable(pcdev->clk);
666
667 if (board && board->reset) {
668 dev_dbg(pcdev->dev, "%s: Asserting camera reset\n",
669 __func__);
670 board->reset(pcdev->dev, 0);
671 }
672
673 if (board && board->power) {
674 dev_dbg(pcdev->dev, "%s: Power off camera\n", __func__);
675 board->power(pcdev->dev, 0);
676 }
677 }
678
679 static irqreturn_t pxa_camera_irq(int irq, void *data)
680 {
681 struct pxa_camera_dev *pcdev = data;
682 unsigned int status = CISR;
683
684 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status);
685
686 if (!status)
687 return IRQ_NONE;
688
689 CISR = status;
690
691 if (status & CISR_EOF) {
692 int i;
693 for (i = 0; i < pcdev->channels; i++) {
694 DDADR(pcdev->dma_chans[i]) =
695 pcdev->active->dmas[i].sg_dma;
696 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
697 }
698 CICR0 |= CICR0_EOFM;
699 }
700
701 return IRQ_HANDLED;
702 }
703
704 /* The following two functions absolutely depend on the fact, that
705 * there can be only one camera on PXA quick capture interface */
706 static int pxa_camera_add_device(struct soc_camera_device *icd)
707 {
708 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
709 struct pxa_camera_dev *pcdev = ici->priv;
710 int ret;
711
712 mutex_lock(&camera_lock);
713
714 if (pcdev->icd) {
715 ret = -EBUSY;
716 goto ebusy;
717 }
718
719 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
720 icd->devnum);
721
722 pxa_camera_activate(pcdev);
723 ret = icd->ops->init(icd);
724
725 if (!ret)
726 pcdev->icd = icd;
727
728 ebusy:
729 mutex_unlock(&camera_lock);
730
731 return ret;
732 }
733
734 static void pxa_camera_remove_device(struct soc_camera_device *icd)
735 {
736 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
737 struct pxa_camera_dev *pcdev = ici->priv;
738
739 BUG_ON(icd != pcdev->icd);
740
741 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
742 icd->devnum);
743
744 /* disable capture, disable interrupts */
745 CICR0 = 0x3ff;
746
747 /* Stop DMA engine */
748 DCSR(pcdev->dma_chans[0]) = 0;
749 DCSR(pcdev->dma_chans[1]) = 0;
750 DCSR(pcdev->dma_chans[2]) = 0;
751
752 icd->ops->release(icd);
753
754 pxa_camera_deactivate(pcdev);
755
756 pcdev->icd = NULL;
757 }
758
759 static int test_platform_param(struct pxa_camera_dev *pcdev,
760 unsigned char buswidth, unsigned long *flags)
761 {
762 /*
763 * Platform specified synchronization and pixel clock polarities are
764 * only a recommendation and are only used during probing. The PXA270
765 * quick capture interface supports both.
766 */
767 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
768 SOCAM_MASTER : SOCAM_SLAVE) |
769 SOCAM_HSYNC_ACTIVE_HIGH |
770 SOCAM_HSYNC_ACTIVE_LOW |
771 SOCAM_VSYNC_ACTIVE_HIGH |
772 SOCAM_VSYNC_ACTIVE_LOW |
773 SOCAM_PCLK_SAMPLE_RISING |
774 SOCAM_PCLK_SAMPLE_FALLING;
775
776 /* If requested data width is supported by the platform, use it */
777 switch (buswidth) {
778 case 10:
779 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
780 return -EINVAL;
781 *flags |= SOCAM_DATAWIDTH_10;
782 break;
783 case 9:
784 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
785 return -EINVAL;
786 *flags |= SOCAM_DATAWIDTH_9;
787 break;
788 case 8:
789 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
790 return -EINVAL;
791 *flags |= SOCAM_DATAWIDTH_8;
792 }
793
794 return 0;
795 }
796
797 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
798 {
799 struct soc_camera_host *ici =
800 to_soc_camera_host(icd->dev.parent);
801 struct pxa_camera_dev *pcdev = ici->priv;
802 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
803 u32 cicr0, cicr1, cicr4 = 0;
804 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
805
806 if (ret < 0)
807 return ret;
808
809 camera_flags = icd->ops->query_bus_param(icd);
810
811 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
812 if (!common_flags)
813 return -EINVAL;
814
815 pcdev->channels = 1;
816
817 /* Make choises, based on platform preferences */
818 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
819 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
820 if (pcdev->platform_flags & PXA_CAMERA_HSP)
821 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
822 else
823 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
824 }
825
826 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
827 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
828 if (pcdev->platform_flags & PXA_CAMERA_VSP)
829 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
830 else
831 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
832 }
833
834 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
835 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
836 if (pcdev->platform_flags & PXA_CAMERA_PCP)
837 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
838 else
839 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
840 }
841
842 ret = icd->ops->set_bus_param(icd, common_flags);
843 if (ret < 0)
844 return ret;
845
846 /* Datawidth is now guaranteed to be equal to one of the three values.
847 * We fix bit-per-pixel equal to data-width... */
848 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
849 case SOCAM_DATAWIDTH_10:
850 icd->buswidth = 10;
851 dw = 4;
852 bpp = 0x40;
853 break;
854 case SOCAM_DATAWIDTH_9:
855 icd->buswidth = 9;
856 dw = 3;
857 bpp = 0x20;
858 break;
859 default:
860 /* Actually it can only be 8 now,
861 * default is just to silence compiler warnings */
862 case SOCAM_DATAWIDTH_8:
863 icd->buswidth = 8;
864 dw = 2;
865 bpp = 0;
866 }
867
868 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
869 cicr4 |= CICR4_PCLK_EN;
870 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
871 cicr4 |= CICR4_MCLK_EN;
872 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
873 cicr4 |= CICR4_PCP;
874 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
875 cicr4 |= CICR4_HSP;
876 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
877 cicr4 |= CICR4_VSP;
878
879 cicr0 = CICR0;
880 if (cicr0 & CICR0_ENB)
881 CICR0 = cicr0 & ~CICR0_ENB;
882
883 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
884
885 switch (pixfmt) {
886 case V4L2_PIX_FMT_YUV422P:
887 pcdev->channels = 3;
888 cicr1 |= CICR1_YCBCR_F;
889 case V4L2_PIX_FMT_YUYV:
890 cicr1 |= CICR1_COLOR_SP_VAL(2);
891 break;
892 case V4L2_PIX_FMT_RGB555:
893 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
894 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
895 break;
896 case V4L2_PIX_FMT_RGB565:
897 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
898 break;
899 }
900
901 CICR1 = cicr1;
902 CICR2 = 0;
903 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
904 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
905 CICR4 = mclk_get_divisor(pcdev) | cicr4;
906
907 /* CIF interrupts are not used, only DMA */
908 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
909 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) |
910 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB);
911
912 return 0;
913 }
914
915 static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
916 {
917 struct soc_camera_host *ici =
918 to_soc_camera_host(icd->dev.parent);
919 struct pxa_camera_dev *pcdev = ici->priv;
920 unsigned long bus_flags, camera_flags;
921 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
922
923 if (ret < 0)
924 return ret;
925
926 camera_flags = icd->ops->query_bus_param(icd);
927
928 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
929 }
930
931 static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd,
932 __u32 pixfmt, struct v4l2_rect *rect)
933 {
934 return icd->ops->set_fmt_cap(icd, pixfmt, rect);
935 }
936
937 static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd,
938 struct v4l2_format *f)
939 {
940 /* limit to pxa hardware capabilities */
941 if (f->fmt.pix.height < 32)
942 f->fmt.pix.height = 32;
943 if (f->fmt.pix.height > 2048)
944 f->fmt.pix.height = 2048;
945 if (f->fmt.pix.width < 48)
946 f->fmt.pix.width = 48;
947 if (f->fmt.pix.width > 2048)
948 f->fmt.pix.width = 2048;
949 f->fmt.pix.width &= ~0x01;
950
951 /* limit to sensor capabilities */
952 return icd->ops->try_fmt_cap(icd, f);
953 }
954
955 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
956 struct v4l2_requestbuffers *p)
957 {
958 int i;
959
960 /* This is for locking debugging only. I removed spinlocks and now I
961 * check whether .prepare is ever called on a linked buffer, or whether
962 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
963 * it hadn't triggered */
964 for (i = 0; i < p->count; i++) {
965 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
966 struct pxa_buffer, vb);
967 buf->inwork = 0;
968 INIT_LIST_HEAD(&buf->vb.queue);
969 }
970
971 return 0;
972 }
973
974 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
975 {
976 struct soc_camera_file *icf = file->private_data;
977 struct pxa_buffer *buf;
978
979 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
980 vb.stream);
981
982 poll_wait(file, &buf->vb.done, pt);
983
984 if (buf->vb.state == VIDEOBUF_DONE ||
985 buf->vb.state == VIDEOBUF_ERROR)
986 return POLLIN|POLLRDNORM;
987
988 return 0;
989 }
990
991 static int pxa_camera_querycap(struct soc_camera_host *ici,
992 struct v4l2_capability *cap)
993 {
994 /* cap->name is set by the firendly caller:-> */
995 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
996 cap->version = PXA_CAM_VERSION_CODE;
997 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
998
999 return 0;
1000 }
1001
1002 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1003 {
1004 struct soc_camera_host *ici =
1005 to_soc_camera_host(icd->dev.parent);
1006 struct pxa_camera_dev *pcdev = ici->priv;
1007 int i = 0, ret = 0;
1008
1009 pcdev->save_cicr[i++] = CICR0;
1010 pcdev->save_cicr[i++] = CICR1;
1011 pcdev->save_cicr[i++] = CICR2;
1012 pcdev->save_cicr[i++] = CICR3;
1013 pcdev->save_cicr[i++] = CICR4;
1014
1015 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1016 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1017
1018 return ret;
1019 }
1020
1021 static int pxa_camera_resume(struct soc_camera_device *icd)
1022 {
1023 struct soc_camera_host *ici =
1024 to_soc_camera_host(icd->dev.parent);
1025 struct pxa_camera_dev *pcdev = ici->priv;
1026 int i = 0, ret = 0;
1027
1028 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1029 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1030 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1031
1032 CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB;
1033 CICR1 = pcdev->save_cicr[i++];
1034 CICR2 = pcdev->save_cicr[i++];
1035 CICR3 = pcdev->save_cicr[i++];
1036 CICR4 = pcdev->save_cicr[i++];
1037
1038 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1039 ret = pcdev->icd->ops->resume(pcdev->icd);
1040
1041 /* Restart frame capture if active buffer exists */
1042 if (!ret && pcdev->active) {
1043 /* Reset the FIFOs */
1044 CIFR |= CIFR_RESET_F;
1045 /* Enable End-Of-Frame Interrupt */
1046 CICR0 &= ~CICR0_EOFM;
1047 /* Restart the Capture Interface */
1048 CICR0 |= CICR0_ENB;
1049 }
1050
1051 return ret;
1052 }
1053
1054 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1055 .owner = THIS_MODULE,
1056 .add = pxa_camera_add_device,
1057 .remove = pxa_camera_remove_device,
1058 .suspend = pxa_camera_suspend,
1059 .resume = pxa_camera_resume,
1060 .set_fmt_cap = pxa_camera_set_fmt_cap,
1061 .try_fmt_cap = pxa_camera_try_fmt_cap,
1062 .init_videobuf = pxa_camera_init_videobuf,
1063 .reqbufs = pxa_camera_reqbufs,
1064 .poll = pxa_camera_poll,
1065 .querycap = pxa_camera_querycap,
1066 .try_bus_param = pxa_camera_try_bus_param,
1067 .set_bus_param = pxa_camera_set_bus_param,
1068 };
1069
1070 /* Should be allocated dynamically too, but we have only one. */
1071 static struct soc_camera_host pxa_soc_camera_host = {
1072 .drv_name = PXA_CAM_DRV_NAME,
1073 .ops = &pxa_soc_camera_host_ops,
1074 };
1075
1076 static int pxa_camera_probe(struct platform_device *pdev)
1077 {
1078 struct pxa_camera_dev *pcdev;
1079 struct resource *res;
1080 void __iomem *base;
1081 int irq;
1082 int err = 0;
1083
1084 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085 irq = platform_get_irq(pdev, 0);
1086 if (!res || irq < 0) {
1087 err = -ENODEV;
1088 goto exit;
1089 }
1090
1091 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1092 if (!pcdev) {
1093 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1094 err = -ENOMEM;
1095 goto exit;
1096 }
1097
1098 pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
1099 if (IS_ERR(pcdev->clk)) {
1100 err = PTR_ERR(pcdev->clk);
1101 goto exit_kfree;
1102 }
1103
1104 dev_set_drvdata(&pdev->dev, pcdev);
1105 pcdev->res = res;
1106
1107 pcdev->pdata = pdev->dev.platform_data;
1108 pcdev->platform_flags = pcdev->pdata->flags;
1109 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1110 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1111 /* Platform hasn't set available data widths. This is bad.
1112 * Warn and use a default. */
1113 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1114 "data widths, using default 10 bit\n");
1115 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1116 }
1117 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz;
1118 if (!pcdev->platform_mclk_10khz) {
1119 dev_warn(&pdev->dev,
1120 "mclk_10khz == 0! Please, fix your platform data. "
1121 "Using default 20MHz\n");
1122 pcdev->platform_mclk_10khz = 2000;
1123 }
1124
1125 INIT_LIST_HEAD(&pcdev->capture);
1126 spin_lock_init(&pcdev->lock);
1127
1128 /*
1129 * Request the regions.
1130 */
1131 if (!request_mem_region(res->start, res->end - res->start + 1,
1132 PXA_CAM_DRV_NAME)) {
1133 err = -EBUSY;
1134 goto exit_clk;
1135 }
1136
1137 base = ioremap(res->start, res->end - res->start + 1);
1138 if (!base) {
1139 err = -ENOMEM;
1140 goto exit_release;
1141 }
1142 pcdev->irq = irq;
1143 pcdev->base = base;
1144 pcdev->dev = &pdev->dev;
1145
1146 /* request dma */
1147 pcdev->dma_chans[0] = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1148 pxa_camera_dma_irq_y, pcdev);
1149 if (pcdev->dma_chans[0] < 0) {
1150 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1151 err = -ENOMEM;
1152 goto exit_iounmap;
1153 }
1154 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1155
1156 pcdev->dma_chans[1] = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1157 pxa_camera_dma_irq_u, pcdev);
1158 if (pcdev->dma_chans[1] < 0) {
1159 dev_err(pcdev->dev, "Can't request DMA for U\n");
1160 err = -ENOMEM;
1161 goto exit_free_dma_y;
1162 }
1163 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1164
1165 pcdev->dma_chans[2] = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1166 pxa_camera_dma_irq_v, pcdev);
1167 if (pcdev->dma_chans[0] < 0) {
1168 dev_err(pcdev->dev, "Can't request DMA for V\n");
1169 err = -ENOMEM;
1170 goto exit_free_dma_u;
1171 }
1172 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1173
1174 DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1175 DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1176 DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1177
1178 /* request irq */
1179 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1180 pcdev);
1181 if (err) {
1182 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1183 goto exit_free_dma;
1184 }
1185
1186 pxa_soc_camera_host.priv = pcdev;
1187 pxa_soc_camera_host.dev.parent = &pdev->dev;
1188 pxa_soc_camera_host.nr = pdev->id;
1189 err = soc_camera_host_register(&pxa_soc_camera_host);
1190 if (err)
1191 goto exit_free_irq;
1192
1193 return 0;
1194
1195 exit_free_irq:
1196 free_irq(pcdev->irq, pcdev);
1197 exit_free_dma:
1198 pxa_free_dma(pcdev->dma_chans[2]);
1199 exit_free_dma_u:
1200 pxa_free_dma(pcdev->dma_chans[1]);
1201 exit_free_dma_y:
1202 pxa_free_dma(pcdev->dma_chans[0]);
1203 exit_iounmap:
1204 iounmap(base);
1205 exit_release:
1206 release_mem_region(res->start, res->end - res->start + 1);
1207 exit_clk:
1208 clk_put(pcdev->clk);
1209 exit_kfree:
1210 kfree(pcdev);
1211 exit:
1212 return err;
1213 }
1214
1215 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1216 {
1217 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1218 struct resource *res;
1219
1220 clk_put(pcdev->clk);
1221
1222 pxa_free_dma(pcdev->dma_chans[0]);
1223 pxa_free_dma(pcdev->dma_chans[1]);
1224 pxa_free_dma(pcdev->dma_chans[2]);
1225 free_irq(pcdev->irq, pcdev);
1226
1227 soc_camera_host_unregister(&pxa_soc_camera_host);
1228
1229 iounmap(pcdev->base);
1230
1231 res = pcdev->res;
1232 release_mem_region(res->start, res->end - res->start + 1);
1233
1234 kfree(pcdev);
1235
1236 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1237
1238 return 0;
1239 }
1240
1241 static struct platform_driver pxa_camera_driver = {
1242 .driver = {
1243 .name = PXA_CAM_DRV_NAME,
1244 },
1245 .probe = pxa_camera_probe,
1246 .remove = __exit_p(pxa_camera_remove),
1247 };
1248
1249
1250 static int __devinit pxa_camera_init(void)
1251 {
1252 return platform_driver_register(&pxa_camera_driver);
1253 }
1254
1255 static void __exit pxa_camera_exit(void)
1256 {
1257 platform_driver_unregister(&pxa_camera_driver);
1258 }
1259
1260 module_init(pxa_camera_init);
1261 module_exit(pxa_camera_exit);
1262
1263 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1264 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1265 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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