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[media] s5p-fimc: Simplify locking by removing the context data structure spinlock
[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-core.c
1 /*
2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
3 *
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29
30 #include "fimc-core.h"
31 #include "fimc-mdevice.h"
32
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
34 "sclk_fimc", "fimc"
35 };
36
37 static struct fimc_fmt fimc_formats[] = {
38 {
39 .name = "RGB565",
40 .fourcc = V4L2_PIX_FMT_RGB565,
41 .depth = { 16 },
42 .color = S5P_FIMC_RGB565,
43 .memplanes = 1,
44 .colplanes = 1,
45 .flags = FMT_FLAGS_M2M,
46 }, {
47 .name = "BGR666",
48 .fourcc = V4L2_PIX_FMT_BGR666,
49 .depth = { 32 },
50 .color = S5P_FIMC_RGB666,
51 .memplanes = 1,
52 .colplanes = 1,
53 .flags = FMT_FLAGS_M2M,
54 }, {
55 .name = "ARGB8888, 32 bpp",
56 .fourcc = V4L2_PIX_FMT_RGB32,
57 .depth = { 32 },
58 .color = S5P_FIMC_RGB888,
59 .memplanes = 1,
60 .colplanes = 1,
61 .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
62 }, {
63 .name = "ARGB1555",
64 .fourcc = V4L2_PIX_FMT_RGB555,
65 .depth = { 16 },
66 .color = S5P_FIMC_RGB555,
67 .memplanes = 1,
68 .colplanes = 1,
69 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
70 }, {
71 .name = "ARGB4444",
72 .fourcc = V4L2_PIX_FMT_RGB444,
73 .depth = { 16 },
74 .color = S5P_FIMC_RGB444,
75 .memplanes = 1,
76 .colplanes = 1,
77 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
78 }, {
79 .name = "YUV 4:2:2 packed, YCbYCr",
80 .fourcc = V4L2_PIX_FMT_YUYV,
81 .depth = { 16 },
82 .color = S5P_FIMC_YCBYCR422,
83 .memplanes = 1,
84 .colplanes = 1,
85 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
86 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
87 }, {
88 .name = "YUV 4:2:2 packed, CbYCrY",
89 .fourcc = V4L2_PIX_FMT_UYVY,
90 .depth = { 16 },
91 .color = S5P_FIMC_CBYCRY422,
92 .memplanes = 1,
93 .colplanes = 1,
94 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
95 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
96 }, {
97 .name = "YUV 4:2:2 packed, CrYCbY",
98 .fourcc = V4L2_PIX_FMT_VYUY,
99 .depth = { 16 },
100 .color = S5P_FIMC_CRYCBY422,
101 .memplanes = 1,
102 .colplanes = 1,
103 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
104 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
105 }, {
106 .name = "YUV 4:2:2 packed, YCrYCb",
107 .fourcc = V4L2_PIX_FMT_YVYU,
108 .depth = { 16 },
109 .color = S5P_FIMC_YCRYCB422,
110 .memplanes = 1,
111 .colplanes = 1,
112 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
113 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
114 }, {
115 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
116 .fourcc = V4L2_PIX_FMT_YUV422P,
117 .depth = { 12 },
118 .color = S5P_FIMC_YCBYCR422,
119 .memplanes = 1,
120 .colplanes = 3,
121 .flags = FMT_FLAGS_M2M,
122 }, {
123 .name = "YUV 4:2:2 planar, Y/CbCr",
124 .fourcc = V4L2_PIX_FMT_NV16,
125 .depth = { 16 },
126 .color = S5P_FIMC_YCBYCR422,
127 .memplanes = 1,
128 .colplanes = 2,
129 .flags = FMT_FLAGS_M2M,
130 }, {
131 .name = "YUV 4:2:2 planar, Y/CrCb",
132 .fourcc = V4L2_PIX_FMT_NV61,
133 .depth = { 16 },
134 .color = S5P_FIMC_YCRYCB422,
135 .memplanes = 1,
136 .colplanes = 2,
137 .flags = FMT_FLAGS_M2M,
138 }, {
139 .name = "YUV 4:2:0 planar, YCbCr",
140 .fourcc = V4L2_PIX_FMT_YUV420,
141 .depth = { 12 },
142 .color = S5P_FIMC_YCBCR420,
143 .memplanes = 1,
144 .colplanes = 3,
145 .flags = FMT_FLAGS_M2M,
146 }, {
147 .name = "YUV 4:2:0 planar, Y/CbCr",
148 .fourcc = V4L2_PIX_FMT_NV12,
149 .depth = { 12 },
150 .color = S5P_FIMC_YCBCR420,
151 .memplanes = 1,
152 .colplanes = 2,
153 .flags = FMT_FLAGS_M2M,
154 }, {
155 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
156 .fourcc = V4L2_PIX_FMT_NV12M,
157 .color = S5P_FIMC_YCBCR420,
158 .depth = { 8, 4 },
159 .memplanes = 2,
160 .colplanes = 2,
161 .flags = FMT_FLAGS_M2M,
162 }, {
163 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
164 .fourcc = V4L2_PIX_FMT_YUV420M,
165 .color = S5P_FIMC_YCBCR420,
166 .depth = { 8, 2, 2 },
167 .memplanes = 3,
168 .colplanes = 3,
169 .flags = FMT_FLAGS_M2M,
170 }, {
171 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
172 .fourcc = V4L2_PIX_FMT_NV12MT,
173 .color = S5P_FIMC_YCBCR420,
174 .depth = { 8, 4 },
175 .memplanes = 2,
176 .colplanes = 2,
177 .flags = FMT_FLAGS_M2M,
178 }, {
179 .name = "JPEG encoded data",
180 .fourcc = V4L2_PIX_FMT_JPEG,
181 .color = S5P_FIMC_JPEG,
182 .depth = { 8 },
183 .memplanes = 1,
184 .colplanes = 1,
185 .mbus_code = V4L2_MBUS_FMT_JPEG_1X8,
186 .flags = FMT_FLAGS_CAM,
187 },
188 };
189
190 static unsigned int get_m2m_fmt_flags(unsigned int stream_type)
191 {
192 if (stream_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
193 return FMT_FLAGS_M2M_IN;
194 else
195 return FMT_FLAGS_M2M_OUT;
196 }
197
198 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
199 int dw, int dh, int rotation)
200 {
201 if (rotation == 90 || rotation == 270)
202 swap(dw, dh);
203
204 if (!ctx->scaler.enabled)
205 return (sw == dw && sh == dh) ? 0 : -EINVAL;
206
207 if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
208 return -EINVAL;
209
210 return 0;
211 }
212
213 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
214 {
215 u32 sh = 6;
216
217 if (src >= 64 * tar)
218 return -EINVAL;
219
220 while (sh--) {
221 u32 tmp = 1 << sh;
222 if (src >= tar * tmp) {
223 *shift = sh, *ratio = tmp;
224 return 0;
225 }
226 }
227 *shift = 0, *ratio = 1;
228 return 0;
229 }
230
231 int fimc_set_scaler_info(struct fimc_ctx *ctx)
232 {
233 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
234 struct device *dev = &ctx->fimc_dev->pdev->dev;
235 struct fimc_scaler *sc = &ctx->scaler;
236 struct fimc_frame *s_frame = &ctx->s_frame;
237 struct fimc_frame *d_frame = &ctx->d_frame;
238 int tx, ty, sx, sy;
239 int ret;
240
241 if (ctx->rotation == 90 || ctx->rotation == 270) {
242 ty = d_frame->width;
243 tx = d_frame->height;
244 } else {
245 tx = d_frame->width;
246 ty = d_frame->height;
247 }
248 if (tx <= 0 || ty <= 0) {
249 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
250 return -EINVAL;
251 }
252
253 sx = s_frame->width;
254 sy = s_frame->height;
255 if (sx <= 0 || sy <= 0) {
256 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
257 return -EINVAL;
258 }
259 sc->real_width = sx;
260 sc->real_height = sy;
261
262 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
263 if (ret)
264 return ret;
265
266 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
267 if (ret)
268 return ret;
269
270 sc->pre_dst_width = sx / sc->pre_hratio;
271 sc->pre_dst_height = sy / sc->pre_vratio;
272
273 if (variant->has_mainscaler_ext) {
274 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
275 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
276 } else {
277 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
278 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
279
280 }
281
282 sc->scaleup_h = (tx >= sx) ? 1 : 0;
283 sc->scaleup_v = (ty >= sy) ? 1 : 0;
284
285 /* check to see if input and output size/format differ */
286 if (s_frame->fmt->color == d_frame->fmt->color
287 && s_frame->width == d_frame->width
288 && s_frame->height == d_frame->height)
289 sc->copy_mode = 1;
290 else
291 sc->copy_mode = 0;
292
293 return 0;
294 }
295
296 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
297 {
298 struct vb2_buffer *src_vb, *dst_vb;
299
300 if (!ctx || !ctx->m2m_ctx)
301 return;
302
303 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
304 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
305
306 if (src_vb && dst_vb) {
307 v4l2_m2m_buf_done(src_vb, vb_state);
308 v4l2_m2m_buf_done(dst_vb, vb_state);
309 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
310 ctx->m2m_ctx);
311 }
312 }
313
314 /* Complete the transaction which has been scheduled for execution. */
315 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
316 {
317 struct fimc_dev *fimc = ctx->fimc_dev;
318 int ret;
319
320 if (!fimc_m2m_pending(fimc))
321 return 0;
322
323 fimc_ctx_state_set(FIMC_CTX_SHUT, ctx);
324
325 ret = wait_event_timeout(fimc->irq_queue,
326 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
327 FIMC_SHUTDOWN_TIMEOUT);
328
329 return ret == 0 ? -ETIMEDOUT : ret;
330 }
331
332 static int start_streaming(struct vb2_queue *q, unsigned int count)
333 {
334 struct fimc_ctx *ctx = q->drv_priv;
335 int ret;
336
337 ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
338 return ret > 0 ? 0 : ret;
339 }
340
341 static int stop_streaming(struct vb2_queue *q)
342 {
343 struct fimc_ctx *ctx = q->drv_priv;
344 int ret;
345
346 ret = fimc_m2m_shutdown(ctx);
347 if (ret == -ETIMEDOUT)
348 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
349
350 pm_runtime_put(&ctx->fimc_dev->pdev->dev);
351 return 0;
352 }
353
354 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
355 {
356 struct fimc_vid_cap *cap = &fimc->vid_cap;
357 struct fimc_vid_buffer *v_buf;
358 struct timeval *tv;
359 struct timespec ts;
360
361 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
362 wake_up(&fimc->irq_queue);
363 return;
364 }
365
366 if (!list_empty(&cap->active_buf_q) &&
367 test_bit(ST_CAPT_RUN, &fimc->state) && final) {
368 ktime_get_real_ts(&ts);
369
370 v_buf = fimc_active_queue_pop(cap);
371
372 tv = &v_buf->vb.v4l2_buf.timestamp;
373 tv->tv_sec = ts.tv_sec;
374 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
375 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
376
377 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
378 }
379
380 if (!list_empty(&cap->pending_buf_q)) {
381
382 v_buf = fimc_pending_queue_pop(cap);
383 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
384 v_buf->index = cap->buf_index;
385
386 /* Move the buffer to the capture active queue */
387 fimc_active_queue_add(cap, v_buf);
388
389 dbg("next frame: %d, done frame: %d",
390 fimc_hw_get_frame_index(fimc), v_buf->index);
391
392 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
393 cap->buf_index = 0;
394 }
395
396 if (cap->active_buf_cnt == 0) {
397 if (final)
398 clear_bit(ST_CAPT_RUN, &fimc->state);
399
400 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
401 cap->buf_index = 0;
402 } else {
403 set_bit(ST_CAPT_RUN, &fimc->state);
404 }
405
406 fimc_capture_config_update(cap->ctx);
407
408 dbg("frame: %d, active_buf_cnt: %d",
409 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
410 }
411
412 static irqreturn_t fimc_irq_handler(int irq, void *priv)
413 {
414 struct fimc_dev *fimc = priv;
415 struct fimc_vid_cap *cap = &fimc->vid_cap;
416 struct fimc_ctx *ctx;
417
418 fimc_hw_clear_irq(fimc);
419
420 spin_lock(&fimc->slock);
421
422 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
423 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
424 set_bit(ST_M2M_SUSPENDED, &fimc->state);
425 wake_up(&fimc->irq_queue);
426 goto out;
427 }
428 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
429 if (ctx != NULL) {
430 spin_unlock(&fimc->slock);
431 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
432
433 if (ctx->state & FIMC_CTX_SHUT) {
434 ctx->state &= ~FIMC_CTX_SHUT;
435 wake_up(&fimc->irq_queue);
436 }
437 return IRQ_HANDLED;
438 }
439 } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
440 fimc_capture_irq_handler(fimc,
441 !test_bit(ST_CAPT_JPEG, &fimc->state));
442 if (cap->active_buf_cnt == 1) {
443 fimc_deactivate_capture(fimc);
444 clear_bit(ST_CAPT_STREAM, &fimc->state);
445 }
446 }
447 out:
448 spin_unlock(&fimc->slock);
449 return IRQ_HANDLED;
450 }
451
452 /* The color format (colplanes, memplanes) must be already configured. */
453 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
454 struct fimc_frame *frame, struct fimc_addr *paddr)
455 {
456 int ret = 0;
457 u32 pix_size;
458
459 if (vb == NULL || frame == NULL)
460 return -EINVAL;
461
462 pix_size = frame->width * frame->height;
463
464 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
465 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
466
467 paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
468
469 if (frame->fmt->memplanes == 1) {
470 switch (frame->fmt->colplanes) {
471 case 1:
472 paddr->cb = 0;
473 paddr->cr = 0;
474 break;
475 case 2:
476 /* decompose Y into Y/Cb */
477 paddr->cb = (u32)(paddr->y + pix_size);
478 paddr->cr = 0;
479 break;
480 case 3:
481 paddr->cb = (u32)(paddr->y + pix_size);
482 /* decompose Y into Y/Cb/Cr */
483 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
484 paddr->cr = (u32)(paddr->cb
485 + (pix_size >> 2));
486 else /* 422 */
487 paddr->cr = (u32)(paddr->cb
488 + (pix_size >> 1));
489 break;
490 default:
491 return -EINVAL;
492 }
493 } else {
494 if (frame->fmt->memplanes >= 2)
495 paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
496
497 if (frame->fmt->memplanes == 3)
498 paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
499 }
500
501 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
502 paddr->y, paddr->cb, paddr->cr, ret);
503
504 return ret;
505 }
506
507 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
508 void fimc_set_yuv_order(struct fimc_ctx *ctx)
509 {
510 /* The one only mode supported in SoC. */
511 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
512 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
513
514 /* Set order for 1 plane input formats. */
515 switch (ctx->s_frame.fmt->color) {
516 case S5P_FIMC_YCRYCB422:
517 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
518 break;
519 case S5P_FIMC_CBYCRY422:
520 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
521 break;
522 case S5P_FIMC_CRYCBY422:
523 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
524 break;
525 case S5P_FIMC_YCBYCR422:
526 default:
527 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
528 break;
529 }
530 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
531
532 switch (ctx->d_frame.fmt->color) {
533 case S5P_FIMC_YCRYCB422:
534 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
535 break;
536 case S5P_FIMC_CBYCRY422:
537 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
538 break;
539 case S5P_FIMC_CRYCBY422:
540 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
541 break;
542 case S5P_FIMC_YCBYCR422:
543 default:
544 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
545 break;
546 }
547 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
548 }
549
550 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
551 {
552 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
553 u32 i, depth = 0;
554
555 for (i = 0; i < f->fmt->colplanes; i++)
556 depth += f->fmt->depth[i];
557
558 f->dma_offset.y_h = f->offs_h;
559 if (!variant->pix_hoff)
560 f->dma_offset.y_h *= (depth >> 3);
561
562 f->dma_offset.y_v = f->offs_v;
563
564 f->dma_offset.cb_h = f->offs_h;
565 f->dma_offset.cb_v = f->offs_v;
566
567 f->dma_offset.cr_h = f->offs_h;
568 f->dma_offset.cr_v = f->offs_v;
569
570 if (!variant->pix_hoff) {
571 if (f->fmt->colplanes == 3) {
572 f->dma_offset.cb_h >>= 1;
573 f->dma_offset.cr_h >>= 1;
574 }
575 if (f->fmt->color == S5P_FIMC_YCBCR420) {
576 f->dma_offset.cb_v >>= 1;
577 f->dma_offset.cr_v >>= 1;
578 }
579 }
580
581 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
582 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
583 }
584
585 /**
586 * fimc_prepare_config - check dimensions, operation and color mode
587 * and pre-calculate offset and the scaling coefficients.
588 *
589 * @ctx: hardware context information
590 * @flags: flags indicating which parameters to check/update
591 *
592 * Return: 0 if dimensions are valid or non zero otherwise.
593 */
594 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
595 {
596 struct fimc_frame *s_frame, *d_frame;
597 struct vb2_buffer *vb = NULL;
598 int ret = 0;
599
600 s_frame = &ctx->s_frame;
601 d_frame = &ctx->d_frame;
602
603 if (flags & FIMC_PARAMS) {
604 /* Prepare the DMA offset ratios for scaler. */
605 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
606 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
607
608 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
609 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
610 err("out of scaler range");
611 return -EINVAL;
612 }
613 fimc_set_yuv_order(ctx);
614 }
615
616 if (flags & FIMC_SRC_ADDR) {
617 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
618 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
619 if (ret)
620 return ret;
621 }
622
623 if (flags & FIMC_DST_ADDR) {
624 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
625 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
626 }
627
628 return ret;
629 }
630
631 static void fimc_dma_run(void *priv)
632 {
633 struct fimc_ctx *ctx = priv;
634 struct fimc_dev *fimc;
635 unsigned long flags;
636 u32 ret;
637
638 if (WARN(!ctx, "null hardware context\n"))
639 return;
640
641 fimc = ctx->fimc_dev;
642 spin_lock_irqsave(&fimc->slock, flags);
643 set_bit(ST_M2M_PEND, &fimc->state);
644
645 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
646 ret = fimc_prepare_config(ctx, ctx->state);
647 if (ret)
648 goto dma_unlock;
649
650 /* Reconfigure hardware if the context has changed. */
651 if (fimc->m2m.ctx != ctx) {
652 ctx->state |= FIMC_PARAMS;
653 fimc->m2m.ctx = ctx;
654 }
655 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
656
657 if (ctx->state & FIMC_PARAMS) {
658 fimc_hw_set_input_path(ctx);
659 fimc_hw_set_in_dma(ctx);
660 ret = fimc_set_scaler_info(ctx);
661 if (ret)
662 goto dma_unlock;
663 fimc_hw_set_prescaler(ctx);
664 fimc_hw_set_mainscaler(ctx);
665 fimc_hw_set_target_format(ctx);
666 fimc_hw_set_rotation(ctx);
667 fimc_hw_set_effect(ctx, false);
668 }
669
670 fimc_hw_set_output_path(ctx);
671 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
672 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
673
674 if (ctx->state & FIMC_PARAMS) {
675 fimc_hw_set_out_dma(ctx);
676 if (fimc->variant->has_alpha)
677 fimc_hw_set_rgb_alpha(ctx);
678 }
679
680 fimc_activate_capture(ctx);
681
682 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
683 FIMC_SRC_FMT | FIMC_DST_FMT);
684 fimc_hw_activate_input_dma(fimc, true);
685 dma_unlock:
686 spin_unlock_irqrestore(&fimc->slock, flags);
687 }
688
689 static void fimc_job_abort(void *priv)
690 {
691 fimc_m2m_shutdown(priv);
692 }
693
694 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
695 unsigned int *num_buffers, unsigned int *num_planes,
696 unsigned int sizes[], void *allocators[])
697 {
698 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
699 struct fimc_frame *f;
700 int i;
701
702 f = ctx_get_frame(ctx, vq->type);
703 if (IS_ERR(f))
704 return PTR_ERR(f);
705 /*
706 * Return number of non-contigous planes (plane buffers)
707 * depending on the configured color format.
708 */
709 if (!f->fmt)
710 return -EINVAL;
711
712 *num_planes = f->fmt->memplanes;
713 for (i = 0; i < f->fmt->memplanes; i++) {
714 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
715 allocators[i] = ctx->fimc_dev->alloc_ctx;
716 }
717 return 0;
718 }
719
720 static int fimc_buf_prepare(struct vb2_buffer *vb)
721 {
722 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
723 struct fimc_frame *frame;
724 int i;
725
726 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
727 if (IS_ERR(frame))
728 return PTR_ERR(frame);
729
730 for (i = 0; i < frame->fmt->memplanes; i++)
731 vb2_set_plane_payload(vb, i, frame->payload[i]);
732
733 return 0;
734 }
735
736 static void fimc_buf_queue(struct vb2_buffer *vb)
737 {
738 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
739
740 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
741
742 if (ctx->m2m_ctx)
743 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
744 }
745
746 static void fimc_lock(struct vb2_queue *vq)
747 {
748 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
749 mutex_lock(&ctx->fimc_dev->lock);
750 }
751
752 static void fimc_unlock(struct vb2_queue *vq)
753 {
754 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
755 mutex_unlock(&ctx->fimc_dev->lock);
756 }
757
758 static struct vb2_ops fimc_qops = {
759 .queue_setup = fimc_queue_setup,
760 .buf_prepare = fimc_buf_prepare,
761 .buf_queue = fimc_buf_queue,
762 .wait_prepare = fimc_unlock,
763 .wait_finish = fimc_lock,
764 .stop_streaming = stop_streaming,
765 .start_streaming = start_streaming,
766 };
767
768 /*
769 * V4L2 controls handling
770 */
771 #define ctrl_to_ctx(__ctrl) \
772 container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
773
774 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
775 {
776 struct fimc_dev *fimc = ctx->fimc_dev;
777 struct samsung_fimc_variant *variant = fimc->variant;
778 unsigned int flags = FIMC_DST_FMT | FIMC_SRC_FMT;
779 int ret = 0;
780
781 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
782 return 0;
783
784 switch (ctrl->id) {
785 case V4L2_CID_HFLIP:
786 ctx->hflip = ctrl->val;
787 break;
788
789 case V4L2_CID_VFLIP:
790 ctx->vflip = ctrl->val;
791 break;
792
793 case V4L2_CID_ROTATE:
794 if (fimc_capture_pending(fimc) ||
795 (ctx->state & flags) == flags) {
796 ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
797 ctx->s_frame.height, ctx->d_frame.width,
798 ctx->d_frame.height, ctrl->val);
799 if (ret)
800 return -EINVAL;
801 }
802 if ((ctrl->val == 90 || ctrl->val == 270) &&
803 !variant->has_out_rot)
804 return -EINVAL;
805
806 ctx->rotation = ctrl->val;
807 break;
808
809 case V4L2_CID_ALPHA_COMPONENT:
810 ctx->d_frame.alpha = ctrl->val;
811 break;
812 }
813 ctx->state |= FIMC_PARAMS;
814 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
815 return 0;
816 }
817
818 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
819 {
820 struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
821 unsigned long flags;
822 int ret;
823
824 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
825 ret = __fimc_s_ctrl(ctx, ctrl);
826 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
827
828 return ret;
829 }
830
831 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
832 .s_ctrl = fimc_s_ctrl,
833 };
834
835 int fimc_ctrls_create(struct fimc_ctx *ctx)
836 {
837 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
838 unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
839
840 if (ctx->ctrls_rdy)
841 return 0;
842 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
843
844 ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
845 V4L2_CID_ROTATE, 0, 270, 90, 0);
846 ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
847 V4L2_CID_HFLIP, 0, 1, 1, 0);
848 ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
849 V4L2_CID_VFLIP, 0, 1, 1, 0);
850 if (variant->has_alpha)
851 ctx->ctrl_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
852 &fimc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
853 0, max_alpha, 1, 0);
854 else
855 ctx->ctrl_alpha = NULL;
856
857 ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
858
859 return ctx->ctrl_handler.error;
860 }
861
862 void fimc_ctrls_delete(struct fimc_ctx *ctx)
863 {
864 if (ctx->ctrls_rdy) {
865 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
866 ctx->ctrls_rdy = false;
867 ctx->ctrl_alpha = NULL;
868 }
869 }
870
871 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
872 {
873 unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
874
875 if (!ctx->ctrls_rdy)
876 return;
877
878 mutex_lock(&ctx->ctrl_handler.lock);
879 v4l2_ctrl_activate(ctx->ctrl_rotate, active);
880 v4l2_ctrl_activate(ctx->ctrl_hflip, active);
881 v4l2_ctrl_activate(ctx->ctrl_vflip, active);
882 if (ctx->ctrl_alpha)
883 v4l2_ctrl_activate(ctx->ctrl_alpha, active && has_alpha);
884
885 if (active) {
886 ctx->rotation = ctx->ctrl_rotate->val;
887 ctx->hflip = ctx->ctrl_hflip->val;
888 ctx->vflip = ctx->ctrl_vflip->val;
889 } else {
890 ctx->rotation = 0;
891 ctx->hflip = 0;
892 ctx->vflip = 0;
893 }
894 mutex_unlock(&ctx->ctrl_handler.lock);
895 }
896
897 /* Update maximum value of the alpha color control */
898 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
899 {
900 struct fimc_dev *fimc = ctx->fimc_dev;
901 struct v4l2_ctrl *ctrl = ctx->ctrl_alpha;
902
903 if (ctrl == NULL || !fimc->variant->has_alpha)
904 return;
905
906 v4l2_ctrl_lock(ctrl);
907 ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
908
909 if (ctrl->cur.val > ctrl->maximum)
910 ctrl->cur.val = ctrl->maximum;
911
912 v4l2_ctrl_unlock(ctrl);
913 }
914
915 /*
916 * V4L2 ioctl handlers
917 */
918 static int fimc_m2m_querycap(struct file *file, void *fh,
919 struct v4l2_capability *cap)
920 {
921 struct fimc_ctx *ctx = fh_to_ctx(fh);
922 struct fimc_dev *fimc = ctx->fimc_dev;
923
924 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
925 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
926 cap->bus_info[0] = 0;
927 cap->capabilities = V4L2_CAP_STREAMING |
928 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
929
930 return 0;
931 }
932
933 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
934 struct v4l2_fmtdesc *f)
935 {
936 struct fimc_fmt *fmt;
937
938 fmt = fimc_find_format(NULL, NULL, get_m2m_fmt_flags(f->type),
939 f->index);
940 if (!fmt)
941 return -EINVAL;
942
943 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
944 f->pixelformat = fmt->fourcc;
945 return 0;
946 }
947
948 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
949 {
950 struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
951 int i;
952
953 pixm->width = frame->o_width;
954 pixm->height = frame->o_height;
955 pixm->field = V4L2_FIELD_NONE;
956 pixm->pixelformat = frame->fmt->fourcc;
957 pixm->colorspace = V4L2_COLORSPACE_JPEG;
958 pixm->num_planes = frame->fmt->memplanes;
959
960 for (i = 0; i < pixm->num_planes; ++i) {
961 int bpl = frame->f_width;
962 if (frame->fmt->colplanes == 1) /* packed formats */
963 bpl = (bpl * frame->fmt->depth[0]) / 8;
964 pixm->plane_fmt[i].bytesperline = bpl;
965 pixm->plane_fmt[i].sizeimage = (frame->o_width *
966 frame->o_height * frame->fmt->depth[i]) / 8;
967 }
968 return 0;
969 }
970
971 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
972 {
973 struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
974
975 frame->f_width = pixm->plane_fmt[0].bytesperline;
976 if (frame->fmt->colplanes == 1)
977 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
978 frame->f_height = pixm->height;
979 frame->width = pixm->width;
980 frame->height = pixm->height;
981 frame->o_width = pixm->width;
982 frame->o_height = pixm->height;
983 frame->offs_h = 0;
984 frame->offs_v = 0;
985 }
986
987 /**
988 * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
989 * @fmt: fimc pixel format description (input)
990 * @width: requested pixel width
991 * @height: requested pixel height
992 * @pix: multi-plane format to adjust
993 */
994 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
995 struct v4l2_pix_format_mplane *pix)
996 {
997 u32 bytesperline = 0;
998 int i;
999
1000 pix->colorspace = V4L2_COLORSPACE_JPEG;
1001 pix->field = V4L2_FIELD_NONE;
1002 pix->num_planes = fmt->memplanes;
1003 pix->pixelformat = fmt->fourcc;
1004 pix->height = height;
1005 pix->width = width;
1006
1007 for (i = 0; i < pix->num_planes; ++i) {
1008 u32 bpl = pix->plane_fmt[i].bytesperline;
1009 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
1010
1011 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
1012 bpl = pix->width; /* Planar */
1013
1014 if (fmt->colplanes == 1 && /* Packed */
1015 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
1016 bpl = (pix->width * fmt->depth[0]) / 8;
1017
1018 if (i == 0) /* Same bytesperline for each plane. */
1019 bytesperline = bpl;
1020
1021 pix->plane_fmt[i].bytesperline = bytesperline;
1022 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
1023 }
1024 }
1025
1026 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
1027 struct v4l2_format *f)
1028 {
1029 struct fimc_ctx *ctx = fh_to_ctx(fh);
1030 struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
1031
1032 if (IS_ERR(frame))
1033 return PTR_ERR(frame);
1034
1035 return fimc_fill_format(frame, f);
1036 }
1037
1038 /**
1039 * fimc_find_format - lookup fimc color format by fourcc or media bus format
1040 * @pixelformat: fourcc to match, ignored if null
1041 * @mbus_code: media bus code to match, ignored if null
1042 * @mask: the color flags to match
1043 * @index: offset in the fimc_formats array, ignored if negative
1044 */
1045 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
1046 unsigned int mask, int index)
1047 {
1048 struct fimc_fmt *fmt, *def_fmt = NULL;
1049 unsigned int i;
1050 int id = 0;
1051
1052 if (index >= ARRAY_SIZE(fimc_formats))
1053 return NULL;
1054
1055 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
1056 fmt = &fimc_formats[i];
1057 if (!(fmt->flags & mask))
1058 continue;
1059 if (pixelformat && fmt->fourcc == *pixelformat)
1060 return fmt;
1061 if (mbus_code && fmt->mbus_code == *mbus_code)
1062 return fmt;
1063 if (index == id)
1064 def_fmt = fmt;
1065 id++;
1066 }
1067 return def_fmt;
1068 }
1069
1070 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1071 {
1072 struct fimc_dev *fimc = ctx->fimc_dev;
1073 struct samsung_fimc_variant *variant = fimc->variant;
1074 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1075 struct fimc_fmt *fmt;
1076 u32 max_w, mod_x, mod_y;
1077
1078 if (!IS_M2M(f->type))
1079 return -EINVAL;
1080
1081 dbg("w: %d, h: %d", pix->width, pix->height);
1082
1083 fmt = fimc_find_format(&pix->pixelformat, NULL,
1084 get_m2m_fmt_flags(f->type), 0);
1085 if (WARN(fmt == NULL, "Pixel format lookup failed"))
1086 return -EINVAL;
1087
1088 if (pix->field == V4L2_FIELD_ANY)
1089 pix->field = V4L2_FIELD_NONE;
1090 else if (pix->field != V4L2_FIELD_NONE)
1091 return -EINVAL;
1092
1093 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1094 max_w = variant->pix_limit->scaler_dis_w;
1095 mod_x = ffs(variant->min_inp_pixsize) - 1;
1096 } else {
1097 max_w = variant->pix_limit->out_rot_dis_w;
1098 mod_x = ffs(variant->min_out_pixsize) - 1;
1099 }
1100
1101 if (tiled_fmt(fmt)) {
1102 mod_x = 6; /* 64 x 32 pixels tile */
1103 mod_y = 5;
1104 } else {
1105 if (variant->min_vsize_align == 1)
1106 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1107 else
1108 mod_y = ffs(variant->min_vsize_align) - 1;
1109 }
1110
1111 v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1112 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1113
1114 fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1115 return 0;
1116 }
1117
1118 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1119 struct v4l2_format *f)
1120 {
1121 struct fimc_ctx *ctx = fh_to_ctx(fh);
1122
1123 return fimc_try_fmt_mplane(ctx, f);
1124 }
1125
1126 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1127 struct v4l2_format *f)
1128 {
1129 struct fimc_ctx *ctx = fh_to_ctx(fh);
1130 struct fimc_dev *fimc = ctx->fimc_dev;
1131 struct vb2_queue *vq;
1132 struct fimc_frame *frame;
1133 struct v4l2_pix_format_mplane *pix;
1134 int i, ret = 0;
1135
1136 ret = fimc_try_fmt_mplane(ctx, f);
1137 if (ret)
1138 return ret;
1139
1140 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1141
1142 if (vb2_is_busy(vq)) {
1143 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1144 return -EBUSY;
1145 }
1146
1147 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1148 frame = &ctx->s_frame;
1149 else
1150 frame = &ctx->d_frame;
1151
1152 pix = &f->fmt.pix_mp;
1153 frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1154 get_m2m_fmt_flags(f->type), 0);
1155 if (!frame->fmt)
1156 return -EINVAL;
1157
1158 /* Update RGB Alpha control state and value range */
1159 fimc_alpha_ctrl_update(ctx);
1160
1161 for (i = 0; i < frame->fmt->colplanes; i++) {
1162 frame->payload[i] =
1163 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1164 }
1165
1166 fimc_fill_frame(frame, f);
1167
1168 ctx->scaler.enabled = 1;
1169
1170 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1171 fimc_ctx_state_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1172 else
1173 fimc_ctx_state_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1174
1175 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1176
1177 return 0;
1178 }
1179
1180 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1181 struct v4l2_requestbuffers *reqbufs)
1182 {
1183 struct fimc_ctx *ctx = fh_to_ctx(fh);
1184
1185 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1186 }
1187
1188 static int fimc_m2m_querybuf(struct file *file, void *fh,
1189 struct v4l2_buffer *buf)
1190 {
1191 struct fimc_ctx *ctx = fh_to_ctx(fh);
1192
1193 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1194 }
1195
1196 static int fimc_m2m_qbuf(struct file *file, void *fh,
1197 struct v4l2_buffer *buf)
1198 {
1199 struct fimc_ctx *ctx = fh_to_ctx(fh);
1200
1201 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1202 }
1203
1204 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1205 struct v4l2_buffer *buf)
1206 {
1207 struct fimc_ctx *ctx = fh_to_ctx(fh);
1208
1209 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1210 }
1211
1212 static int fimc_m2m_streamon(struct file *file, void *fh,
1213 enum v4l2_buf_type type)
1214 {
1215 struct fimc_ctx *ctx = fh_to_ctx(fh);
1216
1217 /* The source and target color format need to be set */
1218 if (V4L2_TYPE_IS_OUTPUT(type)) {
1219 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1220 return -EINVAL;
1221 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1222 return -EINVAL;
1223 }
1224
1225 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1226 }
1227
1228 static int fimc_m2m_streamoff(struct file *file, void *fh,
1229 enum v4l2_buf_type type)
1230 {
1231 struct fimc_ctx *ctx = fh_to_ctx(fh);
1232
1233 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1234 }
1235
1236 static int fimc_m2m_cropcap(struct file *file, void *fh,
1237 struct v4l2_cropcap *cr)
1238 {
1239 struct fimc_ctx *ctx = fh_to_ctx(fh);
1240 struct fimc_frame *frame;
1241
1242 frame = ctx_get_frame(ctx, cr->type);
1243 if (IS_ERR(frame))
1244 return PTR_ERR(frame);
1245
1246 cr->bounds.left = 0;
1247 cr->bounds.top = 0;
1248 cr->bounds.width = frame->o_width;
1249 cr->bounds.height = frame->o_height;
1250 cr->defrect = cr->bounds;
1251
1252 return 0;
1253 }
1254
1255 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1256 {
1257 struct fimc_ctx *ctx = fh_to_ctx(fh);
1258 struct fimc_frame *frame;
1259
1260 frame = ctx_get_frame(ctx, cr->type);
1261 if (IS_ERR(frame))
1262 return PTR_ERR(frame);
1263
1264 cr->c.left = frame->offs_h;
1265 cr->c.top = frame->offs_v;
1266 cr->c.width = frame->width;
1267 cr->c.height = frame->height;
1268
1269 return 0;
1270 }
1271
1272 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1273 {
1274 struct fimc_dev *fimc = ctx->fimc_dev;
1275 struct fimc_frame *f;
1276 u32 min_size, halign, depth = 0;
1277 int i;
1278
1279 if (cr->c.top < 0 || cr->c.left < 0) {
1280 v4l2_err(fimc->m2m.vfd,
1281 "doesn't support negative values for top & left\n");
1282 return -EINVAL;
1283 }
1284 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1285 f = &ctx->d_frame;
1286 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1287 f = &ctx->s_frame;
1288 else
1289 return -EINVAL;
1290
1291 min_size = (f == &ctx->s_frame) ?
1292 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1293
1294 /* Get pixel alignment constraints. */
1295 if (fimc->variant->min_vsize_align == 1)
1296 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1297 else
1298 halign = ffs(fimc->variant->min_vsize_align) - 1;
1299
1300 for (i = 0; i < f->fmt->colplanes; i++)
1301 depth += f->fmt->depth[i];
1302
1303 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1304 ffs(min_size) - 1,
1305 &cr->c.height, min_size, f->o_height,
1306 halign, 64/(ALIGN(depth, 8)));
1307
1308 /* adjust left/top if cropping rectangle is out of bounds */
1309 if (cr->c.left + cr->c.width > f->o_width)
1310 cr->c.left = f->o_width - cr->c.width;
1311 if (cr->c.top + cr->c.height > f->o_height)
1312 cr->c.top = f->o_height - cr->c.height;
1313
1314 cr->c.left = round_down(cr->c.left, min_size);
1315 cr->c.top = round_down(cr->c.top, fimc->variant->hor_offs_align);
1316
1317 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1318 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1319 f->f_width, f->f_height);
1320
1321 return 0;
1322 }
1323
1324 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1325 {
1326 struct fimc_ctx *ctx = fh_to_ctx(fh);
1327 struct fimc_dev *fimc = ctx->fimc_dev;
1328 struct fimc_frame *f;
1329 int ret;
1330
1331 ret = fimc_m2m_try_crop(ctx, cr);
1332 if (ret)
1333 return ret;
1334
1335 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1336 &ctx->s_frame : &ctx->d_frame;
1337
1338 /* Check to see if scaling ratio is within supported range */
1339 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1340 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1341 ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1342 cr->c.height, ctx->d_frame.width,
1343 ctx->d_frame.height, ctx->rotation);
1344 } else {
1345 ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1346 ctx->s_frame.height, cr->c.width,
1347 cr->c.height, ctx->rotation);
1348 }
1349 if (ret) {
1350 v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1351 return -EINVAL;
1352 }
1353 }
1354
1355 f->offs_h = cr->c.left;
1356 f->offs_v = cr->c.top;
1357 f->width = cr->c.width;
1358 f->height = cr->c.height;
1359
1360 fimc_ctx_state_set(FIMC_PARAMS, ctx);
1361
1362 return 0;
1363 }
1364
1365 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1366 .vidioc_querycap = fimc_m2m_querycap,
1367
1368 .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1369 .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1370
1371 .vidioc_g_fmt_vid_cap_mplane = fimc_m2m_g_fmt_mplane,
1372 .vidioc_g_fmt_vid_out_mplane = fimc_m2m_g_fmt_mplane,
1373
1374 .vidioc_try_fmt_vid_cap_mplane = fimc_m2m_try_fmt_mplane,
1375 .vidioc_try_fmt_vid_out_mplane = fimc_m2m_try_fmt_mplane,
1376
1377 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1378 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1379
1380 .vidioc_reqbufs = fimc_m2m_reqbufs,
1381 .vidioc_querybuf = fimc_m2m_querybuf,
1382
1383 .vidioc_qbuf = fimc_m2m_qbuf,
1384 .vidioc_dqbuf = fimc_m2m_dqbuf,
1385
1386 .vidioc_streamon = fimc_m2m_streamon,
1387 .vidioc_streamoff = fimc_m2m_streamoff,
1388
1389 .vidioc_g_crop = fimc_m2m_g_crop,
1390 .vidioc_s_crop = fimc_m2m_s_crop,
1391 .vidioc_cropcap = fimc_m2m_cropcap
1392
1393 };
1394
1395 static int queue_init(void *priv, struct vb2_queue *src_vq,
1396 struct vb2_queue *dst_vq)
1397 {
1398 struct fimc_ctx *ctx = priv;
1399 int ret;
1400
1401 memset(src_vq, 0, sizeof(*src_vq));
1402 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1403 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1404 src_vq->drv_priv = ctx;
1405 src_vq->ops = &fimc_qops;
1406 src_vq->mem_ops = &vb2_dma_contig_memops;
1407 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1408
1409 ret = vb2_queue_init(src_vq);
1410 if (ret)
1411 return ret;
1412
1413 memset(dst_vq, 0, sizeof(*dst_vq));
1414 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1415 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1416 dst_vq->drv_priv = ctx;
1417 dst_vq->ops = &fimc_qops;
1418 dst_vq->mem_ops = &vb2_dma_contig_memops;
1419 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1420
1421 return vb2_queue_init(dst_vq);
1422 }
1423
1424 static int fimc_m2m_open(struct file *file)
1425 {
1426 struct fimc_dev *fimc = video_drvdata(file);
1427 struct fimc_ctx *ctx;
1428 int ret;
1429
1430 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1431 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1432
1433 /*
1434 * Return if the corresponding video capture node
1435 * is already opened.
1436 */
1437 if (fimc->vid_cap.refcnt > 0)
1438 return -EBUSY;
1439
1440 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1441 if (!ctx)
1442 return -ENOMEM;
1443 v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1444 ctx->fimc_dev = fimc;
1445
1446 /* Default color format */
1447 ctx->s_frame.fmt = &fimc_formats[0];
1448 ctx->d_frame.fmt = &fimc_formats[0];
1449
1450 ret = fimc_ctrls_create(ctx);
1451 if (ret)
1452 goto error_fh;
1453
1454 /* Use separate control handler per file handle */
1455 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1456 file->private_data = &ctx->fh;
1457 v4l2_fh_add(&ctx->fh);
1458
1459 /* Setup the device context for memory-to-memory mode */
1460 ctx->state = FIMC_CTX_M2M;
1461 ctx->flags = 0;
1462 ctx->in_path = FIMC_DMA;
1463 ctx->out_path = FIMC_DMA;
1464
1465 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1466 if (IS_ERR(ctx->m2m_ctx)) {
1467 ret = PTR_ERR(ctx->m2m_ctx);
1468 goto error_c;
1469 }
1470
1471 if (fimc->m2m.refcnt++ == 0)
1472 set_bit(ST_M2M_RUN, &fimc->state);
1473 return 0;
1474
1475 error_c:
1476 fimc_ctrls_delete(ctx);
1477 error_fh:
1478 v4l2_fh_del(&ctx->fh);
1479 v4l2_fh_exit(&ctx->fh);
1480 kfree(ctx);
1481 return ret;
1482 }
1483
1484 static int fimc_m2m_release(struct file *file)
1485 {
1486 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1487 struct fimc_dev *fimc = ctx->fimc_dev;
1488
1489 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1490 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1491
1492 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1493 fimc_ctrls_delete(ctx);
1494 v4l2_fh_del(&ctx->fh);
1495 v4l2_fh_exit(&ctx->fh);
1496
1497 if (--fimc->m2m.refcnt <= 0)
1498 clear_bit(ST_M2M_RUN, &fimc->state);
1499 kfree(ctx);
1500 return 0;
1501 }
1502
1503 static unsigned int fimc_m2m_poll(struct file *file,
1504 struct poll_table_struct *wait)
1505 {
1506 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1507
1508 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1509 }
1510
1511
1512 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1513 {
1514 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1515
1516 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1517 }
1518
1519 static const struct v4l2_file_operations fimc_m2m_fops = {
1520 .owner = THIS_MODULE,
1521 .open = fimc_m2m_open,
1522 .release = fimc_m2m_release,
1523 .poll = fimc_m2m_poll,
1524 .unlocked_ioctl = video_ioctl2,
1525 .mmap = fimc_m2m_mmap,
1526 };
1527
1528 static struct v4l2_m2m_ops m2m_ops = {
1529 .device_run = fimc_dma_run,
1530 .job_abort = fimc_job_abort,
1531 };
1532
1533 int fimc_register_m2m_device(struct fimc_dev *fimc,
1534 struct v4l2_device *v4l2_dev)
1535 {
1536 struct video_device *vfd;
1537 struct platform_device *pdev;
1538 int ret = 0;
1539
1540 if (!fimc)
1541 return -ENODEV;
1542
1543 pdev = fimc->pdev;
1544 fimc->v4l2_dev = v4l2_dev;
1545
1546 vfd = video_device_alloc();
1547 if (!vfd) {
1548 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1549 return -ENOMEM;
1550 }
1551
1552 vfd->fops = &fimc_m2m_fops;
1553 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1554 vfd->v4l2_dev = v4l2_dev;
1555 vfd->minor = -1;
1556 vfd->release = video_device_release;
1557 vfd->lock = &fimc->lock;
1558
1559 snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1560 video_set_drvdata(vfd, fimc);
1561
1562 fimc->m2m.vfd = vfd;
1563 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1564 if (IS_ERR(fimc->m2m.m2m_dev)) {
1565 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1566 ret = PTR_ERR(fimc->m2m.m2m_dev);
1567 goto err_init;
1568 }
1569
1570 ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1571 if (!ret)
1572 return 0;
1573
1574 v4l2_m2m_release(fimc->m2m.m2m_dev);
1575 err_init:
1576 video_device_release(fimc->m2m.vfd);
1577 return ret;
1578 }
1579
1580 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1581 {
1582 if (!fimc)
1583 return;
1584
1585 if (fimc->m2m.m2m_dev)
1586 v4l2_m2m_release(fimc->m2m.m2m_dev);
1587 if (fimc->m2m.vfd) {
1588 media_entity_cleanup(&fimc->m2m.vfd->entity);
1589 /* Can also be called if video device wasn't registered */
1590 video_unregister_device(fimc->m2m.vfd);
1591 }
1592 }
1593
1594 static void fimc_clk_put(struct fimc_dev *fimc)
1595 {
1596 int i;
1597 for (i = 0; i < fimc->num_clocks; i++) {
1598 if (IS_ERR_OR_NULL(fimc->clock[i]))
1599 continue;
1600 clk_unprepare(fimc->clock[i]);
1601 clk_put(fimc->clock[i]);
1602 fimc->clock[i] = NULL;
1603 }
1604 }
1605
1606 static int fimc_clk_get(struct fimc_dev *fimc)
1607 {
1608 int i, ret;
1609
1610 for (i = 0; i < fimc->num_clocks; i++) {
1611 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1612 if (IS_ERR(fimc->clock[i]))
1613 goto err;
1614 ret = clk_prepare(fimc->clock[i]);
1615 if (ret < 0) {
1616 clk_put(fimc->clock[i]);
1617 fimc->clock[i] = NULL;
1618 goto err;
1619 }
1620 }
1621 return 0;
1622 err:
1623 fimc_clk_put(fimc);
1624 dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
1625 fimc_clocks[i]);
1626 return -ENXIO;
1627 }
1628
1629 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1630 {
1631 unsigned long flags;
1632 int timeout;
1633
1634 spin_lock_irqsave(&fimc->slock, flags);
1635 if (!fimc_m2m_pending(fimc)) {
1636 spin_unlock_irqrestore(&fimc->slock, flags);
1637 return 0;
1638 }
1639 clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1640 set_bit(ST_M2M_SUSPENDING, &fimc->state);
1641 spin_unlock_irqrestore(&fimc->slock, flags);
1642
1643 timeout = wait_event_timeout(fimc->irq_queue,
1644 test_bit(ST_M2M_SUSPENDED, &fimc->state),
1645 FIMC_SHUTDOWN_TIMEOUT);
1646
1647 clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1648 return timeout == 0 ? -EAGAIN : 0;
1649 }
1650
1651 static int fimc_m2m_resume(struct fimc_dev *fimc)
1652 {
1653 unsigned long flags;
1654
1655 spin_lock_irqsave(&fimc->slock, flags);
1656 /* Clear for full H/W setup in first run after resume */
1657 fimc->m2m.ctx = NULL;
1658 spin_unlock_irqrestore(&fimc->slock, flags);
1659
1660 if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1661 fimc_m2m_job_finish(fimc->m2m.ctx,
1662 VB2_BUF_STATE_ERROR);
1663 return 0;
1664 }
1665
1666 static int fimc_probe(struct platform_device *pdev)
1667 {
1668 struct fimc_dev *fimc;
1669 struct resource *res;
1670 struct samsung_fimc_driverdata *drv_data;
1671 struct s5p_platform_fimc *pdata;
1672 int ret = 0;
1673
1674 drv_data = (struct samsung_fimc_driverdata *)
1675 platform_get_device_id(pdev)->driver_data;
1676
1677 if (pdev->id >= drv_data->num_entities) {
1678 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1679 pdev->id);
1680 return -EINVAL;
1681 }
1682
1683 fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
1684 if (!fimc)
1685 return -ENOMEM;
1686
1687 fimc->id = pdev->id;
1688
1689 fimc->variant = drv_data->variant[fimc->id];
1690 fimc->pdev = pdev;
1691 pdata = pdev->dev.platform_data;
1692 fimc->pdata = pdata;
1693
1694 init_waitqueue_head(&fimc->irq_queue);
1695 spin_lock_init(&fimc->slock);
1696 mutex_init(&fimc->lock);
1697
1698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1699 fimc->regs = devm_request_and_ioremap(&pdev->dev, res);
1700 if (fimc->regs == NULL) {
1701 dev_err(&pdev->dev, "Failed to obtain io memory\n");
1702 return -ENOENT;
1703 }
1704
1705 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1706 if (res == NULL) {
1707 dev_err(&pdev->dev, "Failed to get IRQ resource\n");
1708 return -ENXIO;
1709 }
1710 fimc->irq = res->start;
1711
1712 fimc->num_clocks = MAX_FIMC_CLOCKS;
1713 ret = fimc_clk_get(fimc);
1714 if (ret)
1715 return ret;
1716 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1717 clk_enable(fimc->clock[CLK_BUS]);
1718
1719 platform_set_drvdata(pdev, fimc);
1720
1721 ret = devm_request_irq(&pdev->dev, fimc->irq, fimc_irq_handler,
1722 0, pdev->name, fimc);
1723 if (ret) {
1724 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1725 goto err_clk;
1726 }
1727
1728 pm_runtime_enable(&pdev->dev);
1729 ret = pm_runtime_get_sync(&pdev->dev);
1730 if (ret < 0)
1731 goto err_clk;
1732 /* Initialize contiguous memory allocator */
1733 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1734 if (IS_ERR(fimc->alloc_ctx)) {
1735 ret = PTR_ERR(fimc->alloc_ctx);
1736 goto err_pm;
1737 }
1738
1739 dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1740
1741 pm_runtime_put(&pdev->dev);
1742 return 0;
1743
1744 err_pm:
1745 pm_runtime_put(&pdev->dev);
1746 err_clk:
1747 fimc_clk_put(fimc);
1748 return ret;
1749 }
1750
1751 static int fimc_runtime_resume(struct device *dev)
1752 {
1753 struct fimc_dev *fimc = dev_get_drvdata(dev);
1754
1755 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1756
1757 /* Enable clocks and perform basic initalization */
1758 clk_enable(fimc->clock[CLK_GATE]);
1759 fimc_hw_reset(fimc);
1760
1761 /* Resume the capture or mem-to-mem device */
1762 if (fimc_capture_busy(fimc))
1763 return fimc_capture_resume(fimc);
1764
1765 return fimc_m2m_resume(fimc);
1766 }
1767
1768 static int fimc_runtime_suspend(struct device *dev)
1769 {
1770 struct fimc_dev *fimc = dev_get_drvdata(dev);
1771 int ret = 0;
1772
1773 if (fimc_capture_busy(fimc))
1774 ret = fimc_capture_suspend(fimc);
1775 else
1776 ret = fimc_m2m_suspend(fimc);
1777 if (!ret)
1778 clk_disable(fimc->clock[CLK_GATE]);
1779
1780 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1781 return ret;
1782 }
1783
1784 #ifdef CONFIG_PM_SLEEP
1785 static int fimc_resume(struct device *dev)
1786 {
1787 struct fimc_dev *fimc = dev_get_drvdata(dev);
1788 unsigned long flags;
1789
1790 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1791
1792 /* Do not resume if the device was idle before system suspend */
1793 spin_lock_irqsave(&fimc->slock, flags);
1794 if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1795 (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1796 spin_unlock_irqrestore(&fimc->slock, flags);
1797 return 0;
1798 }
1799 fimc_hw_reset(fimc);
1800 spin_unlock_irqrestore(&fimc->slock, flags);
1801
1802 if (fimc_capture_busy(fimc))
1803 return fimc_capture_resume(fimc);
1804
1805 return fimc_m2m_resume(fimc);
1806 }
1807
1808 static int fimc_suspend(struct device *dev)
1809 {
1810 struct fimc_dev *fimc = dev_get_drvdata(dev);
1811
1812 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1813
1814 if (test_and_set_bit(ST_LPM, &fimc->state))
1815 return 0;
1816 if (fimc_capture_busy(fimc))
1817 return fimc_capture_suspend(fimc);
1818
1819 return fimc_m2m_suspend(fimc);
1820 }
1821 #endif /* CONFIG_PM_SLEEP */
1822
1823 static int __devexit fimc_remove(struct platform_device *pdev)
1824 {
1825 struct fimc_dev *fimc = platform_get_drvdata(pdev);
1826
1827 pm_runtime_disable(&pdev->dev);
1828 pm_runtime_set_suspended(&pdev->dev);
1829
1830 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1831
1832 clk_disable(fimc->clock[CLK_BUS]);
1833 fimc_clk_put(fimc);
1834
1835 dev_info(&pdev->dev, "driver unloaded\n");
1836 return 0;
1837 }
1838
1839 /* Image pixel limits, similar across several FIMC HW revisions. */
1840 static struct fimc_pix_limit s5p_pix_limit[4] = {
1841 [0] = {
1842 .scaler_en_w = 3264,
1843 .scaler_dis_w = 8192,
1844 .in_rot_en_h = 1920,
1845 .in_rot_dis_w = 8192,
1846 .out_rot_en_w = 1920,
1847 .out_rot_dis_w = 4224,
1848 },
1849 [1] = {
1850 .scaler_en_w = 4224,
1851 .scaler_dis_w = 8192,
1852 .in_rot_en_h = 1920,
1853 .in_rot_dis_w = 8192,
1854 .out_rot_en_w = 1920,
1855 .out_rot_dis_w = 4224,
1856 },
1857 [2] = {
1858 .scaler_en_w = 1920,
1859 .scaler_dis_w = 8192,
1860 .in_rot_en_h = 1280,
1861 .in_rot_dis_w = 8192,
1862 .out_rot_en_w = 1280,
1863 .out_rot_dis_w = 1920,
1864 },
1865 [3] = {
1866 .scaler_en_w = 1920,
1867 .scaler_dis_w = 8192,
1868 .in_rot_en_h = 1366,
1869 .in_rot_dis_w = 8192,
1870 .out_rot_en_w = 1366,
1871 .out_rot_dis_w = 1920,
1872 },
1873 };
1874
1875 static struct samsung_fimc_variant fimc0_variant_s5p = {
1876 .has_inp_rot = 1,
1877 .has_out_rot = 1,
1878 .has_cam_if = 1,
1879 .min_inp_pixsize = 16,
1880 .min_out_pixsize = 16,
1881 .hor_offs_align = 8,
1882 .min_vsize_align = 16,
1883 .out_buf_count = 4,
1884 .pix_limit = &s5p_pix_limit[0],
1885 };
1886
1887 static struct samsung_fimc_variant fimc2_variant_s5p = {
1888 .has_cam_if = 1,
1889 .min_inp_pixsize = 16,
1890 .min_out_pixsize = 16,
1891 .hor_offs_align = 8,
1892 .min_vsize_align = 16,
1893 .out_buf_count = 4,
1894 .pix_limit = &s5p_pix_limit[1],
1895 };
1896
1897 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1898 .pix_hoff = 1,
1899 .has_inp_rot = 1,
1900 .has_out_rot = 1,
1901 .has_cam_if = 1,
1902 .min_inp_pixsize = 16,
1903 .min_out_pixsize = 16,
1904 .hor_offs_align = 8,
1905 .min_vsize_align = 16,
1906 .out_buf_count = 4,
1907 .pix_limit = &s5p_pix_limit[1],
1908 };
1909
1910 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1911 .pix_hoff = 1,
1912 .has_inp_rot = 1,
1913 .has_out_rot = 1,
1914 .has_cam_if = 1,
1915 .has_mainscaler_ext = 1,
1916 .min_inp_pixsize = 16,
1917 .min_out_pixsize = 16,
1918 .hor_offs_align = 1,
1919 .min_vsize_align = 1,
1920 .out_buf_count = 4,
1921 .pix_limit = &s5p_pix_limit[2],
1922 };
1923
1924 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1925 .has_cam_if = 1,
1926 .pix_hoff = 1,
1927 .min_inp_pixsize = 16,
1928 .min_out_pixsize = 16,
1929 .hor_offs_align = 8,
1930 .min_vsize_align = 16,
1931 .out_buf_count = 4,
1932 .pix_limit = &s5p_pix_limit[2],
1933 };
1934
1935 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1936 .pix_hoff = 1,
1937 .has_inp_rot = 1,
1938 .has_out_rot = 1,
1939 .has_cam_if = 1,
1940 .has_cistatus2 = 1,
1941 .has_mainscaler_ext = 1,
1942 .has_alpha = 1,
1943 .min_inp_pixsize = 16,
1944 .min_out_pixsize = 16,
1945 .hor_offs_align = 2,
1946 .min_vsize_align = 1,
1947 .out_buf_count = 32,
1948 .pix_limit = &s5p_pix_limit[1],
1949 };
1950
1951 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1952 .pix_hoff = 1,
1953 .has_cam_if = 1,
1954 .has_cistatus2 = 1,
1955 .has_mainscaler_ext = 1,
1956 .has_alpha = 1,
1957 .min_inp_pixsize = 16,
1958 .min_out_pixsize = 16,
1959 .hor_offs_align = 2,
1960 .min_vsize_align = 1,
1961 .out_buf_count = 32,
1962 .pix_limit = &s5p_pix_limit[3],
1963 };
1964
1965 /* S5PC100 */
1966 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1967 .variant = {
1968 [0] = &fimc0_variant_s5p,
1969 [1] = &fimc0_variant_s5p,
1970 [2] = &fimc2_variant_s5p,
1971 },
1972 .num_entities = 3,
1973 .lclk_frequency = 133000000UL,
1974 };
1975
1976 /* S5PV210, S5PC110 */
1977 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1978 .variant = {
1979 [0] = &fimc0_variant_s5pv210,
1980 [1] = &fimc1_variant_s5pv210,
1981 [2] = &fimc2_variant_s5pv210,
1982 },
1983 .num_entities = 3,
1984 .lclk_frequency = 166000000UL,
1985 };
1986
1987 /* S5PV310, S5PC210 */
1988 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1989 .variant = {
1990 [0] = &fimc0_variant_exynos4,
1991 [1] = &fimc0_variant_exynos4,
1992 [2] = &fimc0_variant_exynos4,
1993 [3] = &fimc3_variant_exynos4,
1994 },
1995 .num_entities = 4,
1996 .lclk_frequency = 166000000UL,
1997 };
1998
1999 static struct platform_device_id fimc_driver_ids[] = {
2000 {
2001 .name = "s5p-fimc",
2002 .driver_data = (unsigned long)&fimc_drvdata_s5p,
2003 }, {
2004 .name = "s5pv210-fimc",
2005 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
2006 }, {
2007 .name = "exynos4-fimc",
2008 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
2009 },
2010 {},
2011 };
2012 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
2013
2014 static const struct dev_pm_ops fimc_pm_ops = {
2015 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
2016 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
2017 };
2018
2019 static struct platform_driver fimc_driver = {
2020 .probe = fimc_probe,
2021 .remove = __devexit_p(fimc_remove),
2022 .id_table = fimc_driver_ids,
2023 .driver = {
2024 .name = FIMC_MODULE_NAME,
2025 .owner = THIS_MODULE,
2026 .pm = &fimc_pm_ops,
2027 }
2028 };
2029
2030 int __init fimc_register_driver(void)
2031 {
2032 return platform_driver_probe(&fimc_driver, fimc_probe);
2033 }
2034
2035 void __exit fimc_unregister_driver(void)
2036 {
2037 platform_driver_unregister(&fimc_driver);
2038 }
Linux kernel - Deliverables
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