projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[media] s5p-fimc: Add runtime PM support in the mem-to-mem driver
[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-core.c
1 /*
2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
3 *
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29
30 #include "fimc-core.h"
31
32 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
33 "sclk_fimc", "fimc", "sclk_cam"
34 };
35
36 static struct fimc_fmt fimc_formats[] = {
37 {
38 .name = "RGB565",
39 .fourcc = V4L2_PIX_FMT_RGB565X,
40 .depth = { 16 },
41 .color = S5P_FIMC_RGB565,
42 .memplanes = 1,
43 .colplanes = 1,
44 .flags = FMT_FLAGS_M2M,
45 }, {
46 .name = "BGR666",
47 .fourcc = V4L2_PIX_FMT_BGR666,
48 .depth = { 32 },
49 .color = S5P_FIMC_RGB666,
50 .memplanes = 1,
51 .colplanes = 1,
52 .flags = FMT_FLAGS_M2M,
53 }, {
54 .name = "XRGB-8-8-8-8, 32 bpp",
55 .fourcc = V4L2_PIX_FMT_RGB32,
56 .depth = { 32 },
57 .color = S5P_FIMC_RGB888,
58 .memplanes = 1,
59 .colplanes = 1,
60 .flags = FMT_FLAGS_M2M,
61 }, {
62 .name = "YUV 4:2:2 packed, YCbYCr",
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .depth = { 16 },
65 .color = S5P_FIMC_YCBYCR422,
66 .memplanes = 1,
67 .colplanes = 1,
68 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
69 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
70 }, {
71 .name = "YUV 4:2:2 packed, CbYCrY",
72 .fourcc = V4L2_PIX_FMT_UYVY,
73 .depth = { 16 },
74 .color = S5P_FIMC_CBYCRY422,
75 .memplanes = 1,
76 .colplanes = 1,
77 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
78 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
79 }, {
80 .name = "YUV 4:2:2 packed, CrYCbY",
81 .fourcc = V4L2_PIX_FMT_VYUY,
82 .depth = { 16 },
83 .color = S5P_FIMC_CRYCBY422,
84 .memplanes = 1,
85 .colplanes = 1,
86 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
87 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
88 }, {
89 .name = "YUV 4:2:2 packed, YCrYCb",
90 .fourcc = V4L2_PIX_FMT_YVYU,
91 .depth = { 16 },
92 .color = S5P_FIMC_YCRYCB422,
93 .memplanes = 1,
94 .colplanes = 1,
95 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
96 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
97 }, {
98 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
99 .fourcc = V4L2_PIX_FMT_YUV422P,
100 .depth = { 12 },
101 .color = S5P_FIMC_YCBYCR422,
102 .memplanes = 1,
103 .colplanes = 3,
104 .flags = FMT_FLAGS_M2M,
105 }, {
106 .name = "YUV 4:2:2 planar, Y/CbCr",
107 .fourcc = V4L2_PIX_FMT_NV16,
108 .depth = { 16 },
109 .color = S5P_FIMC_YCBYCR422,
110 .memplanes = 1,
111 .colplanes = 2,
112 .flags = FMT_FLAGS_M2M,
113 }, {
114 .name = "YUV 4:2:2 planar, Y/CrCb",
115 .fourcc = V4L2_PIX_FMT_NV61,
116 .depth = { 16 },
117 .color = S5P_FIMC_YCRYCB422,
118 .memplanes = 1,
119 .colplanes = 2,
120 .flags = FMT_FLAGS_M2M,
121 }, {
122 .name = "YUV 4:2:0 planar, YCbCr",
123 .fourcc = V4L2_PIX_FMT_YUV420,
124 .depth = { 12 },
125 .color = S5P_FIMC_YCBCR420,
126 .memplanes = 1,
127 .colplanes = 3,
128 .flags = FMT_FLAGS_M2M,
129 }, {
130 .name = "YUV 4:2:0 planar, Y/CbCr",
131 .fourcc = V4L2_PIX_FMT_NV12,
132 .depth = { 12 },
133 .color = S5P_FIMC_YCBCR420,
134 .memplanes = 1,
135 .colplanes = 2,
136 .flags = FMT_FLAGS_M2M,
137 }, {
138 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
139 .fourcc = V4L2_PIX_FMT_NV12M,
140 .color = S5P_FIMC_YCBCR420,
141 .depth = { 8, 4 },
142 .memplanes = 2,
143 .colplanes = 2,
144 .flags = FMT_FLAGS_M2M,
145 }, {
146 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
147 .fourcc = V4L2_PIX_FMT_YUV420M,
148 .color = S5P_FIMC_YCBCR420,
149 .depth = { 8, 2, 2 },
150 .memplanes = 3,
151 .colplanes = 3,
152 .flags = FMT_FLAGS_M2M,
153 }, {
154 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
155 .fourcc = V4L2_PIX_FMT_NV12MT,
156 .color = S5P_FIMC_YCBCR420,
157 .depth = { 8, 4 },
158 .memplanes = 2,
159 .colplanes = 2,
160 .flags = FMT_FLAGS_M2M,
161 },
162 };
163
164 static struct v4l2_queryctrl fimc_ctrls[] = {
165 {
166 .id = V4L2_CID_HFLIP,
167 .type = V4L2_CTRL_TYPE_BOOLEAN,
168 .name = "Horizontal flip",
169 .minimum = 0,
170 .maximum = 1,
171 .default_value = 0,
172 }, {
173 .id = V4L2_CID_VFLIP,
174 .type = V4L2_CTRL_TYPE_BOOLEAN,
175 .name = "Vertical flip",
176 .minimum = 0,
177 .maximum = 1,
178 .default_value = 0,
179 }, {
180 .id = V4L2_CID_ROTATE,
181 .type = V4L2_CTRL_TYPE_INTEGER,
182 .name = "Rotation (CCW)",
183 .minimum = 0,
184 .maximum = 270,
185 .step = 90,
186 .default_value = 0,
187 },
188 };
189
190
191 static struct v4l2_queryctrl *get_ctrl(int id)
192 {
193 int i;
194
195 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
196 if (id == fimc_ctrls[i].id)
197 return &fimc_ctrls[i];
198 return NULL;
199 }
200
201 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
202 {
203 int tx, ty;
204
205 if (rot == 90 || rot == 270) {
206 ty = dw;
207 tx = dh;
208 } else {
209 tx = dw;
210 ty = dh;
211 }
212
213 if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
214 return -EINVAL;
215
216 return 0;
217 }
218
219 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
220 {
221 u32 sh = 6;
222
223 if (src >= 64 * tar)
224 return -EINVAL;
225
226 while (sh--) {
227 u32 tmp = 1 << sh;
228 if (src >= tar * tmp) {
229 *shift = sh, *ratio = tmp;
230 return 0;
231 }
232 }
233 *shift = 0, *ratio = 1;
234 return 0;
235 }
236
237 int fimc_set_scaler_info(struct fimc_ctx *ctx)
238 {
239 struct fimc_scaler *sc = &ctx->scaler;
240 struct fimc_frame *s_frame = &ctx->s_frame;
241 struct fimc_frame *d_frame = &ctx->d_frame;
242 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
243 int tx, ty, sx, sy;
244 int ret;
245
246 if (ctx->rotation == 90 || ctx->rotation == 270) {
247 ty = d_frame->width;
248 tx = d_frame->height;
249 } else {
250 tx = d_frame->width;
251 ty = d_frame->height;
252 }
253 if (tx <= 0 || ty <= 0) {
254 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
255 "invalid target size: %d x %d", tx, ty);
256 return -EINVAL;
257 }
258
259 sx = s_frame->width;
260 sy = s_frame->height;
261 if (sx <= 0 || sy <= 0) {
262 err("invalid source size: %d x %d", sx, sy);
263 return -EINVAL;
264 }
265 sc->real_width = sx;
266 sc->real_height = sy;
267
268 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
269 if (ret)
270 return ret;
271
272 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
273 if (ret)
274 return ret;
275
276 sc->pre_dst_width = sx / sc->pre_hratio;
277 sc->pre_dst_height = sy / sc->pre_vratio;
278
279 if (variant->has_mainscaler_ext) {
280 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
281 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
282 } else {
283 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
284 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
285
286 }
287
288 sc->scaleup_h = (tx >= sx) ? 1 : 0;
289 sc->scaleup_v = (ty >= sy) ? 1 : 0;
290
291 /* check to see if input and output size/format differ */
292 if (s_frame->fmt->color == d_frame->fmt->color
293 && s_frame->width == d_frame->width
294 && s_frame->height == d_frame->height)
295 sc->copy_mode = 1;
296 else
297 sc->copy_mode = 0;
298
299 return 0;
300 }
301
302 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
303 {
304 struct vb2_buffer *src_vb, *dst_vb;
305
306 if (!ctx || !ctx->m2m_ctx)
307 return;
308
309 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
310 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
311
312 if (src_vb && dst_vb) {
313 v4l2_m2m_buf_done(src_vb, vb_state);
314 v4l2_m2m_buf_done(dst_vb, vb_state);
315 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
316 ctx->m2m_ctx);
317 }
318 }
319
320 /* Complete the transaction which has been scheduled for execution. */
321 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
322 {
323 struct fimc_dev *fimc = ctx->fimc_dev;
324 int ret;
325
326 if (!fimc_m2m_pending(fimc))
327 return 0;
328
329 fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
330
331 ret = wait_event_timeout(fimc->irq_queue,
332 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
333 FIMC_SHUTDOWN_TIMEOUT);
334
335 return ret == 0 ? -ETIMEDOUT : ret;
336 }
337
338 static int start_streaming(struct vb2_queue *q, unsigned int count)
339 {
340 struct fimc_ctx *ctx = q->drv_priv;
341 int ret;
342
343 ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
344 return ret > 0 ? 0 : ret;
345 }
346
347 static int stop_streaming(struct vb2_queue *q)
348 {
349 struct fimc_ctx *ctx = q->drv_priv;
350 int ret;
351
352 ret = fimc_m2m_shutdown(ctx);
353 if (ret == -ETIMEDOUT)
354 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
355
356 pm_runtime_put(&ctx->fimc_dev->pdev->dev);
357 return 0;
358 }
359
360 static void fimc_capture_irq_handler(struct fimc_dev *fimc)
361 {
362 struct fimc_vid_cap *cap = &fimc->vid_cap;
363 struct fimc_vid_buffer *v_buf;
364 struct timeval *tv;
365 struct timespec ts;
366
367 if (!list_empty(&cap->active_buf_q) &&
368 test_bit(ST_CAPT_RUN, &fimc->state)) {
369 ktime_get_real_ts(&ts);
370
371 v_buf = active_queue_pop(cap);
372
373 tv = &v_buf->vb.v4l2_buf.timestamp;
374 tv->tv_sec = ts.tv_sec;
375 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
376 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
377
378 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
379 }
380
381 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
382 wake_up(&fimc->irq_queue);
383 return;
384 }
385
386 if (!list_empty(&cap->pending_buf_q)) {
387
388 v_buf = pending_queue_pop(cap);
389 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
390 v_buf->index = cap->buf_index;
391
392 /* Move the buffer to the capture active queue */
393 active_queue_add(cap, v_buf);
394
395 dbg("next frame: %d, done frame: %d",
396 fimc_hw_get_frame_index(fimc), v_buf->index);
397
398 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
399 cap->buf_index = 0;
400 }
401
402 if (cap->active_buf_cnt == 0) {
403 clear_bit(ST_CAPT_RUN, &fimc->state);
404
405 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
406 cap->buf_index = 0;
407 } else {
408 set_bit(ST_CAPT_RUN, &fimc->state);
409 }
410
411 dbg("frame: %d, active_buf_cnt: %d",
412 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
413 }
414
415 static irqreturn_t fimc_irq_handler(int irq, void *priv)
416 {
417 struct fimc_dev *fimc = priv;
418 struct fimc_vid_cap *cap = &fimc->vid_cap;
419 struct fimc_ctx *ctx;
420
421 fimc_hw_clear_irq(fimc);
422
423 spin_lock(&fimc->slock);
424
425 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
426 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
427 set_bit(ST_M2M_SUSPENDED, &fimc->state);
428 wake_up(&fimc->irq_queue);
429 goto out;
430 }
431 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
432 if (ctx != NULL) {
433 spin_unlock(&fimc->slock);
434 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
435
436 spin_lock(&ctx->slock);
437 if (ctx->state & FIMC_CTX_SHUT) {
438 ctx->state &= ~FIMC_CTX_SHUT;
439 wake_up(&fimc->irq_queue);
440 }
441 spin_unlock(&ctx->slock);
442 }
443 return IRQ_HANDLED;
444 } else {
445 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
446 fimc_capture_irq_handler(fimc);
447
448 if (cap->active_buf_cnt == 1) {
449 fimc_deactivate_capture(fimc);
450 clear_bit(ST_CAPT_STREAM, &fimc->state);
451 }
452 }
453 }
454 out:
455 spin_unlock(&fimc->slock);
456 return IRQ_HANDLED;
457 }
458
459 /* The color format (colplanes, memplanes) must be already configured. */
460 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
461 struct fimc_frame *frame, struct fimc_addr *paddr)
462 {
463 int ret = 0;
464 u32 pix_size;
465
466 if (vb == NULL || frame == NULL)
467 return -EINVAL;
468
469 pix_size = frame->width * frame->height;
470
471 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
472 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
473
474 paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
475
476 if (frame->fmt->memplanes == 1) {
477 switch (frame->fmt->colplanes) {
478 case 1:
479 paddr->cb = 0;
480 paddr->cr = 0;
481 break;
482 case 2:
483 /* decompose Y into Y/Cb */
484 paddr->cb = (u32)(paddr->y + pix_size);
485 paddr->cr = 0;
486 break;
487 case 3:
488 paddr->cb = (u32)(paddr->y + pix_size);
489 /* decompose Y into Y/Cb/Cr */
490 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
491 paddr->cr = (u32)(paddr->cb
492 + (pix_size >> 2));
493 else /* 422 */
494 paddr->cr = (u32)(paddr->cb
495 + (pix_size >> 1));
496 break;
497 default:
498 return -EINVAL;
499 }
500 } else {
501 if (frame->fmt->memplanes >= 2)
502 paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
503
504 if (frame->fmt->memplanes == 3)
505 paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
506 }
507
508 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
509 paddr->y, paddr->cb, paddr->cr, ret);
510
511 return ret;
512 }
513
514 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
515 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
516 {
517 /* The one only mode supported in SoC. */
518 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
519 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
520
521 /* Set order for 1 plane input formats. */
522 switch (ctx->s_frame.fmt->color) {
523 case S5P_FIMC_YCRYCB422:
524 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
525 break;
526 case S5P_FIMC_CBYCRY422:
527 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
528 break;
529 case S5P_FIMC_CRYCBY422:
530 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
531 break;
532 case S5P_FIMC_YCBYCR422:
533 default:
534 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
535 break;
536 }
537 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
538
539 switch (ctx->d_frame.fmt->color) {
540 case S5P_FIMC_YCRYCB422:
541 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
542 break;
543 case S5P_FIMC_CBYCRY422:
544 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
545 break;
546 case S5P_FIMC_CRYCBY422:
547 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
548 break;
549 case S5P_FIMC_YCBYCR422:
550 default:
551 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
552 break;
553 }
554 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
555 }
556
557 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
558 {
559 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
560 u32 i, depth = 0;
561
562 for (i = 0; i < f->fmt->colplanes; i++)
563 depth += f->fmt->depth[i];
564
565 f->dma_offset.y_h = f->offs_h;
566 if (!variant->pix_hoff)
567 f->dma_offset.y_h *= (depth >> 3);
568
569 f->dma_offset.y_v = f->offs_v;
570
571 f->dma_offset.cb_h = f->offs_h;
572 f->dma_offset.cb_v = f->offs_v;
573
574 f->dma_offset.cr_h = f->offs_h;
575 f->dma_offset.cr_v = f->offs_v;
576
577 if (!variant->pix_hoff) {
578 if (f->fmt->colplanes == 3) {
579 f->dma_offset.cb_h >>= 1;
580 f->dma_offset.cr_h >>= 1;
581 }
582 if (f->fmt->color == S5P_FIMC_YCBCR420) {
583 f->dma_offset.cb_v >>= 1;
584 f->dma_offset.cr_v >>= 1;
585 }
586 }
587
588 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
589 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
590 }
591
592 /**
593 * fimc_prepare_config - check dimensions, operation and color mode
594 * and pre-calculate offset and the scaling coefficients.
595 *
596 * @ctx: hardware context information
597 * @flags: flags indicating which parameters to check/update
598 *
599 * Return: 0 if dimensions are valid or non zero otherwise.
600 */
601 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
602 {
603 struct fimc_frame *s_frame, *d_frame;
604 struct vb2_buffer *vb = NULL;
605 int ret = 0;
606
607 s_frame = &ctx->s_frame;
608 d_frame = &ctx->d_frame;
609
610 if (flags & FIMC_PARAMS) {
611 /* Prepare the DMA offset ratios for scaler. */
612 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
613 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
614
615 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
616 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
617 err("out of scaler range");
618 return -EINVAL;
619 }
620 fimc_set_yuv_order(ctx);
621 }
622
623 /* Input DMA mode is not allowed when the scaler is disabled. */
624 ctx->scaler.enabled = 1;
625
626 if (flags & FIMC_SRC_ADDR) {
627 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
628 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
629 if (ret)
630 return ret;
631 }
632
633 if (flags & FIMC_DST_ADDR) {
634 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
635 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
636 }
637
638 return ret;
639 }
640
641 static void fimc_dma_run(void *priv)
642 {
643 struct fimc_ctx *ctx = priv;
644 struct fimc_dev *fimc;
645 unsigned long flags;
646 u32 ret;
647
648 if (WARN(!ctx, "null hardware context\n"))
649 return;
650
651 fimc = ctx->fimc_dev;
652 spin_lock_irqsave(&fimc->slock, flags);
653 set_bit(ST_M2M_PEND, &fimc->state);
654
655 spin_lock(&ctx->slock);
656 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
657 ret = fimc_prepare_config(ctx, ctx->state);
658 if (ret)
659 goto dma_unlock;
660
661 /* Reconfigure hardware if the context has changed. */
662 if (fimc->m2m.ctx != ctx) {
663 ctx->state |= FIMC_PARAMS;
664 fimc->m2m.ctx = ctx;
665 }
666 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
667
668 if (ctx->state & FIMC_PARAMS) {
669 fimc_hw_set_input_path(ctx);
670 fimc_hw_set_in_dma(ctx);
671 ret = fimc_set_scaler_info(ctx);
672 if (ret) {
673 spin_unlock(&fimc->slock);
674 goto dma_unlock;
675 }
676 fimc_hw_set_prescaler(ctx);
677 fimc_hw_set_mainscaler(ctx);
678 fimc_hw_set_target_format(ctx);
679 fimc_hw_set_rotation(ctx);
680 fimc_hw_set_effect(ctx);
681 }
682
683 fimc_hw_set_output_path(ctx);
684 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
685 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
686
687 if (ctx->state & FIMC_PARAMS)
688 fimc_hw_set_out_dma(ctx);
689
690 fimc_activate_capture(ctx);
691
692 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
693 FIMC_SRC_FMT | FIMC_DST_FMT);
694 fimc_hw_activate_input_dma(fimc, true);
695 dma_unlock:
696 spin_unlock(&ctx->slock);
697 spin_unlock_irqrestore(&fimc->slock, flags);
698 }
699
700 static void fimc_job_abort(void *priv)
701 {
702 fimc_m2m_shutdown(priv);
703 }
704
705 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
706 unsigned int *num_planes, unsigned int sizes[],
707 void *allocators[])
708 {
709 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
710 struct fimc_frame *f;
711 int i;
712
713 f = ctx_get_frame(ctx, vq->type);
714 if (IS_ERR(f))
715 return PTR_ERR(f);
716 /*
717 * Return number of non-contigous planes (plane buffers)
718 * depending on the configured color format.
719 */
720 if (!f->fmt)
721 return -EINVAL;
722
723 *num_planes = f->fmt->memplanes;
724 for (i = 0; i < f->fmt->memplanes; i++) {
725 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
726 allocators[i] = ctx->fimc_dev->alloc_ctx;
727 }
728 return 0;
729 }
730
731 static int fimc_buf_prepare(struct vb2_buffer *vb)
732 {
733 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
734 struct fimc_frame *frame;
735 int i;
736
737 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
738 if (IS_ERR(frame))
739 return PTR_ERR(frame);
740
741 for (i = 0; i < frame->fmt->memplanes; i++)
742 vb2_set_plane_payload(vb, i, frame->payload[i]);
743
744 return 0;
745 }
746
747 static void fimc_buf_queue(struct vb2_buffer *vb)
748 {
749 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
750
751 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
752
753 if (ctx->m2m_ctx)
754 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
755 }
756
757 static void fimc_lock(struct vb2_queue *vq)
758 {
759 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
760 mutex_lock(&ctx->fimc_dev->lock);
761 }
762
763 static void fimc_unlock(struct vb2_queue *vq)
764 {
765 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
766 mutex_unlock(&ctx->fimc_dev->lock);
767 }
768
769 static struct vb2_ops fimc_qops = {
770 .queue_setup = fimc_queue_setup,
771 .buf_prepare = fimc_buf_prepare,
772 .buf_queue = fimc_buf_queue,
773 .wait_prepare = fimc_unlock,
774 .wait_finish = fimc_lock,
775 .stop_streaming = stop_streaming,
776 .start_streaming = start_streaming,
777 };
778
779 static int fimc_m2m_querycap(struct file *file, void *priv,
780 struct v4l2_capability *cap)
781 {
782 struct fimc_ctx *ctx = file->private_data;
783 struct fimc_dev *fimc = ctx->fimc_dev;
784
785 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
786 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
787 cap->bus_info[0] = 0;
788 cap->capabilities = V4L2_CAP_STREAMING |
789 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
790 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
791
792 return 0;
793 }
794
795 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
796 struct v4l2_fmtdesc *f)
797 {
798 struct fimc_fmt *fmt;
799
800 if (f->index >= ARRAY_SIZE(fimc_formats))
801 return -EINVAL;
802
803 fmt = &fimc_formats[f->index];
804 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
805 f->pixelformat = fmt->fourcc;
806
807 return 0;
808 }
809
810 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
811 struct v4l2_format *f)
812 {
813 struct fimc_ctx *ctx = priv;
814 struct fimc_frame *frame;
815 struct v4l2_pix_format_mplane *pixm;
816 int i;
817
818 frame = ctx_get_frame(ctx, f->type);
819 if (IS_ERR(frame))
820 return PTR_ERR(frame);
821
822 pixm = &f->fmt.pix_mp;
823
824 pixm->width = frame->width;
825 pixm->height = frame->height;
826 pixm->field = V4L2_FIELD_NONE;
827 pixm->pixelformat = frame->fmt->fourcc;
828 pixm->colorspace = V4L2_COLORSPACE_JPEG;
829 pixm->num_planes = frame->fmt->memplanes;
830
831 for (i = 0; i < pixm->num_planes; ++i) {
832 int bpl = frame->o_width;
833
834 if (frame->fmt->colplanes == 1) /* packed formats */
835 bpl = (bpl * frame->fmt->depth[0]) / 8;
836
837 pixm->plane_fmt[i].bytesperline = bpl;
838
839 pixm->plane_fmt[i].sizeimage = (frame->o_width *
840 frame->o_height * frame->fmt->depth[i]) / 8;
841 }
842
843 return 0;
844 }
845
846 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
847 {
848 struct fimc_fmt *fmt;
849 unsigned int i;
850
851 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
852 fmt = &fimc_formats[i];
853 if (fmt->fourcc == f->fmt.pix_mp.pixelformat &&
854 (fmt->flags & mask))
855 break;
856 }
857
858 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
859 }
860
861 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
862 unsigned int mask)
863 {
864 struct fimc_fmt *fmt;
865 unsigned int i;
866
867 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
868 fmt = &fimc_formats[i];
869 if (fmt->mbus_code == f->code && (fmt->flags & mask))
870 break;
871 }
872
873 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
874 }
875
876
877 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
878 struct v4l2_format *f)
879 {
880 struct fimc_ctx *ctx = priv;
881 struct fimc_dev *fimc = ctx->fimc_dev;
882 struct samsung_fimc_variant *variant = fimc->variant;
883 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
884 struct fimc_fmt *fmt;
885 u32 max_width, mod_x, mod_y, mask;
886 int i, is_output = 0;
887
888 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
889 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
890 return -EINVAL;
891 is_output = 1;
892 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
893 return -EINVAL;
894 }
895
896 dbg("w: %d, h: %d", pix->width, pix->height);
897
898 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
899 fmt = find_format(f, mask);
900 if (!fmt) {
901 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
902 pix->pixelformat);
903 return -EINVAL;
904 }
905
906 if (pix->field == V4L2_FIELD_ANY)
907 pix->field = V4L2_FIELD_NONE;
908 else if (V4L2_FIELD_NONE != pix->field)
909 return -EINVAL;
910
911 if (is_output) {
912 max_width = variant->pix_limit->scaler_dis_w;
913 mod_x = ffs(variant->min_inp_pixsize) - 1;
914 } else {
915 max_width = variant->pix_limit->out_rot_dis_w;
916 mod_x = ffs(variant->min_out_pixsize) - 1;
917 }
918
919 if (tiled_fmt(fmt)) {
920 mod_x = 6; /* 64 x 32 pixels tile */
921 mod_y = 5;
922 } else {
923 if (fimc->id == 1 && variant->pix_hoff)
924 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
925 else
926 mod_y = mod_x;
927 }
928
929 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
930
931 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
932 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
933
934 pix->num_planes = fmt->memplanes;
935 pix->colorspace = V4L2_COLORSPACE_JPEG;
936
937
938 for (i = 0; i < pix->num_planes; ++i) {
939 u32 bpl = pix->plane_fmt[i].bytesperline;
940 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
941
942 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
943 bpl = pix->width; /* Planar */
944
945 if (fmt->colplanes == 1 && /* Packed */
946 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
947 bpl = (pix->width * fmt->depth[0]) / 8;
948
949 if (i == 0) /* Same bytesperline for each plane. */
950 mod_x = bpl;
951
952 pix->plane_fmt[i].bytesperline = mod_x;
953 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
954 }
955
956 return 0;
957 }
958
959 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
960 struct v4l2_format *f)
961 {
962 struct fimc_ctx *ctx = priv;
963 struct fimc_dev *fimc = ctx->fimc_dev;
964 struct vb2_queue *vq;
965 struct fimc_frame *frame;
966 struct v4l2_pix_format_mplane *pix;
967 int i, ret = 0;
968
969 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
970 if (ret)
971 return ret;
972
973 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
974
975 if (vb2_is_busy(vq)) {
976 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
977 return -EBUSY;
978 }
979
980 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
981 frame = &ctx->s_frame;
982 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
983 frame = &ctx->d_frame;
984 } else {
985 v4l2_err(&fimc->m2m.v4l2_dev,
986 "Wrong buffer/video queue type (%d)\n", f->type);
987 return -EINVAL;
988 }
989
990 pix = &f->fmt.pix_mp;
991 frame->fmt = find_format(f, FMT_FLAGS_M2M);
992 if (!frame->fmt)
993 return -EINVAL;
994
995 for (i = 0; i < frame->fmt->colplanes; i++) {
996 frame->payload[i] =
997 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
998 }
999
1000 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
1001 frame->fmt->depth[0];
1002 frame->f_height = pix->height;
1003 frame->width = pix->width;
1004 frame->height = pix->height;
1005 frame->o_width = pix->width;
1006 frame->o_height = pix->height;
1007 frame->offs_h = 0;
1008 frame->offs_v = 0;
1009
1010 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1011 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1012 else
1013 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1014
1015 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1016
1017 return 0;
1018 }
1019
1020 static int fimc_m2m_reqbufs(struct file *file, void *priv,
1021 struct v4l2_requestbuffers *reqbufs)
1022 {
1023 struct fimc_ctx *ctx = priv;
1024 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1025 }
1026
1027 static int fimc_m2m_querybuf(struct file *file, void *priv,
1028 struct v4l2_buffer *buf)
1029 {
1030 struct fimc_ctx *ctx = priv;
1031 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1032 }
1033
1034 static int fimc_m2m_qbuf(struct file *file, void *priv,
1035 struct v4l2_buffer *buf)
1036 {
1037 struct fimc_ctx *ctx = priv;
1038
1039 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1040 }
1041
1042 static int fimc_m2m_dqbuf(struct file *file, void *priv,
1043 struct v4l2_buffer *buf)
1044 {
1045 struct fimc_ctx *ctx = priv;
1046 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1047 }
1048
1049 static int fimc_m2m_streamon(struct file *file, void *priv,
1050 enum v4l2_buf_type type)
1051 {
1052 struct fimc_ctx *ctx = priv;
1053
1054 /* The source and target color format need to be set */
1055 if (V4L2_TYPE_IS_OUTPUT(type)) {
1056 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1057 return -EINVAL;
1058 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1059 return -EINVAL;
1060 }
1061
1062 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1063 }
1064
1065 static int fimc_m2m_streamoff(struct file *file, void *priv,
1066 enum v4l2_buf_type type)
1067 {
1068 struct fimc_ctx *ctx = priv;
1069 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1070 }
1071
1072 int fimc_vidioc_queryctrl(struct file *file, void *priv,
1073 struct v4l2_queryctrl *qc)
1074 {
1075 struct fimc_ctx *ctx = priv;
1076 struct v4l2_queryctrl *c;
1077 int ret = -EINVAL;
1078
1079 c = get_ctrl(qc->id);
1080 if (c) {
1081 *qc = *c;
1082 return 0;
1083 }
1084
1085 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1086 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1087 core, queryctrl, qc);
1088 }
1089 return ret;
1090 }
1091
1092 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1093 struct v4l2_control *ctrl)
1094 {
1095 struct fimc_ctx *ctx = priv;
1096 struct fimc_dev *fimc = ctx->fimc_dev;
1097
1098 switch (ctrl->id) {
1099 case V4L2_CID_HFLIP:
1100 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1101 break;
1102 case V4L2_CID_VFLIP:
1103 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1104 break;
1105 case V4L2_CID_ROTATE:
1106 ctrl->value = ctx->rotation;
1107 break;
1108 default:
1109 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1110 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1111 g_ctrl, ctrl);
1112 } else {
1113 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1114 return -EINVAL;
1115 }
1116 }
1117 dbg("ctrl->value= %d", ctrl->value);
1118
1119 return 0;
1120 }
1121
1122 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1123 {
1124 struct v4l2_queryctrl *c;
1125 c = get_ctrl(ctrl->id);
1126 if (!c)
1127 return -EINVAL;
1128
1129 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1130 || (c->step != 0 && ctrl->value % c->step != 0)) {
1131 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1132 "Invalid control value\n");
1133 return -ERANGE;
1134 }
1135
1136 return 0;
1137 }
1138
1139 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1140 {
1141 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1142 struct fimc_dev *fimc = ctx->fimc_dev;
1143 int ret = 0;
1144
1145 switch (ctrl->id) {
1146 case V4L2_CID_HFLIP:
1147 if (ctrl->value)
1148 ctx->flip |= FLIP_X_AXIS;
1149 else
1150 ctx->flip &= ~FLIP_X_AXIS;
1151 break;
1152
1153 case V4L2_CID_VFLIP:
1154 if (ctrl->value)
1155 ctx->flip |= FLIP_Y_AXIS;
1156 else
1157 ctx->flip &= ~FLIP_Y_AXIS;
1158 break;
1159
1160 case V4L2_CID_ROTATE:
1161 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1162 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1163 ctx->s_frame.height, ctx->d_frame.width,
1164 ctx->d_frame.height, ctrl->value);
1165 }
1166
1167 if (ret) {
1168 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1169 return -EINVAL;
1170 }
1171
1172 /* Check for the output rotator availability */
1173 if ((ctrl->value == 90 || ctrl->value == 270) &&
1174 (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
1175 return -EINVAL;
1176 ctx->rotation = ctrl->value;
1177 break;
1178
1179 default:
1180 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1181 return -EINVAL;
1182 }
1183
1184 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1185
1186 return 0;
1187 }
1188
1189 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1190 struct v4l2_control *ctrl)
1191 {
1192 struct fimc_ctx *ctx = priv;
1193 int ret = 0;
1194
1195 ret = check_ctrl_val(ctx, ctrl);
1196 if (ret)
1197 return ret;
1198
1199 ret = fimc_s_ctrl(ctx, ctrl);
1200 return 0;
1201 }
1202
1203 static int fimc_m2m_cropcap(struct file *file, void *fh,
1204 struct v4l2_cropcap *cr)
1205 {
1206 struct fimc_frame *frame;
1207 struct fimc_ctx *ctx = fh;
1208
1209 frame = ctx_get_frame(ctx, cr->type);
1210 if (IS_ERR(frame))
1211 return PTR_ERR(frame);
1212
1213 cr->bounds.left = 0;
1214 cr->bounds.top = 0;
1215 cr->bounds.width = frame->f_width;
1216 cr->bounds.height = frame->f_height;
1217 cr->defrect = cr->bounds;
1218
1219 return 0;
1220 }
1221
1222 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1223 {
1224 struct fimc_frame *frame;
1225 struct fimc_ctx *ctx = file->private_data;
1226
1227 frame = ctx_get_frame(ctx, cr->type);
1228 if (IS_ERR(frame))
1229 return PTR_ERR(frame);
1230
1231 cr->c.left = frame->offs_h;
1232 cr->c.top = frame->offs_v;
1233 cr->c.width = frame->width;
1234 cr->c.height = frame->height;
1235
1236 return 0;
1237 }
1238
1239 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1240 {
1241 struct fimc_dev *fimc = ctx->fimc_dev;
1242 struct fimc_frame *f;
1243 u32 min_size, halign, depth = 0;
1244 bool is_capture_ctx;
1245 int i;
1246
1247 if (cr->c.top < 0 || cr->c.left < 0) {
1248 v4l2_err(&fimc->m2m.v4l2_dev,
1249 "doesn't support negative values for top & left\n");
1250 return -EINVAL;
1251 }
1252
1253 is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1254
1255 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1256 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1257 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1258 !is_capture_ctx)
1259 f = &ctx->s_frame;
1260 else
1261 return -EINVAL;
1262
1263 min_size = (f == &ctx->s_frame) ?
1264 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1265
1266 /* Get pixel alignment constraints. */
1267 if (is_capture_ctx) {
1268 min_size = 16;
1269 halign = 4;
1270 } else {
1271 if (fimc->id == 1 && fimc->variant->pix_hoff)
1272 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1273 else
1274 halign = ffs(min_size) - 1;
1275 }
1276
1277 for (i = 0; i < f->fmt->colplanes; i++)
1278 depth += f->fmt->depth[i];
1279
1280 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1281 ffs(min_size) - 1,
1282 &cr->c.height, min_size, f->o_height,
1283 halign, 64/(ALIGN(depth, 8)));
1284
1285 /* adjust left/top if cropping rectangle is out of bounds */
1286 if (cr->c.left + cr->c.width > f->o_width)
1287 cr->c.left = f->o_width - cr->c.width;
1288 if (cr->c.top + cr->c.height > f->o_height)
1289 cr->c.top = f->o_height - cr->c.height;
1290
1291 cr->c.left = round_down(cr->c.left, min_size);
1292 cr->c.top = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1293
1294 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1295 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1296 f->f_width, f->f_height);
1297
1298 return 0;
1299 }
1300
1301 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1302 {
1303 struct fimc_ctx *ctx = file->private_data;
1304 struct fimc_dev *fimc = ctx->fimc_dev;
1305 struct fimc_frame *f;
1306 int ret;
1307
1308 ret = fimc_try_crop(ctx, cr);
1309 if (ret)
1310 return ret;
1311
1312 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1313 &ctx->s_frame : &ctx->d_frame;
1314
1315 /* Check to see if scaling ratio is within supported range */
1316 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1317 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1318 ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1319 ctx->d_frame.width,
1320 ctx->d_frame.height,
1321 ctx->rotation);
1322 } else {
1323 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1324 ctx->s_frame.height,
1325 cr->c.width, cr->c.height,
1326 ctx->rotation);
1327 }
1328 if (ret) {
1329 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1330 return -EINVAL;
1331 }
1332 }
1333
1334 f->offs_h = cr->c.left;
1335 f->offs_v = cr->c.top;
1336 f->width = cr->c.width;
1337 f->height = cr->c.height;
1338
1339 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1340
1341 return 0;
1342 }
1343
1344 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1345 .vidioc_querycap = fimc_m2m_querycap,
1346
1347 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1348 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1349
1350 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1351 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1352
1353 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1354 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1355
1356 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1357 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1358
1359 .vidioc_reqbufs = fimc_m2m_reqbufs,
1360 .vidioc_querybuf = fimc_m2m_querybuf,
1361
1362 .vidioc_qbuf = fimc_m2m_qbuf,
1363 .vidioc_dqbuf = fimc_m2m_dqbuf,
1364
1365 .vidioc_streamon = fimc_m2m_streamon,
1366 .vidioc_streamoff = fimc_m2m_streamoff,
1367
1368 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1369 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1370 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1371
1372 .vidioc_g_crop = fimc_m2m_g_crop,
1373 .vidioc_s_crop = fimc_m2m_s_crop,
1374 .vidioc_cropcap = fimc_m2m_cropcap
1375
1376 };
1377
1378 static int queue_init(void *priv, struct vb2_queue *src_vq,
1379 struct vb2_queue *dst_vq)
1380 {
1381 struct fimc_ctx *ctx = priv;
1382 int ret;
1383
1384 memset(src_vq, 0, sizeof(*src_vq));
1385 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1386 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1387 src_vq->drv_priv = ctx;
1388 src_vq->ops = &fimc_qops;
1389 src_vq->mem_ops = &vb2_dma_contig_memops;
1390 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1391
1392 ret = vb2_queue_init(src_vq);
1393 if (ret)
1394 return ret;
1395
1396 memset(dst_vq, 0, sizeof(*dst_vq));
1397 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1398 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1399 dst_vq->drv_priv = ctx;
1400 dst_vq->ops = &fimc_qops;
1401 dst_vq->mem_ops = &vb2_dma_contig_memops;
1402 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1403
1404 return vb2_queue_init(dst_vq);
1405 }
1406
1407 static int fimc_m2m_open(struct file *file)
1408 {
1409 struct fimc_dev *fimc = video_drvdata(file);
1410 struct fimc_ctx *ctx = NULL;
1411
1412 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1413 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1414
1415 /*
1416 * Return if the corresponding video capture node
1417 * is already opened.
1418 */
1419 if (fimc->vid_cap.refcnt > 0)
1420 return -EBUSY;
1421
1422 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1423 if (!ctx)
1424 return -ENOMEM;
1425
1426 file->private_data = ctx;
1427 ctx->fimc_dev = fimc;
1428 /* Default color format */
1429 ctx->s_frame.fmt = &fimc_formats[0];
1430 ctx->d_frame.fmt = &fimc_formats[0];
1431 /* Setup the device context for mem2mem mode. */
1432 ctx->state = FIMC_CTX_M2M;
1433 ctx->flags = 0;
1434 ctx->in_path = FIMC_DMA;
1435 ctx->out_path = FIMC_DMA;
1436 spin_lock_init(&ctx->slock);
1437
1438 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1439 if (IS_ERR(ctx->m2m_ctx)) {
1440 int err = PTR_ERR(ctx->m2m_ctx);
1441 kfree(ctx);
1442 return err;
1443 }
1444
1445 if (fimc->m2m.refcnt++ == 0)
1446 set_bit(ST_M2M_RUN, &fimc->state);
1447
1448 return 0;
1449 }
1450
1451 static int fimc_m2m_release(struct file *file)
1452 {
1453 struct fimc_ctx *ctx = file->private_data;
1454 struct fimc_dev *fimc = ctx->fimc_dev;
1455
1456 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1457 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1458
1459 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1460
1461 if (--fimc->m2m.refcnt <= 0)
1462 clear_bit(ST_M2M_RUN, &fimc->state);
1463 kfree(ctx);
1464 return 0;
1465 }
1466
1467 static unsigned int fimc_m2m_poll(struct file *file,
1468 struct poll_table_struct *wait)
1469 {
1470 struct fimc_ctx *ctx = file->private_data;
1471
1472 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1473 }
1474
1475
1476 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1477 {
1478 struct fimc_ctx *ctx = file->private_data;
1479
1480 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1481 }
1482
1483 static const struct v4l2_file_operations fimc_m2m_fops = {
1484 .owner = THIS_MODULE,
1485 .open = fimc_m2m_open,
1486 .release = fimc_m2m_release,
1487 .poll = fimc_m2m_poll,
1488 .unlocked_ioctl = video_ioctl2,
1489 .mmap = fimc_m2m_mmap,
1490 };
1491
1492 static struct v4l2_m2m_ops m2m_ops = {
1493 .device_run = fimc_dma_run,
1494 .job_abort = fimc_job_abort,
1495 };
1496
1497 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1498 {
1499 struct video_device *vfd;
1500 struct platform_device *pdev;
1501 struct v4l2_device *v4l2_dev;
1502 int ret = 0;
1503
1504 if (!fimc)
1505 return -ENODEV;
1506
1507 pdev = fimc->pdev;
1508 v4l2_dev = &fimc->m2m.v4l2_dev;
1509
1510 /* set name if it is empty */
1511 if (!v4l2_dev->name[0])
1512 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1513 "%s.m2m", dev_name(&pdev->dev));
1514
1515 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1516 if (ret)
1517 goto err_m2m_r1;
1518
1519 vfd = video_device_alloc();
1520 if (!vfd) {
1521 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1522 goto err_m2m_r1;
1523 }
1524
1525 vfd->fops = &fimc_m2m_fops;
1526 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1527 vfd->minor = -1;
1528 vfd->release = video_device_release;
1529 vfd->lock = &fimc->lock;
1530
1531 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1532
1533 video_set_drvdata(vfd, fimc);
1534 platform_set_drvdata(pdev, fimc);
1535
1536 fimc->m2m.vfd = vfd;
1537 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1538 if (IS_ERR(fimc->m2m.m2m_dev)) {
1539 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1540 ret = PTR_ERR(fimc->m2m.m2m_dev);
1541 goto err_m2m_r2;
1542 }
1543
1544 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1545 if (ret) {
1546 v4l2_err(v4l2_dev,
1547 "%s(): failed to register video device\n", __func__);
1548 goto err_m2m_r3;
1549 }
1550 v4l2_info(v4l2_dev,
1551 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1552
1553 return 0;
1554
1555 err_m2m_r3:
1556 v4l2_m2m_release(fimc->m2m.m2m_dev);
1557 err_m2m_r2:
1558 video_device_release(fimc->m2m.vfd);
1559 err_m2m_r1:
1560 v4l2_device_unregister(v4l2_dev);
1561
1562 return ret;
1563 }
1564
1565 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1566 {
1567 if (fimc) {
1568 v4l2_m2m_release(fimc->m2m.m2m_dev);
1569 video_unregister_device(fimc->m2m.vfd);
1570
1571 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1572 }
1573 }
1574
1575 static void fimc_clk_put(struct fimc_dev *fimc)
1576 {
1577 int i;
1578 for (i = 0; i < fimc->num_clocks; i++) {
1579 if (fimc->clock[i])
1580 clk_put(fimc->clock[i]);
1581 }
1582 }
1583
1584 static int fimc_clk_get(struct fimc_dev *fimc)
1585 {
1586 int i;
1587 for (i = 0; i < fimc->num_clocks; i++) {
1588 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1589 if (!IS_ERR_OR_NULL(fimc->clock[i]))
1590 continue;
1591 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1592 fimc_clocks[i]);
1593 return -ENXIO;
1594 }
1595
1596 return 0;
1597 }
1598
1599 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1600 {
1601 unsigned long flags;
1602 int timeout;
1603
1604 spin_lock_irqsave(&fimc->slock, flags);
1605 if (!fimc_m2m_pending(fimc)) {
1606 spin_unlock_irqrestore(&fimc->slock, flags);
1607 return 0;
1608 }
1609 clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1610 set_bit(ST_M2M_SUSPENDING, &fimc->state);
1611 spin_unlock_irqrestore(&fimc->slock, flags);
1612
1613 timeout = wait_event_timeout(fimc->irq_queue,
1614 test_bit(ST_M2M_SUSPENDED, &fimc->state),
1615 FIMC_SHUTDOWN_TIMEOUT);
1616
1617 clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1618 return timeout == 0 ? -EAGAIN : 0;
1619 }
1620
1621 static int fimc_m2m_resume(struct fimc_dev *fimc)
1622 {
1623 unsigned long flags;
1624
1625 spin_lock_irqsave(&fimc->slock, flags);
1626 /* Clear for full H/W setup in first run after resume */
1627 fimc->m2m.ctx = NULL;
1628 spin_unlock_irqrestore(&fimc->slock, flags);
1629
1630 if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1631 fimc_m2m_job_finish(fimc->m2m.ctx,
1632 VB2_BUF_STATE_ERROR);
1633 return 0;
1634 }
1635
1636 static int fimc_probe(struct platform_device *pdev)
1637 {
1638 struct fimc_dev *fimc;
1639 struct resource *res;
1640 struct samsung_fimc_driverdata *drv_data;
1641 struct s5p_platform_fimc *pdata;
1642 int ret = 0;
1643 int cap_input_index = -1;
1644
1645 dev_dbg(&pdev->dev, "%s():\n", __func__);
1646
1647 drv_data = (struct samsung_fimc_driverdata *)
1648 platform_get_device_id(pdev)->driver_data;
1649
1650 if (pdev->id >= drv_data->num_entities) {
1651 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1652 pdev->id);
1653 return -EINVAL;
1654 }
1655
1656 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1657 if (!fimc)
1658 return -ENOMEM;
1659
1660 fimc->id = pdev->id;
1661
1662 fimc->variant = drv_data->variant[fimc->id];
1663 fimc->pdev = pdev;
1664 pdata = pdev->dev.platform_data;
1665 fimc->pdata = pdata;
1666
1667 set_bit(ST_LPM, &fimc->state);
1668
1669 init_waitqueue_head(&fimc->irq_queue);
1670 spin_lock_init(&fimc->slock);
1671
1672 mutex_init(&fimc->lock);
1673
1674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675 if (!res) {
1676 dev_err(&pdev->dev, "failed to find the registers\n");
1677 ret = -ENOENT;
1678 goto err_info;
1679 }
1680
1681 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1682 dev_name(&pdev->dev));
1683 if (!fimc->regs_res) {
1684 dev_err(&pdev->dev, "failed to obtain register region\n");
1685 ret = -ENOENT;
1686 goto err_info;
1687 }
1688
1689 fimc->regs = ioremap(res->start, resource_size(res));
1690 if (!fimc->regs) {
1691 dev_err(&pdev->dev, "failed to map registers\n");
1692 ret = -ENXIO;
1693 goto err_req_region;
1694 }
1695
1696 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1697
1698 /* Check if a video capture node needs to be registered. */
1699 if (pdata && pdata->num_clients > 0) {
1700 cap_input_index = 0;
1701 fimc->num_clocks++;
1702 }
1703
1704 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1705 if (!res) {
1706 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1707 ret = -ENXIO;
1708 goto err_regs_unmap;
1709 }
1710 fimc->irq = res->start;
1711
1712 ret = fimc_clk_get(fimc);
1713 if (ret)
1714 goto err_regs_unmap;
1715 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1716 clk_enable(fimc->clock[CLK_BUS]);
1717
1718 platform_set_drvdata(pdev, fimc);
1719
1720 ret = request_irq(fimc->irq, fimc_irq_handler, 0, pdev->name, fimc);
1721 if (ret) {
1722 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1723 goto err_clk;
1724 }
1725
1726 pm_runtime_enable(&pdev->dev);
1727 ret = pm_runtime_get_sync(&pdev->dev);
1728 if (ret < 0)
1729 goto err_irq;
1730 /* Initialize contiguous memory allocator */
1731 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1732 if (IS_ERR(fimc->alloc_ctx)) {
1733 ret = PTR_ERR(fimc->alloc_ctx);
1734 goto err_pm;
1735 }
1736
1737 ret = fimc_register_m2m_device(fimc);
1738 if (ret)
1739 goto err_alloc;
1740
1741 /* At least one camera sensor is required to register capture node */
1742 if (cap_input_index >= 0) {
1743 ret = fimc_register_capture_device(fimc);
1744 if (ret)
1745 goto err_m2m;
1746 }
1747
1748 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1749 __func__, fimc->id);
1750
1751 pm_runtime_put(&pdev->dev);
1752 return 0;
1753
1754 err_m2m:
1755 fimc_unregister_m2m_device(fimc);
1756 err_alloc:
1757 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1758 err_pm:
1759 pm_runtime_put(&pdev->dev);
1760 err_irq:
1761 free_irq(fimc->irq, fimc);
1762 err_clk:
1763 fimc_clk_put(fimc);
1764 err_regs_unmap:
1765 iounmap(fimc->regs);
1766 err_req_region:
1767 release_resource(fimc->regs_res);
1768 kfree(fimc->regs_res);
1769 err_info:
1770 kfree(fimc);
1771
1772 return ret;
1773 }
1774
1775 static int fimc_runtime_resume(struct device *dev)
1776 {
1777 struct fimc_dev *fimc = dev_get_drvdata(dev);
1778
1779 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1780
1781 /* Enable clocks and perform basic initalization */
1782 clk_enable(fimc->clock[CLK_GATE]);
1783 fimc_hw_reset(fimc);
1784 if (fimc->variant->out_buf_count > 4)
1785 fimc_hw_set_dma_seq(fimc, 0xF);
1786
1787 /* Resume the capture or mem-to-mem device */
1788 if (fimc_capture_busy(fimc))
1789 return fimc_capture_resume(fimc);
1790 else if (fimc_m2m_pending(fimc))
1791 return fimc_m2m_resume(fimc);
1792 return 0;
1793 }
1794
1795 static int fimc_runtime_suspend(struct device *dev)
1796 {
1797 struct fimc_dev *fimc = dev_get_drvdata(dev);
1798 int ret = 0;
1799
1800 if (fimc_capture_busy(fimc))
1801 ret = fimc_capture_suspend(fimc);
1802 else
1803 ret = fimc_m2m_suspend(fimc);
1804 if (!ret)
1805 clk_disable(fimc->clock[CLK_GATE]);
1806
1807 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1808 return ret;
1809 }
1810
1811 #ifdef CONFIG_PM_SLEEP
1812 static int fimc_resume(struct device *dev)
1813 {
1814 struct fimc_dev *fimc = dev_get_drvdata(dev);
1815 unsigned long flags;
1816
1817 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1818
1819 /* Do not resume if the device was idle before system suspend */
1820 spin_lock_irqsave(&fimc->slock, flags);
1821 if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1822 (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1823 spin_unlock_irqrestore(&fimc->slock, flags);
1824 return 0;
1825 }
1826 fimc_hw_reset(fimc);
1827 if (fimc->variant->out_buf_count > 4)
1828 fimc_hw_set_dma_seq(fimc, 0xF);
1829 spin_unlock_irqrestore(&fimc->slock, flags);
1830
1831 if (fimc_capture_busy(fimc))
1832 return fimc_capture_resume(fimc);
1833
1834 return fimc_m2m_resume(fimc);
1835 }
1836
1837 static int fimc_suspend(struct device *dev)
1838 {
1839 struct fimc_dev *fimc = dev_get_drvdata(dev);
1840
1841 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1842
1843 if (test_and_set_bit(ST_LPM, &fimc->state))
1844 return 0;
1845 if (fimc_capture_busy(fimc))
1846 return fimc_capture_suspend(fimc);
1847
1848 return fimc_m2m_suspend(fimc);
1849 }
1850 #endif /* CONFIG_PM_SLEEP */
1851
1852 static int __devexit fimc_remove(struct platform_device *pdev)
1853 {
1854 struct fimc_dev *fimc = platform_get_drvdata(pdev);
1855
1856 pm_runtime_disable(&pdev->dev);
1857 fimc_runtime_suspend(&pdev->dev);
1858 pm_runtime_set_suspended(&pdev->dev);
1859
1860 fimc_unregister_m2m_device(fimc);
1861 fimc_unregister_capture_device(fimc);
1862
1863 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1864
1865 clk_disable(fimc->clock[CLK_BUS]);
1866 fimc_clk_put(fimc);
1867 free_irq(fimc->irq, fimc);
1868 iounmap(fimc->regs);
1869 release_resource(fimc->regs_res);
1870 kfree(fimc->regs_res);
1871 kfree(fimc);
1872
1873 dev_info(&pdev->dev, "driver unloaded\n");
1874 return 0;
1875 }
1876
1877 /* Image pixel limits, similar across several FIMC HW revisions. */
1878 static struct fimc_pix_limit s5p_pix_limit[4] = {
1879 [0] = {
1880 .scaler_en_w = 3264,
1881 .scaler_dis_w = 8192,
1882 .in_rot_en_h = 1920,
1883 .in_rot_dis_w = 8192,
1884 .out_rot_en_w = 1920,
1885 .out_rot_dis_w = 4224,
1886 },
1887 [1] = {
1888 .scaler_en_w = 4224,
1889 .scaler_dis_w = 8192,
1890 .in_rot_en_h = 1920,
1891 .in_rot_dis_w = 8192,
1892 .out_rot_en_w = 1920,
1893 .out_rot_dis_w = 4224,
1894 },
1895 [2] = {
1896 .scaler_en_w = 1920,
1897 .scaler_dis_w = 8192,
1898 .in_rot_en_h = 1280,
1899 .in_rot_dis_w = 8192,
1900 .out_rot_en_w = 1280,
1901 .out_rot_dis_w = 1920,
1902 },
1903 [3] = {
1904 .scaler_en_w = 1920,
1905 .scaler_dis_w = 8192,
1906 .in_rot_en_h = 1366,
1907 .in_rot_dis_w = 8192,
1908 .out_rot_en_w = 1366,
1909 .out_rot_dis_w = 1920,
1910 },
1911 };
1912
1913 static struct samsung_fimc_variant fimc0_variant_s5p = {
1914 .has_inp_rot = 1,
1915 .has_out_rot = 1,
1916 .min_inp_pixsize = 16,
1917 .min_out_pixsize = 16,
1918 .hor_offs_align = 8,
1919 .out_buf_count = 4,
1920 .pix_limit = &s5p_pix_limit[0],
1921 };
1922
1923 static struct samsung_fimc_variant fimc2_variant_s5p = {
1924 .min_inp_pixsize = 16,
1925 .min_out_pixsize = 16,
1926 .hor_offs_align = 8,
1927 .out_buf_count = 4,
1928 .pix_limit = &s5p_pix_limit[1],
1929 };
1930
1931 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1932 .pix_hoff = 1,
1933 .has_inp_rot = 1,
1934 .has_out_rot = 1,
1935 .min_inp_pixsize = 16,
1936 .min_out_pixsize = 16,
1937 .hor_offs_align = 8,
1938 .out_buf_count = 4,
1939 .pix_limit = &s5p_pix_limit[1],
1940 };
1941
1942 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1943 .pix_hoff = 1,
1944 .has_inp_rot = 1,
1945 .has_out_rot = 1,
1946 .has_mainscaler_ext = 1,
1947 .min_inp_pixsize = 16,
1948 .min_out_pixsize = 16,
1949 .hor_offs_align = 1,
1950 .out_buf_count = 4,
1951 .pix_limit = &s5p_pix_limit[2],
1952 };
1953
1954 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1955 .pix_hoff = 1,
1956 .min_inp_pixsize = 16,
1957 .min_out_pixsize = 16,
1958 .hor_offs_align = 8,
1959 .out_buf_count = 4,
1960 .pix_limit = &s5p_pix_limit[2],
1961 };
1962
1963 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1964 .pix_hoff = 1,
1965 .has_inp_rot = 1,
1966 .has_out_rot = 1,
1967 .has_cistatus2 = 1,
1968 .has_mainscaler_ext = 1,
1969 .min_inp_pixsize = 16,
1970 .min_out_pixsize = 16,
1971 .hor_offs_align = 1,
1972 .out_buf_count = 32,
1973 .pix_limit = &s5p_pix_limit[1],
1974 };
1975
1976 static struct samsung_fimc_variant fimc2_variant_exynos4 = {
1977 .pix_hoff = 1,
1978 .has_cistatus2 = 1,
1979 .has_mainscaler_ext = 1,
1980 .min_inp_pixsize = 16,
1981 .min_out_pixsize = 16,
1982 .hor_offs_align = 1,
1983 .out_buf_count = 32,
1984 .pix_limit = &s5p_pix_limit[3],
1985 };
1986
1987 /* S5PC100 */
1988 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1989 .variant = {
1990 [0] = &fimc0_variant_s5p,
1991 [1] = &fimc0_variant_s5p,
1992 [2] = &fimc2_variant_s5p,
1993 },
1994 .num_entities = 3,
1995 .lclk_frequency = 133000000UL,
1996 };
1997
1998 /* S5PV210, S5PC110 */
1999 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
2000 .variant = {
2001 [0] = &fimc0_variant_s5pv210,
2002 [1] = &fimc1_variant_s5pv210,
2003 [2] = &fimc2_variant_s5pv210,
2004 },
2005 .num_entities = 3,
2006 .lclk_frequency = 166000000UL,
2007 };
2008
2009 /* S5PV310, S5PC210 */
2010 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
2011 .variant = {
2012 [0] = &fimc0_variant_exynos4,
2013 [1] = &fimc0_variant_exynos4,
2014 [2] = &fimc0_variant_exynos4,
2015 [3] = &fimc2_variant_exynos4,
2016 },
2017 .num_entities = 4,
2018 .lclk_frequency = 166000000UL,
2019 };
2020
2021 static struct platform_device_id fimc_driver_ids[] = {
2022 {
2023 .name = "s5p-fimc",
2024 .driver_data = (unsigned long)&fimc_drvdata_s5p,
2025 }, {
2026 .name = "s5pv210-fimc",
2027 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
2028 }, {
2029 .name = "exynos4-fimc",
2030 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
2031 },
2032 {},
2033 };
2034 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
2035
2036 static const struct dev_pm_ops fimc_pm_ops = {
2037 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
2038 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
2039 };
2040
2041 static struct platform_driver fimc_driver = {
2042 .probe = fimc_probe,
2043 .remove = __devexit_p(fimc_remove),
2044 .id_table = fimc_driver_ids,
2045 .driver = {
2046 .name = MODULE_NAME,
2047 .owner = THIS_MODULE,
2048 .pm = &fimc_pm_ops,
2049 }
2050 };
2051
2052 static int __init fimc_init(void)
2053 {
2054 int ret = platform_driver_register(&fimc_driver);
2055 if (ret)
2056 err("platform_driver_register failed: %d\n", ret);
2057 return ret;
2058 }
2059
2060 static void __exit fimc_exit(void)
2061 {
2062 platform_driver_unregister(&fimc_driver);
2063 }
2064
2065 module_init(fimc_init);
2066 module_exit(fimc_exit);
2067
2068 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
2069 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
2070 MODULE_LICENSE("GPL");
2071 MODULE_VERSION("1.0.1");
Linux kernel - Deliverables
This page took 0.095023 seconds and 5 git commands to generate.