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Merge branch 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux...
[deliverable/linux.git] / drivers / media / video / s5p-fimc / fimc-core.c
1 /*
2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
3 *
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/version.h>
16 #include <linux/types.h>
17 #include <linux/errno.h>
18 #include <linux/bug.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/list.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29
30 #include "fimc-core.h"
31
32 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
33 "sclk_fimc", "fimc", "sclk_cam"
34 };
35
36 static struct fimc_fmt fimc_formats[] = {
37 {
38 .name = "RGB565",
39 .fourcc = V4L2_PIX_FMT_RGB565X,
40 .depth = { 16 },
41 .color = S5P_FIMC_RGB565,
42 .memplanes = 1,
43 .colplanes = 1,
44 .flags = FMT_FLAGS_M2M,
45 }, {
46 .name = "BGR666",
47 .fourcc = V4L2_PIX_FMT_BGR666,
48 .depth = { 32 },
49 .color = S5P_FIMC_RGB666,
50 .memplanes = 1,
51 .colplanes = 1,
52 .flags = FMT_FLAGS_M2M,
53 }, {
54 .name = "XRGB-8-8-8-8, 32 bpp",
55 .fourcc = V4L2_PIX_FMT_RGB32,
56 .depth = { 32 },
57 .color = S5P_FIMC_RGB888,
58 .memplanes = 1,
59 .colplanes = 1,
60 .flags = FMT_FLAGS_M2M,
61 }, {
62 .name = "YUV 4:2:2 packed, YCbYCr",
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .depth = { 16 },
65 .color = S5P_FIMC_YCBYCR422,
66 .memplanes = 1,
67 .colplanes = 1,
68 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
69 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
70 }, {
71 .name = "YUV 4:2:2 packed, CbYCrY",
72 .fourcc = V4L2_PIX_FMT_UYVY,
73 .depth = { 16 },
74 .color = S5P_FIMC_CBYCRY422,
75 .memplanes = 1,
76 .colplanes = 1,
77 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
78 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
79 }, {
80 .name = "YUV 4:2:2 packed, CrYCbY",
81 .fourcc = V4L2_PIX_FMT_VYUY,
82 .depth = { 16 },
83 .color = S5P_FIMC_CRYCBY422,
84 .memplanes = 1,
85 .colplanes = 1,
86 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
87 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
88 }, {
89 .name = "YUV 4:2:2 packed, YCrYCb",
90 .fourcc = V4L2_PIX_FMT_YVYU,
91 .depth = { 16 },
92 .color = S5P_FIMC_YCRYCB422,
93 .memplanes = 1,
94 .colplanes = 1,
95 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
96 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
97 }, {
98 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
99 .fourcc = V4L2_PIX_FMT_YUV422P,
100 .depth = { 12 },
101 .color = S5P_FIMC_YCBYCR422,
102 .memplanes = 1,
103 .colplanes = 3,
104 .flags = FMT_FLAGS_M2M,
105 }, {
106 .name = "YUV 4:2:2 planar, Y/CbCr",
107 .fourcc = V4L2_PIX_FMT_NV16,
108 .depth = { 16 },
109 .color = S5P_FIMC_YCBYCR422,
110 .memplanes = 1,
111 .colplanes = 2,
112 .flags = FMT_FLAGS_M2M,
113 }, {
114 .name = "YUV 4:2:2 planar, Y/CrCb",
115 .fourcc = V4L2_PIX_FMT_NV61,
116 .depth = { 16 },
117 .color = S5P_FIMC_YCRYCB422,
118 .memplanes = 1,
119 .colplanes = 2,
120 .flags = FMT_FLAGS_M2M,
121 }, {
122 .name = "YUV 4:2:0 planar, YCbCr",
123 .fourcc = V4L2_PIX_FMT_YUV420,
124 .depth = { 12 },
125 .color = S5P_FIMC_YCBCR420,
126 .memplanes = 1,
127 .colplanes = 3,
128 .flags = FMT_FLAGS_M2M,
129 }, {
130 .name = "YUV 4:2:0 planar, Y/CbCr",
131 .fourcc = V4L2_PIX_FMT_NV12,
132 .depth = { 12 },
133 .color = S5P_FIMC_YCBCR420,
134 .memplanes = 1,
135 .colplanes = 2,
136 .flags = FMT_FLAGS_M2M,
137 }, {
138 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
139 .fourcc = V4L2_PIX_FMT_NV12M,
140 .color = S5P_FIMC_YCBCR420,
141 .depth = { 8, 4 },
142 .memplanes = 2,
143 .colplanes = 2,
144 .flags = FMT_FLAGS_M2M,
145 }, {
146 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
147 .fourcc = V4L2_PIX_FMT_YUV420M,
148 .color = S5P_FIMC_YCBCR420,
149 .depth = { 8, 2, 2 },
150 .memplanes = 3,
151 .colplanes = 3,
152 .flags = FMT_FLAGS_M2M,
153 }, {
154 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
155 .fourcc = V4L2_PIX_FMT_NV12MT,
156 .color = S5P_FIMC_YCBCR420,
157 .depth = { 8, 4 },
158 .memplanes = 2,
159 .colplanes = 2,
160 .flags = FMT_FLAGS_M2M,
161 },
162 };
163
164 static struct v4l2_queryctrl fimc_ctrls[] = {
165 {
166 .id = V4L2_CID_HFLIP,
167 .type = V4L2_CTRL_TYPE_BOOLEAN,
168 .name = "Horizontal flip",
169 .minimum = 0,
170 .maximum = 1,
171 .default_value = 0,
172 }, {
173 .id = V4L2_CID_VFLIP,
174 .type = V4L2_CTRL_TYPE_BOOLEAN,
175 .name = "Vertical flip",
176 .minimum = 0,
177 .maximum = 1,
178 .default_value = 0,
179 }, {
180 .id = V4L2_CID_ROTATE,
181 .type = V4L2_CTRL_TYPE_INTEGER,
182 .name = "Rotation (CCW)",
183 .minimum = 0,
184 .maximum = 270,
185 .step = 90,
186 .default_value = 0,
187 },
188 };
189
190
191 static struct v4l2_queryctrl *get_ctrl(int id)
192 {
193 int i;
194
195 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
196 if (id == fimc_ctrls[i].id)
197 return &fimc_ctrls[i];
198 return NULL;
199 }
200
201 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
202 {
203 int tx, ty;
204
205 if (rot == 90 || rot == 270) {
206 ty = dw;
207 tx = dh;
208 } else {
209 tx = dw;
210 ty = dh;
211 }
212
213 if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
214 return -EINVAL;
215
216 return 0;
217 }
218
219 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
220 {
221 u32 sh = 6;
222
223 if (src >= 64 * tar)
224 return -EINVAL;
225
226 while (sh--) {
227 u32 tmp = 1 << sh;
228 if (src >= tar * tmp) {
229 *shift = sh, *ratio = tmp;
230 return 0;
231 }
232 }
233 *shift = 0, *ratio = 1;
234 return 0;
235 }
236
237 int fimc_set_scaler_info(struct fimc_ctx *ctx)
238 {
239 struct fimc_scaler *sc = &ctx->scaler;
240 struct fimc_frame *s_frame = &ctx->s_frame;
241 struct fimc_frame *d_frame = &ctx->d_frame;
242 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
243 int tx, ty, sx, sy;
244 int ret;
245
246 if (ctx->rotation == 90 || ctx->rotation == 270) {
247 ty = d_frame->width;
248 tx = d_frame->height;
249 } else {
250 tx = d_frame->width;
251 ty = d_frame->height;
252 }
253 if (tx <= 0 || ty <= 0) {
254 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
255 "invalid target size: %d x %d", tx, ty);
256 return -EINVAL;
257 }
258
259 sx = s_frame->width;
260 sy = s_frame->height;
261 if (sx <= 0 || sy <= 0) {
262 err("invalid source size: %d x %d", sx, sy);
263 return -EINVAL;
264 }
265 sc->real_width = sx;
266 sc->real_height = sy;
267
268 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
269 if (ret)
270 return ret;
271
272 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
273 if (ret)
274 return ret;
275
276 sc->pre_dst_width = sx / sc->pre_hratio;
277 sc->pre_dst_height = sy / sc->pre_vratio;
278
279 if (variant->has_mainscaler_ext) {
280 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
281 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
282 } else {
283 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
284 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
285
286 }
287
288 sc->scaleup_h = (tx >= sx) ? 1 : 0;
289 sc->scaleup_v = (ty >= sy) ? 1 : 0;
290
291 /* check to see if input and output size/format differ */
292 if (s_frame->fmt->color == d_frame->fmt->color
293 && s_frame->width == d_frame->width
294 && s_frame->height == d_frame->height)
295 sc->copy_mode = 1;
296 else
297 sc->copy_mode = 0;
298
299 return 0;
300 }
301
302 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
303 {
304 struct vb2_buffer *src_vb, *dst_vb;
305 struct fimc_dev *fimc = ctx->fimc_dev;
306
307 if (!ctx || !ctx->m2m_ctx)
308 return;
309
310 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
311 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
312
313 if (src_vb && dst_vb) {
314 v4l2_m2m_buf_done(src_vb, vb_state);
315 v4l2_m2m_buf_done(dst_vb, vb_state);
316 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
317 }
318 }
319
320 /* Complete the transaction which has been scheduled for execution. */
321 static void fimc_m2m_shutdown(struct fimc_ctx *ctx)
322 {
323 struct fimc_dev *fimc = ctx->fimc_dev;
324 int ret;
325
326 if (!fimc_m2m_pending(fimc))
327 return;
328
329 fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
330
331 ret = wait_event_timeout(fimc->irq_queue,
332 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
333 FIMC_SHUTDOWN_TIMEOUT);
334 /*
335 * In case of a timeout the buffers are not released in the interrupt
336 * handler so return them here with the error flag set, if there are
337 * any on the queue.
338 */
339 if (ret == 0)
340 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
341 }
342
343 static int stop_streaming(struct vb2_queue *q)
344 {
345 struct fimc_ctx *ctx = q->drv_priv;
346
347 fimc_m2m_shutdown(ctx);
348
349 return 0;
350 }
351
352 static void fimc_capture_irq_handler(struct fimc_dev *fimc)
353 {
354 struct fimc_vid_cap *cap = &fimc->vid_cap;
355 struct fimc_vid_buffer *v_buf;
356 struct timeval *tv;
357 struct timespec ts;
358
359 if (!list_empty(&cap->active_buf_q) &&
360 test_bit(ST_CAPT_RUN, &fimc->state)) {
361 ktime_get_real_ts(&ts);
362
363 v_buf = active_queue_pop(cap);
364
365 tv = &v_buf->vb.v4l2_buf.timestamp;
366 tv->tv_sec = ts.tv_sec;
367 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
368 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
369
370 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
371 }
372
373 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
374 wake_up(&fimc->irq_queue);
375 return;
376 }
377
378 if (!list_empty(&cap->pending_buf_q)) {
379
380 v_buf = pending_queue_pop(cap);
381 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
382 v_buf->index = cap->buf_index;
383
384 /* Move the buffer to the capture active queue */
385 active_queue_add(cap, v_buf);
386
387 dbg("next frame: %d, done frame: %d",
388 fimc_hw_get_frame_index(fimc), v_buf->index);
389
390 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
391 cap->buf_index = 0;
392 }
393
394 if (cap->active_buf_cnt == 0) {
395 clear_bit(ST_CAPT_RUN, &fimc->state);
396
397 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
398 cap->buf_index = 0;
399 } else {
400 set_bit(ST_CAPT_RUN, &fimc->state);
401 }
402
403 dbg("frame: %d, active_buf_cnt: %d",
404 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
405 }
406
407 static irqreturn_t fimc_isr(int irq, void *priv)
408 {
409 struct fimc_dev *fimc = priv;
410 struct fimc_vid_cap *cap = &fimc->vid_cap;
411 struct fimc_ctx *ctx;
412
413 fimc_hw_clear_irq(fimc);
414
415 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
416 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
417 if (ctx != NULL) {
418 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
419
420 spin_lock(&ctx->slock);
421 if (ctx->state & FIMC_CTX_SHUT) {
422 ctx->state &= ~FIMC_CTX_SHUT;
423 wake_up(&fimc->irq_queue);
424 }
425 spin_unlock(&ctx->slock);
426 }
427
428 return IRQ_HANDLED;
429 }
430
431 spin_lock(&fimc->slock);
432
433 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
434 fimc_capture_irq_handler(fimc);
435
436 if (cap->active_buf_cnt == 1) {
437 fimc_deactivate_capture(fimc);
438 clear_bit(ST_CAPT_STREAM, &fimc->state);
439 }
440 }
441
442 spin_unlock(&fimc->slock);
443 return IRQ_HANDLED;
444 }
445
446 /* The color format (colplanes, memplanes) must be already configured. */
447 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
448 struct fimc_frame *frame, struct fimc_addr *paddr)
449 {
450 int ret = 0;
451 u32 pix_size;
452
453 if (vb == NULL || frame == NULL)
454 return -EINVAL;
455
456 pix_size = frame->width * frame->height;
457
458 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
459 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
460
461 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
462
463 if (frame->fmt->memplanes == 1) {
464 switch (frame->fmt->colplanes) {
465 case 1:
466 paddr->cb = 0;
467 paddr->cr = 0;
468 break;
469 case 2:
470 /* decompose Y into Y/Cb */
471 paddr->cb = (u32)(paddr->y + pix_size);
472 paddr->cr = 0;
473 break;
474 case 3:
475 paddr->cb = (u32)(paddr->y + pix_size);
476 /* decompose Y into Y/Cb/Cr */
477 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
478 paddr->cr = (u32)(paddr->cb
479 + (pix_size >> 2));
480 else /* 422 */
481 paddr->cr = (u32)(paddr->cb
482 + (pix_size >> 1));
483 break;
484 default:
485 return -EINVAL;
486 }
487 } else {
488 if (frame->fmt->memplanes >= 2)
489 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
490
491 if (frame->fmt->memplanes == 3)
492 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
493 }
494
495 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
496 paddr->y, paddr->cb, paddr->cr, ret);
497
498 return ret;
499 }
500
501 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
502 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
503 {
504 /* The one only mode supported in SoC. */
505 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
506 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
507
508 /* Set order for 1 plane input formats. */
509 switch (ctx->s_frame.fmt->color) {
510 case S5P_FIMC_YCRYCB422:
511 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
512 break;
513 case S5P_FIMC_CBYCRY422:
514 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
515 break;
516 case S5P_FIMC_CRYCBY422:
517 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
518 break;
519 case S5P_FIMC_YCBYCR422:
520 default:
521 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
522 break;
523 }
524 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
525
526 switch (ctx->d_frame.fmt->color) {
527 case S5P_FIMC_YCRYCB422:
528 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
529 break;
530 case S5P_FIMC_CBYCRY422:
531 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
532 break;
533 case S5P_FIMC_CRYCBY422:
534 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
535 break;
536 case S5P_FIMC_YCBYCR422:
537 default:
538 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
539 break;
540 }
541 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
542 }
543
544 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
545 {
546 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
547 u32 i, depth = 0;
548
549 for (i = 0; i < f->fmt->colplanes; i++)
550 depth += f->fmt->depth[i];
551
552 f->dma_offset.y_h = f->offs_h;
553 if (!variant->pix_hoff)
554 f->dma_offset.y_h *= (depth >> 3);
555
556 f->dma_offset.y_v = f->offs_v;
557
558 f->dma_offset.cb_h = f->offs_h;
559 f->dma_offset.cb_v = f->offs_v;
560
561 f->dma_offset.cr_h = f->offs_h;
562 f->dma_offset.cr_v = f->offs_v;
563
564 if (!variant->pix_hoff) {
565 if (f->fmt->colplanes == 3) {
566 f->dma_offset.cb_h >>= 1;
567 f->dma_offset.cr_h >>= 1;
568 }
569 if (f->fmt->color == S5P_FIMC_YCBCR420) {
570 f->dma_offset.cb_v >>= 1;
571 f->dma_offset.cr_v >>= 1;
572 }
573 }
574
575 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
576 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
577 }
578
579 /**
580 * fimc_prepare_config - check dimensions, operation and color mode
581 * and pre-calculate offset and the scaling coefficients.
582 *
583 * @ctx: hardware context information
584 * @flags: flags indicating which parameters to check/update
585 *
586 * Return: 0 if dimensions are valid or non zero otherwise.
587 */
588 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
589 {
590 struct fimc_frame *s_frame, *d_frame;
591 struct vb2_buffer *vb = NULL;
592 int ret = 0;
593
594 s_frame = &ctx->s_frame;
595 d_frame = &ctx->d_frame;
596
597 if (flags & FIMC_PARAMS) {
598 /* Prepare the DMA offset ratios for scaler. */
599 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
600 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
601
602 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
603 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
604 err("out of scaler range");
605 return -EINVAL;
606 }
607 fimc_set_yuv_order(ctx);
608 }
609
610 /* Input DMA mode is not allowed when the scaler is disabled. */
611 ctx->scaler.enabled = 1;
612
613 if (flags & FIMC_SRC_ADDR) {
614 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
615 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
616 if (ret)
617 return ret;
618 }
619
620 if (flags & FIMC_DST_ADDR) {
621 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
622 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
623 }
624
625 return ret;
626 }
627
628 static void fimc_dma_run(void *priv)
629 {
630 struct fimc_ctx *ctx = priv;
631 struct fimc_dev *fimc;
632 unsigned long flags;
633 u32 ret;
634
635 if (WARN(!ctx, "null hardware context\n"))
636 return;
637
638 fimc = ctx->fimc_dev;
639
640 spin_lock_irqsave(&ctx->slock, flags);
641 set_bit(ST_M2M_PEND, &fimc->state);
642
643 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
644 ret = fimc_prepare_config(ctx, ctx->state);
645 if (ret)
646 goto dma_unlock;
647
648 /* Reconfigure hardware if the context has changed. */
649 if (fimc->m2m.ctx != ctx) {
650 ctx->state |= FIMC_PARAMS;
651 fimc->m2m.ctx = ctx;
652 }
653
654 spin_lock(&fimc->slock);
655 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
656
657 if (ctx->state & FIMC_PARAMS) {
658 fimc_hw_set_input_path(ctx);
659 fimc_hw_set_in_dma(ctx);
660 ret = fimc_set_scaler_info(ctx);
661 if (ret) {
662 spin_unlock(&fimc->slock);
663 goto dma_unlock;
664 }
665 fimc_hw_set_prescaler(ctx);
666 fimc_hw_set_mainscaler(ctx);
667 fimc_hw_set_target_format(ctx);
668 fimc_hw_set_rotation(ctx);
669 fimc_hw_set_effect(ctx);
670 }
671
672 fimc_hw_set_output_path(ctx);
673 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
674 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
675
676 if (ctx->state & FIMC_PARAMS)
677 fimc_hw_set_out_dma(ctx);
678
679 fimc_activate_capture(ctx);
680
681 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
682 FIMC_SRC_FMT | FIMC_DST_FMT);
683 fimc_hw_activate_input_dma(fimc, true);
684 spin_unlock(&fimc->slock);
685
686 dma_unlock:
687 spin_unlock_irqrestore(&ctx->slock, flags);
688 }
689
690 static void fimc_job_abort(void *priv)
691 {
692 fimc_m2m_shutdown(priv);
693 }
694
695 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
696 unsigned int *num_planes, unsigned long sizes[],
697 void *allocators[])
698 {
699 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
700 struct fimc_frame *f;
701 int i;
702
703 f = ctx_get_frame(ctx, vq->type);
704 if (IS_ERR(f))
705 return PTR_ERR(f);
706 /*
707 * Return number of non-contigous planes (plane buffers)
708 * depending on the configured color format.
709 */
710 if (!f->fmt)
711 return -EINVAL;
712
713 *num_planes = f->fmt->memplanes;
714 for (i = 0; i < f->fmt->memplanes; i++) {
715 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
716 allocators[i] = ctx->fimc_dev->alloc_ctx;
717 }
718 return 0;
719 }
720
721 static int fimc_buf_prepare(struct vb2_buffer *vb)
722 {
723 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
724 struct fimc_frame *frame;
725 int i;
726
727 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
728 if (IS_ERR(frame))
729 return PTR_ERR(frame);
730
731 for (i = 0; i < frame->fmt->memplanes; i++)
732 vb2_set_plane_payload(vb, i, frame->payload[i]);
733
734 return 0;
735 }
736
737 static void fimc_buf_queue(struct vb2_buffer *vb)
738 {
739 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
740
741 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
742
743 if (ctx->m2m_ctx)
744 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
745 }
746
747 static void fimc_lock(struct vb2_queue *vq)
748 {
749 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
750 mutex_lock(&ctx->fimc_dev->lock);
751 }
752
753 static void fimc_unlock(struct vb2_queue *vq)
754 {
755 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
756 mutex_unlock(&ctx->fimc_dev->lock);
757 }
758
759 static struct vb2_ops fimc_qops = {
760 .queue_setup = fimc_queue_setup,
761 .buf_prepare = fimc_buf_prepare,
762 .buf_queue = fimc_buf_queue,
763 .wait_prepare = fimc_unlock,
764 .wait_finish = fimc_lock,
765 .stop_streaming = stop_streaming,
766 };
767
768 static int fimc_m2m_querycap(struct file *file, void *priv,
769 struct v4l2_capability *cap)
770 {
771 struct fimc_ctx *ctx = file->private_data;
772 struct fimc_dev *fimc = ctx->fimc_dev;
773
774 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
775 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
776 cap->bus_info[0] = 0;
777 cap->version = KERNEL_VERSION(1, 0, 0);
778 cap->capabilities = V4L2_CAP_STREAMING |
779 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
780 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
781
782 return 0;
783 }
784
785 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
786 struct v4l2_fmtdesc *f)
787 {
788 struct fimc_fmt *fmt;
789
790 if (f->index >= ARRAY_SIZE(fimc_formats))
791 return -EINVAL;
792
793 fmt = &fimc_formats[f->index];
794 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
795 f->pixelformat = fmt->fourcc;
796
797 return 0;
798 }
799
800 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
801 struct v4l2_format *f)
802 {
803 struct fimc_ctx *ctx = priv;
804 struct fimc_frame *frame;
805 struct v4l2_pix_format_mplane *pixm;
806 int i;
807
808 frame = ctx_get_frame(ctx, f->type);
809 if (IS_ERR(frame))
810 return PTR_ERR(frame);
811
812 pixm = &f->fmt.pix_mp;
813
814 pixm->width = frame->width;
815 pixm->height = frame->height;
816 pixm->field = V4L2_FIELD_NONE;
817 pixm->pixelformat = frame->fmt->fourcc;
818 pixm->colorspace = V4L2_COLORSPACE_JPEG;
819 pixm->num_planes = frame->fmt->memplanes;
820
821 for (i = 0; i < pixm->num_planes; ++i) {
822 int bpl = frame->o_width;
823
824 if (frame->fmt->colplanes == 1) /* packed formats */
825 bpl = (bpl * frame->fmt->depth[0]) / 8;
826
827 pixm->plane_fmt[i].bytesperline = bpl;
828
829 pixm->plane_fmt[i].sizeimage = (frame->o_width *
830 frame->o_height * frame->fmt->depth[i]) / 8;
831 }
832
833 return 0;
834 }
835
836 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
837 {
838 struct fimc_fmt *fmt;
839 unsigned int i;
840
841 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
842 fmt = &fimc_formats[i];
843 if (fmt->fourcc == f->fmt.pix_mp.pixelformat &&
844 (fmt->flags & mask))
845 break;
846 }
847
848 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
849 }
850
851 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
852 unsigned int mask)
853 {
854 struct fimc_fmt *fmt;
855 unsigned int i;
856
857 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
858 fmt = &fimc_formats[i];
859 if (fmt->mbus_code == f->code && (fmt->flags & mask))
860 break;
861 }
862
863 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
864 }
865
866
867 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
868 struct v4l2_format *f)
869 {
870 struct fimc_ctx *ctx = priv;
871 struct fimc_dev *fimc = ctx->fimc_dev;
872 struct samsung_fimc_variant *variant = fimc->variant;
873 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
874 struct fimc_fmt *fmt;
875 u32 max_width, mod_x, mod_y, mask;
876 int i, is_output = 0;
877
878
879 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
880 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
881 return -EINVAL;
882 is_output = 1;
883 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
884 return -EINVAL;
885 }
886
887 dbg("w: %d, h: %d", pix->width, pix->height);
888
889 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
890 fmt = find_format(f, mask);
891 if (!fmt) {
892 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
893 pix->pixelformat);
894 return -EINVAL;
895 }
896
897 if (pix->field == V4L2_FIELD_ANY)
898 pix->field = V4L2_FIELD_NONE;
899 else if (V4L2_FIELD_NONE != pix->field)
900 return -EINVAL;
901
902 if (is_output) {
903 max_width = variant->pix_limit->scaler_dis_w;
904 mod_x = ffs(variant->min_inp_pixsize) - 1;
905 } else {
906 max_width = variant->pix_limit->out_rot_dis_w;
907 mod_x = ffs(variant->min_out_pixsize) - 1;
908 }
909
910 if (tiled_fmt(fmt)) {
911 mod_x = 6; /* 64 x 32 pixels tile */
912 mod_y = 5;
913 } else {
914 if (fimc->id == 1 && variant->pix_hoff)
915 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
916 else
917 mod_y = mod_x;
918 }
919
920 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
921
922 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
923 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
924
925 pix->num_planes = fmt->memplanes;
926 pix->colorspace = V4L2_COLORSPACE_JPEG;
927
928
929 for (i = 0; i < pix->num_planes; ++i) {
930 u32 bpl = pix->plane_fmt[i].bytesperline;
931 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
932
933 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
934 bpl = pix->width; /* Planar */
935
936 if (fmt->colplanes == 1 && /* Packed */
937 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
938 bpl = (pix->width * fmt->depth[0]) / 8;
939
940 if (i == 0) /* Same bytesperline for each plane. */
941 mod_x = bpl;
942
943 pix->plane_fmt[i].bytesperline = mod_x;
944 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
945 }
946
947 return 0;
948 }
949
950 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
951 struct v4l2_format *f)
952 {
953 struct fimc_ctx *ctx = priv;
954 struct fimc_dev *fimc = ctx->fimc_dev;
955 struct vb2_queue *vq;
956 struct fimc_frame *frame;
957 struct v4l2_pix_format_mplane *pix;
958 int i, ret = 0;
959
960 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
961 if (ret)
962 return ret;
963
964 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
965
966 if (vb2_is_busy(vq)) {
967 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
968 return -EBUSY;
969 }
970
971 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
972 frame = &ctx->s_frame;
973 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
974 frame = &ctx->d_frame;
975 } else {
976 v4l2_err(&fimc->m2m.v4l2_dev,
977 "Wrong buffer/video queue type (%d)\n", f->type);
978 return -EINVAL;
979 }
980
981 pix = &f->fmt.pix_mp;
982 frame->fmt = find_format(f, FMT_FLAGS_M2M);
983 if (!frame->fmt)
984 return -EINVAL;
985
986 for (i = 0; i < frame->fmt->colplanes; i++) {
987 frame->payload[i] =
988 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
989 }
990
991 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
992 frame->fmt->depth[0];
993 frame->f_height = pix->height;
994 frame->width = pix->width;
995 frame->height = pix->height;
996 frame->o_width = pix->width;
997 frame->o_height = pix->height;
998 frame->offs_h = 0;
999 frame->offs_v = 0;
1000
1001 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1002 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1003 else
1004 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1005
1006 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1007
1008 return 0;
1009 }
1010
1011 static int fimc_m2m_reqbufs(struct file *file, void *priv,
1012 struct v4l2_requestbuffers *reqbufs)
1013 {
1014 struct fimc_ctx *ctx = priv;
1015 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1016 }
1017
1018 static int fimc_m2m_querybuf(struct file *file, void *priv,
1019 struct v4l2_buffer *buf)
1020 {
1021 struct fimc_ctx *ctx = priv;
1022 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1023 }
1024
1025 static int fimc_m2m_qbuf(struct file *file, void *priv,
1026 struct v4l2_buffer *buf)
1027 {
1028 struct fimc_ctx *ctx = priv;
1029
1030 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1031 }
1032
1033 static int fimc_m2m_dqbuf(struct file *file, void *priv,
1034 struct v4l2_buffer *buf)
1035 {
1036 struct fimc_ctx *ctx = priv;
1037 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1038 }
1039
1040 static int fimc_m2m_streamon(struct file *file, void *priv,
1041 enum v4l2_buf_type type)
1042 {
1043 struct fimc_ctx *ctx = priv;
1044
1045 /* The source and target color format need to be set */
1046 if (V4L2_TYPE_IS_OUTPUT(type)) {
1047 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1048 return -EINVAL;
1049 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1050 return -EINVAL;
1051 }
1052
1053 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1054 }
1055
1056 static int fimc_m2m_streamoff(struct file *file, void *priv,
1057 enum v4l2_buf_type type)
1058 {
1059 struct fimc_ctx *ctx = priv;
1060 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1061 }
1062
1063 int fimc_vidioc_queryctrl(struct file *file, void *priv,
1064 struct v4l2_queryctrl *qc)
1065 {
1066 struct fimc_ctx *ctx = priv;
1067 struct v4l2_queryctrl *c;
1068 int ret = -EINVAL;
1069
1070 c = get_ctrl(qc->id);
1071 if (c) {
1072 *qc = *c;
1073 return 0;
1074 }
1075
1076 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1077 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1078 core, queryctrl, qc);
1079 }
1080 return ret;
1081 }
1082
1083 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1084 struct v4l2_control *ctrl)
1085 {
1086 struct fimc_ctx *ctx = priv;
1087 struct fimc_dev *fimc = ctx->fimc_dev;
1088
1089 switch (ctrl->id) {
1090 case V4L2_CID_HFLIP:
1091 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1092 break;
1093 case V4L2_CID_VFLIP:
1094 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1095 break;
1096 case V4L2_CID_ROTATE:
1097 ctrl->value = ctx->rotation;
1098 break;
1099 default:
1100 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1101 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1102 g_ctrl, ctrl);
1103 } else {
1104 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1105 return -EINVAL;
1106 }
1107 }
1108 dbg("ctrl->value= %d", ctrl->value);
1109
1110 return 0;
1111 }
1112
1113 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1114 {
1115 struct v4l2_queryctrl *c;
1116 c = get_ctrl(ctrl->id);
1117 if (!c)
1118 return -EINVAL;
1119
1120 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1121 || (c->step != 0 && ctrl->value % c->step != 0)) {
1122 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1123 "Invalid control value\n");
1124 return -ERANGE;
1125 }
1126
1127 return 0;
1128 }
1129
1130 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1131 {
1132 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1133 struct fimc_dev *fimc = ctx->fimc_dev;
1134 int ret = 0;
1135
1136 switch (ctrl->id) {
1137 case V4L2_CID_HFLIP:
1138 if (ctrl->value)
1139 ctx->flip |= FLIP_X_AXIS;
1140 else
1141 ctx->flip &= ~FLIP_X_AXIS;
1142 break;
1143
1144 case V4L2_CID_VFLIP:
1145 if (ctrl->value)
1146 ctx->flip |= FLIP_Y_AXIS;
1147 else
1148 ctx->flip &= ~FLIP_Y_AXIS;
1149 break;
1150
1151 case V4L2_CID_ROTATE:
1152 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1153 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1154 ctx->s_frame.height, ctx->d_frame.width,
1155 ctx->d_frame.height, ctrl->value);
1156 }
1157
1158 if (ret) {
1159 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1160 return -EINVAL;
1161 }
1162
1163 /* Check for the output rotator availability */
1164 if ((ctrl->value == 90 || ctrl->value == 270) &&
1165 (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
1166 return -EINVAL;
1167 ctx->rotation = ctrl->value;
1168 break;
1169
1170 default:
1171 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1172 return -EINVAL;
1173 }
1174
1175 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1176
1177 return 0;
1178 }
1179
1180 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1181 struct v4l2_control *ctrl)
1182 {
1183 struct fimc_ctx *ctx = priv;
1184 int ret = 0;
1185
1186 ret = check_ctrl_val(ctx, ctrl);
1187 if (ret)
1188 return ret;
1189
1190 ret = fimc_s_ctrl(ctx, ctrl);
1191 return 0;
1192 }
1193
1194 static int fimc_m2m_cropcap(struct file *file, void *fh,
1195 struct v4l2_cropcap *cr)
1196 {
1197 struct fimc_frame *frame;
1198 struct fimc_ctx *ctx = fh;
1199
1200 frame = ctx_get_frame(ctx, cr->type);
1201 if (IS_ERR(frame))
1202 return PTR_ERR(frame);
1203
1204 cr->bounds.left = 0;
1205 cr->bounds.top = 0;
1206 cr->bounds.width = frame->f_width;
1207 cr->bounds.height = frame->f_height;
1208 cr->defrect = cr->bounds;
1209
1210 return 0;
1211 }
1212
1213 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1214 {
1215 struct fimc_frame *frame;
1216 struct fimc_ctx *ctx = file->private_data;
1217
1218 frame = ctx_get_frame(ctx, cr->type);
1219 if (IS_ERR(frame))
1220 return PTR_ERR(frame);
1221
1222 cr->c.left = frame->offs_h;
1223 cr->c.top = frame->offs_v;
1224 cr->c.width = frame->width;
1225 cr->c.height = frame->height;
1226
1227 return 0;
1228 }
1229
1230 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1231 {
1232 struct fimc_dev *fimc = ctx->fimc_dev;
1233 struct fimc_frame *f;
1234 u32 min_size, halign, depth = 0;
1235 bool is_capture_ctx;
1236 int i;
1237
1238 if (cr->c.top < 0 || cr->c.left < 0) {
1239 v4l2_err(&fimc->m2m.v4l2_dev,
1240 "doesn't support negative values for top & left\n");
1241 return -EINVAL;
1242 }
1243
1244 is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1245
1246 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1247 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1248 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1249 !is_capture_ctx)
1250 f = &ctx->s_frame;
1251 else
1252 return -EINVAL;
1253
1254 min_size = (f == &ctx->s_frame) ?
1255 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1256
1257 /* Get pixel alignment constraints. */
1258 if (is_capture_ctx) {
1259 min_size = 16;
1260 halign = 4;
1261 } else {
1262 if (fimc->id == 1 && fimc->variant->pix_hoff)
1263 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1264 else
1265 halign = ffs(min_size) - 1;
1266 }
1267
1268 for (i = 0; i < f->fmt->colplanes; i++)
1269 depth += f->fmt->depth[i];
1270
1271 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1272 ffs(min_size) - 1,
1273 &cr->c.height, min_size, f->o_height,
1274 halign, 64/(ALIGN(depth, 8)));
1275
1276 /* adjust left/top if cropping rectangle is out of bounds */
1277 if (cr->c.left + cr->c.width > f->o_width)
1278 cr->c.left = f->o_width - cr->c.width;
1279 if (cr->c.top + cr->c.height > f->o_height)
1280 cr->c.top = f->o_height - cr->c.height;
1281
1282 cr->c.left = round_down(cr->c.left, min_size);
1283 cr->c.top = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1284
1285 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1286 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1287 f->f_width, f->f_height);
1288
1289 return 0;
1290 }
1291
1292 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1293 {
1294 struct fimc_ctx *ctx = file->private_data;
1295 struct fimc_dev *fimc = ctx->fimc_dev;
1296 struct fimc_frame *f;
1297 int ret;
1298
1299 ret = fimc_try_crop(ctx, cr);
1300 if (ret)
1301 return ret;
1302
1303 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1304 &ctx->s_frame : &ctx->d_frame;
1305
1306 /* Check to see if scaling ratio is within supported range */
1307 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1308 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1309 ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1310 ctx->d_frame.width,
1311 ctx->d_frame.height,
1312 ctx->rotation);
1313 } else {
1314 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1315 ctx->s_frame.height,
1316 cr->c.width, cr->c.height,
1317 ctx->rotation);
1318 }
1319 if (ret) {
1320 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1321 return -EINVAL;
1322 }
1323 }
1324
1325 f->offs_h = cr->c.left;
1326 f->offs_v = cr->c.top;
1327 f->width = cr->c.width;
1328 f->height = cr->c.height;
1329
1330 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1331
1332 return 0;
1333 }
1334
1335 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1336 .vidioc_querycap = fimc_m2m_querycap,
1337
1338 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1339 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1340
1341 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1342 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1343
1344 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1345 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1346
1347 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1348 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1349
1350 .vidioc_reqbufs = fimc_m2m_reqbufs,
1351 .vidioc_querybuf = fimc_m2m_querybuf,
1352
1353 .vidioc_qbuf = fimc_m2m_qbuf,
1354 .vidioc_dqbuf = fimc_m2m_dqbuf,
1355
1356 .vidioc_streamon = fimc_m2m_streamon,
1357 .vidioc_streamoff = fimc_m2m_streamoff,
1358
1359 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1360 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1361 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1362
1363 .vidioc_g_crop = fimc_m2m_g_crop,
1364 .vidioc_s_crop = fimc_m2m_s_crop,
1365 .vidioc_cropcap = fimc_m2m_cropcap
1366
1367 };
1368
1369 static int queue_init(void *priv, struct vb2_queue *src_vq,
1370 struct vb2_queue *dst_vq)
1371 {
1372 struct fimc_ctx *ctx = priv;
1373 int ret;
1374
1375 memset(src_vq, 0, sizeof(*src_vq));
1376 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1377 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1378 src_vq->drv_priv = ctx;
1379 src_vq->ops = &fimc_qops;
1380 src_vq->mem_ops = &vb2_dma_contig_memops;
1381 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1382
1383 ret = vb2_queue_init(src_vq);
1384 if (ret)
1385 return ret;
1386
1387 memset(dst_vq, 0, sizeof(*dst_vq));
1388 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1389 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1390 dst_vq->drv_priv = ctx;
1391 dst_vq->ops = &fimc_qops;
1392 dst_vq->mem_ops = &vb2_dma_contig_memops;
1393 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1394
1395 return vb2_queue_init(dst_vq);
1396 }
1397
1398 static int fimc_m2m_open(struct file *file)
1399 {
1400 struct fimc_dev *fimc = video_drvdata(file);
1401 struct fimc_ctx *ctx = NULL;
1402
1403 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1404 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1405
1406 /*
1407 * Return if the corresponding video capture node
1408 * is already opened.
1409 */
1410 if (fimc->vid_cap.refcnt > 0)
1411 return -EBUSY;
1412
1413 fimc->m2m.refcnt++;
1414 set_bit(ST_OUTDMA_RUN, &fimc->state);
1415
1416 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1417 if (!ctx)
1418 return -ENOMEM;
1419
1420 file->private_data = ctx;
1421 ctx->fimc_dev = fimc;
1422 /* Default color format */
1423 ctx->s_frame.fmt = &fimc_formats[0];
1424 ctx->d_frame.fmt = &fimc_formats[0];
1425 /* Setup the device context for mem2mem mode. */
1426 ctx->state = FIMC_CTX_M2M;
1427 ctx->flags = 0;
1428 ctx->in_path = FIMC_DMA;
1429 ctx->out_path = FIMC_DMA;
1430 spin_lock_init(&ctx->slock);
1431
1432 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1433 if (IS_ERR(ctx->m2m_ctx)) {
1434 int err = PTR_ERR(ctx->m2m_ctx);
1435 kfree(ctx);
1436 return err;
1437 }
1438
1439 return 0;
1440 }
1441
1442 static int fimc_m2m_release(struct file *file)
1443 {
1444 struct fimc_ctx *ctx = file->private_data;
1445 struct fimc_dev *fimc = ctx->fimc_dev;
1446
1447 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1448 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1449
1450 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1451 kfree(ctx);
1452 if (--fimc->m2m.refcnt <= 0)
1453 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1454
1455 return 0;
1456 }
1457
1458 static unsigned int fimc_m2m_poll(struct file *file,
1459 struct poll_table_struct *wait)
1460 {
1461 struct fimc_ctx *ctx = file->private_data;
1462
1463 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1464 }
1465
1466
1467 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1468 {
1469 struct fimc_ctx *ctx = file->private_data;
1470
1471 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1472 }
1473
1474 static const struct v4l2_file_operations fimc_m2m_fops = {
1475 .owner = THIS_MODULE,
1476 .open = fimc_m2m_open,
1477 .release = fimc_m2m_release,
1478 .poll = fimc_m2m_poll,
1479 .unlocked_ioctl = video_ioctl2,
1480 .mmap = fimc_m2m_mmap,
1481 };
1482
1483 static struct v4l2_m2m_ops m2m_ops = {
1484 .device_run = fimc_dma_run,
1485 .job_abort = fimc_job_abort,
1486 };
1487
1488 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1489 {
1490 struct video_device *vfd;
1491 struct platform_device *pdev;
1492 struct v4l2_device *v4l2_dev;
1493 int ret = 0;
1494
1495 if (!fimc)
1496 return -ENODEV;
1497
1498 pdev = fimc->pdev;
1499 v4l2_dev = &fimc->m2m.v4l2_dev;
1500
1501 /* set name if it is empty */
1502 if (!v4l2_dev->name[0])
1503 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1504 "%s.m2m", dev_name(&pdev->dev));
1505
1506 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1507 if (ret)
1508 goto err_m2m_r1;
1509
1510 vfd = video_device_alloc();
1511 if (!vfd) {
1512 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1513 goto err_m2m_r1;
1514 }
1515
1516 vfd->fops = &fimc_m2m_fops;
1517 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1518 vfd->minor = -1;
1519 vfd->release = video_device_release;
1520 vfd->lock = &fimc->lock;
1521
1522 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1523
1524 video_set_drvdata(vfd, fimc);
1525 platform_set_drvdata(pdev, fimc);
1526
1527 fimc->m2m.vfd = vfd;
1528 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1529 if (IS_ERR(fimc->m2m.m2m_dev)) {
1530 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1531 ret = PTR_ERR(fimc->m2m.m2m_dev);
1532 goto err_m2m_r2;
1533 }
1534
1535 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1536 if (ret) {
1537 v4l2_err(v4l2_dev,
1538 "%s(): failed to register video device\n", __func__);
1539 goto err_m2m_r3;
1540 }
1541 v4l2_info(v4l2_dev,
1542 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1543
1544 return 0;
1545
1546 err_m2m_r3:
1547 v4l2_m2m_release(fimc->m2m.m2m_dev);
1548 err_m2m_r2:
1549 video_device_release(fimc->m2m.vfd);
1550 err_m2m_r1:
1551 v4l2_device_unregister(v4l2_dev);
1552
1553 return ret;
1554 }
1555
1556 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1557 {
1558 if (fimc) {
1559 v4l2_m2m_release(fimc->m2m.m2m_dev);
1560 video_unregister_device(fimc->m2m.vfd);
1561
1562 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1563 }
1564 }
1565
1566 static void fimc_clk_release(struct fimc_dev *fimc)
1567 {
1568 int i;
1569 for (i = 0; i < fimc->num_clocks; i++) {
1570 if (fimc->clock[i]) {
1571 clk_disable(fimc->clock[i]);
1572 clk_put(fimc->clock[i]);
1573 }
1574 }
1575 }
1576
1577 static int fimc_clk_get(struct fimc_dev *fimc)
1578 {
1579 int i;
1580 for (i = 0; i < fimc->num_clocks; i++) {
1581 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1582
1583 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1584 clk_enable(fimc->clock[i]);
1585 continue;
1586 }
1587 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1588 fimc_clocks[i]);
1589 return -ENXIO;
1590 }
1591 return 0;
1592 }
1593
1594 static int fimc_probe(struct platform_device *pdev)
1595 {
1596 struct fimc_dev *fimc;
1597 struct resource *res;
1598 struct samsung_fimc_driverdata *drv_data;
1599 struct s5p_platform_fimc *pdata;
1600 int ret = 0;
1601 int cap_input_index = -1;
1602
1603 dev_dbg(&pdev->dev, "%s():\n", __func__);
1604
1605 drv_data = (struct samsung_fimc_driverdata *)
1606 platform_get_device_id(pdev)->driver_data;
1607
1608 if (pdev->id >= drv_data->num_entities) {
1609 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1610 pdev->id);
1611 return -EINVAL;
1612 }
1613
1614 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1615 if (!fimc)
1616 return -ENOMEM;
1617
1618 fimc->id = pdev->id;
1619 fimc->variant = drv_data->variant[fimc->id];
1620 fimc->pdev = pdev;
1621 pdata = pdev->dev.platform_data;
1622 fimc->pdata = pdata;
1623 fimc->state = ST_IDLE;
1624
1625 init_waitqueue_head(&fimc->irq_queue);
1626 spin_lock_init(&fimc->slock);
1627
1628 mutex_init(&fimc->lock);
1629
1630 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1631 if (!res) {
1632 dev_err(&pdev->dev, "failed to find the registers\n");
1633 ret = -ENOENT;
1634 goto err_info;
1635 }
1636
1637 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1638 dev_name(&pdev->dev));
1639 if (!fimc->regs_res) {
1640 dev_err(&pdev->dev, "failed to obtain register region\n");
1641 ret = -ENOENT;
1642 goto err_info;
1643 }
1644
1645 fimc->regs = ioremap(res->start, resource_size(res));
1646 if (!fimc->regs) {
1647 dev_err(&pdev->dev, "failed to map registers\n");
1648 ret = -ENXIO;
1649 goto err_req_region;
1650 }
1651
1652 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1653
1654 /* Check if a video capture node needs to be registered. */
1655 if (pdata && pdata->num_clients > 0) {
1656 cap_input_index = 0;
1657 fimc->num_clocks++;
1658 }
1659
1660 ret = fimc_clk_get(fimc);
1661 if (ret)
1662 goto err_regs_unmap;
1663 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1664
1665 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1666 if (!res) {
1667 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1668 ret = -ENXIO;
1669 goto err_clk;
1670 }
1671 fimc->irq = res->start;
1672
1673 fimc_hw_reset(fimc);
1674
1675 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1676 if (ret) {
1677 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1678 goto err_clk;
1679 }
1680
1681 /* Initialize contiguous memory allocator */
1682 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1683 if (IS_ERR(fimc->alloc_ctx)) {
1684 ret = PTR_ERR(fimc->alloc_ctx);
1685 goto err_irq;
1686 }
1687
1688 ret = fimc_register_m2m_device(fimc);
1689 if (ret)
1690 goto err_irq;
1691
1692 /* At least one camera sensor is required to register capture node */
1693 if (cap_input_index >= 0) {
1694 ret = fimc_register_capture_device(fimc);
1695 if (ret)
1696 goto err_m2m;
1697 clk_disable(fimc->clock[CLK_CAM]);
1698 }
1699 /*
1700 * Exclude the additional output DMA address registers by masking
1701 * them out on HW revisions that provide extended capabilites.
1702 */
1703 if (fimc->variant->out_buf_count > 4)
1704 fimc_hw_set_dma_seq(fimc, 0xF);
1705
1706 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1707 __func__, fimc->id);
1708
1709 return 0;
1710
1711 err_m2m:
1712 fimc_unregister_m2m_device(fimc);
1713 err_irq:
1714 free_irq(fimc->irq, fimc);
1715 err_clk:
1716 fimc_clk_release(fimc);
1717 err_regs_unmap:
1718 iounmap(fimc->regs);
1719 err_req_region:
1720 release_resource(fimc->regs_res);
1721 kfree(fimc->regs_res);
1722 err_info:
1723 kfree(fimc);
1724
1725 return ret;
1726 }
1727
1728 static int __devexit fimc_remove(struct platform_device *pdev)
1729 {
1730 struct fimc_dev *fimc =
1731 (struct fimc_dev *)platform_get_drvdata(pdev);
1732
1733 free_irq(fimc->irq, fimc);
1734 fimc_hw_reset(fimc);
1735
1736 fimc_unregister_m2m_device(fimc);
1737 fimc_unregister_capture_device(fimc);
1738
1739 fimc_clk_release(fimc);
1740
1741 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1742
1743 iounmap(fimc->regs);
1744 release_resource(fimc->regs_res);
1745 kfree(fimc->regs_res);
1746 kfree(fimc);
1747
1748 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1749 return 0;
1750 }
1751
1752 /* Image pixel limits, similar across several FIMC HW revisions. */
1753 static struct fimc_pix_limit s5p_pix_limit[4] = {
1754 [0] = {
1755 .scaler_en_w = 3264,
1756 .scaler_dis_w = 8192,
1757 .in_rot_en_h = 1920,
1758 .in_rot_dis_w = 8192,
1759 .out_rot_en_w = 1920,
1760 .out_rot_dis_w = 4224,
1761 },
1762 [1] = {
1763 .scaler_en_w = 4224,
1764 .scaler_dis_w = 8192,
1765 .in_rot_en_h = 1920,
1766 .in_rot_dis_w = 8192,
1767 .out_rot_en_w = 1920,
1768 .out_rot_dis_w = 4224,
1769 },
1770 [2] = {
1771 .scaler_en_w = 1920,
1772 .scaler_dis_w = 8192,
1773 .in_rot_en_h = 1280,
1774 .in_rot_dis_w = 8192,
1775 .out_rot_en_w = 1280,
1776 .out_rot_dis_w = 1920,
1777 },
1778 [3] = {
1779 .scaler_en_w = 1920,
1780 .scaler_dis_w = 8192,
1781 .in_rot_en_h = 1366,
1782 .in_rot_dis_w = 8192,
1783 .out_rot_en_w = 1366,
1784 .out_rot_dis_w = 1920,
1785 },
1786 };
1787
1788 static struct samsung_fimc_variant fimc0_variant_s5p = {
1789 .has_inp_rot = 1,
1790 .has_out_rot = 1,
1791 .min_inp_pixsize = 16,
1792 .min_out_pixsize = 16,
1793 .hor_offs_align = 8,
1794 .out_buf_count = 4,
1795 .pix_limit = &s5p_pix_limit[0],
1796 };
1797
1798 static struct samsung_fimc_variant fimc2_variant_s5p = {
1799 .min_inp_pixsize = 16,
1800 .min_out_pixsize = 16,
1801 .hor_offs_align = 8,
1802 .out_buf_count = 4,
1803 .pix_limit = &s5p_pix_limit[1],
1804 };
1805
1806 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1807 .pix_hoff = 1,
1808 .has_inp_rot = 1,
1809 .has_out_rot = 1,
1810 .min_inp_pixsize = 16,
1811 .min_out_pixsize = 16,
1812 .hor_offs_align = 8,
1813 .out_buf_count = 4,
1814 .pix_limit = &s5p_pix_limit[1],
1815 };
1816
1817 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1818 .pix_hoff = 1,
1819 .has_inp_rot = 1,
1820 .has_out_rot = 1,
1821 .has_mainscaler_ext = 1,
1822 .min_inp_pixsize = 16,
1823 .min_out_pixsize = 16,
1824 .hor_offs_align = 1,
1825 .out_buf_count = 4,
1826 .pix_limit = &s5p_pix_limit[2],
1827 };
1828
1829 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1830 .pix_hoff = 1,
1831 .min_inp_pixsize = 16,
1832 .min_out_pixsize = 16,
1833 .hor_offs_align = 8,
1834 .out_buf_count = 4,
1835 .pix_limit = &s5p_pix_limit[2],
1836 };
1837
1838 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1839 .pix_hoff = 1,
1840 .has_inp_rot = 1,
1841 .has_out_rot = 1,
1842 .has_cistatus2 = 1,
1843 .has_mainscaler_ext = 1,
1844 .min_inp_pixsize = 16,
1845 .min_out_pixsize = 16,
1846 .hor_offs_align = 1,
1847 .out_buf_count = 32,
1848 .pix_limit = &s5p_pix_limit[1],
1849 };
1850
1851 static struct samsung_fimc_variant fimc2_variant_exynos4 = {
1852 .pix_hoff = 1,
1853 .has_cistatus2 = 1,
1854 .has_mainscaler_ext = 1,
1855 .min_inp_pixsize = 16,
1856 .min_out_pixsize = 16,
1857 .hor_offs_align = 1,
1858 .out_buf_count = 32,
1859 .pix_limit = &s5p_pix_limit[3],
1860 };
1861
1862 /* S5PC100 */
1863 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1864 .variant = {
1865 [0] = &fimc0_variant_s5p,
1866 [1] = &fimc0_variant_s5p,
1867 [2] = &fimc2_variant_s5p,
1868 },
1869 .num_entities = 3,
1870 .lclk_frequency = 133000000UL,
1871 };
1872
1873 /* S5PV210, S5PC110 */
1874 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1875 .variant = {
1876 [0] = &fimc0_variant_s5pv210,
1877 [1] = &fimc1_variant_s5pv210,
1878 [2] = &fimc2_variant_s5pv210,
1879 },
1880 .num_entities = 3,
1881 .lclk_frequency = 166000000UL,
1882 };
1883
1884 /* S5PV310, S5PC210 */
1885 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1886 .variant = {
1887 [0] = &fimc0_variant_exynos4,
1888 [1] = &fimc0_variant_exynos4,
1889 [2] = &fimc0_variant_exynos4,
1890 [3] = &fimc2_variant_exynos4,
1891 },
1892 .num_entities = 4,
1893 .lclk_frequency = 166000000UL,
1894 };
1895
1896 static struct platform_device_id fimc_driver_ids[] = {
1897 {
1898 .name = "s5p-fimc",
1899 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1900 }, {
1901 .name = "s5pv210-fimc",
1902 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1903 }, {
1904 .name = "exynos4-fimc",
1905 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
1906 },
1907 {},
1908 };
1909 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1910
1911 static struct platform_driver fimc_driver = {
1912 .probe = fimc_probe,
1913 .remove = __devexit_p(fimc_remove),
1914 .id_table = fimc_driver_ids,
1915 .driver = {
1916 .name = MODULE_NAME,
1917 .owner = THIS_MODULE,
1918 }
1919 };
1920
1921 static int __init fimc_init(void)
1922 {
1923 int ret = platform_driver_register(&fimc_driver);
1924 if (ret)
1925 err("platform_driver_register failed: %d\n", ret);
1926 return ret;
1927 }
1928
1929 static void __exit fimc_exit(void)
1930 {
1931 platform_driver_unregister(&fimc_driver);
1932 }
1933
1934 module_init(fimc_init);
1935 module_exit(fimc_exit);
1936
1937 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1938 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1939 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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