2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/version.h>
16 #include <linux/types.h>
17 #include <linux/errno.h>
18 #include <linux/bug.h>
19 #include <linux/interrupt.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/list.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
30 #include "fimc-core.h"
32 static char *fimc_clocks
[MAX_FIMC_CLOCKS
] = {
33 "sclk_fimc", "fimc", "sclk_cam"
36 static struct fimc_fmt fimc_formats
[] = {
39 .fourcc
= V4L2_PIX_FMT_RGB565X
,
41 .color
= S5P_FIMC_RGB565
,
44 .flags
= FMT_FLAGS_M2M
,
47 .fourcc
= V4L2_PIX_FMT_BGR666
,
49 .color
= S5P_FIMC_RGB666
,
52 .flags
= FMT_FLAGS_M2M
,
54 .name
= "XRGB-8-8-8-8, 32 bpp",
55 .fourcc
= V4L2_PIX_FMT_RGB32
,
57 .color
= S5P_FIMC_RGB888
,
60 .flags
= FMT_FLAGS_M2M
,
62 .name
= "YUV 4:2:2 packed, YCbYCr",
63 .fourcc
= V4L2_PIX_FMT_YUYV
,
65 .color
= S5P_FIMC_YCBYCR422
,
68 .mbus_code
= V4L2_MBUS_FMT_YUYV8_2X8
,
69 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
71 .name
= "YUV 4:2:2 packed, CbYCrY",
72 .fourcc
= V4L2_PIX_FMT_UYVY
,
74 .color
= S5P_FIMC_CBYCRY422
,
77 .mbus_code
= V4L2_MBUS_FMT_UYVY8_2X8
,
78 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
80 .name
= "YUV 4:2:2 packed, CrYCbY",
81 .fourcc
= V4L2_PIX_FMT_VYUY
,
83 .color
= S5P_FIMC_CRYCBY422
,
86 .mbus_code
= V4L2_MBUS_FMT_VYUY8_2X8
,
87 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
89 .name
= "YUV 4:2:2 packed, YCrYCb",
90 .fourcc
= V4L2_PIX_FMT_YVYU
,
92 .color
= S5P_FIMC_YCRYCB422
,
95 .mbus_code
= V4L2_MBUS_FMT_YVYU8_2X8
,
96 .flags
= FMT_FLAGS_M2M
| FMT_FLAGS_CAM
,
98 .name
= "YUV 4:2:2 planar, Y/Cb/Cr",
99 .fourcc
= V4L2_PIX_FMT_YUV422P
,
101 .color
= S5P_FIMC_YCBYCR422
,
104 .flags
= FMT_FLAGS_M2M
,
106 .name
= "YUV 4:2:2 planar, Y/CbCr",
107 .fourcc
= V4L2_PIX_FMT_NV16
,
109 .color
= S5P_FIMC_YCBYCR422
,
112 .flags
= FMT_FLAGS_M2M
,
114 .name
= "YUV 4:2:2 planar, Y/CrCb",
115 .fourcc
= V4L2_PIX_FMT_NV61
,
117 .color
= S5P_FIMC_YCRYCB422
,
120 .flags
= FMT_FLAGS_M2M
,
122 .name
= "YUV 4:2:0 planar, YCbCr",
123 .fourcc
= V4L2_PIX_FMT_YUV420
,
125 .color
= S5P_FIMC_YCBCR420
,
128 .flags
= FMT_FLAGS_M2M
,
130 .name
= "YUV 4:2:0 planar, Y/CbCr",
131 .fourcc
= V4L2_PIX_FMT_NV12
,
133 .color
= S5P_FIMC_YCBCR420
,
136 .flags
= FMT_FLAGS_M2M
,
138 .name
= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
139 .fourcc
= V4L2_PIX_FMT_NV12M
,
140 .color
= S5P_FIMC_YCBCR420
,
144 .flags
= FMT_FLAGS_M2M
,
146 .name
= "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
147 .fourcc
= V4L2_PIX_FMT_YUV420M
,
148 .color
= S5P_FIMC_YCBCR420
,
149 .depth
= { 8, 2, 2 },
152 .flags
= FMT_FLAGS_M2M
,
154 .name
= "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
155 .fourcc
= V4L2_PIX_FMT_NV12MT
,
156 .color
= S5P_FIMC_YCBCR420
,
160 .flags
= FMT_FLAGS_M2M
,
164 static struct v4l2_queryctrl fimc_ctrls
[] = {
166 .id
= V4L2_CID_HFLIP
,
167 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
168 .name
= "Horizontal flip",
173 .id
= V4L2_CID_VFLIP
,
174 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
175 .name
= "Vertical flip",
180 .id
= V4L2_CID_ROTATE
,
181 .type
= V4L2_CTRL_TYPE_INTEGER
,
182 .name
= "Rotation (CCW)",
191 static struct v4l2_queryctrl
*get_ctrl(int id
)
195 for (i
= 0; i
< ARRAY_SIZE(fimc_ctrls
); ++i
)
196 if (id
== fimc_ctrls
[i
].id
)
197 return &fimc_ctrls
[i
];
201 int fimc_check_scaler_ratio(int sw
, int sh
, int dw
, int dh
, int rot
)
205 if (rot
== 90 || rot
== 270) {
213 if ((sw
>= SCALER_MAX_HRATIO
* tx
) || (sh
>= SCALER_MAX_VRATIO
* ty
))
219 static int fimc_get_scaler_factor(u32 src
, u32 tar
, u32
*ratio
, u32
*shift
)
228 if (src
>= tar
* tmp
) {
229 *shift
= sh
, *ratio
= tmp
;
233 *shift
= 0, *ratio
= 1;
237 int fimc_set_scaler_info(struct fimc_ctx
*ctx
)
239 struct fimc_scaler
*sc
= &ctx
->scaler
;
240 struct fimc_frame
*s_frame
= &ctx
->s_frame
;
241 struct fimc_frame
*d_frame
= &ctx
->d_frame
;
242 struct samsung_fimc_variant
*variant
= ctx
->fimc_dev
->variant
;
246 if (ctx
->rotation
== 90 || ctx
->rotation
== 270) {
248 tx
= d_frame
->height
;
251 ty
= d_frame
->height
;
253 if (tx
<= 0 || ty
<= 0) {
254 v4l2_err(&ctx
->fimc_dev
->m2m
.v4l2_dev
,
255 "invalid target size: %d x %d", tx
, ty
);
260 sy
= s_frame
->height
;
261 if (sx
<= 0 || sy
<= 0) {
262 err("invalid source size: %d x %d", sx
, sy
);
266 sc
->real_height
= sy
;
268 ret
= fimc_get_scaler_factor(sx
, tx
, &sc
->pre_hratio
, &sc
->hfactor
);
272 ret
= fimc_get_scaler_factor(sy
, ty
, &sc
->pre_vratio
, &sc
->vfactor
);
276 sc
->pre_dst_width
= sx
/ sc
->pre_hratio
;
277 sc
->pre_dst_height
= sy
/ sc
->pre_vratio
;
279 if (variant
->has_mainscaler_ext
) {
280 sc
->main_hratio
= (sx
<< 14) / (tx
<< sc
->hfactor
);
281 sc
->main_vratio
= (sy
<< 14) / (ty
<< sc
->vfactor
);
283 sc
->main_hratio
= (sx
<< 8) / (tx
<< sc
->hfactor
);
284 sc
->main_vratio
= (sy
<< 8) / (ty
<< sc
->vfactor
);
288 sc
->scaleup_h
= (tx
>= sx
) ? 1 : 0;
289 sc
->scaleup_v
= (ty
>= sy
) ? 1 : 0;
291 /* check to see if input and output size/format differ */
292 if (s_frame
->fmt
->color
== d_frame
->fmt
->color
293 && s_frame
->width
== d_frame
->width
294 && s_frame
->height
== d_frame
->height
)
302 static void fimc_m2m_job_finish(struct fimc_ctx
*ctx
, int vb_state
)
304 struct vb2_buffer
*src_vb
, *dst_vb
;
305 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
307 if (!ctx
|| !ctx
->m2m_ctx
)
310 src_vb
= v4l2_m2m_src_buf_remove(ctx
->m2m_ctx
);
311 dst_vb
= v4l2_m2m_dst_buf_remove(ctx
->m2m_ctx
);
313 if (src_vb
&& dst_vb
) {
314 v4l2_m2m_buf_done(src_vb
, vb_state
);
315 v4l2_m2m_buf_done(dst_vb
, vb_state
);
316 v4l2_m2m_job_finish(fimc
->m2m
.m2m_dev
, ctx
->m2m_ctx
);
320 /* Complete the transaction which has been scheduled for execution. */
321 static void fimc_m2m_shutdown(struct fimc_ctx
*ctx
)
323 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
326 if (!fimc_m2m_pending(fimc
))
329 fimc_ctx_state_lock_set(FIMC_CTX_SHUT
, ctx
);
331 ret
= wait_event_timeout(fimc
->irq_queue
,
332 !fimc_ctx_state_is_set(FIMC_CTX_SHUT
, ctx
),
333 FIMC_SHUTDOWN_TIMEOUT
);
335 * In case of a timeout the buffers are not released in the interrupt
336 * handler so return them here with the error flag set, if there are
340 fimc_m2m_job_finish(ctx
, VB2_BUF_STATE_ERROR
);
343 static int stop_streaming(struct vb2_queue
*q
)
345 struct fimc_ctx
*ctx
= q
->drv_priv
;
347 fimc_m2m_shutdown(ctx
);
352 static void fimc_capture_irq_handler(struct fimc_dev
*fimc
)
354 struct fimc_vid_cap
*cap
= &fimc
->vid_cap
;
355 struct fimc_vid_buffer
*v_buf
;
359 if (!list_empty(&cap
->active_buf_q
) &&
360 test_bit(ST_CAPT_RUN
, &fimc
->state
)) {
361 ktime_get_real_ts(&ts
);
363 v_buf
= active_queue_pop(cap
);
365 tv
= &v_buf
->vb
.v4l2_buf
.timestamp
;
366 tv
->tv_sec
= ts
.tv_sec
;
367 tv
->tv_usec
= ts
.tv_nsec
/ NSEC_PER_USEC
;
368 v_buf
->vb
.v4l2_buf
.sequence
= cap
->frame_count
++;
370 vb2_buffer_done(&v_buf
->vb
, VB2_BUF_STATE_DONE
);
373 if (test_and_clear_bit(ST_CAPT_SHUT
, &fimc
->state
)) {
374 wake_up(&fimc
->irq_queue
);
378 if (!list_empty(&cap
->pending_buf_q
)) {
380 v_buf
= pending_queue_pop(cap
);
381 fimc_hw_set_output_addr(fimc
, &v_buf
->paddr
, cap
->buf_index
);
382 v_buf
->index
= cap
->buf_index
;
384 /* Move the buffer to the capture active queue */
385 active_queue_add(cap
, v_buf
);
387 dbg("next frame: %d, done frame: %d",
388 fimc_hw_get_frame_index(fimc
), v_buf
->index
);
390 if (++cap
->buf_index
>= FIMC_MAX_OUT_BUFS
)
394 if (cap
->active_buf_cnt
== 0) {
395 clear_bit(ST_CAPT_RUN
, &fimc
->state
);
397 if (++cap
->buf_index
>= FIMC_MAX_OUT_BUFS
)
400 set_bit(ST_CAPT_RUN
, &fimc
->state
);
403 dbg("frame: %d, active_buf_cnt: %d",
404 fimc_hw_get_frame_index(fimc
), cap
->active_buf_cnt
);
407 static irqreturn_t
fimc_isr(int irq
, void *priv
)
409 struct fimc_dev
*fimc
= priv
;
410 struct fimc_vid_cap
*cap
= &fimc
->vid_cap
;
411 struct fimc_ctx
*ctx
;
413 fimc_hw_clear_irq(fimc
);
415 if (test_and_clear_bit(ST_M2M_PEND
, &fimc
->state
)) {
416 ctx
= v4l2_m2m_get_curr_priv(fimc
->m2m
.m2m_dev
);
418 fimc_m2m_job_finish(ctx
, VB2_BUF_STATE_DONE
);
420 spin_lock(&ctx
->slock
);
421 if (ctx
->state
& FIMC_CTX_SHUT
) {
422 ctx
->state
&= ~FIMC_CTX_SHUT
;
423 wake_up(&fimc
->irq_queue
);
425 spin_unlock(&ctx
->slock
);
431 spin_lock(&fimc
->slock
);
433 if (test_bit(ST_CAPT_PEND
, &fimc
->state
)) {
434 fimc_capture_irq_handler(fimc
);
436 if (cap
->active_buf_cnt
== 1) {
437 fimc_deactivate_capture(fimc
);
438 clear_bit(ST_CAPT_STREAM
, &fimc
->state
);
442 spin_unlock(&fimc
->slock
);
446 /* The color format (colplanes, memplanes) must be already configured. */
447 int fimc_prepare_addr(struct fimc_ctx
*ctx
, struct vb2_buffer
*vb
,
448 struct fimc_frame
*frame
, struct fimc_addr
*paddr
)
453 if (vb
== NULL
|| frame
== NULL
)
456 pix_size
= frame
->width
* frame
->height
;
458 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
459 frame
->fmt
->memplanes
, frame
->fmt
->colplanes
, pix_size
);
461 paddr
->y
= vb2_dma_contig_plane_paddr(vb
, 0);
463 if (frame
->fmt
->memplanes
== 1) {
464 switch (frame
->fmt
->colplanes
) {
470 /* decompose Y into Y/Cb */
471 paddr
->cb
= (u32
)(paddr
->y
+ pix_size
);
475 paddr
->cb
= (u32
)(paddr
->y
+ pix_size
);
476 /* decompose Y into Y/Cb/Cr */
477 if (S5P_FIMC_YCBCR420
== frame
->fmt
->color
)
478 paddr
->cr
= (u32
)(paddr
->cb
481 paddr
->cr
= (u32
)(paddr
->cb
488 if (frame
->fmt
->memplanes
>= 2)
489 paddr
->cb
= vb2_dma_contig_plane_paddr(vb
, 1);
491 if (frame
->fmt
->memplanes
== 3)
492 paddr
->cr
= vb2_dma_contig_plane_paddr(vb
, 2);
495 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
496 paddr
->y
, paddr
->cb
, paddr
->cr
, ret
);
501 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
502 static void fimc_set_yuv_order(struct fimc_ctx
*ctx
)
504 /* The one only mode supported in SoC. */
505 ctx
->in_order_2p
= S5P_FIMC_LSB_CRCB
;
506 ctx
->out_order_2p
= S5P_FIMC_LSB_CRCB
;
508 /* Set order for 1 plane input formats. */
509 switch (ctx
->s_frame
.fmt
->color
) {
510 case S5P_FIMC_YCRYCB422
:
511 ctx
->in_order_1p
= S5P_MSCTRL_ORDER422_CBYCRY
;
513 case S5P_FIMC_CBYCRY422
:
514 ctx
->in_order_1p
= S5P_MSCTRL_ORDER422_YCRYCB
;
516 case S5P_FIMC_CRYCBY422
:
517 ctx
->in_order_1p
= S5P_MSCTRL_ORDER422_YCBYCR
;
519 case S5P_FIMC_YCBYCR422
:
521 ctx
->in_order_1p
= S5P_MSCTRL_ORDER422_CRYCBY
;
524 dbg("ctx->in_order_1p= %d", ctx
->in_order_1p
);
526 switch (ctx
->d_frame
.fmt
->color
) {
527 case S5P_FIMC_YCRYCB422
:
528 ctx
->out_order_1p
= S5P_CIOCTRL_ORDER422_CBYCRY
;
530 case S5P_FIMC_CBYCRY422
:
531 ctx
->out_order_1p
= S5P_CIOCTRL_ORDER422_YCRYCB
;
533 case S5P_FIMC_CRYCBY422
:
534 ctx
->out_order_1p
= S5P_CIOCTRL_ORDER422_YCBYCR
;
536 case S5P_FIMC_YCBYCR422
:
538 ctx
->out_order_1p
= S5P_CIOCTRL_ORDER422_CRYCBY
;
541 dbg("ctx->out_order_1p= %d", ctx
->out_order_1p
);
544 static void fimc_prepare_dma_offset(struct fimc_ctx
*ctx
, struct fimc_frame
*f
)
546 struct samsung_fimc_variant
*variant
= ctx
->fimc_dev
->variant
;
549 for (i
= 0; i
< f
->fmt
->colplanes
; i
++)
550 depth
+= f
->fmt
->depth
[i
];
552 f
->dma_offset
.y_h
= f
->offs_h
;
553 if (!variant
->pix_hoff
)
554 f
->dma_offset
.y_h
*= (depth
>> 3);
556 f
->dma_offset
.y_v
= f
->offs_v
;
558 f
->dma_offset
.cb_h
= f
->offs_h
;
559 f
->dma_offset
.cb_v
= f
->offs_v
;
561 f
->dma_offset
.cr_h
= f
->offs_h
;
562 f
->dma_offset
.cr_v
= f
->offs_v
;
564 if (!variant
->pix_hoff
) {
565 if (f
->fmt
->colplanes
== 3) {
566 f
->dma_offset
.cb_h
>>= 1;
567 f
->dma_offset
.cr_h
>>= 1;
569 if (f
->fmt
->color
== S5P_FIMC_YCBCR420
) {
570 f
->dma_offset
.cb_v
>>= 1;
571 f
->dma_offset
.cr_v
>>= 1;
575 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
576 f
->fmt
->color
, f
->dma_offset
.y_h
, f
->dma_offset
.y_v
);
580 * fimc_prepare_config - check dimensions, operation and color mode
581 * and pre-calculate offset and the scaling coefficients.
583 * @ctx: hardware context information
584 * @flags: flags indicating which parameters to check/update
586 * Return: 0 if dimensions are valid or non zero otherwise.
588 int fimc_prepare_config(struct fimc_ctx
*ctx
, u32 flags
)
590 struct fimc_frame
*s_frame
, *d_frame
;
591 struct vb2_buffer
*vb
= NULL
;
594 s_frame
= &ctx
->s_frame
;
595 d_frame
= &ctx
->d_frame
;
597 if (flags
& FIMC_PARAMS
) {
598 /* Prepare the DMA offset ratios for scaler. */
599 fimc_prepare_dma_offset(ctx
, &ctx
->s_frame
);
600 fimc_prepare_dma_offset(ctx
, &ctx
->d_frame
);
602 if (s_frame
->height
> (SCALER_MAX_VRATIO
* d_frame
->height
) ||
603 s_frame
->width
> (SCALER_MAX_HRATIO
* d_frame
->width
)) {
604 err("out of scaler range");
607 fimc_set_yuv_order(ctx
);
610 /* Input DMA mode is not allowed when the scaler is disabled. */
611 ctx
->scaler
.enabled
= 1;
613 if (flags
& FIMC_SRC_ADDR
) {
614 vb
= v4l2_m2m_next_src_buf(ctx
->m2m_ctx
);
615 ret
= fimc_prepare_addr(ctx
, vb
, s_frame
, &s_frame
->paddr
);
620 if (flags
& FIMC_DST_ADDR
) {
621 vb
= v4l2_m2m_next_dst_buf(ctx
->m2m_ctx
);
622 ret
= fimc_prepare_addr(ctx
, vb
, d_frame
, &d_frame
->paddr
);
628 static void fimc_dma_run(void *priv
)
630 struct fimc_ctx
*ctx
= priv
;
631 struct fimc_dev
*fimc
;
635 if (WARN(!ctx
, "null hardware context\n"))
638 fimc
= ctx
->fimc_dev
;
640 spin_lock_irqsave(&ctx
->slock
, flags
);
641 set_bit(ST_M2M_PEND
, &fimc
->state
);
643 ctx
->state
|= (FIMC_SRC_ADDR
| FIMC_DST_ADDR
);
644 ret
= fimc_prepare_config(ctx
, ctx
->state
);
648 /* Reconfigure hardware if the context has changed. */
649 if (fimc
->m2m
.ctx
!= ctx
) {
650 ctx
->state
|= FIMC_PARAMS
;
654 spin_lock(&fimc
->slock
);
655 fimc_hw_set_input_addr(fimc
, &ctx
->s_frame
.paddr
);
657 if (ctx
->state
& FIMC_PARAMS
) {
658 fimc_hw_set_input_path(ctx
);
659 fimc_hw_set_in_dma(ctx
);
660 ret
= fimc_set_scaler_info(ctx
);
662 spin_unlock(&fimc
->slock
);
665 fimc_hw_set_prescaler(ctx
);
666 fimc_hw_set_mainscaler(ctx
);
667 fimc_hw_set_target_format(ctx
);
668 fimc_hw_set_rotation(ctx
);
669 fimc_hw_set_effect(ctx
);
672 fimc_hw_set_output_path(ctx
);
673 if (ctx
->state
& (FIMC_DST_ADDR
| FIMC_PARAMS
))
674 fimc_hw_set_output_addr(fimc
, &ctx
->d_frame
.paddr
, -1);
676 if (ctx
->state
& FIMC_PARAMS
)
677 fimc_hw_set_out_dma(ctx
);
679 fimc_activate_capture(ctx
);
681 ctx
->state
&= (FIMC_CTX_M2M
| FIMC_CTX_CAP
|
682 FIMC_SRC_FMT
| FIMC_DST_FMT
);
683 fimc_hw_activate_input_dma(fimc
, true);
684 spin_unlock(&fimc
->slock
);
687 spin_unlock_irqrestore(&ctx
->slock
, flags
);
690 static void fimc_job_abort(void *priv
)
692 fimc_m2m_shutdown(priv
);
695 static int fimc_queue_setup(struct vb2_queue
*vq
, unsigned int *num_buffers
,
696 unsigned int *num_planes
, unsigned long sizes
[],
699 struct fimc_ctx
*ctx
= vb2_get_drv_priv(vq
);
700 struct fimc_frame
*f
;
703 f
= ctx_get_frame(ctx
, vq
->type
);
707 * Return number of non-contigous planes (plane buffers)
708 * depending on the configured color format.
713 *num_planes
= f
->fmt
->memplanes
;
714 for (i
= 0; i
< f
->fmt
->memplanes
; i
++) {
715 sizes
[i
] = (f
->f_width
* f
->f_height
* f
->fmt
->depth
[i
]) / 8;
716 allocators
[i
] = ctx
->fimc_dev
->alloc_ctx
;
721 static int fimc_buf_prepare(struct vb2_buffer
*vb
)
723 struct fimc_ctx
*ctx
= vb2_get_drv_priv(vb
->vb2_queue
);
724 struct fimc_frame
*frame
;
727 frame
= ctx_get_frame(ctx
, vb
->vb2_queue
->type
);
729 return PTR_ERR(frame
);
731 for (i
= 0; i
< frame
->fmt
->memplanes
; i
++)
732 vb2_set_plane_payload(vb
, i
, frame
->payload
[i
]);
737 static void fimc_buf_queue(struct vb2_buffer
*vb
)
739 struct fimc_ctx
*ctx
= vb2_get_drv_priv(vb
->vb2_queue
);
741 dbg("ctx: %p, ctx->state: 0x%x", ctx
, ctx
->state
);
744 v4l2_m2m_buf_queue(ctx
->m2m_ctx
, vb
);
747 static void fimc_lock(struct vb2_queue
*vq
)
749 struct fimc_ctx
*ctx
= vb2_get_drv_priv(vq
);
750 mutex_lock(&ctx
->fimc_dev
->lock
);
753 static void fimc_unlock(struct vb2_queue
*vq
)
755 struct fimc_ctx
*ctx
= vb2_get_drv_priv(vq
);
756 mutex_unlock(&ctx
->fimc_dev
->lock
);
759 static struct vb2_ops fimc_qops
= {
760 .queue_setup
= fimc_queue_setup
,
761 .buf_prepare
= fimc_buf_prepare
,
762 .buf_queue
= fimc_buf_queue
,
763 .wait_prepare
= fimc_unlock
,
764 .wait_finish
= fimc_lock
,
765 .stop_streaming
= stop_streaming
,
768 static int fimc_m2m_querycap(struct file
*file
, void *priv
,
769 struct v4l2_capability
*cap
)
771 struct fimc_ctx
*ctx
= file
->private_data
;
772 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
774 strncpy(cap
->driver
, fimc
->pdev
->name
, sizeof(cap
->driver
) - 1);
775 strncpy(cap
->card
, fimc
->pdev
->name
, sizeof(cap
->card
) - 1);
776 cap
->bus_info
[0] = 0;
777 cap
->version
= KERNEL_VERSION(1, 0, 0);
778 cap
->capabilities
= V4L2_CAP_STREAMING
|
779 V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_VIDEO_OUTPUT
|
780 V4L2_CAP_VIDEO_CAPTURE_MPLANE
| V4L2_CAP_VIDEO_OUTPUT_MPLANE
;
785 int fimc_vidioc_enum_fmt_mplane(struct file
*file
, void *priv
,
786 struct v4l2_fmtdesc
*f
)
788 struct fimc_fmt
*fmt
;
790 if (f
->index
>= ARRAY_SIZE(fimc_formats
))
793 fmt
= &fimc_formats
[f
->index
];
794 strncpy(f
->description
, fmt
->name
, sizeof(f
->description
) - 1);
795 f
->pixelformat
= fmt
->fourcc
;
800 int fimc_vidioc_g_fmt_mplane(struct file
*file
, void *priv
,
801 struct v4l2_format
*f
)
803 struct fimc_ctx
*ctx
= priv
;
804 struct fimc_frame
*frame
;
805 struct v4l2_pix_format_mplane
*pixm
;
808 frame
= ctx_get_frame(ctx
, f
->type
);
810 return PTR_ERR(frame
);
812 pixm
= &f
->fmt
.pix_mp
;
814 pixm
->width
= frame
->width
;
815 pixm
->height
= frame
->height
;
816 pixm
->field
= V4L2_FIELD_NONE
;
817 pixm
->pixelformat
= frame
->fmt
->fourcc
;
818 pixm
->colorspace
= V4L2_COLORSPACE_JPEG
;
819 pixm
->num_planes
= frame
->fmt
->memplanes
;
821 for (i
= 0; i
< pixm
->num_planes
; ++i
) {
822 int bpl
= frame
->o_width
;
824 if (frame
->fmt
->colplanes
== 1) /* packed formats */
825 bpl
= (bpl
* frame
->fmt
->depth
[0]) / 8;
827 pixm
->plane_fmt
[i
].bytesperline
= bpl
;
829 pixm
->plane_fmt
[i
].sizeimage
= (frame
->o_width
*
830 frame
->o_height
* frame
->fmt
->depth
[i
]) / 8;
836 struct fimc_fmt
*find_format(struct v4l2_format
*f
, unsigned int mask
)
838 struct fimc_fmt
*fmt
;
841 for (i
= 0; i
< ARRAY_SIZE(fimc_formats
); ++i
) {
842 fmt
= &fimc_formats
[i
];
843 if (fmt
->fourcc
== f
->fmt
.pix_mp
.pixelformat
&&
848 return (i
== ARRAY_SIZE(fimc_formats
)) ? NULL
: fmt
;
851 struct fimc_fmt
*find_mbus_format(struct v4l2_mbus_framefmt
*f
,
854 struct fimc_fmt
*fmt
;
857 for (i
= 0; i
< ARRAY_SIZE(fimc_formats
); ++i
) {
858 fmt
= &fimc_formats
[i
];
859 if (fmt
->mbus_code
== f
->code
&& (fmt
->flags
& mask
))
863 return (i
== ARRAY_SIZE(fimc_formats
)) ? NULL
: fmt
;
867 int fimc_vidioc_try_fmt_mplane(struct file
*file
, void *priv
,
868 struct v4l2_format
*f
)
870 struct fimc_ctx
*ctx
= priv
;
871 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
872 struct samsung_fimc_variant
*variant
= fimc
->variant
;
873 struct v4l2_pix_format_mplane
*pix
= &f
->fmt
.pix_mp
;
874 struct fimc_fmt
*fmt
;
875 u32 max_width
, mod_x
, mod_y
, mask
;
876 int i
, is_output
= 0;
879 if (f
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
) {
880 if (fimc_ctx_state_is_set(FIMC_CTX_CAP
, ctx
))
883 } else if (f
->type
!= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
) {
887 dbg("w: %d, h: %d", pix
->width
, pix
->height
);
889 mask
= is_output
? FMT_FLAGS_M2M
: FMT_FLAGS_M2M
| FMT_FLAGS_CAM
;
890 fmt
= find_format(f
, mask
);
892 v4l2_err(&fimc
->m2m
.v4l2_dev
, "Fourcc format (0x%X) invalid.\n",
897 if (pix
->field
== V4L2_FIELD_ANY
)
898 pix
->field
= V4L2_FIELD_NONE
;
899 else if (V4L2_FIELD_NONE
!= pix
->field
)
903 max_width
= variant
->pix_limit
->scaler_dis_w
;
904 mod_x
= ffs(variant
->min_inp_pixsize
) - 1;
906 max_width
= variant
->pix_limit
->out_rot_dis_w
;
907 mod_x
= ffs(variant
->min_out_pixsize
) - 1;
910 if (tiled_fmt(fmt
)) {
911 mod_x
= 6; /* 64 x 32 pixels tile */
914 if (fimc
->id
== 1 && variant
->pix_hoff
)
915 mod_y
= fimc_fmt_is_rgb(fmt
->color
) ? 0 : 1;
920 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x
, mod_y
, max_width
);
922 v4l_bound_align_image(&pix
->width
, 16, max_width
, mod_x
,
923 &pix
->height
, 8, variant
->pix_limit
->scaler_dis_w
, mod_y
, 0);
925 pix
->num_planes
= fmt
->memplanes
;
926 pix
->colorspace
= V4L2_COLORSPACE_JPEG
;
929 for (i
= 0; i
< pix
->num_planes
; ++i
) {
930 u32 bpl
= pix
->plane_fmt
[i
].bytesperline
;
931 u32
*sizeimage
= &pix
->plane_fmt
[i
].sizeimage
;
933 if (fmt
->colplanes
> 1 && (bpl
== 0 || bpl
< pix
->width
))
934 bpl
= pix
->width
; /* Planar */
936 if (fmt
->colplanes
== 1 && /* Packed */
937 (bpl
== 0 || ((bpl
* 8) / fmt
->depth
[i
]) < pix
->width
))
938 bpl
= (pix
->width
* fmt
->depth
[0]) / 8;
940 if (i
== 0) /* Same bytesperline for each plane. */
943 pix
->plane_fmt
[i
].bytesperline
= mod_x
;
944 *sizeimage
= (pix
->width
* pix
->height
* fmt
->depth
[i
]) / 8;
950 static int fimc_m2m_s_fmt_mplane(struct file
*file
, void *priv
,
951 struct v4l2_format
*f
)
953 struct fimc_ctx
*ctx
= priv
;
954 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
955 struct vb2_queue
*vq
;
956 struct fimc_frame
*frame
;
957 struct v4l2_pix_format_mplane
*pix
;
960 ret
= fimc_vidioc_try_fmt_mplane(file
, priv
, f
);
964 vq
= v4l2_m2m_get_vq(ctx
->m2m_ctx
, f
->type
);
966 if (vb2_is_busy(vq
)) {
967 v4l2_err(&fimc
->m2m
.v4l2_dev
, "queue (%d) busy\n", f
->type
);
971 if (f
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
) {
972 frame
= &ctx
->s_frame
;
973 } else if (f
->type
== V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
) {
974 frame
= &ctx
->d_frame
;
976 v4l2_err(&fimc
->m2m
.v4l2_dev
,
977 "Wrong buffer/video queue type (%d)\n", f
->type
);
981 pix
= &f
->fmt
.pix_mp
;
982 frame
->fmt
= find_format(f
, FMT_FLAGS_M2M
);
986 for (i
= 0; i
< frame
->fmt
->colplanes
; i
++) {
988 (pix
->width
* pix
->height
* frame
->fmt
->depth
[i
]) / 8;
991 frame
->f_width
= pix
->plane_fmt
[0].bytesperline
* 8 /
992 frame
->fmt
->depth
[0];
993 frame
->f_height
= pix
->height
;
994 frame
->width
= pix
->width
;
995 frame
->height
= pix
->height
;
996 frame
->o_width
= pix
->width
;
997 frame
->o_height
= pix
->height
;
1001 if (f
->type
== V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
)
1002 fimc_ctx_state_lock_set(FIMC_PARAMS
| FIMC_DST_FMT
, ctx
);
1004 fimc_ctx_state_lock_set(FIMC_PARAMS
| FIMC_SRC_FMT
, ctx
);
1006 dbg("f_w: %d, f_h: %d", frame
->f_width
, frame
->f_height
);
1011 static int fimc_m2m_reqbufs(struct file
*file
, void *priv
,
1012 struct v4l2_requestbuffers
*reqbufs
)
1014 struct fimc_ctx
*ctx
= priv
;
1015 return v4l2_m2m_reqbufs(file
, ctx
->m2m_ctx
, reqbufs
);
1018 static int fimc_m2m_querybuf(struct file
*file
, void *priv
,
1019 struct v4l2_buffer
*buf
)
1021 struct fimc_ctx
*ctx
= priv
;
1022 return v4l2_m2m_querybuf(file
, ctx
->m2m_ctx
, buf
);
1025 static int fimc_m2m_qbuf(struct file
*file
, void *priv
,
1026 struct v4l2_buffer
*buf
)
1028 struct fimc_ctx
*ctx
= priv
;
1030 return v4l2_m2m_qbuf(file
, ctx
->m2m_ctx
, buf
);
1033 static int fimc_m2m_dqbuf(struct file
*file
, void *priv
,
1034 struct v4l2_buffer
*buf
)
1036 struct fimc_ctx
*ctx
= priv
;
1037 return v4l2_m2m_dqbuf(file
, ctx
->m2m_ctx
, buf
);
1040 static int fimc_m2m_streamon(struct file
*file
, void *priv
,
1041 enum v4l2_buf_type type
)
1043 struct fimc_ctx
*ctx
= priv
;
1045 /* The source and target color format need to be set */
1046 if (V4L2_TYPE_IS_OUTPUT(type
)) {
1047 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT
, ctx
))
1049 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT
, ctx
)) {
1053 return v4l2_m2m_streamon(file
, ctx
->m2m_ctx
, type
);
1056 static int fimc_m2m_streamoff(struct file
*file
, void *priv
,
1057 enum v4l2_buf_type type
)
1059 struct fimc_ctx
*ctx
= priv
;
1060 return v4l2_m2m_streamoff(file
, ctx
->m2m_ctx
, type
);
1063 int fimc_vidioc_queryctrl(struct file
*file
, void *priv
,
1064 struct v4l2_queryctrl
*qc
)
1066 struct fimc_ctx
*ctx
= priv
;
1067 struct v4l2_queryctrl
*c
;
1070 c
= get_ctrl(qc
->id
);
1076 if (fimc_ctx_state_is_set(FIMC_CTX_CAP
, ctx
)) {
1077 return v4l2_subdev_call(ctx
->fimc_dev
->vid_cap
.sd
,
1078 core
, queryctrl
, qc
);
1083 int fimc_vidioc_g_ctrl(struct file
*file
, void *priv
,
1084 struct v4l2_control
*ctrl
)
1086 struct fimc_ctx
*ctx
= priv
;
1087 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
1090 case V4L2_CID_HFLIP
:
1091 ctrl
->value
= (FLIP_X_AXIS
& ctx
->flip
) ? 1 : 0;
1093 case V4L2_CID_VFLIP
:
1094 ctrl
->value
= (FLIP_Y_AXIS
& ctx
->flip
) ? 1 : 0;
1096 case V4L2_CID_ROTATE
:
1097 ctrl
->value
= ctx
->rotation
;
1100 if (fimc_ctx_state_is_set(FIMC_CTX_CAP
, ctx
)) {
1101 return v4l2_subdev_call(fimc
->vid_cap
.sd
, core
,
1104 v4l2_err(&fimc
->m2m
.v4l2_dev
, "Invalid control\n");
1108 dbg("ctrl->value= %d", ctrl
->value
);
1113 int check_ctrl_val(struct fimc_ctx
*ctx
, struct v4l2_control
*ctrl
)
1115 struct v4l2_queryctrl
*c
;
1116 c
= get_ctrl(ctrl
->id
);
1120 if (ctrl
->value
< c
->minimum
|| ctrl
->value
> c
->maximum
1121 || (c
->step
!= 0 && ctrl
->value
% c
->step
!= 0)) {
1122 v4l2_err(&ctx
->fimc_dev
->m2m
.v4l2_dev
,
1123 "Invalid control value\n");
1130 int fimc_s_ctrl(struct fimc_ctx
*ctx
, struct v4l2_control
*ctrl
)
1132 struct samsung_fimc_variant
*variant
= ctx
->fimc_dev
->variant
;
1133 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
1137 case V4L2_CID_HFLIP
:
1139 ctx
->flip
|= FLIP_X_AXIS
;
1141 ctx
->flip
&= ~FLIP_X_AXIS
;
1144 case V4L2_CID_VFLIP
:
1146 ctx
->flip
|= FLIP_Y_AXIS
;
1148 ctx
->flip
&= ~FLIP_Y_AXIS
;
1151 case V4L2_CID_ROTATE
:
1152 if (fimc_ctx_state_is_set(FIMC_DST_FMT
| FIMC_SRC_FMT
, ctx
)) {
1153 ret
= fimc_check_scaler_ratio(ctx
->s_frame
.width
,
1154 ctx
->s_frame
.height
, ctx
->d_frame
.width
,
1155 ctx
->d_frame
.height
, ctrl
->value
);
1159 v4l2_err(&fimc
->m2m
.v4l2_dev
, "Out of scaler range\n");
1163 /* Check for the output rotator availability */
1164 if ((ctrl
->value
== 90 || ctrl
->value
== 270) &&
1165 (ctx
->in_path
== FIMC_DMA
&& !variant
->has_out_rot
))
1167 ctx
->rotation
= ctrl
->value
;
1171 v4l2_err(&fimc
->m2m
.v4l2_dev
, "Invalid control\n");
1175 fimc_ctx_state_lock_set(FIMC_PARAMS
, ctx
);
1180 static int fimc_m2m_s_ctrl(struct file
*file
, void *priv
,
1181 struct v4l2_control
*ctrl
)
1183 struct fimc_ctx
*ctx
= priv
;
1186 ret
= check_ctrl_val(ctx
, ctrl
);
1190 ret
= fimc_s_ctrl(ctx
, ctrl
);
1194 static int fimc_m2m_cropcap(struct file
*file
, void *fh
,
1195 struct v4l2_cropcap
*cr
)
1197 struct fimc_frame
*frame
;
1198 struct fimc_ctx
*ctx
= fh
;
1200 frame
= ctx_get_frame(ctx
, cr
->type
);
1202 return PTR_ERR(frame
);
1204 cr
->bounds
.left
= 0;
1206 cr
->bounds
.width
= frame
->f_width
;
1207 cr
->bounds
.height
= frame
->f_height
;
1208 cr
->defrect
= cr
->bounds
;
1213 static int fimc_m2m_g_crop(struct file
*file
, void *fh
, struct v4l2_crop
*cr
)
1215 struct fimc_frame
*frame
;
1216 struct fimc_ctx
*ctx
= file
->private_data
;
1218 frame
= ctx_get_frame(ctx
, cr
->type
);
1220 return PTR_ERR(frame
);
1222 cr
->c
.left
= frame
->offs_h
;
1223 cr
->c
.top
= frame
->offs_v
;
1224 cr
->c
.width
= frame
->width
;
1225 cr
->c
.height
= frame
->height
;
1230 int fimc_try_crop(struct fimc_ctx
*ctx
, struct v4l2_crop
*cr
)
1232 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
1233 struct fimc_frame
*f
;
1234 u32 min_size
, halign
, depth
= 0;
1235 bool is_capture_ctx
;
1238 if (cr
->c
.top
< 0 || cr
->c
.left
< 0) {
1239 v4l2_err(&fimc
->m2m
.v4l2_dev
,
1240 "doesn't support negative values for top & left\n");
1244 is_capture_ctx
= fimc_ctx_state_is_set(FIMC_CTX_CAP
, ctx
);
1246 if (cr
->type
== V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
)
1247 f
= is_capture_ctx
? &ctx
->s_frame
: &ctx
->d_frame
;
1248 else if (cr
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
&&
1254 min_size
= (f
== &ctx
->s_frame
) ?
1255 fimc
->variant
->min_inp_pixsize
: fimc
->variant
->min_out_pixsize
;
1257 /* Get pixel alignment constraints. */
1258 if (is_capture_ctx
) {
1262 if (fimc
->id
== 1 && fimc
->variant
->pix_hoff
)
1263 halign
= fimc_fmt_is_rgb(f
->fmt
->color
) ? 0 : 1;
1265 halign
= ffs(min_size
) - 1;
1268 for (i
= 0; i
< f
->fmt
->colplanes
; i
++)
1269 depth
+= f
->fmt
->depth
[i
];
1271 v4l_bound_align_image(&cr
->c
.width
, min_size
, f
->o_width
,
1273 &cr
->c
.height
, min_size
, f
->o_height
,
1274 halign
, 64/(ALIGN(depth
, 8)));
1276 /* adjust left/top if cropping rectangle is out of bounds */
1277 if (cr
->c
.left
+ cr
->c
.width
> f
->o_width
)
1278 cr
->c
.left
= f
->o_width
- cr
->c
.width
;
1279 if (cr
->c
.top
+ cr
->c
.height
> f
->o_height
)
1280 cr
->c
.top
= f
->o_height
- cr
->c
.height
;
1282 cr
->c
.left
= round_down(cr
->c
.left
, min_size
);
1283 cr
->c
.top
= round_down(cr
->c
.top
, is_capture_ctx
? 16 : 8);
1285 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1286 cr
->c
.left
, cr
->c
.top
, cr
->c
.width
, cr
->c
.height
,
1287 f
->f_width
, f
->f_height
);
1292 static int fimc_m2m_s_crop(struct file
*file
, void *fh
, struct v4l2_crop
*cr
)
1294 struct fimc_ctx
*ctx
= file
->private_data
;
1295 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
1296 struct fimc_frame
*f
;
1299 ret
= fimc_try_crop(ctx
, cr
);
1303 f
= (cr
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
) ?
1304 &ctx
->s_frame
: &ctx
->d_frame
;
1306 /* Check to see if scaling ratio is within supported range */
1307 if (fimc_ctx_state_is_set(FIMC_DST_FMT
| FIMC_SRC_FMT
, ctx
)) {
1308 if (cr
->type
== V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
) {
1309 ret
= fimc_check_scaler_ratio(cr
->c
.width
, cr
->c
.height
,
1311 ctx
->d_frame
.height
,
1314 ret
= fimc_check_scaler_ratio(ctx
->s_frame
.width
,
1315 ctx
->s_frame
.height
,
1316 cr
->c
.width
, cr
->c
.height
,
1320 v4l2_err(&fimc
->m2m
.v4l2_dev
, "Out of scaler range\n");
1325 f
->offs_h
= cr
->c
.left
;
1326 f
->offs_v
= cr
->c
.top
;
1327 f
->width
= cr
->c
.width
;
1328 f
->height
= cr
->c
.height
;
1330 fimc_ctx_state_lock_set(FIMC_PARAMS
, ctx
);
1335 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops
= {
1336 .vidioc_querycap
= fimc_m2m_querycap
,
1338 .vidioc_enum_fmt_vid_cap_mplane
= fimc_vidioc_enum_fmt_mplane
,
1339 .vidioc_enum_fmt_vid_out_mplane
= fimc_vidioc_enum_fmt_mplane
,
1341 .vidioc_g_fmt_vid_cap_mplane
= fimc_vidioc_g_fmt_mplane
,
1342 .vidioc_g_fmt_vid_out_mplane
= fimc_vidioc_g_fmt_mplane
,
1344 .vidioc_try_fmt_vid_cap_mplane
= fimc_vidioc_try_fmt_mplane
,
1345 .vidioc_try_fmt_vid_out_mplane
= fimc_vidioc_try_fmt_mplane
,
1347 .vidioc_s_fmt_vid_cap_mplane
= fimc_m2m_s_fmt_mplane
,
1348 .vidioc_s_fmt_vid_out_mplane
= fimc_m2m_s_fmt_mplane
,
1350 .vidioc_reqbufs
= fimc_m2m_reqbufs
,
1351 .vidioc_querybuf
= fimc_m2m_querybuf
,
1353 .vidioc_qbuf
= fimc_m2m_qbuf
,
1354 .vidioc_dqbuf
= fimc_m2m_dqbuf
,
1356 .vidioc_streamon
= fimc_m2m_streamon
,
1357 .vidioc_streamoff
= fimc_m2m_streamoff
,
1359 .vidioc_queryctrl
= fimc_vidioc_queryctrl
,
1360 .vidioc_g_ctrl
= fimc_vidioc_g_ctrl
,
1361 .vidioc_s_ctrl
= fimc_m2m_s_ctrl
,
1363 .vidioc_g_crop
= fimc_m2m_g_crop
,
1364 .vidioc_s_crop
= fimc_m2m_s_crop
,
1365 .vidioc_cropcap
= fimc_m2m_cropcap
1369 static int queue_init(void *priv
, struct vb2_queue
*src_vq
,
1370 struct vb2_queue
*dst_vq
)
1372 struct fimc_ctx
*ctx
= priv
;
1375 memset(src_vq
, 0, sizeof(*src_vq
));
1376 src_vq
->type
= V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
;
1377 src_vq
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
1378 src_vq
->drv_priv
= ctx
;
1379 src_vq
->ops
= &fimc_qops
;
1380 src_vq
->mem_ops
= &vb2_dma_contig_memops
;
1381 src_vq
->buf_struct_size
= sizeof(struct v4l2_m2m_buffer
);
1383 ret
= vb2_queue_init(src_vq
);
1387 memset(dst_vq
, 0, sizeof(*dst_vq
));
1388 dst_vq
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
;
1389 dst_vq
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
1390 dst_vq
->drv_priv
= ctx
;
1391 dst_vq
->ops
= &fimc_qops
;
1392 dst_vq
->mem_ops
= &vb2_dma_contig_memops
;
1393 dst_vq
->buf_struct_size
= sizeof(struct v4l2_m2m_buffer
);
1395 return vb2_queue_init(dst_vq
);
1398 static int fimc_m2m_open(struct file
*file
)
1400 struct fimc_dev
*fimc
= video_drvdata(file
);
1401 struct fimc_ctx
*ctx
= NULL
;
1403 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1404 task_pid_nr(current
), fimc
->state
, fimc
->vid_cap
.refcnt
);
1407 * Return if the corresponding video capture node
1408 * is already opened.
1410 if (fimc
->vid_cap
.refcnt
> 0)
1414 set_bit(ST_OUTDMA_RUN
, &fimc
->state
);
1416 ctx
= kzalloc(sizeof *ctx
, GFP_KERNEL
);
1420 file
->private_data
= ctx
;
1421 ctx
->fimc_dev
= fimc
;
1422 /* Default color format */
1423 ctx
->s_frame
.fmt
= &fimc_formats
[0];
1424 ctx
->d_frame
.fmt
= &fimc_formats
[0];
1425 /* Setup the device context for mem2mem mode. */
1426 ctx
->state
= FIMC_CTX_M2M
;
1428 ctx
->in_path
= FIMC_DMA
;
1429 ctx
->out_path
= FIMC_DMA
;
1430 spin_lock_init(&ctx
->slock
);
1432 ctx
->m2m_ctx
= v4l2_m2m_ctx_init(fimc
->m2m
.m2m_dev
, ctx
, queue_init
);
1433 if (IS_ERR(ctx
->m2m_ctx
)) {
1434 int err
= PTR_ERR(ctx
->m2m_ctx
);
1442 static int fimc_m2m_release(struct file
*file
)
1444 struct fimc_ctx
*ctx
= file
->private_data
;
1445 struct fimc_dev
*fimc
= ctx
->fimc_dev
;
1447 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1448 task_pid_nr(current
), fimc
->state
, fimc
->m2m
.refcnt
);
1450 v4l2_m2m_ctx_release(ctx
->m2m_ctx
);
1452 if (--fimc
->m2m
.refcnt
<= 0)
1453 clear_bit(ST_OUTDMA_RUN
, &fimc
->state
);
1458 static unsigned int fimc_m2m_poll(struct file
*file
,
1459 struct poll_table_struct
*wait
)
1461 struct fimc_ctx
*ctx
= file
->private_data
;
1463 return v4l2_m2m_poll(file
, ctx
->m2m_ctx
, wait
);
1467 static int fimc_m2m_mmap(struct file
*file
, struct vm_area_struct
*vma
)
1469 struct fimc_ctx
*ctx
= file
->private_data
;
1471 return v4l2_m2m_mmap(file
, ctx
->m2m_ctx
, vma
);
1474 static const struct v4l2_file_operations fimc_m2m_fops
= {
1475 .owner
= THIS_MODULE
,
1476 .open
= fimc_m2m_open
,
1477 .release
= fimc_m2m_release
,
1478 .poll
= fimc_m2m_poll
,
1479 .unlocked_ioctl
= video_ioctl2
,
1480 .mmap
= fimc_m2m_mmap
,
1483 static struct v4l2_m2m_ops m2m_ops
= {
1484 .device_run
= fimc_dma_run
,
1485 .job_abort
= fimc_job_abort
,
1488 static int fimc_register_m2m_device(struct fimc_dev
*fimc
)
1490 struct video_device
*vfd
;
1491 struct platform_device
*pdev
;
1492 struct v4l2_device
*v4l2_dev
;
1499 v4l2_dev
= &fimc
->m2m
.v4l2_dev
;
1501 /* set name if it is empty */
1502 if (!v4l2_dev
->name
[0])
1503 snprintf(v4l2_dev
->name
, sizeof(v4l2_dev
->name
),
1504 "%s.m2m", dev_name(&pdev
->dev
));
1506 ret
= v4l2_device_register(&pdev
->dev
, v4l2_dev
);
1510 vfd
= video_device_alloc();
1512 v4l2_err(v4l2_dev
, "Failed to allocate video device\n");
1516 vfd
->fops
= &fimc_m2m_fops
;
1517 vfd
->ioctl_ops
= &fimc_m2m_ioctl_ops
;
1519 vfd
->release
= video_device_release
;
1520 vfd
->lock
= &fimc
->lock
;
1522 snprintf(vfd
->name
, sizeof(vfd
->name
), "%s:m2m", dev_name(&pdev
->dev
));
1524 video_set_drvdata(vfd
, fimc
);
1525 platform_set_drvdata(pdev
, fimc
);
1527 fimc
->m2m
.vfd
= vfd
;
1528 fimc
->m2m
.m2m_dev
= v4l2_m2m_init(&m2m_ops
);
1529 if (IS_ERR(fimc
->m2m
.m2m_dev
)) {
1530 v4l2_err(v4l2_dev
, "failed to initialize v4l2-m2m device\n");
1531 ret
= PTR_ERR(fimc
->m2m
.m2m_dev
);
1535 ret
= video_register_device(vfd
, VFL_TYPE_GRABBER
, -1);
1538 "%s(): failed to register video device\n", __func__
);
1542 "FIMC m2m driver registered as /dev/video%d\n", vfd
->num
);
1547 v4l2_m2m_release(fimc
->m2m
.m2m_dev
);
1549 video_device_release(fimc
->m2m
.vfd
);
1551 v4l2_device_unregister(v4l2_dev
);
1556 static void fimc_unregister_m2m_device(struct fimc_dev
*fimc
)
1559 v4l2_m2m_release(fimc
->m2m
.m2m_dev
);
1560 video_unregister_device(fimc
->m2m
.vfd
);
1562 v4l2_device_unregister(&fimc
->m2m
.v4l2_dev
);
1566 static void fimc_clk_release(struct fimc_dev
*fimc
)
1569 for (i
= 0; i
< fimc
->num_clocks
; i
++) {
1570 if (fimc
->clock
[i
]) {
1571 clk_disable(fimc
->clock
[i
]);
1572 clk_put(fimc
->clock
[i
]);
1577 static int fimc_clk_get(struct fimc_dev
*fimc
)
1580 for (i
= 0; i
< fimc
->num_clocks
; i
++) {
1581 fimc
->clock
[i
] = clk_get(&fimc
->pdev
->dev
, fimc_clocks
[i
]);
1583 if (!IS_ERR_OR_NULL(fimc
->clock
[i
])) {
1584 clk_enable(fimc
->clock
[i
]);
1587 dev_err(&fimc
->pdev
->dev
, "failed to get fimc clock: %s\n",
1594 static int fimc_probe(struct platform_device
*pdev
)
1596 struct fimc_dev
*fimc
;
1597 struct resource
*res
;
1598 struct samsung_fimc_driverdata
*drv_data
;
1599 struct s5p_platform_fimc
*pdata
;
1601 int cap_input_index
= -1;
1603 dev_dbg(&pdev
->dev
, "%s():\n", __func__
);
1605 drv_data
= (struct samsung_fimc_driverdata
*)
1606 platform_get_device_id(pdev
)->driver_data
;
1608 if (pdev
->id
>= drv_data
->num_entities
) {
1609 dev_err(&pdev
->dev
, "Invalid platform device id: %d\n",
1614 fimc
= kzalloc(sizeof(struct fimc_dev
), GFP_KERNEL
);
1618 fimc
->id
= pdev
->id
;
1619 fimc
->variant
= drv_data
->variant
[fimc
->id
];
1621 pdata
= pdev
->dev
.platform_data
;
1622 fimc
->pdata
= pdata
;
1623 fimc
->state
= ST_IDLE
;
1625 init_waitqueue_head(&fimc
->irq_queue
);
1626 spin_lock_init(&fimc
->slock
);
1628 mutex_init(&fimc
->lock
);
1630 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1632 dev_err(&pdev
->dev
, "failed to find the registers\n");
1637 fimc
->regs_res
= request_mem_region(res
->start
, resource_size(res
),
1638 dev_name(&pdev
->dev
));
1639 if (!fimc
->regs_res
) {
1640 dev_err(&pdev
->dev
, "failed to obtain register region\n");
1645 fimc
->regs
= ioremap(res
->start
, resource_size(res
));
1647 dev_err(&pdev
->dev
, "failed to map registers\n");
1649 goto err_req_region
;
1652 fimc
->num_clocks
= MAX_FIMC_CLOCKS
- 1;
1654 /* Check if a video capture node needs to be registered. */
1655 if (pdata
&& pdata
->num_clients
> 0) {
1656 cap_input_index
= 0;
1660 ret
= fimc_clk_get(fimc
);
1662 goto err_regs_unmap
;
1663 clk_set_rate(fimc
->clock
[CLK_BUS
], drv_data
->lclk_frequency
);
1665 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1667 dev_err(&pdev
->dev
, "failed to get IRQ resource\n");
1671 fimc
->irq
= res
->start
;
1673 fimc_hw_reset(fimc
);
1675 ret
= request_irq(fimc
->irq
, fimc_isr
, 0, pdev
->name
, fimc
);
1677 dev_err(&pdev
->dev
, "failed to install irq (%d)\n", ret
);
1681 /* Initialize contiguous memory allocator */
1682 fimc
->alloc_ctx
= vb2_dma_contig_init_ctx(&fimc
->pdev
->dev
);
1683 if (IS_ERR(fimc
->alloc_ctx
)) {
1684 ret
= PTR_ERR(fimc
->alloc_ctx
);
1688 ret
= fimc_register_m2m_device(fimc
);
1692 /* At least one camera sensor is required to register capture node */
1693 if (cap_input_index
>= 0) {
1694 ret
= fimc_register_capture_device(fimc
);
1697 clk_disable(fimc
->clock
[CLK_CAM
]);
1700 * Exclude the additional output DMA address registers by masking
1701 * them out on HW revisions that provide extended capabilites.
1703 if (fimc
->variant
->out_buf_count
> 4)
1704 fimc_hw_set_dma_seq(fimc
, 0xF);
1706 dev_dbg(&pdev
->dev
, "%s(): fimc-%d registered successfully\n",
1707 __func__
, fimc
->id
);
1712 fimc_unregister_m2m_device(fimc
);
1714 free_irq(fimc
->irq
, fimc
);
1716 fimc_clk_release(fimc
);
1718 iounmap(fimc
->regs
);
1720 release_resource(fimc
->regs_res
);
1721 kfree(fimc
->regs_res
);
1728 static int __devexit
fimc_remove(struct platform_device
*pdev
)
1730 struct fimc_dev
*fimc
=
1731 (struct fimc_dev
*)platform_get_drvdata(pdev
);
1733 free_irq(fimc
->irq
, fimc
);
1734 fimc_hw_reset(fimc
);
1736 fimc_unregister_m2m_device(fimc
);
1737 fimc_unregister_capture_device(fimc
);
1739 fimc_clk_release(fimc
);
1741 vb2_dma_contig_cleanup_ctx(fimc
->alloc_ctx
);
1743 iounmap(fimc
->regs
);
1744 release_resource(fimc
->regs_res
);
1745 kfree(fimc
->regs_res
);
1748 dev_info(&pdev
->dev
, "%s driver unloaded\n", pdev
->name
);
1752 /* Image pixel limits, similar across several FIMC HW revisions. */
1753 static struct fimc_pix_limit s5p_pix_limit
[4] = {
1755 .scaler_en_w
= 3264,
1756 .scaler_dis_w
= 8192,
1757 .in_rot_en_h
= 1920,
1758 .in_rot_dis_w
= 8192,
1759 .out_rot_en_w
= 1920,
1760 .out_rot_dis_w
= 4224,
1763 .scaler_en_w
= 4224,
1764 .scaler_dis_w
= 8192,
1765 .in_rot_en_h
= 1920,
1766 .in_rot_dis_w
= 8192,
1767 .out_rot_en_w
= 1920,
1768 .out_rot_dis_w
= 4224,
1771 .scaler_en_w
= 1920,
1772 .scaler_dis_w
= 8192,
1773 .in_rot_en_h
= 1280,
1774 .in_rot_dis_w
= 8192,
1775 .out_rot_en_w
= 1280,
1776 .out_rot_dis_w
= 1920,
1779 .scaler_en_w
= 1920,
1780 .scaler_dis_w
= 8192,
1781 .in_rot_en_h
= 1366,
1782 .in_rot_dis_w
= 8192,
1783 .out_rot_en_w
= 1366,
1784 .out_rot_dis_w
= 1920,
1788 static struct samsung_fimc_variant fimc0_variant_s5p
= {
1791 .min_inp_pixsize
= 16,
1792 .min_out_pixsize
= 16,
1793 .hor_offs_align
= 8,
1795 .pix_limit
= &s5p_pix_limit
[0],
1798 static struct samsung_fimc_variant fimc2_variant_s5p
= {
1799 .min_inp_pixsize
= 16,
1800 .min_out_pixsize
= 16,
1801 .hor_offs_align
= 8,
1803 .pix_limit
= &s5p_pix_limit
[1],
1806 static struct samsung_fimc_variant fimc0_variant_s5pv210
= {
1810 .min_inp_pixsize
= 16,
1811 .min_out_pixsize
= 16,
1812 .hor_offs_align
= 8,
1814 .pix_limit
= &s5p_pix_limit
[1],
1817 static struct samsung_fimc_variant fimc1_variant_s5pv210
= {
1821 .has_mainscaler_ext
= 1,
1822 .min_inp_pixsize
= 16,
1823 .min_out_pixsize
= 16,
1824 .hor_offs_align
= 1,
1826 .pix_limit
= &s5p_pix_limit
[2],
1829 static struct samsung_fimc_variant fimc2_variant_s5pv210
= {
1831 .min_inp_pixsize
= 16,
1832 .min_out_pixsize
= 16,
1833 .hor_offs_align
= 8,
1835 .pix_limit
= &s5p_pix_limit
[2],
1838 static struct samsung_fimc_variant fimc0_variant_exynos4
= {
1843 .has_mainscaler_ext
= 1,
1844 .min_inp_pixsize
= 16,
1845 .min_out_pixsize
= 16,
1846 .hor_offs_align
= 1,
1847 .out_buf_count
= 32,
1848 .pix_limit
= &s5p_pix_limit
[1],
1851 static struct samsung_fimc_variant fimc2_variant_exynos4
= {
1854 .has_mainscaler_ext
= 1,
1855 .min_inp_pixsize
= 16,
1856 .min_out_pixsize
= 16,
1857 .hor_offs_align
= 1,
1858 .out_buf_count
= 32,
1859 .pix_limit
= &s5p_pix_limit
[3],
1863 static struct samsung_fimc_driverdata fimc_drvdata_s5p
= {
1865 [0] = &fimc0_variant_s5p
,
1866 [1] = &fimc0_variant_s5p
,
1867 [2] = &fimc2_variant_s5p
,
1870 .lclk_frequency
= 133000000UL,
1873 /* S5PV210, S5PC110 */
1874 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210
= {
1876 [0] = &fimc0_variant_s5pv210
,
1877 [1] = &fimc1_variant_s5pv210
,
1878 [2] = &fimc2_variant_s5pv210
,
1881 .lclk_frequency
= 166000000UL,
1884 /* S5PV310, S5PC210 */
1885 static struct samsung_fimc_driverdata fimc_drvdata_exynos4
= {
1887 [0] = &fimc0_variant_exynos4
,
1888 [1] = &fimc0_variant_exynos4
,
1889 [2] = &fimc0_variant_exynos4
,
1890 [3] = &fimc2_variant_exynos4
,
1893 .lclk_frequency
= 166000000UL,
1896 static struct platform_device_id fimc_driver_ids
[] = {
1899 .driver_data
= (unsigned long)&fimc_drvdata_s5p
,
1901 .name
= "s5pv210-fimc",
1902 .driver_data
= (unsigned long)&fimc_drvdata_s5pv210
,
1904 .name
= "exynos4-fimc",
1905 .driver_data
= (unsigned long)&fimc_drvdata_exynos4
,
1909 MODULE_DEVICE_TABLE(platform
, fimc_driver_ids
);
1911 static struct platform_driver fimc_driver
= {
1912 .probe
= fimc_probe
,
1913 .remove
= __devexit_p(fimc_remove
),
1914 .id_table
= fimc_driver_ids
,
1916 .name
= MODULE_NAME
,
1917 .owner
= THIS_MODULE
,
1921 static int __init
fimc_init(void)
1923 int ret
= platform_driver_register(&fimc_driver
);
1925 err("platform_driver_register failed: %d\n", ret
);
1929 static void __exit
fimc_exit(void)
1931 platform_driver_unregister(&fimc_driver
);
1934 module_init(fimc_init
);
1935 module_exit(fimc_exit
);
1937 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1938 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1939 MODULE_LICENSE("GPL");