drivers/media/video/s5p-fimc/fimc-core.h

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics
   3  *
   4  * Sylwester Nawrocki, <s.nawrocki@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef FIMC_CORE_H_
  12 #define FIMC_CORE_H_
  13
  14 /*#define DEBUG*/
  15
  16 #include <linux/sched.h>
  17 #include <linux/types.h>
  18 #include <linux/videodev2.h>
  19 #include <linux/io.h>
  20 #include <media/videobuf2-core.h>
  21 #include <media/v4l2-device.h>
  22 #include <media/v4l2-mem2mem.h>
  23 #include <media/v4l2-mediabus.h>
  24 #include <media/s3c_fimc.h>
  25
  26 #include "regs-fimc.h"
  27
  28 #define err(fmt, args...) \
  29         printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  30
  31 #ifdef DEBUG
  32 #define dbg(fmt, args...) \
  33         printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  34 #else
  35 #define dbg(fmt, args...)
  36 #endif
  37
  38 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
  39 #define FIMC_SHUTDOWN_TIMEOUT   ((100*HZ)/1000)
  40 #define NUM_FIMC_CLOCKS         2
  41 #define MODULE_NAME             "s5p-fimc"
  42 #define FIMC_MAX_DEVS           4
  43 #define FIMC_MAX_OUT_BUFS       4
  44 #define SCALER_MAX_HRATIO       64
  45 #define SCALER_MAX_VRATIO       64
  46 #define DMA_MIN_SIZE            8
  47
  48 /* FIMC device state flags */
  49 enum fimc_dev_flags {
  50         /* for m2m node */
  51         ST_IDLE,
  52         ST_OUTDMA_RUN,
  53         ST_M2M_PEND,
  54         /* for capture node */
  55         ST_CAPT_PEND,
  56         ST_CAPT_RUN,
  57         ST_CAPT_STREAM,
  58         ST_CAPT_SHUT,
  59 };
  60
  61 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
  62 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
  63
  64 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
  65 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
  66
  67 #define fimc_capture_active(dev) \
  68         (test_bit(ST_CAPT_RUN, &(dev)->state) || \
  69          test_bit(ST_CAPT_PEND, &(dev)->state))
  70
  71 #define fimc_capture_streaming(dev) \
  72         test_bit(ST_CAPT_STREAM, &(dev)->state)
  73
  74 enum fimc_datapath {
  75         FIMC_CAMERA,
  76         FIMC_DMA,
  77         FIMC_LCDFIFO,
  78         FIMC_WRITEBACK
  79 };
  80
  81 enum fimc_color_fmt {
  82         S5P_FIMC_RGB565 = 0x10,
  83         S5P_FIMC_RGB666,
  84         S5P_FIMC_RGB888,
  85         S5P_FIMC_RGB30_LOCAL,
  86         S5P_FIMC_YCBCR420 = 0x20,
  87         S5P_FIMC_YCBYCR422,
  88         S5P_FIMC_YCRYCB422,
  89         S5P_FIMC_CBYCRY422,
  90         S5P_FIMC_CRYCBY422,
  91         S5P_FIMC_YCBCR444_LOCAL,
  92 };
  93
  94 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
  95
  96 /* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
  97 #define S5P_FIMC_OUT_CRYCBY     S5P_CIOCTRL_ORDER422_CRYCBY
  98 #define S5P_FIMC_OUT_CBYCRY     S5P_CIOCTRL_ORDER422_YCRYCB
  99 #define S5P_FIMC_OUT_YCRYCB     S5P_CIOCTRL_ORDER422_CBYCRY
 100 #define S5P_FIMC_OUT_YCBYCR     S5P_CIOCTRL_ORDER422_YCBYCR
 101
 102 /* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
 103 #define S5P_FIMC_IN_CRYCBY      S5P_MSCTRL_ORDER422_CRYCBY
 104 #define S5P_FIMC_IN_CBYCRY      S5P_MSCTRL_ORDER422_YCRYCB
 105 #define S5P_FIMC_IN_YCRYCB      S5P_MSCTRL_ORDER422_CBYCRY
 106 #define S5P_FIMC_IN_YCBYCR      S5P_MSCTRL_ORDER422_YCBYCR
 107
 108 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
 109 #define S5P_FIMC_LSB_CRCB       S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
 110
 111 /* The embedded image effect selection */
 112 #define S5P_FIMC_EFFECT_ORIGINAL        S5P_CIIMGEFF_FIN_BYPASS
 113 #define S5P_FIMC_EFFECT_ARBITRARY       S5P_CIIMGEFF_FIN_ARBITRARY
 114 #define S5P_FIMC_EFFECT_NEGATIVE        S5P_CIIMGEFF_FIN_NEGATIVE
 115 #define S5P_FIMC_EFFECT_ARTFREEZE       S5P_CIIMGEFF_FIN_ARTFREEZE
 116 #define S5P_FIMC_EFFECT_EMBOSSING       S5P_CIIMGEFF_FIN_EMBOSSING
 117 #define S5P_FIMC_EFFECT_SIKHOUETTE      S5P_CIIMGEFF_FIN_SILHOUETTE
 118
 119 /* The hardware context state. */
 120 #define FIMC_PARAMS             (1 << 0)
 121 #define FIMC_SRC_ADDR           (1 << 1)
 122 #define FIMC_DST_ADDR           (1 << 2)
 123 #define FIMC_SRC_FMT            (1 << 3)
 124 #define FIMC_DST_FMT            (1 << 4)
 125 #define FIMC_CTX_M2M            (1 << 5)
 126 #define FIMC_CTX_CAP            (1 << 6)
 127
 128 /* Image conversion flags */
 129 #define FIMC_IN_DMA_ACCESS_TILED        (1 << 0)
 130 #define FIMC_IN_DMA_ACCESS_LINEAR       (0 << 0)
 131 #define FIMC_OUT_DMA_ACCESS_TILED       (1 << 1)
 132 #define FIMC_OUT_DMA_ACCESS_LINEAR      (0 << 1)
 133 #define FIMC_SCAN_MODE_PROGRESSIVE      (0 << 2)
 134 #define FIMC_SCAN_MODE_INTERLACED       (1 << 2)
 135 /*
 136  * YCbCr data dynamic range for RGB-YUV color conversion.
 137  * Y/Cb/Cr: (0 ~ 255) */
 138 #define FIMC_COLOR_RANGE_WIDE           (0 << 3)
 139 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
 140 #define FIMC_COLOR_RANGE_NARROW         (1 << 3)
 141
 142 #define FLIP_NONE                       0
 143 #define FLIP_X_AXIS                     1
 144 #define FLIP_Y_AXIS                     2
 145 #define FLIP_XY_AXIS                    (FLIP_X_AXIS | FLIP_Y_AXIS)
 146
 147 /**
 148  * struct fimc_fmt - the driver's internal color format data
 149  * @mbus_code: Media Bus pixel code, -1 if not applicable
 150  * @name: format description
 151  * @fourcc: the fourcc code for this format, 0 if not applicable
 152  * @color: the corresponding fimc_color_fmt
 153  * @depth: per plane driver's private 'number of bits per pixel'
 154  * @memplanes: number of physically non-contiguous data planes
 155  * @colplanes: number of physically contiguous data planes
 156  */
 157 struct fimc_fmt {
 158         enum v4l2_mbus_pixelcode mbus_code;
 159         char    *name;
 160         u32     fourcc;
 161         u32     color;
 162         u16     memplanes;
 163         u16     colplanes;
 164         u8      depth[VIDEO_MAX_PLANES];
 165         u16     flags;
 166 #define FMT_FLAGS_CAM   (1 << 0)
 167 #define FMT_FLAGS_M2M   (1 << 1)
 168 };
 169
 170 /**
 171  * struct fimc_dma_offset - pixel offset information for DMA
 172  * @y_h:        y value horizontal offset
 173  * @y_v:        y value vertical offset
 174  * @cb_h:       cb value horizontal offset
 175  * @cb_v:       cb value vertical offset
 176  * @cr_h:       cr value horizontal offset
 177  * @cr_v:       cr value vertical offset
 178  */
 179 struct fimc_dma_offset {
 180         int     y_h;
 181         int     y_v;
 182         int     cb_h;
 183         int     cb_v;
 184         int     cr_h;
 185         int     cr_v;
 186 };
 187
 188 /**
 189  * struct fimc_effect - the configuration data for the "Arbitrary" image effect
 190  * @type:       effect type
 191  * @pat_cb:     cr value when type is "arbitrary"
 192  * @pat_cr:     cr value when type is "arbitrary"
 193  */
 194 struct fimc_effect {
 195         u32     type;
 196         u8      pat_cb;
 197         u8      pat_cr;
 198 };
 199
 200 /**
 201  * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 202  *
 203  * @scaleup_h:          flag indicating scaling up horizontally
 204  * @scaleup_v:          flag indicating scaling up vertically
 205  * @copy_mode:          flag indicating transparent DMA transfer (no scaling
 206  *                      and color format conversion)
 207  * @enabled:            flag indicating if the scaler is used
 208  * @hfactor:            horizontal shift factor
 209  * @vfactor:            vertical shift factor
 210  * @pre_hratio:         horizontal ratio of the prescaler
 211  * @pre_vratio:         vertical ratio of the prescaler
 212  * @pre_dst_width:      the prescaler's destination width
 213  * @pre_dst_height:     the prescaler's destination height
 214  * @main_hratio:        the main scaler's horizontal ratio
 215  * @main_vratio:        the main scaler's vertical ratio
 216  * @real_width:         source pixel (width - offset)
 217  * @real_height:        source pixel (height - offset)
 218  */
 219 struct fimc_scaler {
 220         unsigned int scaleup_h:1;
 221         unsigned int scaleup_v:1;
 222         unsigned int copy_mode:1;
 223         unsigned int enabled:1;
 224         u32     hfactor;
 225         u32     vfactor;
 226         u32     pre_hratio;
 227         u32     pre_vratio;
 228         u32     pre_dst_width;
 229         u32     pre_dst_height;
 230         u32     main_hratio;
 231         u32     main_vratio;
 232         u32     real_width;
 233         u32     real_height;
 234 };
 235
 236 /**
 237  * struct fimc_addr - the FIMC physical address set for DMA
 238  *
 239  * @y:   luminance plane physical address
 240  * @cb:  Cb plane physical address
 241  * @cr:  Cr plane physical address
 242  */
 243 struct fimc_addr {
 244         u32     y;
 245         u32     cb;
 246         u32     cr;
 247 };
 248
 249 /**
 250  * struct fimc_vid_buffer - the driver's video buffer
 251  * @vb:    v4l videobuf buffer
 252  * @paddr: precalculated physical address set
 253  * @index: buffer index for the output DMA engine
 254  */
 255 struct fimc_vid_buffer {
 256         struct vb2_buffer       vb;
 257         struct list_head        list;
 258         struct fimc_addr        paddr;
 259         int                     index;
 260 };
 261
 262 /**
 263  * struct fimc_frame - source/target frame properties
 264  * @f_width:    image full width (virtual screen size)
 265  * @f_height:   image full height (virtual screen size)
 266  * @o_width:    original image width as set by S_FMT
 267  * @o_height:   original image height as set by S_FMT
 268  * @offs_h:     image horizontal pixel offset
 269  * @offs_v:     image vertical pixel offset
 270  * @width:      image pixel width
 271  * @height:     image pixel weight
 272  * @paddr:      image frame buffer physical addresses
 273  * @buf_cnt:    number of buffers depending on a color format
 274  * @payload:    image size in bytes (w x h x bpp)
 275  * @color:      color format
 276  * @dma_offset: DMA offset in bytes
 277  */
 278 struct fimc_frame {
 279         u32     f_width;
 280         u32     f_height;
 281         u32     o_width;
 282         u32     o_height;
 283         u32     offs_h;
 284         u32     offs_v;
 285         u32     width;
 286         u32     height;
 287         unsigned long           payload[VIDEO_MAX_PLANES];
 288         struct fimc_addr        paddr;
 289         struct fimc_dma_offset  dma_offset;
 290         struct fimc_fmt         *fmt;
 291 };
 292
 293 /**
 294  * struct fimc_m2m_device - v4l2 memory-to-memory device data
 295  * @vfd: the video device node for v4l2 m2m mode
 296  * @v4l2_dev: v4l2 device for m2m mode
 297  * @m2m_dev: v4l2 memory-to-memory device data
 298  * @ctx: hardware context data
 299  * @refcnt: the reference counter
 300  */
 301 struct fimc_m2m_device {
 302         struct video_device     *vfd;
 303         struct v4l2_device      v4l2_dev;
 304         struct v4l2_m2m_dev     *m2m_dev;
 305         struct fimc_ctx         *ctx;
 306         int                     refcnt;
 307 };
 308
 309 /**
 310  * struct fimc_vid_cap - camera capture device information
 311  * @ctx: hardware context data
 312  * @vfd: video device node for camera capture mode
 313  * @v4l2_dev: v4l2_device struct to manage subdevs
 314  * @sd: pointer to camera sensor subdevice currently in use
 315  * @fmt: Media Bus format configured at selected image sensor
 316  * @pending_buf_q: the pending buffer queue head
 317  * @active_buf_q: the queue head of buffers scheduled in hardware
 318  * @vbq: the capture am video buffer queue
 319  * @active_buf_cnt: number of video buffers scheduled in hardware
 320  * @buf_index: index for managing the output DMA buffers
 321  * @frame_count: the frame counter for statistics
 322  * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
 323  * @input_index: input (camera sensor) index
 324  * @refcnt: driver's private reference counter
 325  */
 326 struct fimc_vid_cap {
 327         struct fimc_ctx                 *ctx;
 328         struct vb2_alloc_ctx            *alloc_ctx;
 329         struct video_device             *vfd;
 330         struct v4l2_device              v4l2_dev;
 331         struct v4l2_subdev              *sd;;
 332         struct v4l2_mbus_framefmt       fmt;
 333         struct list_head                pending_buf_q;
 334         struct list_head                active_buf_q;
 335         struct vb2_queue                vbq;
 336         int                             active_buf_cnt;
 337         int                             buf_index;
 338         unsigned int                    frame_count;
 339         unsigned int                    reqbufs_count;
 340         int                             input_index;
 341         int                             refcnt;
 342 };
 343
 344 /**
 345  *  struct fimc_pix_limit - image pixel size limits in various IP configurations
 346  *
 347  *  @scaler_en_w: max input pixel width when the scaler is enabled
 348  *  @scaler_dis_w: max input pixel width when the scaler is disabled
 349  *  @in_rot_en_h: max input width with the input rotator is on
 350  *  @in_rot_dis_w: max input width with the input rotator is off
 351  *  @out_rot_en_w: max output width with the output rotator on
 352  *  @out_rot_dis_w: max output width with the output rotator off
 353  */
 354 struct fimc_pix_limit {
 355         u16 scaler_en_w;
 356         u16 scaler_dis_w;
 357         u16 in_rot_en_h;
 358         u16 in_rot_dis_w;
 359         u16 out_rot_en_w;
 360         u16 out_rot_dis_w;
 361 };
 362
 363 /**
 364  * struct samsung_fimc_variant - camera interface variant information
 365  *
 366  * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 367  * @has_inp_rot: set if has input rotator
 368  * @has_out_rot: set if has output rotator
 369  * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
 370  * @pix_limit: pixel size constraints for the scaler
 371  * @min_inp_pixsize: minimum input pixel size
 372  * @min_out_pixsize: minimum output pixel size
 373  * @hor_offs_align: horizontal pixel offset aligment
 374  * @out_buf_count: the number of buffers in output DMA sequence
 375  */
 376 struct samsung_fimc_variant {
 377         unsigned int    pix_hoff:1;
 378         unsigned int    has_inp_rot:1;
 379         unsigned int    has_out_rot:1;
 380         unsigned int    has_cistatus2:1;
 381         struct fimc_pix_limit *pix_limit;
 382         u16             min_inp_pixsize;
 383         u16             min_out_pixsize;
 384         u16             hor_offs_align;
 385         u16             out_buf_count;
 386 };
 387
 388 /**
 389  * struct samsung_fimc_driverdata - per device type driver data for init time.
 390  *
 391  * @variant: the variant information for this driver.
 392  * @dev_cnt: number of fimc sub-devices available in SoC
 393  * @lclk_frequency: fimc bus clock frequency
 394  */
 395 struct samsung_fimc_driverdata {
 396         struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
 397         unsigned long   lclk_frequency;
 398         int             num_entities;
 399 };
 400
 401 struct fimc_ctx;
 402
 403 /**
 404  * struct fimc_dev - abstraction for FIMC entity
 405  *
 406  * @slock:      the spinlock protecting this data structure
 407  * @lock:       the mutex protecting this data structure
 408  * @pdev:       pointer to the FIMC platform device
 409  * @pdata:      pointer to the device platform data
 410  * @id:         FIMC device index (0..2)
 411  * @clock[]:    the clocks required for FIMC operation
 412  * @regs:       the mapped hardware registers
 413  * @regs_res:   the resource claimed for IO registers
 414  * @irq:        interrupt number of the FIMC subdevice
 415  * @irq_queue:
 416  * @m2m:        memory-to-memory V4L2 device information
 417  * @vid_cap:    camera capture device information
 418  * @state:      flags used to synchronize m2m and capture mode operation
 419  */
 420 struct fimc_dev {
 421         spinlock_t                      slock;
 422         struct mutex                    lock;
 423         struct platform_device          *pdev;
 424         struct s3c_platform_fimc        *pdata;
 425         struct samsung_fimc_variant     *variant;
 426         int                             id;
 427         struct clk                      *clock[NUM_FIMC_CLOCKS];
 428         void __iomem                    *regs;
 429         struct resource                 *regs_res;
 430         int                             irq;
 431         wait_queue_head_t               irq_queue;
 432         struct fimc_m2m_device          m2m;
 433         struct fimc_vid_cap             vid_cap;
 434         unsigned long                   state;
 435         struct vb2_alloc_ctx            *alloc_ctx;
 436 };
 437
 438 /**
 439  * fimc_ctx - the device context data
 440  *
 441  * @lock:               mutex protecting this data structure
 442  * @s_frame:            source frame properties
 443  * @d_frame:            destination frame properties
 444  * @out_order_1p:       output 1-plane YCBCR order
 445  * @out_order_2p:       output 2-plane YCBCR order
 446  * @in_order_1p         input 1-plane YCBCR order
 447  * @in_order_2p:        input 2-plane YCBCR order
 448  * @in_path:            input mode (DMA or camera)
 449  * @out_path:           output mode (DMA or FIFO)
 450  * @scaler:             image scaler properties
 451  * @effect:             image effect
 452  * @rotation:           image clockwise rotation in degrees
 453  * @flip:               image flip mode
 454  * @flags:              additional flags for image conversion
 455  * @state:              flags to keep track of user configuration
 456  * @fimc_dev:           the FIMC device this context applies to
 457  * @m2m_ctx:            memory-to-memory device context
 458  */
 459 struct fimc_ctx {
 460         spinlock_t              slock;
 461         struct fimc_frame       s_frame;
 462         struct fimc_frame       d_frame;
 463         u32                     out_order_1p;
 464         u32                     out_order_2p;
 465         u32                     in_order_1p;
 466         u32                     in_order_2p;
 467         enum fimc_datapath      in_path;
 468         enum fimc_datapath      out_path;
 469         struct fimc_scaler      scaler;
 470         struct fimc_effect      effect;
 471         int                     rotation;
 472         u32                     flip;
 473         u32                     flags;
 474         u32                     state;
 475         struct fimc_dev         *fimc_dev;
 476         struct v4l2_m2m_ctx     *m2m_ctx;
 477 };
 478
 479 static inline int tiled_fmt(struct fimc_fmt *fmt)
 480 {
 481         return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
 482 }
 483
 484 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
 485 {
 486         u32 cfg = readl(dev->regs + S5P_CIGCTRL);
 487         cfg |= S5P_CIGCTRL_IRQ_CLR;
 488         writel(cfg, dev->regs + S5P_CIGCTRL);
 489 }
 490
 491 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
 492 {
 493         u32 cfg = readl(dev->regs + S5P_CISCCTRL);
 494         if (on)
 495                 cfg |= S5P_CISCCTRL_SCALERSTART;
 496         else
 497                 cfg &= ~S5P_CISCCTRL_SCALERSTART;
 498         writel(cfg, dev->regs + S5P_CISCCTRL);
 499 }
 500
 501 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
 502 {
 503         u32 cfg = readl(dev->regs + S5P_MSCTRL);
 504         if (on)
 505                 cfg |= S5P_MSCTRL_ENVID;
 506         else
 507                 cfg &= ~S5P_MSCTRL_ENVID;
 508         writel(cfg, dev->regs + S5P_MSCTRL);
 509 }
 510
 511 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
 512 {
 513         u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
 514         cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
 515         writel(cfg, dev->regs + S5P_CIIMGCPT);
 516 }
 517
 518 /**
 519  * fimc_hw_set_dma_seq - configure output DMA buffer sequence
 520  * @mask: each bit corresponds to one of 32 output buffer registers set
 521  *        1 to include buffer in the sequence, 0 to disable
 522  *
 523  * This function mask output DMA ring buffers, i.e. it allows to configure
 524  * which of the output buffer address registers will be used by the DMA
 525  * engine.
 526  */
 527 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
 528 {
 529         writel(mask, dev->regs + S5P_CIFCNTSEQ);
 530 }
 531
 532 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
 533                                                enum v4l2_buf_type type)
 534 {
 535         struct fimc_frame *frame;
 536
 537         if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
 538                 if (ctx->state & FIMC_CTX_M2M)
 539                         frame = &ctx->s_frame;
 540                 else
 541                         return ERR_PTR(-EINVAL);
 542         } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
 543                 frame = &ctx->d_frame;
 544         } else {
 545                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
 546                         "Wrong buffer/video queue type (%d)\n", type);
 547                 return ERR_PTR(-EINVAL);
 548         }
 549
 550         return frame;
 551 }
 552
 553 /* Return an index to the buffer actually being written. */
 554 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
 555 {
 556         u32 reg;
 557
 558         if (dev->variant->has_cistatus2) {
 559                 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
 560                 return reg > 0 ? --reg : reg;
 561         } else {
 562                 reg = readl(dev->regs + S5P_CISTATUS);
 563                 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
 564                         S5P_CISTATUS_FRAMECNT_SHIFT;
 565         }
 566 }
 567
 568 /* -----------------------------------------------------*/
 569 /* fimc-reg.c                                           */
 570 void fimc_hw_reset(struct fimc_dev *fimc);
 571 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
 572 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
 573 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
 574 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
 575 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
 576 void fimc_hw_set_scaler(struct fimc_ctx *ctx);
 577 void fimc_hw_en_capture(struct fimc_ctx *ctx);
 578 void fimc_hw_set_effect(struct fimc_ctx *ctx);
 579 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
 580 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
 581 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
 582 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
 583 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
 584                              int index);
 585 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 586                               struct s3c_fimc_isp_info *cam);
 587 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
 588 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
 589                                 struct s3c_fimc_isp_info *cam);
 590 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 591                             struct s3c_fimc_isp_info *cam);
 592
 593 /* -----------------------------------------------------*/
 594 /* fimc-core.c */
 595 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
 596                                 struct v4l2_fmtdesc *f);
 597 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
 598                              struct v4l2_format *f);
 599 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
 600                                struct v4l2_format *f);
 601 int fimc_vidioc_queryctrl(struct file *file, void *priv,
 602                           struct v4l2_queryctrl *qc);
 603 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
 604                        struct v4l2_control *ctrl);
 605
 606 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
 607 int check_ctrl_val(struct fimc_ctx *ctx,  struct v4l2_control *ctrl);
 608 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
 609
 610 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
 611 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
 612                                   unsigned int mask);
 613
 614 int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f);
 615 int fimc_set_scaler_info(struct fimc_ctx *ctx);
 616 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
 617 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 618                       struct fimc_frame *frame, struct fimc_addr *paddr);
 619
 620 /* -----------------------------------------------------*/
 621 /* fimc-capture.c                                       */
 622 int fimc_register_capture_device(struct fimc_dev *fimc);
 623 void fimc_unregister_capture_device(struct fimc_dev *fimc);
 624 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
 625 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
 626                              struct fimc_vid_buffer *fimc_vb);
 627
 628 /* Locking: the caller holds fimc->slock */
 629 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
 630 {
 631         fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
 632         fimc_hw_en_capture(ctx);
 633 }
 634
 635 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
 636 {
 637         fimc_hw_en_lastirq(fimc, true);
 638         fimc_hw_dis_capture(fimc);
 639         fimc_hw_enable_scaler(fimc, false);
 640         fimc_hw_en_lastirq(fimc, false);
 641 }
 642
 643 /*
 644  * Add buf to the capture active buffers queue.
 645  * Locking: Need to be called with fimc_dev::slock held.
 646  */
 647 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
 648                                     struct fimc_vid_buffer *buf)
 649 {
 650         list_add_tail(&buf->list, &vid_cap->active_buf_q);
 651         vid_cap->active_buf_cnt++;
 652 }
 653
 654 /*
 655  * Pop a video buffer from the capture active buffers queue
 656  * Locking: Need to be called with fimc_dev::slock held.
 657  */
 658 static inline struct fimc_vid_buffer *
 659 active_queue_pop(struct fimc_vid_cap *vid_cap)
 660 {
 661         struct fimc_vid_buffer *buf;
 662         buf = list_entry(vid_cap->active_buf_q.next,
 663                          struct fimc_vid_buffer, list);
 664         list_del(&buf->list);
 665         vid_cap->active_buf_cnt--;
 666         return buf;
 667 }
 668
 669 /* Add video buffer to the capture pending buffers queue */
 670 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
 671                                           struct fimc_vid_buffer *buf)
 672 {
 673         list_add_tail(&buf->list, &vid_cap->pending_buf_q);
 674 }
 675
 676 /* Add video buffer to the capture pending buffers queue */
 677 static inline struct fimc_vid_buffer *
 678 pending_queue_pop(struct fimc_vid_cap *vid_cap)
 679 {
 680         struct fimc_vid_buffer *buf;
 681         buf = list_entry(vid_cap->pending_buf_q.next,
 682                         struct fimc_vid_buffer, list);
 683         list_del(&buf->list);
 684         return buf;
 685 }
 686
 687 #endif /* FIMC_CORE_H_ */