2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/types.h>
18 #include <linux/videodev2.h>
21 #include <media/media-entity.h>
22 #include <media/videobuf2-core.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-mem2mem.h>
26 #include <media/v4l2-mediabus.h>
27 #include <media/s5p_fimc.h>
29 #include "regs-fimc.h"
31 #define err(fmt, args...) \
32 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34 #define dbg(fmt, args...) \
35 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
37 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
38 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
39 #define MAX_FIMC_CLOCKS 2
40 #define FIMC_MODULE_NAME "s5p-fimc"
41 #define FIMC_MAX_DEVS 4
42 #define FIMC_MAX_OUT_BUFS 4
43 #define SCALER_MAX_HRATIO 64
44 #define SCALER_MAX_VRATIO 64
45 #define DMA_MIN_SIZE 8
46 #define FIMC_CAMIF_MAX_HEIGHT 0x2000
48 /* indices to the clocks array */
73 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
74 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
76 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
77 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
78 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
88 S5P_FIMC_RGB565
= 0x10,
92 S5P_FIMC_YCBCR420
= 0x20,
97 S5P_FIMC_YCBCR444_LOCAL
,
101 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
102 #define fimc_fmt_is_jpeg(x) (!!((x) & 0x40))
104 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
105 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
107 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
108 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
110 /* The embedded image effect selection */
111 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
112 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
113 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
114 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
115 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
116 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
118 /* The hardware context state. */
119 #define FIMC_PARAMS (1 << 0)
120 #define FIMC_SRC_ADDR (1 << 1)
121 #define FIMC_DST_ADDR (1 << 2)
122 #define FIMC_SRC_FMT (1 << 3)
123 #define FIMC_DST_FMT (1 << 4)
124 #define FIMC_DST_CROP (1 << 5)
125 #define FIMC_CTX_M2M (1 << 16)
126 #define FIMC_CTX_CAP (1 << 17)
127 #define FIMC_CTX_SHUT (1 << 18)
129 /* Image conversion flags */
130 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
131 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
132 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
133 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
134 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
135 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
137 * YCbCr data dynamic range for RGB-YUV color conversion.
138 * Y/Cb/Cr: (0 ~ 255) */
139 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
140 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
141 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
144 * struct fimc_fmt - the driver's internal color format data
145 * @mbus_code: Media Bus pixel code, -1 if not applicable
146 * @name: format description
147 * @fourcc: the fourcc code for this format, 0 if not applicable
148 * @color: the corresponding fimc_color_fmt
149 * @memplanes: number of physically non-contiguous data planes
150 * @colplanes: number of physically contiguous data planes
151 * @depth: per plane driver's private 'number of bits per pixel'
152 * @flags: flags indicating which operation mode format applies to
155 enum v4l2_mbus_pixelcode mbus_code
;
161 u8 depth
[VIDEO_MAX_PLANES
];
163 #define FMT_FLAGS_CAM (1 << 0)
164 #define FMT_FLAGS_M2M (1 << 1)
168 * struct fimc_dma_offset - pixel offset information for DMA
169 * @y_h: y value horizontal offset
170 * @y_v: y value vertical offset
171 * @cb_h: cb value horizontal offset
172 * @cb_v: cb value vertical offset
173 * @cr_h: cr value horizontal offset
174 * @cr_v: cr value vertical offset
176 struct fimc_dma_offset
{
186 * struct fimc_effect - color effect information
188 * @pat_cb: cr value when type is "arbitrary"
189 * @pat_cr: cr value when type is "arbitrary"
198 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
199 * @scaleup_h: flag indicating scaling up horizontally
200 * @scaleup_v: flag indicating scaling up vertically
201 * @copy_mode: flag indicating transparent DMA transfer (no scaling
202 * and color format conversion)
203 * @enabled: flag indicating if the scaler is used
204 * @hfactor: horizontal shift factor
205 * @vfactor: vertical shift factor
206 * @pre_hratio: horizontal ratio of the prescaler
207 * @pre_vratio: vertical ratio of the prescaler
208 * @pre_dst_width: the prescaler's destination width
209 * @pre_dst_height: the prescaler's destination height
210 * @main_hratio: the main scaler's horizontal ratio
211 * @main_vratio: the main scaler's vertical ratio
212 * @real_width: source pixel (width - offset)
213 * @real_height: source pixel (height - offset)
216 unsigned int scaleup_h
:1;
217 unsigned int scaleup_v
:1;
218 unsigned int copy_mode
:1;
219 unsigned int enabled
:1;
233 * struct fimc_addr - the FIMC physical address set for DMA
234 * @y: luminance plane physical address
235 * @cb: Cb plane physical address
236 * @cr: Cr plane physical address
245 * struct fimc_vid_buffer - the driver's video buffer
246 * @vb: v4l videobuf buffer
247 * @list: linked list structure for buffer queue
248 * @paddr: precalculated physical address set
249 * @index: buffer index for the output DMA engine
251 struct fimc_vid_buffer
{
252 struct vb2_buffer vb
;
253 struct list_head list
;
254 struct fimc_addr paddr
;
259 * struct fimc_frame - source/target frame properties
260 * @f_width: image full width (virtual screen size)
261 * @f_height: image full height (virtual screen size)
262 * @o_width: original image width as set by S_FMT
263 * @o_height: original image height as set by S_FMT
264 * @offs_h: image horizontal pixel offset
265 * @offs_v: image vertical pixel offset
266 * @width: image pixel width
267 * @height: image pixel weight
268 * @payload: image size in bytes (w x h x bpp)
269 * @paddr: image frame buffer physical addresses
270 * @dma_offset: DMA offset in bytes
271 * @fmt: fimc color format pointer
282 unsigned long payload
[VIDEO_MAX_PLANES
];
283 struct fimc_addr paddr
;
284 struct fimc_dma_offset dma_offset
;
285 struct fimc_fmt
*fmt
;
289 * struct fimc_m2m_device - v4l2 memory-to-memory device data
290 * @vfd: the video device node for v4l2 m2m mode
291 * @m2m_dev: v4l2 memory-to-memory device data
292 * @ctx: hardware context data
293 * @refcnt: the reference counter
295 struct fimc_m2m_device
{
296 struct video_device
*vfd
;
297 struct v4l2_m2m_dev
*m2m_dev
;
298 struct fimc_ctx
*ctx
;
302 #define FIMC_SD_PAD_SINK 0
303 #define FIMC_SD_PAD_SOURCE 1
304 #define FIMC_SD_PADS_NUM 2
307 * struct fimc_vid_cap - camera capture device information
308 * @ctx: hardware context data
309 * @vfd: video device node for camera capture mode
310 * @subdev: subdev exposing the FIMC processing block
311 * @vd_pad: fimc video capture node pad
312 * @sd_pads: fimc video processing block pads
313 * @mf: media bus format at the FIMC camera input (and the scaler output) pad
314 * @pending_buf_q: the pending buffer queue head
315 * @active_buf_q: the queue head of buffers scheduled in hardware
316 * @vbq: the capture am video buffer queue
317 * @active_buf_cnt: number of video buffers scheduled in hardware
318 * @buf_index: index for managing the output DMA buffers
319 * @frame_count: the frame counter for statistics
320 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
321 * @input_index: input (camera sensor) index
322 * @refcnt: driver's private reference counter
323 * @input: capture input type, grp_id of the attached subdev
324 * @user_subdev_api: true if subdevs are not configured by the host driver
326 struct fimc_vid_cap
{
327 struct fimc_ctx
*ctx
;
328 struct vb2_alloc_ctx
*alloc_ctx
;
329 struct video_device
*vfd
;
330 struct v4l2_subdev
*subdev
;
331 struct media_pad vd_pad
;
332 struct v4l2_mbus_framefmt mf
;
333 struct media_pad sd_pads
[FIMC_SD_PADS_NUM
];
334 struct list_head pending_buf_q
;
335 struct list_head active_buf_q
;
336 struct vb2_queue vbq
;
339 unsigned int frame_count
;
340 unsigned int reqbufs_count
;
344 bool user_subdev_api
;
348 * struct fimc_pix_limit - image pixel size limits in various IP configurations
350 * @scaler_en_w: max input pixel width when the scaler is enabled
351 * @scaler_dis_w: max input pixel width when the scaler is disabled
352 * @in_rot_en_h: max input width with the input rotator is on
353 * @in_rot_dis_w: max input width with the input rotator is off
354 * @out_rot_en_w: max output width with the output rotator on
355 * @out_rot_dis_w: max output width with the output rotator off
357 struct fimc_pix_limit
{
367 * struct samsung_fimc_variant - camera interface variant information
369 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
370 * @has_inp_rot: set if has input rotator
371 * @has_out_rot: set if has output rotator
372 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
373 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
374 * are present in this IP revision
375 * @has_cam_if: set if this instance has a camera input interface
376 * @pix_limit: pixel size constraints for the scaler
377 * @min_inp_pixsize: minimum input pixel size
378 * @min_out_pixsize: minimum output pixel size
379 * @hor_offs_align: horizontal pixel offset aligment
380 * @min_vsize_align: minimum vertical pixel size alignment
381 * @out_buf_count: the number of buffers in output DMA sequence
383 struct samsung_fimc_variant
{
384 unsigned int pix_hoff
:1;
385 unsigned int has_inp_rot
:1;
386 unsigned int has_out_rot
:1;
387 unsigned int has_cistatus2
:1;
388 unsigned int has_mainscaler_ext
:1;
389 unsigned int has_cam_if
:1;
390 struct fimc_pix_limit
*pix_limit
;
399 * struct samsung_fimc_driverdata - per device type driver data for init time.
401 * @variant: the variant information for this driver.
402 * @dev_cnt: number of fimc sub-devices available in SoC
403 * @lclk_frequency: fimc bus clock frequency
405 struct samsung_fimc_driverdata
{
406 struct samsung_fimc_variant
*variant
[FIMC_MAX_DEVS
];
407 unsigned long lclk_frequency
;
411 struct fimc_pipeline
{
412 struct media_pipeline
*pipe
;
413 struct v4l2_subdev
*sensor
;
414 struct v4l2_subdev
*csis
;
420 * struct fimc_dev - abstraction for FIMC entity
421 * @slock: the spinlock protecting this data structure
422 * @lock: the mutex protecting this data structure
423 * @pdev: pointer to the FIMC platform device
424 * @pdata: pointer to the device platform data
425 * @variant: the IP variant information
426 * @id: FIMC device index (0..FIMC_MAX_DEVS)
427 * @num_clocks: the number of clocks managed by this device instance
428 * @clock: clocks required for FIMC operation
429 * @regs: the mapped hardware registers
430 * @regs_res: the resource claimed for IO registers
431 * @irq: FIMC interrupt number
432 * @irq_queue: interrupt handler waitqueue
433 * @v4l2_dev: root v4l2_device
434 * @m2m: memory-to-memory V4L2 device information
435 * @vid_cap: camera capture device information
436 * @state: flags used to synchronize m2m and capture mode operation
437 * @alloc_ctx: videobuf2 memory allocator context
438 * @pipeline: fimc video capture pipeline data structure
443 struct platform_device
*pdev
;
444 struct s5p_platform_fimc
*pdata
;
445 struct samsung_fimc_variant
*variant
;
448 struct clk
*clock
[MAX_FIMC_CLOCKS
];
450 struct resource
*regs_res
;
452 wait_queue_head_t irq_queue
;
453 struct v4l2_device
*v4l2_dev
;
454 struct fimc_m2m_device m2m
;
455 struct fimc_vid_cap vid_cap
;
457 struct vb2_alloc_ctx
*alloc_ctx
;
458 struct fimc_pipeline pipeline
;
462 * fimc_ctx - the device context data
463 * @slock: spinlock protecting this data structure
464 * @s_frame: source frame properties
465 * @d_frame: destination frame properties
466 * @out_order_1p: output 1-plane YCBCR order
467 * @out_order_2p: output 2-plane YCBCR order
468 * @in_order_1p input 1-plane YCBCR order
469 * @in_order_2p: input 2-plane YCBCR order
470 * @in_path: input mode (DMA or camera)
471 * @out_path: output mode (DMA or FIFO)
472 * @scaler: image scaler properties
473 * @effect: image effect
474 * @rotation: image clockwise rotation in degrees
475 * @hflip: indicates image horizontal flip if set
476 * @vflip: indicates image vertical flip if set
477 * @flags: additional flags for image conversion
478 * @state: flags to keep track of user configuration
479 * @fimc_dev: the FIMC device this context applies to
480 * @m2m_ctx: memory-to-memory device context
481 * @fh: v4l2 file handle
482 * @ctrl_handler: v4l2 controls handler
483 * @ctrl_rotate image rotation control
484 * @ctrl_hflip horizontal flip control
485 * @ctrl_vflip vartical flip control
486 * @ctrls_rdy: true if the control handler is initialized
490 struct fimc_frame s_frame
;
491 struct fimc_frame d_frame
;
496 enum fimc_datapath in_path
;
497 enum fimc_datapath out_path
;
498 struct fimc_scaler scaler
;
499 struct fimc_effect effect
;
501 unsigned int hflip
:1;
502 unsigned int vflip
:1;
505 struct fimc_dev
*fimc_dev
;
506 struct v4l2_m2m_ctx
*m2m_ctx
;
508 struct v4l2_ctrl_handler ctrl_handler
;
509 struct v4l2_ctrl
*ctrl_rotate
;
510 struct v4l2_ctrl
*ctrl_hflip
;
511 struct v4l2_ctrl
*ctrl_vflip
;
515 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
517 static inline void set_frame_bounds(struct fimc_frame
*f
, u32 width
, u32 height
)
520 f
->o_height
= height
;
522 f
->f_height
= height
;
525 static inline void set_frame_crop(struct fimc_frame
*f
,
526 u32 left
, u32 top
, u32 width
, u32 height
)
534 static inline u32
fimc_get_format_depth(struct fimc_fmt
*ff
)
539 for (i
= 0; i
< ff
->colplanes
; i
++)
540 depth
+= ff
->depth
[i
];
544 static inline bool fimc_capture_active(struct fimc_dev
*fimc
)
549 spin_lock_irqsave(&fimc
->slock
, flags
);
550 ret
= !!(fimc
->state
& (1 << ST_CAPT_RUN
) ||
551 fimc
->state
& (1 << ST_CAPT_PEND
));
552 spin_unlock_irqrestore(&fimc
->slock
, flags
);
556 static inline void fimc_ctx_state_lock_set(u32 state
, struct fimc_ctx
*ctx
)
560 spin_lock_irqsave(&ctx
->slock
, flags
);
562 spin_unlock_irqrestore(&ctx
->slock
, flags
);
565 static inline bool fimc_ctx_state_is_set(u32 mask
, struct fimc_ctx
*ctx
)
570 spin_lock_irqsave(&ctx
->slock
, flags
);
571 ret
= (ctx
->state
& mask
) == mask
;
572 spin_unlock_irqrestore(&ctx
->slock
, flags
);
576 static inline int tiled_fmt(struct fimc_fmt
*fmt
)
578 return fmt
->fourcc
== V4L2_PIX_FMT_NV12MT
;
581 static inline void fimc_hw_clear_irq(struct fimc_dev
*dev
)
583 u32 cfg
= readl(dev
->regs
+ S5P_CIGCTRL
);
584 cfg
|= S5P_CIGCTRL_IRQ_CLR
;
585 writel(cfg
, dev
->regs
+ S5P_CIGCTRL
);
588 static inline void fimc_hw_enable_scaler(struct fimc_dev
*dev
, bool on
)
590 u32 cfg
= readl(dev
->regs
+ S5P_CISCCTRL
);
592 cfg
|= S5P_CISCCTRL_SCALERSTART
;
594 cfg
&= ~S5P_CISCCTRL_SCALERSTART
;
595 writel(cfg
, dev
->regs
+ S5P_CISCCTRL
);
598 static inline void fimc_hw_activate_input_dma(struct fimc_dev
*dev
, bool on
)
600 u32 cfg
= readl(dev
->regs
+ S5P_MSCTRL
);
602 cfg
|= S5P_MSCTRL_ENVID
;
604 cfg
&= ~S5P_MSCTRL_ENVID
;
605 writel(cfg
, dev
->regs
+ S5P_MSCTRL
);
608 static inline void fimc_hw_dis_capture(struct fimc_dev
*dev
)
610 u32 cfg
= readl(dev
->regs
+ S5P_CIIMGCPT
);
611 cfg
&= ~(S5P_CIIMGCPT_IMGCPTEN
| S5P_CIIMGCPT_IMGCPTEN_SC
);
612 writel(cfg
, dev
->regs
+ S5P_CIIMGCPT
);
616 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
617 * @mask: each bit corresponds to one of 32 output buffer registers set
618 * 1 to include buffer in the sequence, 0 to disable
620 * This function mask output DMA ring buffers, i.e. it allows to configure
621 * which of the output buffer address registers will be used by the DMA
624 static inline void fimc_hw_set_dma_seq(struct fimc_dev
*dev
, u32 mask
)
626 writel(mask
, dev
->regs
+ S5P_CIFCNTSEQ
);
629 static inline struct fimc_frame
*ctx_get_frame(struct fimc_ctx
*ctx
,
630 enum v4l2_buf_type type
)
632 struct fimc_frame
*frame
;
634 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
== type
) {
635 if (fimc_ctx_state_is_set(FIMC_CTX_M2M
, ctx
))
636 frame
= &ctx
->s_frame
;
638 return ERR_PTR(-EINVAL
);
639 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
== type
) {
640 frame
= &ctx
->d_frame
;
642 v4l2_err(ctx
->fimc_dev
->v4l2_dev
,
643 "Wrong buffer/video queue type (%d)\n", type
);
644 return ERR_PTR(-EINVAL
);
650 /* Return an index to the buffer actually being written. */
651 static inline u32
fimc_hw_get_frame_index(struct fimc_dev
*dev
)
655 if (dev
->variant
->has_cistatus2
) {
656 reg
= readl(dev
->regs
+ S5P_CISTATUS2
) & 0x3F;
657 return reg
> 0 ? --reg
: reg
;
659 reg
= readl(dev
->regs
+ S5P_CISTATUS
);
660 return (reg
& S5P_CISTATUS_FRAMECNT_MASK
) >>
661 S5P_CISTATUS_FRAMECNT_SHIFT
;
665 /* -----------------------------------------------------*/
667 void fimc_hw_reset(struct fimc_dev
*fimc
);
668 void fimc_hw_set_rotation(struct fimc_ctx
*ctx
);
669 void fimc_hw_set_target_format(struct fimc_ctx
*ctx
);
670 void fimc_hw_set_out_dma(struct fimc_ctx
*ctx
);
671 void fimc_hw_en_lastirq(struct fimc_dev
*fimc
, int enable
);
672 void fimc_hw_en_irq(struct fimc_dev
*fimc
, int enable
);
673 void fimc_hw_set_prescaler(struct fimc_ctx
*ctx
);
674 void fimc_hw_set_mainscaler(struct fimc_ctx
*ctx
);
675 void fimc_hw_en_capture(struct fimc_ctx
*ctx
);
676 void fimc_hw_set_effect(struct fimc_ctx
*ctx
, bool active
);
677 void fimc_hw_set_in_dma(struct fimc_ctx
*ctx
);
678 void fimc_hw_set_input_path(struct fimc_ctx
*ctx
);
679 void fimc_hw_set_output_path(struct fimc_ctx
*ctx
);
680 void fimc_hw_set_input_addr(struct fimc_dev
*fimc
, struct fimc_addr
*paddr
);
681 void fimc_hw_set_output_addr(struct fimc_dev
*fimc
, struct fimc_addr
*paddr
,
683 int fimc_hw_set_camera_source(struct fimc_dev
*fimc
,
684 struct s5p_fimc_isp_info
*cam
);
685 int fimc_hw_set_camera_offset(struct fimc_dev
*fimc
, struct fimc_frame
*f
);
686 int fimc_hw_set_camera_polarity(struct fimc_dev
*fimc
,
687 struct s5p_fimc_isp_info
*cam
);
688 int fimc_hw_set_camera_type(struct fimc_dev
*fimc
,
689 struct s5p_fimc_isp_info
*cam
);
691 /* -----------------------------------------------------*/
693 int fimc_vidioc_enum_fmt_mplane(struct file
*file
, void *priv
,
694 struct v4l2_fmtdesc
*f
);
695 int fimc_ctrls_create(struct fimc_ctx
*ctx
);
696 void fimc_ctrls_delete(struct fimc_ctx
*ctx
);
697 void fimc_ctrls_activate(struct fimc_ctx
*ctx
, bool active
);
698 int fimc_fill_format(struct fimc_frame
*frame
, struct v4l2_format
*f
);
699 void fimc_adjust_mplane_format(struct fimc_fmt
*fmt
, u32 width
, u32 height
,
700 struct v4l2_pix_format_mplane
*pix
);
701 struct fimc_fmt
*fimc_find_format(u32
*pixelformat
, u32
*mbus_code
,
702 unsigned int mask
, int index
);
704 int fimc_check_scaler_ratio(struct fimc_ctx
*ctx
, int sw
, int sh
,
705 int dw
, int dh
, int rotation
);
706 int fimc_set_scaler_info(struct fimc_ctx
*ctx
);
707 int fimc_prepare_config(struct fimc_ctx
*ctx
, u32 flags
);
708 int fimc_prepare_addr(struct fimc_ctx
*ctx
, struct vb2_buffer
*vb
,
709 struct fimc_frame
*frame
, struct fimc_addr
*paddr
);
710 void fimc_prepare_dma_offset(struct fimc_ctx
*ctx
, struct fimc_frame
*f
);
711 void fimc_set_yuv_order(struct fimc_ctx
*ctx
);
712 void fimc_fill_frame(struct fimc_frame
*frame
, struct v4l2_format
*f
);
713 void fimc_capture_irq_handler(struct fimc_dev
*fimc
, bool done
);
715 int fimc_register_m2m_device(struct fimc_dev
*fimc
,
716 struct v4l2_device
*v4l2_dev
);
717 void fimc_unregister_m2m_device(struct fimc_dev
*fimc
);
718 int fimc_register_driver(void);
719 void fimc_unregister_driver(void);
721 /* -----------------------------------------------------*/
723 int fimc_register_capture_device(struct fimc_dev
*fimc
,
724 struct v4l2_device
*v4l2_dev
);
725 void fimc_unregister_capture_device(struct fimc_dev
*fimc
);
726 int fimc_capture_ctrls_create(struct fimc_dev
*fimc
);
727 int fimc_vid_cap_buf_queue(struct fimc_dev
*fimc
,
728 struct fimc_vid_buffer
*fimc_vb
);
729 void fimc_sensor_notify(struct v4l2_subdev
*sd
, unsigned int notification
,
731 int fimc_capture_suspend(struct fimc_dev
*fimc
);
732 int fimc_capture_resume(struct fimc_dev
*fimc
);
733 int fimc_capture_config_update(struct fimc_ctx
*ctx
);
735 /* Locking: the caller holds fimc->slock */
736 static inline void fimc_activate_capture(struct fimc_ctx
*ctx
)
738 fimc_hw_enable_scaler(ctx
->fimc_dev
, ctx
->scaler
.enabled
);
739 fimc_hw_en_capture(ctx
);
742 static inline void fimc_deactivate_capture(struct fimc_dev
*fimc
)
744 fimc_hw_en_lastirq(fimc
, true);
745 fimc_hw_dis_capture(fimc
);
746 fimc_hw_enable_scaler(fimc
, false);
747 fimc_hw_en_lastirq(fimc
, false);
751 * Buffer list manipulation functions. Must be called with fimc.slock held.
755 * fimc_active_queue_add - add buffer to the capture active buffers queue
756 * @buf: buffer to add to the active buffers list
758 static inline void fimc_active_queue_add(struct fimc_vid_cap
*vid_cap
,
759 struct fimc_vid_buffer
*buf
)
761 list_add_tail(&buf
->list
, &vid_cap
->active_buf_q
);
762 vid_cap
->active_buf_cnt
++;
766 * fimc_active_queue_pop - pop buffer from the capture active buffers queue
768 * The caller must assure the active_buf_q list is not empty.
770 static inline struct fimc_vid_buffer
*fimc_active_queue_pop(
771 struct fimc_vid_cap
*vid_cap
)
773 struct fimc_vid_buffer
*buf
;
774 buf
= list_entry(vid_cap
->active_buf_q
.next
,
775 struct fimc_vid_buffer
, list
);
776 list_del(&buf
->list
);
777 vid_cap
->active_buf_cnt
--;
782 * fimc_pending_queue_add - add buffer to the capture pending buffers queue
783 * @buf: buffer to add to the pending buffers list
785 static inline void fimc_pending_queue_add(struct fimc_vid_cap
*vid_cap
,
786 struct fimc_vid_buffer
*buf
)
788 list_add_tail(&buf
->list
, &vid_cap
->pending_buf_q
);
792 * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
794 * The caller must assure the pending_buf_q list is not empty.
796 static inline struct fimc_vid_buffer
*fimc_pending_queue_pop(
797 struct fimc_vid_cap
*vid_cap
)
799 struct fimc_vid_buffer
*buf
;
800 buf
= list_entry(vid_cap
->pending_buf_q
.next
,
801 struct fimc_vid_buffer
, list
);
802 list_del(&buf
->list
);
806 #endif /* FIMC_CORE_H_ */