drivers/media/video/s5p-fimc/fimc-core.h

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics
   3  *
   4  * Sylwester Nawrocki, <s.nawrocki@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef FIMC_CORE_H_
  12 #define FIMC_CORE_H_
  13
  14 /*#define DEBUG*/
  15
  16 #include <linux/types.h>
  17 #include <media/videobuf-core.h>
  18 #include <media/v4l2-device.h>
  19 #include <media/v4l2-mem2mem.h>
  20 #include <media/v4l2-mediabus.h>
  21 #include <media/s3c_fimc.h>
  22 #include <linux/videodev2.h>
  23 #include "regs-fimc.h"
  24
  25 #define err(fmt, args...) \
  26         printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  27
  28 #ifdef DEBUG
  29 #define dbg(fmt, args...) \
  30         printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  31 #else
  32 #define dbg(fmt, args...)
  33 #endif
  34
  35 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
  36 #define FIMC_SHUTDOWN_TIMEOUT   ((100*HZ)/1000)
  37 #define NUM_FIMC_CLOCKS         2
  38 #define MODULE_NAME             "s5p-fimc"
  39 #define FIMC_MAX_DEVS           4
  40 #define FIMC_MAX_OUT_BUFS       4
  41 #define SCALER_MAX_HRATIO       64
  42 #define SCALER_MAX_VRATIO       64
  43 #define DMA_MIN_SIZE            8
  44
  45 /* FIMC device state flags */
  46 enum fimc_dev_flags {
  47         /* for m2m node */
  48         ST_IDLE,
  49         ST_OUTDMA_RUN,
  50         ST_M2M_PEND,
  51         /* for capture node */
  52         ST_CAPT_PEND,
  53         ST_CAPT_RUN,
  54         ST_CAPT_STREAM,
  55         ST_CAPT_SHUT,
  56 };
  57
  58 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
  59 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
  60
  61 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
  62 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
  63
  64 #define fimc_capture_active(dev) \
  65         (test_bit(ST_CAPT_RUN, &(dev)->state) || \
  66          test_bit(ST_CAPT_PEND, &(dev)->state))
  67
  68 #define fimc_capture_streaming(dev) \
  69         test_bit(ST_CAPT_STREAM, &(dev)->state)
  70
  71 #define fimc_buf_finish(dev, vid_buf) do { \
  72         spin_lock(&(dev)->irqlock); \
  73         (vid_buf)->vb.state = VIDEOBUF_DONE; \
  74         spin_unlock(&(dev)->irqlock); \
  75         wake_up(&(vid_buf)->vb.done); \
  76 } while (0)
  77
  78 enum fimc_datapath {
  79         FIMC_CAMERA,
  80         FIMC_DMA,
  81         FIMC_LCDFIFO,
  82         FIMC_WRITEBACK
  83 };
  84
  85 enum fimc_color_fmt {
  86         S5P_FIMC_RGB565 = 0x10,
  87         S5P_FIMC_RGB666,
  88         S5P_FIMC_RGB888,
  89         S5P_FIMC_RGB30_LOCAL,
  90         S5P_FIMC_YCBCR420 = 0x20,
  91         S5P_FIMC_YCBCR422,
  92         S5P_FIMC_YCBYCR422,
  93         S5P_FIMC_YCRYCB422,
  94         S5P_FIMC_CBYCRY422,
  95         S5P_FIMC_CRYCBY422,
  96         S5P_FIMC_YCBCR444_LOCAL,
  97 };
  98
  99 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
 100
 101 /* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
 102 #define S5P_FIMC_OUT_CRYCBY     S5P_CIOCTRL_ORDER422_CRYCBY
 103 #define S5P_FIMC_OUT_CBYCRY     S5P_CIOCTRL_ORDER422_YCRYCB
 104 #define S5P_FIMC_OUT_YCRYCB     S5P_CIOCTRL_ORDER422_CBYCRY
 105 #define S5P_FIMC_OUT_YCBYCR     S5P_CIOCTRL_ORDER422_YCBYCR
 106
 107 /* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
 108 #define S5P_FIMC_IN_CRYCBY      S5P_MSCTRL_ORDER422_CRYCBY
 109 #define S5P_FIMC_IN_CBYCRY      S5P_MSCTRL_ORDER422_YCRYCB
 110 #define S5P_FIMC_IN_YCRYCB      S5P_MSCTRL_ORDER422_CBYCRY
 111 #define S5P_FIMC_IN_YCBYCR      S5P_MSCTRL_ORDER422_YCBYCR
 112
 113 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
 114 #define S5P_FIMC_LSB_CRCB       S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
 115
 116 /* The embedded image effect selection */
 117 #define S5P_FIMC_EFFECT_ORIGINAL        S5P_CIIMGEFF_FIN_BYPASS
 118 #define S5P_FIMC_EFFECT_ARBITRARY       S5P_CIIMGEFF_FIN_ARBITRARY
 119 #define S5P_FIMC_EFFECT_NEGATIVE        S5P_CIIMGEFF_FIN_NEGATIVE
 120 #define S5P_FIMC_EFFECT_ARTFREEZE       S5P_CIIMGEFF_FIN_ARTFREEZE
 121 #define S5P_FIMC_EFFECT_EMBOSSING       S5P_CIIMGEFF_FIN_EMBOSSING
 122 #define S5P_FIMC_EFFECT_SIKHOUETTE      S5P_CIIMGEFF_FIN_SILHOUETTE
 123
 124 /* The hardware context state. */
 125 #define FIMC_PARAMS             (1 << 0)
 126 #define FIMC_SRC_ADDR           (1 << 1)
 127 #define FIMC_DST_ADDR           (1 << 2)
 128 #define FIMC_SRC_FMT            (1 << 3)
 129 #define FIMC_DST_FMT            (1 << 4)
 130 #define FIMC_CTX_M2M            (1 << 5)
 131 #define FIMC_CTX_CAP            (1 << 6)
 132
 133 /* Image conversion flags */
 134 #define FIMC_IN_DMA_ACCESS_TILED        (1 << 0)
 135 #define FIMC_IN_DMA_ACCESS_LINEAR       (0 << 0)
 136 #define FIMC_OUT_DMA_ACCESS_TILED       (1 << 1)
 137 #define FIMC_OUT_DMA_ACCESS_LINEAR      (0 << 1)
 138 #define FIMC_SCAN_MODE_PROGRESSIVE      (0 << 2)
 139 #define FIMC_SCAN_MODE_INTERLACED       (1 << 2)
 140 /*
 141  * YCbCr data dynamic range for RGB-YUV color conversion.
 142  * Y/Cb/Cr: (0 ~ 255) */
 143 #define FIMC_COLOR_RANGE_WIDE           (0 << 3)
 144 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
 145 #define FIMC_COLOR_RANGE_NARROW         (1 << 3)
 146
 147 #define FLIP_NONE                       0
 148 #define FLIP_X_AXIS                     1
 149 #define FLIP_Y_AXIS                     2
 150 #define FLIP_XY_AXIS                    (FLIP_X_AXIS | FLIP_Y_AXIS)
 151
 152 /**
 153  * struct fimc_fmt - the driver's internal color format data
 154  * @mbus_code: Media Bus pixel code, -1 if not applicable
 155  * @name: format description
 156  * @fourcc: the fourcc code for this format, 0 if not applicable
 157  * @color: the corresponding fimc_color_fmt
 158  * @depth: driver's private 'number of bits per pixel'
 159  * @buff_cnt: number of physically non-contiguous data planes
 160  * @planes_cnt: number of physically contiguous data planes
 161  */
 162 struct fimc_fmt {
 163         enum v4l2_mbus_pixelcode mbus_code;
 164         char    *name;
 165         u32     fourcc;
 166         u32     color;
 167         u16     buff_cnt;
 168         u16     planes_cnt;
 169         u16     depth;
 170         u16     flags;
 171 #define FMT_FLAGS_CAM   (1 << 0)
 172 #define FMT_FLAGS_M2M   (1 << 1)
 173 };
 174
 175 /**
 176  * struct fimc_dma_offset - pixel offset information for DMA
 177  * @y_h:        y value horizontal offset
 178  * @y_v:        y value vertical offset
 179  * @cb_h:       cb value horizontal offset
 180  * @cb_v:       cb value vertical offset
 181  * @cr_h:       cr value horizontal offset
 182  * @cr_v:       cr value vertical offset
 183  */
 184 struct fimc_dma_offset {
 185         int     y_h;
 186         int     y_v;
 187         int     cb_h;
 188         int     cb_v;
 189         int     cr_h;
 190         int     cr_v;
 191 };
 192
 193 /**
 194  * struct fimc_effect - the configuration data for the "Arbitrary" image effect
 195  * @type:       effect type
 196  * @pat_cb:     cr value when type is "arbitrary"
 197  * @pat_cr:     cr value when type is "arbitrary"
 198  */
 199 struct fimc_effect {
 200         u32     type;
 201         u8      pat_cb;
 202         u8      pat_cr;
 203 };
 204
 205 /**
 206  * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 207  *
 208  * @scaleup_h:          flag indicating scaling up horizontally
 209  * @scaleup_v:          flag indicating scaling up vertically
 210  * @copy_mode:          flag indicating transparent DMA transfer (no scaling
 211  *                      and color format conversion)
 212  * @enabled:            flag indicating if the scaler is used
 213  * @hfactor:            horizontal shift factor
 214  * @vfactor:            vertical shift factor
 215  * @pre_hratio:         horizontal ratio of the prescaler
 216  * @pre_vratio:         vertical ratio of the prescaler
 217  * @pre_dst_width:      the prescaler's destination width
 218  * @pre_dst_height:     the prescaler's destination height
 219  * @main_hratio:        the main scaler's horizontal ratio
 220  * @main_vratio:        the main scaler's vertical ratio
 221  * @real_width:         source pixel (width - offset)
 222  * @real_height:        source pixel (height - offset)
 223  */
 224 struct fimc_scaler {
 225         int     scaleup_h:1;
 226         int     scaleup_v:1;
 227         int     copy_mode:1;
 228         int     enabled:1;
 229         u32     hfactor;
 230         u32     vfactor;
 231         u32     pre_hratio;
 232         u32     pre_vratio;
 233         u32     pre_dst_width;
 234         u32     pre_dst_height;
 235         u32     main_hratio;
 236         u32     main_vratio;
 237         u32     real_width;
 238         u32     real_height;
 239 };
 240
 241 /**
 242  * struct fimc_addr - the FIMC physical address set for DMA
 243  *
 244  * @y:   luminance plane physical address
 245  * @cb:  Cb plane physical address
 246  * @cr:  Cr plane physical address
 247  */
 248 struct fimc_addr {
 249         u32     y;
 250         u32     cb;
 251         u32     cr;
 252 };
 253
 254 /**
 255  * struct fimc_vid_buffer - the driver's video buffer
 256  * @vb:    v4l videobuf buffer
 257  * @paddr: precalculated physical address set
 258  * @index: buffer index for the output DMA engine
 259  */
 260 struct fimc_vid_buffer {
 261         struct videobuf_buffer  vb;
 262         struct fimc_addr        paddr;
 263         int                     index;
 264 };
 265
 266 /**
 267  * struct fimc_frame - source/target frame properties
 268  * @f_width:    image full width (virtual screen size)
 269  * @f_height:   image full height (virtual screen size)
 270  * @o_width:    original image width as set by S_FMT
 271  * @o_height:   original image height as set by S_FMT
 272  * @offs_h:     image horizontal pixel offset
 273  * @offs_v:     image vertical pixel offset
 274  * @width:      image pixel width
 275  * @height:     image pixel weight
 276  * @paddr:      image frame buffer physical addresses
 277  * @buf_cnt:    number of buffers depending on a color format
 278  * @size:       image size in bytes
 279  * @color:      color format
 280  * @dma_offset: DMA offset in bytes
 281  */
 282 struct fimc_frame {
 283         u32     f_width;
 284         u32     f_height;
 285         u32     o_width;
 286         u32     o_height;
 287         u32     offs_h;
 288         u32     offs_v;
 289         u32     width;
 290         u32     height;
 291         u32     size;
 292         struct fimc_addr        paddr;
 293         struct fimc_dma_offset  dma_offset;
 294         struct fimc_fmt         *fmt;
 295 };
 296
 297 /**
 298  * struct fimc_m2m_device - v4l2 memory-to-memory device data
 299  * @vfd: the video device node for v4l2 m2m mode
 300  * @v4l2_dev: v4l2 device for m2m mode
 301  * @m2m_dev: v4l2 memory-to-memory device data
 302  * @ctx: hardware context data
 303  * @refcnt: the reference counter
 304  */
 305 struct fimc_m2m_device {
 306         struct video_device     *vfd;
 307         struct v4l2_device      v4l2_dev;
 308         struct v4l2_m2m_dev     *m2m_dev;
 309         struct fimc_ctx         *ctx;
 310         int                     refcnt;
 311 };
 312
 313 /**
 314  * struct fimc_vid_cap - camera capture device information
 315  * @ctx: hardware context data
 316  * @vfd: video device node for camera capture mode
 317  * @v4l2_dev: v4l2_device struct to manage subdevs
 318  * @sd: pointer to camera sensor subdevice currently in use
 319  * @fmt: Media Bus format configured at selected image sensor
 320  * @pending_buf_q: the pending buffer queue head
 321  * @active_buf_q: the queue head of buffers scheduled in hardware
 322  * @vbq: the capture am video buffer queue
 323  * @active_buf_cnt: number of video buffers scheduled in hardware
 324  * @buf_index: index for managing the output DMA buffers
 325  * @frame_count: the frame counter for statistics
 326  * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
 327  * @input_index: input (camera sensor) index
 328  * @refcnt: driver's private reference counter
 329  */
 330 struct fimc_vid_cap {
 331         struct fimc_ctx                 *ctx;
 332         struct video_device             *vfd;
 333         struct v4l2_device              v4l2_dev;
 334         struct v4l2_subdev              *sd;
 335         struct v4l2_mbus_framefmt       fmt;
 336         struct list_head                pending_buf_q;
 337         struct list_head                active_buf_q;
 338         struct videobuf_queue           vbq;
 339         int                             active_buf_cnt;
 340         int                             buf_index;
 341         unsigned int                    frame_count;
 342         unsigned int                    reqbufs_count;
 343         int                             input_index;
 344         int                             refcnt;
 345 };
 346
 347 /**
 348  *  struct fimc_pix_limit - image pixel size limits in various IP configurations
 349  *
 350  *  @scaler_en_w: max input pixel width when the scaler is enabled
 351  *  @scaler_dis_w: max input pixel width when the scaler is disabled
 352  *  @in_rot_en_h: max input width with the input rotator is on
 353  *  @in_rot_dis_w: max input width with the input rotator is off
 354  *  @out_rot_en_w: max output width with the output rotator on
 355  *  @out_rot_dis_w: max output width with the output rotator off
 356  */
 357 struct fimc_pix_limit {
 358         u16 scaler_en_w;
 359         u16 scaler_dis_w;
 360         u16 in_rot_en_h;
 361         u16 in_rot_dis_w;
 362         u16 out_rot_en_w;
 363         u16 out_rot_dis_w;
 364 };
 365
 366 /**
 367  * struct samsung_fimc_variant - camera interface variant information
 368  *
 369  * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 370  * @has_inp_rot: set if has input rotator
 371  * @has_out_rot: set if has output rotator
 372  * @pix_limit: pixel size constraints for the scaler
 373  * @min_inp_pixsize: minimum input pixel size
 374  * @min_out_pixsize: minimum output pixel size
 375  * @hor_offs_align: horizontal pixel offset aligment
 376  * @out_buf_count: the number of buffers in output DMA sequence
 377  */
 378 struct samsung_fimc_variant {
 379         unsigned int    pix_hoff:1;
 380         unsigned int    has_inp_rot:1;
 381         unsigned int    has_out_rot:1;
 382         struct fimc_pix_limit *pix_limit;
 383         u16             min_inp_pixsize;
 384         u16             min_out_pixsize;
 385         u16             hor_offs_align;
 386         u16             out_buf_count;
 387 };
 388
 389 /**
 390  * struct samsung_fimc_driverdata - per device type driver data for init time.
 391  *
 392  * @variant: the variant information for this driver.
 393  * @dev_cnt: number of fimc sub-devices available in SoC
 394  * @lclk_frequency: fimc bus clock frequency
 395  */
 396 struct samsung_fimc_driverdata {
 397         struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
 398         unsigned long   lclk_frequency;
 399         int             num_entities;
 400 };
 401
 402 struct fimc_ctx;
 403
 404 /**
 405  * struct fimc_dev - abstraction for FIMC entity
 406  *
 407  * @slock:      the spinlock protecting this data structure
 408  * @lock:       the mutex protecting this data structure
 409  * @pdev:       pointer to the FIMC platform device
 410  * @pdata:      pointer to the device platform data
 411  * @id:         FIMC device index (0..2)
 412  * @clock[]:    the clocks required for FIMC operation
 413  * @regs:       the mapped hardware registers
 414  * @regs_res:   the resource claimed for IO registers
 415  * @irq:        interrupt number of the FIMC subdevice
 416  * @irqlock:    spinlock protecting videobuffer queue
 417  * @irq_queue:
 418  * @m2m:        memory-to-memory V4L2 device information
 419  * @vid_cap:    camera capture device information
 420  * @state:      flags used to synchronize m2m and capture mode operation
 421  */
 422 struct fimc_dev {
 423         spinlock_t                      slock;
 424         struct mutex                    lock;
 425         struct platform_device          *pdev;
 426         struct s3c_platform_fimc        *pdata;
 427         struct samsung_fimc_variant     *variant;
 428         int                             id;
 429         struct clk                      *clock[NUM_FIMC_CLOCKS];
 430         void __iomem                    *regs;
 431         struct resource                 *regs_res;
 432         int                             irq;
 433         spinlock_t                      irqlock;
 434         wait_queue_head_t               irq_queue;
 435         struct fimc_m2m_device          m2m;
 436         struct fimc_vid_cap             vid_cap;
 437         unsigned long                   state;
 438 };
 439
 440 /**
 441  * fimc_ctx - the device context data
 442  *
 443  * @lock:               mutex protecting this data structure
 444  * @s_frame:            source frame properties
 445  * @d_frame:            destination frame properties
 446  * @out_order_1p:       output 1-plane YCBCR order
 447  * @out_order_2p:       output 2-plane YCBCR order
 448  * @in_order_1p         input 1-plane YCBCR order
 449  * @in_order_2p:        input 2-plane YCBCR order
 450  * @in_path:            input mode (DMA or camera)
 451  * @out_path:           output mode (DMA or FIFO)
 452  * @scaler:             image scaler properties
 453  * @effect:             image effect
 454  * @rotation:           image clockwise rotation in degrees
 455  * @flip:               image flip mode
 456  * @flags:              additional flags for image conversion
 457  * @state:              flags to keep track of user configuration
 458  * @fimc_dev:           the FIMC device this context applies to
 459  * @m2m_ctx:            memory-to-memory device context
 460  */
 461 struct fimc_ctx {
 462         spinlock_t              slock;
 463         struct fimc_frame       s_frame;
 464         struct fimc_frame       d_frame;
 465         u32                     out_order_1p;
 466         u32                     out_order_2p;
 467         u32                     in_order_1p;
 468         u32                     in_order_2p;
 469         enum fimc_datapath      in_path;
 470         enum fimc_datapath      out_path;
 471         struct fimc_scaler      scaler;
 472         struct fimc_effect      effect;
 473         int                     rotation;
 474         u32                     flip;
 475         u32                     flags;
 476         u32                     state;
 477         struct fimc_dev         *fimc_dev;
 478         struct v4l2_m2m_ctx     *m2m_ctx;
 479 };
 480
 481 extern struct videobuf_queue_ops fimc_qops;
 482
 483 static inline int tiled_fmt(struct fimc_fmt *fmt)
 484 {
 485         return 0;
 486 }
 487
 488 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
 489 {
 490         u32 cfg = readl(dev->regs + S5P_CIGCTRL);
 491         cfg |= S5P_CIGCTRL_IRQ_CLR;
 492         writel(cfg, dev->regs + S5P_CIGCTRL);
 493 }
 494
 495 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
 496 {
 497         u32 cfg = readl(dev->regs + S5P_CISCCTRL);
 498         if (on)
 499                 cfg |= S5P_CISCCTRL_SCALERSTART;
 500         else
 501                 cfg &= ~S5P_CISCCTRL_SCALERSTART;
 502         writel(cfg, dev->regs + S5P_CISCCTRL);
 503 }
 504
 505 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
 506 {
 507         u32 cfg = readl(dev->regs + S5P_MSCTRL);
 508         if (on)
 509                 cfg |= S5P_MSCTRL_ENVID;
 510         else
 511                 cfg &= ~S5P_MSCTRL_ENVID;
 512         writel(cfg, dev->regs + S5P_MSCTRL);
 513 }
 514
 515 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
 516 {
 517         u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
 518         cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
 519         writel(cfg, dev->regs + S5P_CIIMGCPT);
 520 }
 521
 522 /**
 523  * fimc_hw_set_dma_seq - configure output DMA buffer sequence
 524  * @mask: each bit corresponds to one of 32 output buffer registers set
 525  *        1 to include buffer in the sequence, 0 to disable
 526  *
 527  * This function mask output DMA ring buffers, i.e. it allows to configure
 528  * which of the output buffer address registers will be used by the DMA
 529  * engine.
 530  */
 531 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
 532 {
 533         writel(mask, dev->regs + S5P_CIFCNTSEQ);
 534 }
 535
 536 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
 537                                                enum v4l2_buf_type type)
 538 {
 539         struct fimc_frame *frame;
 540
 541         if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type) {
 542                 if (ctx->state & FIMC_CTX_M2M)
 543                         frame = &ctx->s_frame;
 544                 else
 545                         return ERR_PTR(-EINVAL);
 546         } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type) {
 547                 frame = &ctx->d_frame;
 548         } else {
 549                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
 550                         "Wrong buffer/video queue type (%d)\n", type);
 551                 return ERR_PTR(-EINVAL);
 552         }
 553
 554         return frame;
 555 }
 556
 557 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
 558 {
 559         u32 reg = readl(dev->regs + S5P_CISTATUS);
 560         return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
 561                 S5P_CISTATUS_FRAMECNT_SHIFT;
 562 }
 563
 564 /* -----------------------------------------------------*/
 565 /* fimc-reg.c                                           */
 566 void fimc_hw_reset(struct fimc_dev *fimc);
 567 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
 568 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
 569 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
 570 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
 571 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
 572 void fimc_hw_set_scaler(struct fimc_ctx *ctx);
 573 void fimc_hw_en_capture(struct fimc_ctx *ctx);
 574 void fimc_hw_set_effect(struct fimc_ctx *ctx);
 575 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
 576 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
 577 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
 578 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
 579 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
 580                               int index);
 581 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 582                               struct s3c_fimc_isp_info *cam);
 583 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
 584 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
 585                                 struct s3c_fimc_isp_info *cam);
 586 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 587                             struct s3c_fimc_isp_info *cam);
 588
 589 /* -----------------------------------------------------*/
 590 /* fimc-core.c */
 591 int fimc_vidioc_enum_fmt(struct file *file, void *priv,
 592                       struct v4l2_fmtdesc *f);
 593 int fimc_vidioc_g_fmt(struct file *file, void *priv,
 594                       struct v4l2_format *f);
 595 int fimc_vidioc_try_fmt(struct file *file, void *priv,
 596                         struct v4l2_format *f);
 597 int fimc_vidioc_g_crop(struct file *file, void *fh,
 598                        struct v4l2_crop *cr);
 599 int fimc_vidioc_cropcap(struct file *file, void *fh,
 600                         struct v4l2_cropcap *cr);
 601 int fimc_vidioc_queryctrl(struct file *file, void *priv,
 602                           struct v4l2_queryctrl *qc);
 603 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
 604                        struct v4l2_control *ctrl);
 605
 606 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
 607 int check_ctrl_val(struct fimc_ctx *ctx,  struct v4l2_control *ctrl);
 608 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
 609
 610 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
 611 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
 612                                   unsigned int mask);
 613
 614 int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f);
 615 int fimc_set_scaler_info(struct fimc_ctx *ctx);
 616 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
 617 int fimc_prepare_addr(struct fimc_ctx *ctx, struct fimc_vid_buffer *buf,
 618                       struct fimc_frame *frame, struct fimc_addr *paddr);
 619
 620 /* -----------------------------------------------------*/
 621 /* fimc-capture.c                                       */
 622 int fimc_register_capture_device(struct fimc_dev *fimc);
 623 void fimc_unregister_capture_device(struct fimc_dev *fimc);
 624 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
 625 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
 626                              struct fimc_vid_buffer *fimc_vb);
 627
 628 /* Locking: the caller holds fimc->slock */
 629 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
 630 {
 631         fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
 632         fimc_hw_en_capture(ctx);
 633 }
 634
 635 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
 636 {
 637         fimc_hw_en_lastirq(fimc, true);
 638         fimc_hw_dis_capture(fimc);
 639         fimc_hw_enable_scaler(fimc, false);
 640         fimc_hw_en_lastirq(fimc, false);
 641 }
 642
 643 /*
 644  * Add video buffer to the active buffers queue.
 645  * The caller holds irqlock spinlock.
 646  */
 647 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
 648                                          struct fimc_vid_buffer *buf)
 649 {
 650         buf->vb.state = VIDEOBUF_ACTIVE;
 651         list_add_tail(&buf->vb.queue, &vid_cap->active_buf_q);
 652         vid_cap->active_buf_cnt++;
 653 }
 654
 655 /*
 656  * Pop a video buffer from the capture active buffers queue
 657  * Locking: Need to be called with dev->slock held.
 658  */
 659 static inline struct fimc_vid_buffer *
 660 active_queue_pop(struct fimc_vid_cap *vid_cap)
 661 {
 662         struct fimc_vid_buffer *buf;
 663         buf = list_entry(vid_cap->active_buf_q.next,
 664                          struct fimc_vid_buffer, vb.queue);
 665         list_del(&buf->vb.queue);
 666         vid_cap->active_buf_cnt--;
 667         return buf;
 668 }
 669
 670 /* Add video buffer to the capture pending buffers queue */
 671 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
 672                                           struct fimc_vid_buffer *buf)
 673 {
 674         buf->vb.state = VIDEOBUF_QUEUED;
 675         list_add_tail(&buf->vb.queue, &vid_cap->pending_buf_q);
 676 }
 677
 678 /* Add video buffer to the capture pending buffers queue */
 679 static inline struct fimc_vid_buffer *
 680 pending_queue_pop(struct fimc_vid_cap *vid_cap)
 681 {
 682         struct fimc_vid_buffer *buf;
 683         buf = list_entry(vid_cap->pending_buf_q.next,
 684                         struct fimc_vid_buffer, vb.queue);
 685         list_del(&buf->vb.queue);
 686         return buf;
 687 }
 688
 689
 690 #endif /* FIMC_CORE_H_ */