drivers/media/video/s5p-fimc/fimc-core.h

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics
   3  *
   4  * Sylwester Nawrocki, <s.nawrocki@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef FIMC_CORE_H_
  12 #define FIMC_CORE_H_
  13
  14 #include <linux/types.h>
  15 #include <media/videobuf-core.h>
  16 #include <media/v4l2-device.h>
  17 #include <media/v4l2-mem2mem.h>
  18 #include <linux/videodev2.h>
  19 #include "regs-fimc.h"
  20
  21 #define err(fmt, args...) \
  22         printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  23
  24 #ifdef DEBUG
  25 #define dbg(fmt, args...) \
  26         printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  27 #else
  28 #define dbg(fmt, args...)
  29 #endif
  30
  31 #define ctx_m2m_get_frame(frame, ctx, type) do { \
  32         if (V4L2_BUF_TYPE_VIDEO_OUTPUT == (type)) { \
  33                 frame = &(ctx)->s_frame; \
  34         } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == (type)) { \
  35                 frame = &(ctx)->d_frame; \
  36         } else { \
  37                 v4l2_err(&(ctx)->fimc_dev->m2m.v4l2_dev,\
  38                         "Wrong buffer/video queue type (%d)\n", type); \
  39                 return -EINVAL; \
  40         } \
  41 } while (0)
  42
  43 #define NUM_FIMC_CLOCKS         2
  44 #define MODULE_NAME             "s5p-fimc"
  45 #define FIMC_MAX_DEVS           3
  46 #define FIMC_MAX_OUT_BUFS       4
  47 #define SCALER_MAX_HRATIO       64
  48 #define SCALER_MAX_VRATIO       64
  49
  50 enum {
  51         ST_IDLE,
  52         ST_OUTDMA_RUN,
  53         ST_M2M_PEND,
  54 };
  55
  56 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
  57 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
  58
  59 enum fimc_datapath {
  60         FIMC_ITU_CAM_A,
  61         FIMC_ITU_CAM_B,
  62         FIMC_MIPI_CAM,
  63         FIMC_DMA,
  64         FIMC_LCDFIFO,
  65         FIMC_WRITEBACK
  66 };
  67
  68 enum fimc_color_fmt {
  69         S5P_FIMC_RGB565,
  70         S5P_FIMC_RGB666,
  71         S5P_FIMC_RGB888,
  72         S5P_FIMC_YCBCR420,
  73         S5P_FIMC_YCBCR422,
  74         S5P_FIMC_YCBYCR422,
  75         S5P_FIMC_YCRYCB422,
  76         S5P_FIMC_CBYCRY422,
  77         S5P_FIMC_CRYCBY422,
  78         S5P_FIMC_RGB30_LOCAL,
  79         S5P_FIMC_YCBCR444_LOCAL,
  80         S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
  81         S5P_FIMC_COLOR_MASK = 0x0F,
  82 };
  83
  84 /* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
  85 #define S5P_FIMC_OUT_CRYCBY     S5P_CIOCTRL_ORDER422_CRYCBY
  86 #define S5P_FIMC_OUT_CBYCRY     S5P_CIOCTRL_ORDER422_YCRYCB
  87 #define S5P_FIMC_OUT_YCRYCB     S5P_CIOCTRL_ORDER422_CBYCRY
  88 #define S5P_FIMC_OUT_YCBYCR     S5P_CIOCTRL_ORDER422_YCBYCR
  89
  90 /* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
  91 #define S5P_FIMC_IN_CRYCBY      S5P_MSCTRL_ORDER422_CRYCBY
  92 #define S5P_FIMC_IN_CBYCRY      S5P_MSCTRL_ORDER422_YCRYCB
  93 #define S5P_FIMC_IN_YCRYCB      S5P_MSCTRL_ORDER422_CBYCRY
  94 #define S5P_FIMC_IN_YCBYCR      S5P_MSCTRL_ORDER422_YCBYCR
  95
  96 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
  97 #define S5P_FIMC_LSB_CRCB       S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
  98
  99 /* The embedded image effect selection */
 100 #define S5P_FIMC_EFFECT_ORIGINAL        S5P_CIIMGEFF_FIN_BYPASS
 101 #define S5P_FIMC_EFFECT_ARBITRARY       S5P_CIIMGEFF_FIN_ARBITRARY
 102 #define S5P_FIMC_EFFECT_NEGATIVE        S5P_CIIMGEFF_FIN_NEGATIVE
 103 #define S5P_FIMC_EFFECT_ARTFREEZE       S5P_CIIMGEFF_FIN_ARTFREEZE
 104 #define S5P_FIMC_EFFECT_EMBOSSING       S5P_CIIMGEFF_FIN_EMBOSSING
 105 #define S5P_FIMC_EFFECT_SIKHOUETTE      S5P_CIIMGEFF_FIN_SILHOUETTE
 106
 107 /* The hardware context state. */
 108 #define FIMC_PARAMS                     (1 << 0)
 109 #define FIMC_SRC_ADDR                   (1 << 1)
 110 #define FIMC_DST_ADDR                   (1 << 2)
 111 #define FIMC_SRC_FMT                    (1 << 3)
 112 #define FIMC_DST_FMT                    (1 << 4)
 113
 114 /* Image conversion flags */
 115 #define FIMC_IN_DMA_ACCESS_TILED        (1 << 0)
 116 #define FIMC_IN_DMA_ACCESS_LINEAR       (0 << 0)
 117 #define FIMC_OUT_DMA_ACCESS_TILED       (1 << 1)
 118 #define FIMC_OUT_DMA_ACCESS_LINEAR      (0 << 1)
 119 #define FIMC_SCAN_MODE_PROGRESSIVE      (0 << 2)
 120 #define FIMC_SCAN_MODE_INTERLACED       (1 << 2)
 121 /* YCbCr data dynamic range for RGB-YUV color conversion. Y/Cb/Cr: (0 ~ 255) */
 122 #define FIMC_COLOR_RANGE_WIDE           (0 << 3)
 123 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
 124 #define FIMC_COLOR_RANGE_NARROW         (1 << 3)
 125
 126 #define FLIP_NONE                       0
 127 #define FLIP_X_AXIS                     1
 128 #define FLIP_Y_AXIS                     2
 129 #define FLIP_XY_AXIS                    (FLIP_X_AXIS | FLIP_Y_AXIS)
 130
 131 /**
 132  * struct fimc_fmt - the driver's internal color format data
 133  * @name: format description
 134  * @fourcc: the fourcc code for this format
 135  * @color: the corresponding fimc_color_fmt
 136  * @depth: number of bits per pixel
 137  * @buff_cnt: number of physically non-contiguous data planes
 138  * @planes_cnt: number of physically contiguous data planes
 139  */
 140 struct fimc_fmt {
 141         char    *name;
 142         u32     fourcc;
 143         u32     color;
 144         u32     depth;
 145         u16     buff_cnt;
 146         u16     planes_cnt;
 147 };
 148
 149 /**
 150  * struct fimc_dma_offset - pixel offset information for DMA
 151  * @y_h:        y value horizontal offset
 152  * @y_v:        y value vertical offset
 153  * @cb_h:       cb value horizontal offset
 154  * @cb_v:       cb value vertical offset
 155  * @cr_h:       cr value horizontal offset
 156  * @cr_v:       cr value vertical offset
 157  */
 158 struct fimc_dma_offset {
 159         int     y_h;
 160         int     y_v;
 161         int     cb_h;
 162         int     cb_v;
 163         int     cr_h;
 164         int     cr_v;
 165 };
 166
 167 /**
 168  * struct fimc_effect - the configuration data for the "Arbitrary" image effect
 169  * @type:       effect type
 170  * @pat_cb:     cr value when type is "arbitrary"
 171  * @pat_cr:     cr value when type is "arbitrary"
 172  */
 173 struct fimc_effect {
 174         u32     type;
 175         u8      pat_cb;
 176         u8      pat_cr;
 177 };
 178
 179 /**
 180  * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 181  *
 182  * @enabled:            the flag set when the scaler is used
 183  * @hfactor:            horizontal shift factor
 184  * @vfactor:            vertical shift factor
 185  * @pre_hratio:         horizontal ratio of the prescaler
 186  * @pre_vratio:         vertical ratio of the prescaler
 187  * @pre_dst_width:      the prescaler's destination width
 188  * @pre_dst_height:     the prescaler's destination height
 189  * @scaleup_h:          flag indicating scaling up horizontally
 190  * @scaleup_v:          flag indicating scaling up vertically
 191  * @main_hratio:        the main scaler's horizontal ratio
 192  * @main_vratio:        the main scaler's vertical ratio
 193  * @real_width:         source width - offset
 194  * @real_height:        source height - offset
 195  * @copy_mode:          flag set if one-to-one mode is used, i.e. no scaling
 196  *                      and color format conversion
 197  */
 198 struct fimc_scaler {
 199         u32     enabled;
 200         u32     hfactor;
 201         u32     vfactor;
 202         u32     pre_hratio;
 203         u32     pre_vratio;
 204         u32     pre_dst_width;
 205         u32     pre_dst_height;
 206         u32     scaleup_h;
 207         u32     scaleup_v;
 208         u32     main_hratio;
 209         u32     main_vratio;
 210         u32     real_width;
 211         u32     real_height;
 212         u32     copy_mode;
 213 };
 214
 215 /**
 216  * struct fimc_addr - the FIMC physical address set for DMA
 217  *
 218  * @y:   luminance plane physical address
 219  * @cb:  Cb plane physical address
 220  * @cr:  Cr plane physical address
 221  */
 222 struct fimc_addr {
 223         u32     y;
 224         u32     cb;
 225         u32     cr;
 226 };
 227
 228 /**
 229  * struct fimc_vid_buffer - the driver's video buffer
 230  * @vb: v4l videobuf buffer
 231  */
 232 struct fimc_vid_buffer {
 233         struct videobuf_buffer  vb;
 234 };
 235
 236 /**
 237  * struct fimc_frame - input/output frame format properties
 238  *
 239  * @f_width:    image full width (virtual screen size)
 240  * @f_height:   image full height (virtual screen size)
 241  * @o_width:    original image width as set by S_FMT
 242  * @o_height:   original image height as set by S_FMT
 243  * @offs_h:     image horizontal pixel offset
 244  * @offs_v:     image vertical pixel offset
 245  * @width:      image pixel width
 246  * @height:     image pixel weight
 247  * @paddr:      image frame buffer physical addresses
 248  * @buf_cnt:    number of buffers depending on a color format
 249  * @size:       image size in bytes
 250  * @color:      color format
 251  * @dma_offset: DMA offset in bytes
 252  */
 253 struct fimc_frame {
 254         u32     f_width;
 255         u32     f_height;
 256         u32     o_width;
 257         u32     o_height;
 258         u32     offs_h;
 259         u32     offs_v;
 260         u32     width;
 261         u32     height;
 262         u32     size;
 263         struct fimc_addr        paddr;
 264         struct fimc_dma_offset  dma_offset;
 265         struct fimc_fmt         *fmt;
 266 };
 267
 268 /**
 269  * struct fimc_m2m_device - v4l2 memory-to-memory device data
 270  * @vfd: the video device node for v4l2 m2m mode
 271  * @v4l2_dev: v4l2 device for m2m mode
 272  * @m2m_dev: v4l2 memory-to-memory device data
 273  * @ctx: hardware context data
 274  * @refcnt: the reference counter
 275  */
 276 struct fimc_m2m_device {
 277         struct video_device     *vfd;
 278         struct v4l2_device      v4l2_dev;
 279         struct v4l2_m2m_dev     *m2m_dev;
 280         struct fimc_ctx         *ctx;
 281         int                     refcnt;
 282 };
 283
 284 /**
 285  * struct samsung_fimc_variant - camera interface variant information
 286  *
 287  * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 288  * @has_inp_rot: set if has input rotator
 289  * @has_out_rot: set if has output rotator
 290  * @min_inp_pixsize: minimum input pixel size
 291  * @min_out_pixsize: minimum output pixel size
 292  * @scaler_en_w: maximum input pixel width when the scaler is enabled
 293  * @scaler_dis_w: maximum input pixel width when the scaler is disabled
 294  * @in_rot_en_h: maximum input width when the input rotator is used
 295  * @in_rot_dis_w: maximum input width when the input rotator is used
 296  * @out_rot_en_w: maximum output width for the output rotator enabled
 297  * @out_rot_dis_w: maximum output width for the output rotator enabled
 298  */
 299 struct samsung_fimc_variant {
 300         unsigned int    pix_hoff:1;
 301         unsigned int    has_inp_rot:1;
 302         unsigned int    has_out_rot:1;
 303
 304         u16             min_inp_pixsize;
 305         u16             min_out_pixsize;
 306         u16             scaler_en_w;
 307         u16             scaler_dis_w;
 308         u16             in_rot_en_h;
 309         u16             in_rot_dis_w;
 310         u16             out_rot_en_w;
 311         u16             out_rot_dis_w;
 312 };
 313
 314 /**
 315  * struct samsung_fimc_driverdata - per-device type driver data for init time.
 316  *
 317  * @variant: the variant information for this driver.
 318  * @dev_cnt: number of fimc sub-devices available in SoC
 319  */
 320 struct samsung_fimc_driverdata {
 321         struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
 322         int     devs_cnt;
 323 };
 324
 325 struct fimc_ctx;
 326
 327 /**
 328  * struct fimc_subdev - abstraction for a FIMC entity
 329  *
 330  * @slock:      the spinlock protecting this data structure
 331  * @lock:       the mutex protecting this data structure
 332  * @pdev:       pointer to the FIMC platform device
 333  * @id:         FIMC device index (0..2)
 334  * @clock[]:    the clocks required for FIMC operation
 335  * @regs:       the mapped hardware registers
 336  * @regs_res:   the resource claimed for IO registers
 337  * @irq:        interrupt number of the FIMC subdevice
 338  * @irqlock:    spinlock protecting videbuffer queue
 339  * @m2m:        memory-to-memory V4L2 device information
 340  * @state:      the FIMC device state flags
 341  */
 342 struct fimc_dev {
 343         spinlock_t                      slock;
 344         struct mutex                    lock;
 345         struct platform_device          *pdev;
 346         struct samsung_fimc_variant     *variant;
 347         int                             id;
 348         struct clk                      *clock[NUM_FIMC_CLOCKS];
 349         void __iomem                    *regs;
 350         struct resource                 *regs_res;
 351         int                             irq;
 352         spinlock_t                      irqlock;
 353         struct workqueue_struct         *work_queue;
 354         struct fimc_m2m_device          m2m;
 355         unsigned long                   state;
 356 };
 357
 358 /**
 359  * fimc_ctx - the device context data
 360  *
 361  * @lock:               mutex protecting this data structure
 362  * @s_frame:            source frame properties
 363  * @d_frame:            destination frame properties
 364  * @out_order_1p:       output 1-plane YCBCR order
 365  * @out_order_2p:       output 2-plane YCBCR order
 366  * @in_order_1p         input 1-plane YCBCR order
 367  * @in_order_2p:        input 2-plane YCBCR order
 368  * @in_path:            input mode (DMA or camera)
 369  * @out_path:           output mode (DMA or FIFO)
 370  * @scaler:             image scaler properties
 371  * @effect:             image effect
 372  * @rotation:           image clockwise rotation in degrees
 373  * @flip:               image flip mode
 374  * @flags:              an additional flags for image conversion
 375  * @state:              flags to keep track of user configuration
 376  * @fimc_dev:           the FIMC device this context applies to
 377  * @m2m_ctx:            memory-to-memory device context
 378  */
 379 struct fimc_ctx {
 380         spinlock_t              slock;
 381         struct fimc_frame       s_frame;
 382         struct fimc_frame       d_frame;
 383         u32                     out_order_1p;
 384         u32                     out_order_2p;
 385         u32                     in_order_1p;
 386         u32                     in_order_2p;
 387         enum fimc_datapath      in_path;
 388         enum fimc_datapath      out_path;
 389         struct fimc_scaler      scaler;
 390         struct fimc_effect      effect;
 391         int                     rotation;
 392         u32                     flip;
 393         u32                     flags;
 394         u32                     state;
 395         struct fimc_dev         *fimc_dev;
 396         struct v4l2_m2m_ctx     *m2m_ctx;
 397 };
 398
 399
 400 static inline int tiled_fmt(struct fimc_fmt *fmt)
 401 {
 402         return 0;
 403 }
 404
 405 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
 406 {
 407         u32 cfg = readl(dev->regs + S5P_CIGCTRL);
 408         cfg |= S5P_CIGCTRL_IRQ_CLR;
 409         writel(cfg, dev->regs + S5P_CIGCTRL);
 410 }
 411
 412 static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
 413 {
 414         u32 cfg = readl(dev->regs + S5P_CISCCTRL);
 415         cfg |= S5P_CISCCTRL_SCALERSTART;
 416         writel(cfg, dev->regs + S5P_CISCCTRL);
 417 }
 418
 419 static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
 420 {
 421         u32 cfg = readl(dev->regs + S5P_CISCCTRL);
 422         cfg &= ~S5P_CISCCTRL_SCALERSTART;
 423         writel(cfg, dev->regs + S5P_CISCCTRL);
 424 }
 425
 426 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
 427 {
 428         u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
 429         cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
 430         writel(cfg, dev->regs + S5P_CIIMGCPT);
 431 }
 432
 433 static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
 434 {
 435         u32 cfg = readl(dev->regs + S5P_MSCTRL);
 436         cfg |= S5P_MSCTRL_ENVID;
 437         writel(cfg, dev->regs + S5P_MSCTRL);
 438 }
 439
 440 static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
 441 {
 442         u32 cfg = readl(dev->regs + S5P_MSCTRL);
 443         cfg &= ~S5P_MSCTRL_ENVID;
 444         writel(cfg, dev->regs + S5P_MSCTRL);
 445 }
 446
 447 /* -----------------------------------------------------*/
 448 /* fimc-reg.c                                           */
 449 void fimc_hw_reset(struct fimc_dev *dev);
 450 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
 451 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
 452 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
 453 void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
 454 void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
 455 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
 456 void fimc_hw_set_scaler(struct fimc_ctx *ctx);
 457 void fimc_hw_en_capture(struct fimc_ctx *ctx);
 458 void fimc_hw_set_effect(struct fimc_ctx *ctx);
 459 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
 460 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
 461 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
 462 void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
 463 void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
 464
 465 #endif /* FIMC_CORE_H_ */