drivers/media/video/s5p-fimc/fimc-core.h

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics
   3  *
   4  * Sylwester Nawrocki, <s.nawrocki@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef FIMC_CORE_H_
  12 #define FIMC_CORE_H_
  13
  14 /*#define DEBUG*/
  15
  16 #include <linux/sched.h>
  17 #include <linux/types.h>
  18 #include <linux/videodev2.h>
  19 #include <media/videobuf-core.h>
  20 #include <media/v4l2-device.h>
  21 #include <media/v4l2-mem2mem.h>
  22 #include <media/v4l2-mediabus.h>
  23 #include <media/s3c_fimc.h>
  24
  25 #include "regs-fimc.h"
  26
  27 #define err(fmt, args...) \
  28         printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  29
  30 #ifdef DEBUG
  31 #define dbg(fmt, args...) \
  32         printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
  33 #else
  34 #define dbg(fmt, args...)
  35 #endif
  36
  37 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
  38 #define FIMC_SHUTDOWN_TIMEOUT   ((100*HZ)/1000)
  39 #define NUM_FIMC_CLOCKS         2
  40 #define MODULE_NAME             "s5p-fimc"
  41 #define FIMC_MAX_DEVS           4
  42 #define FIMC_MAX_OUT_BUFS       4
  43 #define SCALER_MAX_HRATIO       64
  44 #define SCALER_MAX_VRATIO       64
  45 #define DMA_MIN_SIZE            8
  46
  47 /* FIMC device state flags */
  48 enum fimc_dev_flags {
  49         /* for m2m node */
  50         ST_IDLE,
  51         ST_OUTDMA_RUN,
  52         ST_M2M_PEND,
  53         /* for capture node */
  54         ST_CAPT_PEND,
  55         ST_CAPT_RUN,
  56         ST_CAPT_STREAM,
  57         ST_CAPT_SHUT,
  58 };
  59
  60 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
  61 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
  62
  63 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
  64 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
  65
  66 #define fimc_capture_active(dev) \
  67         (test_bit(ST_CAPT_RUN, &(dev)->state) || \
  68          test_bit(ST_CAPT_PEND, &(dev)->state))
  69
  70 #define fimc_capture_streaming(dev) \
  71         test_bit(ST_CAPT_STREAM, &(dev)->state)
  72
  73 #define fimc_buf_finish(dev, vid_buf) do { \
  74         spin_lock(&(dev)->irqlock); \
  75         (vid_buf)->vb.state = VIDEOBUF_DONE; \
  76         spin_unlock(&(dev)->irqlock); \
  77         wake_up(&(vid_buf)->vb.done); \
  78 } while (0)
  79
  80 enum fimc_datapath {
  81         FIMC_CAMERA,
  82         FIMC_DMA,
  83         FIMC_LCDFIFO,
  84         FIMC_WRITEBACK
  85 };
  86
  87 enum fimc_color_fmt {
  88         S5P_FIMC_RGB565 = 0x10,
  89         S5P_FIMC_RGB666,
  90         S5P_FIMC_RGB888,
  91         S5P_FIMC_RGB30_LOCAL,
  92         S5P_FIMC_YCBCR420 = 0x20,
  93         S5P_FIMC_YCBCR422,
  94         S5P_FIMC_YCBYCR422,
  95         S5P_FIMC_YCRYCB422,
  96         S5P_FIMC_CBYCRY422,
  97         S5P_FIMC_CRYCBY422,
  98         S5P_FIMC_YCBCR444_LOCAL,
  99 };
 100
 101 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
 102
 103 /* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
 104 #define S5P_FIMC_OUT_CRYCBY     S5P_CIOCTRL_ORDER422_CRYCBY
 105 #define S5P_FIMC_OUT_CBYCRY     S5P_CIOCTRL_ORDER422_YCRYCB
 106 #define S5P_FIMC_OUT_YCRYCB     S5P_CIOCTRL_ORDER422_CBYCRY
 107 #define S5P_FIMC_OUT_YCBYCR     S5P_CIOCTRL_ORDER422_YCBYCR
 108
 109 /* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
 110 #define S5P_FIMC_IN_CRYCBY      S5P_MSCTRL_ORDER422_CRYCBY
 111 #define S5P_FIMC_IN_CBYCRY      S5P_MSCTRL_ORDER422_YCRYCB
 112 #define S5P_FIMC_IN_YCRYCB      S5P_MSCTRL_ORDER422_CBYCRY
 113 #define S5P_FIMC_IN_YCBYCR      S5P_MSCTRL_ORDER422_YCBYCR
 114
 115 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
 116 #define S5P_FIMC_LSB_CRCB       S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
 117
 118 /* The embedded image effect selection */
 119 #define S5P_FIMC_EFFECT_ORIGINAL        S5P_CIIMGEFF_FIN_BYPASS
 120 #define S5P_FIMC_EFFECT_ARBITRARY       S5P_CIIMGEFF_FIN_ARBITRARY
 121 #define S5P_FIMC_EFFECT_NEGATIVE        S5P_CIIMGEFF_FIN_NEGATIVE
 122 #define S5P_FIMC_EFFECT_ARTFREEZE       S5P_CIIMGEFF_FIN_ARTFREEZE
 123 #define S5P_FIMC_EFFECT_EMBOSSING       S5P_CIIMGEFF_FIN_EMBOSSING
 124 #define S5P_FIMC_EFFECT_SIKHOUETTE      S5P_CIIMGEFF_FIN_SILHOUETTE
 125
 126 /* The hardware context state. */
 127 #define FIMC_PARAMS             (1 << 0)
 128 #define FIMC_SRC_ADDR           (1 << 1)
 129 #define FIMC_DST_ADDR           (1 << 2)
 130 #define FIMC_SRC_FMT            (1 << 3)
 131 #define FIMC_DST_FMT            (1 << 4)
 132 #define FIMC_CTX_M2M            (1 << 5)
 133 #define FIMC_CTX_CAP            (1 << 6)
 134
 135 /* Image conversion flags */
 136 #define FIMC_IN_DMA_ACCESS_TILED        (1 << 0)
 137 #define FIMC_IN_DMA_ACCESS_LINEAR       (0 << 0)
 138 #define FIMC_OUT_DMA_ACCESS_TILED       (1 << 1)
 139 #define FIMC_OUT_DMA_ACCESS_LINEAR      (0 << 1)
 140 #define FIMC_SCAN_MODE_PROGRESSIVE      (0 << 2)
 141 #define FIMC_SCAN_MODE_INTERLACED       (1 << 2)
 142 /*
 143  * YCbCr data dynamic range for RGB-YUV color conversion.
 144  * Y/Cb/Cr: (0 ~ 255) */
 145 #define FIMC_COLOR_RANGE_WIDE           (0 << 3)
 146 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
 147 #define FIMC_COLOR_RANGE_NARROW         (1 << 3)
 148
 149 #define FLIP_NONE                       0
 150 #define FLIP_X_AXIS                     1
 151 #define FLIP_Y_AXIS                     2
 152 #define FLIP_XY_AXIS                    (FLIP_X_AXIS | FLIP_Y_AXIS)
 153
 154 /**
 155  * struct fimc_fmt - the driver's internal color format data
 156  * @mbus_code: Media Bus pixel code, -1 if not applicable
 157  * @name: format description
 158  * @fourcc: the fourcc code for this format, 0 if not applicable
 159  * @color: the corresponding fimc_color_fmt
 160  * @depth: driver's private 'number of bits per pixel'
 161  * @buff_cnt: number of physically non-contiguous data planes
 162  * @planes_cnt: number of physically contiguous data planes
 163  */
 164 struct fimc_fmt {
 165         enum v4l2_mbus_pixelcode mbus_code;
 166         char    *name;
 167         u32     fourcc;
 168         u32     color;
 169         u16     buff_cnt;
 170         u16     planes_cnt;
 171         u16     depth;
 172         u16     flags;
 173 #define FMT_FLAGS_CAM   (1 << 0)
 174 #define FMT_FLAGS_M2M   (1 << 1)
 175 };
 176
 177 /**
 178  * struct fimc_dma_offset - pixel offset information for DMA
 179  * @y_h:        y value horizontal offset
 180  * @y_v:        y value vertical offset
 181  * @cb_h:       cb value horizontal offset
 182  * @cb_v:       cb value vertical offset
 183  * @cr_h:       cr value horizontal offset
 184  * @cr_v:       cr value vertical offset
 185  */
 186 struct fimc_dma_offset {
 187         int     y_h;
 188         int     y_v;
 189         int     cb_h;
 190         int     cb_v;
 191         int     cr_h;
 192         int     cr_v;
 193 };
 194
 195 /**
 196  * struct fimc_effect - the configuration data for the "Arbitrary" image effect
 197  * @type:       effect type
 198  * @pat_cb:     cr value when type is "arbitrary"
 199  * @pat_cr:     cr value when type is "arbitrary"
 200  */
 201 struct fimc_effect {
 202         u32     type;
 203         u8      pat_cb;
 204         u8      pat_cr;
 205 };
 206
 207 /**
 208  * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
 209  *
 210  * @scaleup_h:          flag indicating scaling up horizontally
 211  * @scaleup_v:          flag indicating scaling up vertically
 212  * @copy_mode:          flag indicating transparent DMA transfer (no scaling
 213  *                      and color format conversion)
 214  * @enabled:            flag indicating if the scaler is used
 215  * @hfactor:            horizontal shift factor
 216  * @vfactor:            vertical shift factor
 217  * @pre_hratio:         horizontal ratio of the prescaler
 218  * @pre_vratio:         vertical ratio of the prescaler
 219  * @pre_dst_width:      the prescaler's destination width
 220  * @pre_dst_height:     the prescaler's destination height
 221  * @main_hratio:        the main scaler's horizontal ratio
 222  * @main_vratio:        the main scaler's vertical ratio
 223  * @real_width:         source pixel (width - offset)
 224  * @real_height:        source pixel (height - offset)
 225  */
 226 struct fimc_scaler {
 227         unsigned int scaleup_h:1;
 228         unsigned int scaleup_v:1;
 229         unsigned int copy_mode:1;
 230         unsigned int enabled:1;
 231         u32     hfactor;
 232         u32     vfactor;
 233         u32     pre_hratio;
 234         u32     pre_vratio;
 235         u32     pre_dst_width;
 236         u32     pre_dst_height;
 237         u32     main_hratio;
 238         u32     main_vratio;
 239         u32     real_width;
 240         u32     real_height;
 241 };
 242
 243 /**
 244  * struct fimc_addr - the FIMC physical address set for DMA
 245  *
 246  * @y:   luminance plane physical address
 247  * @cb:  Cb plane physical address
 248  * @cr:  Cr plane physical address
 249  */
 250 struct fimc_addr {
 251         u32     y;
 252         u32     cb;
 253         u32     cr;
 254 };
 255
 256 /**
 257  * struct fimc_vid_buffer - the driver's video buffer
 258  * @vb:    v4l videobuf buffer
 259  * @paddr: precalculated physical address set
 260  * @index: buffer index for the output DMA engine
 261  */
 262 struct fimc_vid_buffer {
 263         struct videobuf_buffer  vb;
 264         struct fimc_addr        paddr;
 265         int                     index;
 266 };
 267
 268 /**
 269  * struct fimc_frame - source/target frame properties
 270  * @f_width:    image full width (virtual screen size)
 271  * @f_height:   image full height (virtual screen size)
 272  * @o_width:    original image width as set by S_FMT
 273  * @o_height:   original image height as set by S_FMT
 274  * @offs_h:     image horizontal pixel offset
 275  * @offs_v:     image vertical pixel offset
 276  * @width:      image pixel width
 277  * @height:     image pixel weight
 278  * @paddr:      image frame buffer physical addresses
 279  * @buf_cnt:    number of buffers depending on a color format
 280  * @size:       image size in bytes
 281  * @color:      color format
 282  * @dma_offset: DMA offset in bytes
 283  */
 284 struct fimc_frame {
 285         u32     f_width;
 286         u32     f_height;
 287         u32     o_width;
 288         u32     o_height;
 289         u32     offs_h;
 290         u32     offs_v;
 291         u32     width;
 292         u32     height;
 293         u32     size;
 294         struct fimc_addr        paddr;
 295         struct fimc_dma_offset  dma_offset;
 296         struct fimc_fmt         *fmt;
 297 };
 298
 299 /**
 300  * struct fimc_m2m_device - v4l2 memory-to-memory device data
 301  * @vfd: the video device node for v4l2 m2m mode
 302  * @v4l2_dev: v4l2 device for m2m mode
 303  * @m2m_dev: v4l2 memory-to-memory device data
 304  * @ctx: hardware context data
 305  * @refcnt: the reference counter
 306  */
 307 struct fimc_m2m_device {
 308         struct video_device     *vfd;
 309         struct v4l2_device      v4l2_dev;
 310         struct v4l2_m2m_dev     *m2m_dev;
 311         struct fimc_ctx         *ctx;
 312         int                     refcnt;
 313 };
 314
 315 /**
 316  * struct fimc_vid_cap - camera capture device information
 317  * @ctx: hardware context data
 318  * @vfd: video device node for camera capture mode
 319  * @v4l2_dev: v4l2_device struct to manage subdevs
 320  * @sd: pointer to camera sensor subdevice currently in use
 321  * @fmt: Media Bus format configured at selected image sensor
 322  * @pending_buf_q: the pending buffer queue head
 323  * @active_buf_q: the queue head of buffers scheduled in hardware
 324  * @vbq: the capture am video buffer queue
 325  * @active_buf_cnt: number of video buffers scheduled in hardware
 326  * @buf_index: index for managing the output DMA buffers
 327  * @frame_count: the frame counter for statistics
 328  * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
 329  * @input_index: input (camera sensor) index
 330  * @refcnt: driver's private reference counter
 331  */
 332 struct fimc_vid_cap {
 333         struct fimc_ctx                 *ctx;
 334         struct video_device             *vfd;
 335         struct v4l2_device              v4l2_dev;
 336         struct v4l2_subdev              *sd;
 337         struct v4l2_mbus_framefmt       fmt;
 338         struct list_head                pending_buf_q;
 339         struct list_head                active_buf_q;
 340         struct videobuf_queue           vbq;
 341         int                             active_buf_cnt;
 342         int                             buf_index;
 343         unsigned int                    frame_count;
 344         unsigned int                    reqbufs_count;
 345         int                             input_index;
 346         int                             refcnt;
 347 };
 348
 349 /**
 350  *  struct fimc_pix_limit - image pixel size limits in various IP configurations
 351  *
 352  *  @scaler_en_w: max input pixel width when the scaler is enabled
 353  *  @scaler_dis_w: max input pixel width when the scaler is disabled
 354  *  @in_rot_en_h: max input width with the input rotator is on
 355  *  @in_rot_dis_w: max input width with the input rotator is off
 356  *  @out_rot_en_w: max output width with the output rotator on
 357  *  @out_rot_dis_w: max output width with the output rotator off
 358  */
 359 struct fimc_pix_limit {
 360         u16 scaler_en_w;
 361         u16 scaler_dis_w;
 362         u16 in_rot_en_h;
 363         u16 in_rot_dis_w;
 364         u16 out_rot_en_w;
 365         u16 out_rot_dis_w;
 366 };
 367
 368 /**
 369  * struct samsung_fimc_variant - camera interface variant information
 370  *
 371  * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
 372  * @has_inp_rot: set if has input rotator
 373  * @has_out_rot: set if has output rotator
 374  * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
 375  * @pix_limit: pixel size constraints for the scaler
 376  * @min_inp_pixsize: minimum input pixel size
 377  * @min_out_pixsize: minimum output pixel size
 378  * @hor_offs_align: horizontal pixel offset aligment
 379  * @out_buf_count: the number of buffers in output DMA sequence
 380  */
 381 struct samsung_fimc_variant {
 382         unsigned int    pix_hoff:1;
 383         unsigned int    has_inp_rot:1;
 384         unsigned int    has_out_rot:1;
 385         unsigned int    has_cistatus2:1;
 386         struct fimc_pix_limit *pix_limit;
 387         u16             min_inp_pixsize;
 388         u16             min_out_pixsize;
 389         u16             hor_offs_align;
 390         u16             out_buf_count;
 391 };
 392
 393 /**
 394  * struct samsung_fimc_driverdata - per device type driver data for init time.
 395  *
 396  * @variant: the variant information for this driver.
 397  * @dev_cnt: number of fimc sub-devices available in SoC
 398  * @lclk_frequency: fimc bus clock frequency
 399  */
 400 struct samsung_fimc_driverdata {
 401         struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
 402         unsigned long   lclk_frequency;
 403         int             num_entities;
 404 };
 405
 406 struct fimc_ctx;
 407
 408 /**
 409  * struct fimc_dev - abstraction for FIMC entity
 410  *
 411  * @slock:      the spinlock protecting this data structure
 412  * @lock:       the mutex protecting this data structure
 413  * @pdev:       pointer to the FIMC platform device
 414  * @pdata:      pointer to the device platform data
 415  * @id:         FIMC device index (0..2)
 416  * @clock[]:    the clocks required for FIMC operation
 417  * @regs:       the mapped hardware registers
 418  * @regs_res:   the resource claimed for IO registers
 419  * @irq:        interrupt number of the FIMC subdevice
 420  * @irqlock:    spinlock protecting videobuffer queue
 421  * @irq_queue:
 422  * @m2m:        memory-to-memory V4L2 device information
 423  * @vid_cap:    camera capture device information
 424  * @state:      flags used to synchronize m2m and capture mode operation
 425  */
 426 struct fimc_dev {
 427         spinlock_t                      slock;
 428         struct mutex                    lock;
 429         struct platform_device          *pdev;
 430         struct s3c_platform_fimc        *pdata;
 431         struct samsung_fimc_variant     *variant;
 432         int                             id;
 433         struct clk                      *clock[NUM_FIMC_CLOCKS];
 434         void __iomem                    *regs;
 435         struct resource                 *regs_res;
 436         int                             irq;
 437         spinlock_t                      irqlock;
 438         wait_queue_head_t               irq_queue;
 439         struct fimc_m2m_device          m2m;
 440         struct fimc_vid_cap             vid_cap;
 441         unsigned long                   state;
 442 };
 443
 444 /**
 445  * fimc_ctx - the device context data
 446  *
 447  * @lock:               mutex protecting this data structure
 448  * @s_frame:            source frame properties
 449  * @d_frame:            destination frame properties
 450  * @out_order_1p:       output 1-plane YCBCR order
 451  * @out_order_2p:       output 2-plane YCBCR order
 452  * @in_order_1p         input 1-plane YCBCR order
 453  * @in_order_2p:        input 2-plane YCBCR order
 454  * @in_path:            input mode (DMA or camera)
 455  * @out_path:           output mode (DMA or FIFO)
 456  * @scaler:             image scaler properties
 457  * @effect:             image effect
 458  * @rotation:           image clockwise rotation in degrees
 459  * @flip:               image flip mode
 460  * @flags:              additional flags for image conversion
 461  * @state:              flags to keep track of user configuration
 462  * @fimc_dev:           the FIMC device this context applies to
 463  * @m2m_ctx:            memory-to-memory device context
 464  */
 465 struct fimc_ctx {
 466         spinlock_t              slock;
 467         struct fimc_frame       s_frame;
 468         struct fimc_frame       d_frame;
 469         u32                     out_order_1p;
 470         u32                     out_order_2p;
 471         u32                     in_order_1p;
 472         u32                     in_order_2p;
 473         enum fimc_datapath      in_path;
 474         enum fimc_datapath      out_path;
 475         struct fimc_scaler      scaler;
 476         struct fimc_effect      effect;
 477         int                     rotation;
 478         u32                     flip;
 479         u32                     flags;
 480         u32                     state;
 481         struct fimc_dev         *fimc_dev;
 482         struct v4l2_m2m_ctx     *m2m_ctx;
 483 };
 484
 485 extern struct videobuf_queue_ops fimc_qops;
 486
 487 static inline int tiled_fmt(struct fimc_fmt *fmt)
 488 {
 489         return 0;
 490 }
 491
 492 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
 493 {
 494         u32 cfg = readl(dev->regs + S5P_CIGCTRL);
 495         cfg |= S5P_CIGCTRL_IRQ_CLR;
 496         writel(cfg, dev->regs + S5P_CIGCTRL);
 497 }
 498
 499 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
 500 {
 501         u32 cfg = readl(dev->regs + S5P_CISCCTRL);
 502         if (on)
 503                 cfg |= S5P_CISCCTRL_SCALERSTART;
 504         else
 505                 cfg &= ~S5P_CISCCTRL_SCALERSTART;
 506         writel(cfg, dev->regs + S5P_CISCCTRL);
 507 }
 508
 509 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
 510 {
 511         u32 cfg = readl(dev->regs + S5P_MSCTRL);
 512         if (on)
 513                 cfg |= S5P_MSCTRL_ENVID;
 514         else
 515                 cfg &= ~S5P_MSCTRL_ENVID;
 516         writel(cfg, dev->regs + S5P_MSCTRL);
 517 }
 518
 519 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
 520 {
 521         u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
 522         cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
 523         writel(cfg, dev->regs + S5P_CIIMGCPT);
 524 }
 525
 526 /**
 527  * fimc_hw_set_dma_seq - configure output DMA buffer sequence
 528  * @mask: each bit corresponds to one of 32 output buffer registers set
 529  *        1 to include buffer in the sequence, 0 to disable
 530  *
 531  * This function mask output DMA ring buffers, i.e. it allows to configure
 532  * which of the output buffer address registers will be used by the DMA
 533  * engine.
 534  */
 535 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
 536 {
 537         writel(mask, dev->regs + S5P_CIFCNTSEQ);
 538 }
 539
 540 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
 541                                                enum v4l2_buf_type type)
 542 {
 543         struct fimc_frame *frame;
 544
 545         if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type) {
 546                 if (ctx->state & FIMC_CTX_M2M)
 547                         frame = &ctx->s_frame;
 548                 else
 549                         return ERR_PTR(-EINVAL);
 550         } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type) {
 551                 frame = &ctx->d_frame;
 552         } else {
 553                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
 554                         "Wrong buffer/video queue type (%d)\n", type);
 555                 return ERR_PTR(-EINVAL);
 556         }
 557
 558         return frame;
 559 }
 560
 561 /* Return an index to the buffer actually being written. */
 562 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
 563 {
 564         u32 reg;
 565
 566         if (dev->variant->has_cistatus2) {
 567                 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
 568                 return reg > 0 ? --reg : reg;
 569         } else {
 570                 reg = readl(dev->regs + S5P_CISTATUS);
 571                 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
 572                         S5P_CISTATUS_FRAMECNT_SHIFT;
 573         }
 574 }
 575
 576 /* -----------------------------------------------------*/
 577 /* fimc-reg.c                                           */
 578 void fimc_hw_reset(struct fimc_dev *fimc);
 579 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
 580 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
 581 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
 582 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
 583 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
 584 void fimc_hw_set_scaler(struct fimc_ctx *ctx);
 585 void fimc_hw_en_capture(struct fimc_ctx *ctx);
 586 void fimc_hw_set_effect(struct fimc_ctx *ctx);
 587 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
 588 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
 589 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
 590 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
 591 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
 592                               int index);
 593 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
 594                               struct s3c_fimc_isp_info *cam);
 595 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
 596 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
 597                                 struct s3c_fimc_isp_info *cam);
 598 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
 599                             struct s3c_fimc_isp_info *cam);
 600
 601 /* -----------------------------------------------------*/
 602 /* fimc-core.c */
 603 int fimc_vidioc_enum_fmt(struct file *file, void *priv,
 604                       struct v4l2_fmtdesc *f);
 605 int fimc_vidioc_g_fmt(struct file *file, void *priv,
 606                       struct v4l2_format *f);
 607 int fimc_vidioc_try_fmt(struct file *file, void *priv,
 608                         struct v4l2_format *f);
 609 int fimc_vidioc_queryctrl(struct file *file, void *priv,
 610                           struct v4l2_queryctrl *qc);
 611 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
 612                        struct v4l2_control *ctrl);
 613
 614 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
 615 int check_ctrl_val(struct fimc_ctx *ctx,  struct v4l2_control *ctrl);
 616 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
 617
 618 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
 619 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
 620                                   unsigned int mask);
 621
 622 int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f);
 623 int fimc_set_scaler_info(struct fimc_ctx *ctx);
 624 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
 625 int fimc_prepare_addr(struct fimc_ctx *ctx, struct fimc_vid_buffer *buf,
 626                       struct fimc_frame *frame, struct fimc_addr *paddr);
 627
 628 /* -----------------------------------------------------*/
 629 /* fimc-capture.c                                       */
 630 int fimc_register_capture_device(struct fimc_dev *fimc);
 631 void fimc_unregister_capture_device(struct fimc_dev *fimc);
 632 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
 633 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
 634                              struct fimc_vid_buffer *fimc_vb);
 635
 636 /* Locking: the caller holds fimc->slock */
 637 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
 638 {
 639         fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
 640         fimc_hw_en_capture(ctx);
 641 }
 642
 643 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
 644 {
 645         fimc_hw_en_lastirq(fimc, true);
 646         fimc_hw_dis_capture(fimc);
 647         fimc_hw_enable_scaler(fimc, false);
 648         fimc_hw_en_lastirq(fimc, false);
 649 }
 650
 651 /*
 652  * Add video buffer to the active buffers queue.
 653  * The caller holds irqlock spinlock.
 654  */
 655 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
 656                                          struct fimc_vid_buffer *buf)
 657 {
 658         buf->vb.state = VIDEOBUF_ACTIVE;
 659         list_add_tail(&buf->vb.queue, &vid_cap->active_buf_q);
 660         vid_cap->active_buf_cnt++;
 661 }
 662
 663 /*
 664  * Pop a video buffer from the capture active buffers queue
 665  * Locking: Need to be called with dev->slock held.
 666  */
 667 static inline struct fimc_vid_buffer *
 668 active_queue_pop(struct fimc_vid_cap *vid_cap)
 669 {
 670         struct fimc_vid_buffer *buf;
 671         buf = list_entry(vid_cap->active_buf_q.next,
 672                          struct fimc_vid_buffer, vb.queue);
 673         list_del(&buf->vb.queue);
 674         vid_cap->active_buf_cnt--;
 675         return buf;
 676 }
 677
 678 /* Add video buffer to the capture pending buffers queue */
 679 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
 680                                           struct fimc_vid_buffer *buf)
 681 {
 682         buf->vb.state = VIDEOBUF_QUEUED;
 683         list_add_tail(&buf->vb.queue, &vid_cap->pending_buf_q);
 684 }
 685
 686 /* Add video buffer to the capture pending buffers queue */
 687 static inline struct fimc_vid_buffer *
 688 pending_queue_pop(struct fimc_vid_cap *vid_cap)
 689 {
 690         struct fimc_vid_buffer *buf;
 691         buf = list_entry(vid_cap->pending_buf_q.next,
 692                         struct fimc_vid_buffer, vb.queue);
 693         list_del(&buf->vb.queue);
 694         return buf;
 695 }
 696
 697
 698 #endif /* FIMC_CORE_H_ */