2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/gpio/driver.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_address.h>
30 #include <linux/of_mtd.h>
31 #include <linux/of_device.h>
32 #include <linux/of_platform.h>
33 #include <linux/omap-gpmc.h>
34 #include <linux/pm_runtime.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
37 #include <linux/platform_data/mtd-onenand-omap2.h>
39 #include <asm/mach-types.h>
41 #define DEVICE_NAME "omap-gpmc"
43 /* GPMC register offsets */
44 #define GPMC_REVISION 0x00
45 #define GPMC_SYSCONFIG 0x10
46 #define GPMC_SYSSTATUS 0x14
47 #define GPMC_IRQSTATUS 0x18
48 #define GPMC_IRQENABLE 0x1c
49 #define GPMC_TIMEOUT_CONTROL 0x40
50 #define GPMC_ERR_ADDRESS 0x44
51 #define GPMC_ERR_TYPE 0x48
52 #define GPMC_CONFIG 0x50
53 #define GPMC_STATUS 0x54
54 #define GPMC_PREFETCH_CONFIG1 0x1e0
55 #define GPMC_PREFETCH_CONFIG2 0x1e4
56 #define GPMC_PREFETCH_CONTROL 0x1ec
57 #define GPMC_PREFETCH_STATUS 0x1f0
58 #define GPMC_ECC_CONFIG 0x1f4
59 #define GPMC_ECC_CONTROL 0x1f8
60 #define GPMC_ECC_SIZE_CONFIG 0x1fc
61 #define GPMC_ECC1_RESULT 0x200
62 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
70 /* GPMC ECC control settings */
71 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
72 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
73 #define GPMC_ECC_CTRL_ECCREG1 0x001
74 #define GPMC_ECC_CTRL_ECCREG2 0x002
75 #define GPMC_ECC_CTRL_ECCREG3 0x003
76 #define GPMC_ECC_CTRL_ECCREG4 0x004
77 #define GPMC_ECC_CTRL_ECCREG5 0x005
78 #define GPMC_ECC_CTRL_ECCREG6 0x006
79 #define GPMC_ECC_CTRL_ECCREG7 0x007
80 #define GPMC_ECC_CTRL_ECCREG8 0x008
81 #define GPMC_ECC_CTRL_ECCREG9 0x009
83 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
85 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
87 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
88 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
89 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
90 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
91 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
92 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
94 #define GPMC_CS0_OFFSET 0x60
95 #define GPMC_CS_SIZE 0x30
96 #define GPMC_BCH_SIZE 0x10
99 * The first 1MB of GPMC address space is typically mapped to
100 * the internal ROM. Never allocate the first page, to
101 * facilitate bug detection; even if we didn't boot from ROM.
102 * As GPMC minimum partition size is 16MB we can only start from
105 #define GPMC_MEM_START 0x1000000
106 #define GPMC_MEM_END 0x3FFFFFFF
108 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
109 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
111 #define CS_NUM_SHIFT 24
112 #define ENABLE_PREFETCH (0x1 << 7)
113 #define DMA_MPU_MODE 2
115 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
116 #define GPMC_REVISION_MINOR(l) (l & 0xf)
118 #define GPMC_HAS_WR_ACCESS 0x1
119 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
120 #define GPMC_HAS_MUX_AAD 0x4
122 #define GPMC_NR_WAITPINS 4
124 #define GPMC_CS_CONFIG1 0x00
125 #define GPMC_CS_CONFIG2 0x04
126 #define GPMC_CS_CONFIG3 0x08
127 #define GPMC_CS_CONFIG4 0x0c
128 #define GPMC_CS_CONFIG5 0x10
129 #define GPMC_CS_CONFIG6 0x14
130 #define GPMC_CS_CONFIG7 0x18
131 #define GPMC_CS_NAND_COMMAND 0x1c
132 #define GPMC_CS_NAND_ADDRESS 0x20
133 #define GPMC_CS_NAND_DATA 0x24
135 /* Control Commands */
136 #define GPMC_CONFIG_RDY_BSY 0x00000001
137 #define GPMC_CONFIG_DEV_SIZE 0x00000002
138 #define GPMC_CONFIG_DEV_TYPE 0x00000003
140 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
141 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
142 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
143 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
144 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
145 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
146 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
147 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
148 /** CLKACTIVATIONTIME Max Ticks */
149 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
150 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
151 /** ATTACHEDDEVICEPAGELENGTH Max Value */
152 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
153 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
154 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
155 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
156 /** WAITMONITORINGTIME Max Ticks */
157 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
158 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
159 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
160 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
161 /** DEVICESIZE Max Value */
162 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
163 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
164 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
165 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
166 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
167 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
168 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
169 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
170 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
171 #define GPMC_CONFIG7_CSVALID (1 << 6)
173 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
174 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
175 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
176 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
177 /* All CONFIG7 bits except reserved bits */
178 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
179 GPMC_CONFIG7_CSVALID_MASK | \
180 GPMC_CONFIG7_MASKADDRESS_MASK)
182 #define GPMC_DEVICETYPE_NOR 0
183 #define GPMC_DEVICETYPE_NAND 2
184 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
185 #define WR_RD_PIN_MONITORING 0x00600000
188 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
189 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
190 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
192 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
194 enum gpmc_clk_domain
{
199 struct gpmc_cs_data
{
202 #define GPMC_CS_RESERVED (1 << 0)
208 /* Structure to save gpmc cs context */
209 struct gpmc_cs_config
{
221 * Structure to save/restore gpmc context
222 * to support core off on OMAP3
224 struct omap3_gpmc_regs
{
229 u32 prefetch_config1
;
230 u32 prefetch_config2
;
231 u32 prefetch_control
;
232 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
238 struct irq_chip irq_chip
;
239 struct gpio_chip gpio_chip
;
243 static struct irq_domain
*gpmc_irq_domain
;
245 static struct resource gpmc_mem_root
;
246 static struct gpmc_cs_data gpmc_cs
[GPMC_CS_NUM
];
247 static DEFINE_SPINLOCK(gpmc_mem_lock
);
248 /* Define chip-selects as reserved by default until probe completes */
249 static unsigned int gpmc_cs_num
= GPMC_CS_NUM
;
250 static unsigned int gpmc_nr_waitpins
;
251 static resource_size_t phys_base
, mem_size
;
252 static unsigned gpmc_capability
;
253 static void __iomem
*gpmc_base
;
255 static struct clk
*gpmc_l3_clk
;
257 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
259 static void gpmc_write_reg(int idx
, u32 val
)
261 writel_relaxed(val
, gpmc_base
+ idx
);
264 static u32
gpmc_read_reg(int idx
)
266 return readl_relaxed(gpmc_base
+ idx
);
269 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
271 void __iomem
*reg_addr
;
273 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
274 writel_relaxed(val
, reg_addr
);
277 static u32
gpmc_cs_read_reg(int cs
, int idx
)
279 void __iomem
*reg_addr
;
281 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
282 return readl_relaxed(reg_addr
);
285 /* TODO: Add support for gpmc_fck to clock framework and use it */
286 static unsigned long gpmc_get_fclk_period(void)
288 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
291 rate
= 1000000000 / rate
; /* In picoseconds */
297 * gpmc_get_clk_period - get period of selected clock domain in ps
298 * @cs Chip Select Region.
301 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
302 * prior to calling this function with GPMC_CD_CLK.
304 static unsigned long gpmc_get_clk_period(int cs
, enum gpmc_clk_domain cd
)
307 unsigned long tick_ps
= gpmc_get_fclk_period();
313 /* get current clk divider */
314 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
315 div
= (l
& 0x03) + 1;
316 /* get GPMC_CLK period */
329 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns
, int cs
,
330 enum gpmc_clk_domain cd
)
332 unsigned long tick_ps
;
334 /* Calculate in picosecs to yield more exact results */
335 tick_ps
= gpmc_get_clk_period(cs
, cd
);
337 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
340 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
342 return gpmc_ns_to_clk_ticks(time_ns
, /* any CS */ 0, GPMC_CD_FCLK
);
345 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
347 unsigned long tick_ps
;
349 /* Calculate in picosecs to yield more exact results */
350 tick_ps
= gpmc_get_fclk_period();
352 return (time_ps
+ tick_ps
- 1) / tick_ps
;
355 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks
, int cs
,
356 enum gpmc_clk_domain cd
)
358 return ticks
* gpmc_get_clk_period(cs
, cd
) / 1000;
361 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
363 return gpmc_clk_ticks_to_ns(ticks
, /* any CS */ 0, GPMC_CD_FCLK
);
366 static unsigned int gpmc_ticks_to_ps(unsigned int ticks
)
368 return ticks
* gpmc_get_fclk_period();
371 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps
)
373 unsigned long ticks
= gpmc_ps_to_ticks(time_ps
);
375 return ticks
* gpmc_get_fclk_period();
378 static inline void gpmc_cs_modify_reg(int cs
, int reg
, u32 mask
, bool value
)
382 l
= gpmc_cs_read_reg(cs
, reg
);
387 gpmc_cs_write_reg(cs
, reg
, l
);
390 static void gpmc_cs_bool_timings(int cs
, const struct gpmc_bool_timings
*p
)
392 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG1
,
393 GPMC_CONFIG1_TIME_PARA_GRAN
,
394 p
->time_para_granularity
);
395 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG2
,
396 GPMC_CONFIG2_CSEXTRADELAY
, p
->cs_extra_delay
);
397 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG3
,
398 GPMC_CONFIG3_ADVEXTRADELAY
, p
->adv_extra_delay
);
399 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
400 GPMC_CONFIG4_OEEXTRADELAY
, p
->oe_extra_delay
);
401 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
402 GPMC_CONFIG4_OEEXTRADELAY
, p
->we_extra_delay
);
403 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
404 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
,
405 p
->cycle2cyclesamecsen
);
406 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
407 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
,
408 p
->cycle2cyclediffcsen
);
411 #ifdef CONFIG_OMAP_GPMC_DEBUG
413 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
414 * @cs: Chip Select Region
415 * @reg: GPMC_CS_CONFIGn register offset.
417 * @end_bit: End Bit. Must be >= @st_bit.
418 * @ma:x Maximum parameter value (before optional @shift).
419 * If 0, maximum is as high as @st_bit and @end_bit allow.
420 * @name: DTS node name, w/o "gpmc,"
421 * @cd: Clock Domain of timing parameter.
422 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
423 * @raw: Raw Format Option.
424 * raw format: gpmc,name = <value>
425 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
426 * Where x ns -- y ns result in the same tick value.
427 * When @max is exceeded, "invalid" is printed inside comment.
428 * @noval: Parameter values equal to 0 are not printed.
429 * @return: Specified timing parameter (after optional @shift).
432 static int get_gpmc_timing_reg(
433 /* timing specifiers */
434 int cs
, int reg
, int st_bit
, int end_bit
, int max
,
435 const char *name
, const enum gpmc_clk_domain cd
,
436 /* value transform */
438 /* format specifiers */
439 bool raw
, bool noval
)
446 l
= gpmc_cs_read_reg(cs
, reg
);
447 nr_bits
= end_bit
- st_bit
+ 1;
448 mask
= (1 << nr_bits
) - 1;
449 l
= (l
>> st_bit
) & mask
;
455 if (noval
&& (l
== 0))
458 /* DTS tick format for timings in ns */
459 unsigned int time_ns
;
460 unsigned int time_ns_min
= 0;
463 time_ns_min
= gpmc_clk_ticks_to_ns(l
- 1, cs
, cd
) + 1;
464 time_ns
= gpmc_clk_ticks_to_ns(l
, cs
, cd
);
465 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
466 name
, time_ns
, time_ns_min
, time_ns
, l
,
467 invalid
? "; invalid " : " ");
470 pr_info("gpmc,%s = <%u>%s\n", name
, l
,
471 invalid
? " /* invalid */" : "");
477 #define GPMC_PRINT_CONFIG(cs, config) \
478 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
479 gpmc_cs_read_reg(cs, config))
480 #define GPMC_GET_RAW(reg, st, end, field) \
481 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
482 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
483 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
484 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
485 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
486 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
487 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
488 #define GPMC_GET_TICKS(reg, st, end, field) \
489 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
490 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
491 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
492 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
493 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
495 static void gpmc_show_regs(int cs
, const char *desc
)
497 pr_info("gpmc cs%i %s:\n", cs
, desc
);
498 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG1
);
499 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG2
);
500 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG3
);
501 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG4
);
502 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG5
);
503 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG6
);
507 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
508 * see commit c9fb809.
510 static void gpmc_cs_show_timings(int cs
, const char *desc
)
512 gpmc_show_regs(cs
, desc
);
514 pr_info("gpmc cs%i access configuration:\n", cs
);
515 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 4, 4, "time-para-granularity");
516 GPMC_GET_RAW(GPMC_CS_CONFIG1
, 8, 9, "mux-add-data");
517 GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1
, 12, 13,
518 GPMC_CONFIG1_DEVICESIZE_MAX
, "device-width");
519 GPMC_GET_RAW(GPMC_CS_CONFIG1
, 16, 17, "wait-pin");
520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 21, 21, "wait-on-write");
521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 22, 22, "wait-on-read");
522 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1
, 23, 24, 4,
523 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX
,
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 27, 27, "sync-write");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 28, 28, "burst-write");
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 29, 29, "gpmc,sync-read");
528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 30, 30, "burst-read");
529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 31, 31, "burst-wrap");
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2
, 7, 7, "cs-extra-delay");
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3
, 7, 7, "adv-extra-delay");
535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4
, 23, 23, "we-extra-delay");
536 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4
, 7, 7, "oe-extra-delay");
538 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6
, 7, 7, "cycle2cycle-samecsen");
539 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6
, 6, 6, "cycle2cycle-diffcsen");
541 pr_info("gpmc cs%i timings configuration:\n", cs
);
542 GPMC_GET_TICKS(GPMC_CS_CONFIG2
, 0, 3, "cs-on-ns");
543 GPMC_GET_TICKS(GPMC_CS_CONFIG2
, 8, 12, "cs-rd-off-ns");
544 GPMC_GET_TICKS(GPMC_CS_CONFIG2
, 16, 20, "cs-wr-off-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 0, 3, "adv-on-ns");
547 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 8, 12, "adv-rd-off-ns");
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 16, 20, "adv-wr-off-ns");
549 if (gpmc_capability
& GPMC_HAS_MUX_AAD
) {
550 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 4, 6, "adv-aad-mux-on-ns");
551 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 24, 26,
552 "adv-aad-mux-rd-off-ns");
553 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 28, 30,
554 "adv-aad-mux-wr-off-ns");
557 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 0, 3, "oe-on-ns");
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 8, 12, "oe-off-ns");
559 if (gpmc_capability
& GPMC_HAS_MUX_AAD
) {
560 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 4, 6, "oe-aad-mux-on-ns");
561 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 13, 15, "oe-aad-mux-off-ns");
563 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 16, 19, "we-on-ns");
564 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 24, 28, "we-off-ns");
566 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 0, 4, "rd-cycle-ns");
567 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 8, 12, "wr-cycle-ns");
568 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 16, 20, "access-ns");
570 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 24, 27, "page-burst-access-ns");
572 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 0, 3, "bus-turnaround-ns");
573 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 8, 11, "cycle2cycle-delay-ns");
575 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1
, 18, 19,
576 GPMC_CONFIG1_WAITMONITORINGTIME_MAX
,
577 "wait-monitoring-ns", GPMC_CD_CLK
);
578 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1
, 25, 26,
579 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX
,
580 "clk-activation-ns", GPMC_CD_FCLK
);
582 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 16, 19, "wr-data-mux-bus-ns");
583 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 24, 28, "wr-access-ns");
586 static inline void gpmc_cs_show_timings(int cs
, const char *desc
)
592 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
593 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
594 * prior to calling this function with @cd equal to GPMC_CD_CLK.
596 * @cs: Chip Select Region.
597 * @reg: GPMC_CS_CONFIGn register offset.
599 * @end_bit: End Bit. Must be >= @st_bit.
600 * @max: Maximum parameter value.
601 * If 0, maximum is as high as @st_bit and @end_bit allow.
602 * @time: Timing parameter in ns.
603 * @cd: Timing parameter clock domain.
604 * @name: Timing parameter name.
605 * @return: 0 on success, -1 on error.
607 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
, int max
,
608 int time
, enum gpmc_clk_domain cd
, const char *name
)
611 int ticks
, mask
, nr_bits
;
616 ticks
= gpmc_ns_to_clk_ticks(time
, cs
, cd
);
617 nr_bits
= end_bit
- st_bit
+ 1;
618 mask
= (1 << nr_bits
) - 1;
624 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
625 __func__
, cs
, name
, time
, ticks
, max
);
630 l
= gpmc_cs_read_reg(cs
, reg
);
631 #ifdef CONFIG_OMAP_GPMC_DEBUG
633 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
634 cs
, name
, ticks
, gpmc_get_clk_period(cs
, cd
) * ticks
/ 1000,
635 (l
>> st_bit
) & mask
, time
);
637 l
&= ~(mask
<< st_bit
);
638 l
|= ticks
<< st_bit
;
639 gpmc_cs_write_reg(cs
, reg
, l
);
644 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
645 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
646 t->field, (cd), #field) < 0) \
649 #define GPMC_SET_ONE(reg, st, end, field) \
650 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
653 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
654 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
655 * read --> don't sample bus too early
656 * write --> data is longer on bus
659 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
660 * / waitmonitoring_ticks)
661 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
664 * @wait_monitoring: WAITMONITORINGTIME in ns.
665 * @return: -1 on failure to scale, else proper divider > 0.
667 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring
)
670 int div
= gpmc_ns_to_ticks(wait_monitoring
);
672 div
+= GPMC_CONFIG1_WAITMONITORINGTIME_MAX
- 1;
673 div
/= GPMC_CONFIG1_WAITMONITORINGTIME_MAX
;
685 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
686 * @sync_clk: GPMC_CLK period in ps.
687 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
690 int gpmc_calc_divider(unsigned int sync_clk
)
692 int div
= gpmc_ps_to_ticks(sync_clk
);
703 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
704 * @cs: Chip Select Region.
705 * @t: GPMC timing parameters.
706 * @s: GPMC timing settings.
707 * @return: 0 on success, -1 on error.
709 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
,
710 const struct gpmc_settings
*s
)
715 div
= gpmc_calc_divider(t
->sync_clk
);
720 * See if we need to change the divider for waitmonitoringtime.
722 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
723 * pure asynchronous accesses, i.e. both read and write asynchronous.
724 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
725 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
727 * This statement must not change div to scale async WAITMONITORINGTIME
728 * to protect mixed synchronous and asynchronous accesses.
730 * We raise an error later if WAITMONITORINGTIME does not fit.
732 if (!s
->sync_read
&& !s
->sync_write
&&
733 (s
->wait_on_read
|| s
->wait_on_write
)
736 div
= gpmc_calc_waitmonitoring_divider(t
->wait_monitoring
);
738 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
746 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
747 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
748 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
750 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
751 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
752 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
753 if (gpmc_capability
& GPMC_HAS_MUX_AAD
) {
754 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 4, 6, adv_aad_mux_on
);
755 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 24, 26, adv_aad_mux_rd_off
);
756 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 28, 30, adv_aad_mux_wr_off
);
759 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
760 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
761 if (gpmc_capability
& GPMC_HAS_MUX_AAD
) {
762 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 4, 6, oe_aad_mux_on
);
763 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 13, 15, oe_aad_mux_off
);
765 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
766 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
768 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
769 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
770 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
772 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
774 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 0, 3, bus_turnaround
);
775 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 8, 11, cycle2cycle_delay
);
777 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
778 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
779 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
780 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
782 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
785 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
787 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1
, 18, 19,
788 GPMC_CONFIG1_WAITMONITORINGTIME_MAX
,
789 wait_monitoring
, GPMC_CD_CLK
);
790 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1
, 25, 26,
791 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX
,
792 clk_activation
, GPMC_CD_FCLK
);
794 #ifdef CONFIG_OMAP_GPMC_DEBUG
795 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
796 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
799 gpmc_cs_bool_timings(cs
, &t
->bool_timings
);
800 gpmc_cs_show_timings(cs
, "after gpmc_cs_set_timings");
805 static int gpmc_cs_set_memconf(int cs
, u32 base
, u32 size
)
811 * Ensure that base address is aligned on a
812 * boundary equal to or greater than size.
814 if (base
& (size
- 1))
817 base
>>= GPMC_CHUNK_SHIFT
;
818 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
819 mask
>>= GPMC_CHUNK_SHIFT
;
820 mask
<<= GPMC_CONFIG7_MASKADDRESS_OFFSET
;
822 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
823 l
&= ~GPMC_CONFIG7_MASK
;
824 l
|= base
& GPMC_CONFIG7_BASEADDRESS_MASK
;
825 l
|= mask
& GPMC_CONFIG7_MASKADDRESS_MASK
;
826 l
|= GPMC_CONFIG7_CSVALID
;
827 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
832 static void gpmc_cs_enable_mem(int cs
)
836 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
837 l
|= GPMC_CONFIG7_CSVALID
;
838 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
841 static void gpmc_cs_disable_mem(int cs
)
845 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
846 l
&= ~GPMC_CONFIG7_CSVALID
;
847 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
850 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
855 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
856 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
857 mask
= (l
>> 8) & 0x0f;
858 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
861 static int gpmc_cs_mem_enabled(int cs
)
865 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
866 return l
& GPMC_CONFIG7_CSVALID
;
869 static void gpmc_cs_set_reserved(int cs
, int reserved
)
871 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
873 gpmc
->flags
|= GPMC_CS_RESERVED
;
876 static bool gpmc_cs_reserved(int cs
)
878 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
880 return gpmc
->flags
& GPMC_CS_RESERVED
;
883 static void gpmc_cs_set_name(int cs
, const char *name
)
885 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
890 static const char *gpmc_cs_get_name(int cs
)
892 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
897 static unsigned long gpmc_mem_align(unsigned long size
)
901 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
902 order
= GPMC_CHUNK_SHIFT
- 1;
911 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
913 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
914 struct resource
*res
= &gpmc
->mem
;
917 size
= gpmc_mem_align(size
);
918 spin_lock(&gpmc_mem_lock
);
920 res
->end
= base
+ size
- 1;
921 r
= request_resource(&gpmc_mem_root
, res
);
922 spin_unlock(&gpmc_mem_lock
);
927 static int gpmc_cs_delete_mem(int cs
)
929 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
930 struct resource
*res
= &gpmc
->mem
;
933 spin_lock(&gpmc_mem_lock
);
934 r
= release_resource(res
);
937 spin_unlock(&gpmc_mem_lock
);
943 * gpmc_cs_remap - remaps a chip-select physical base address
944 * @cs: chip-select to remap
945 * @base: physical base address to re-map chip-select to
947 * Re-maps a chip-select to a new physical base address specified by
948 * "base". Returns 0 on success and appropriate negative error code
951 static int gpmc_cs_remap(int cs
, u32 base
)
956 if (cs
> gpmc_cs_num
) {
957 pr_err("%s: requested chip-select is disabled\n", __func__
);
962 * Make sure we ignore any device offsets from the GPMC partition
963 * allocated for the chip select and that the new base confirms
964 * to the GPMC 16MB minimum granularity.
966 base
&= ~(SZ_16M
- 1);
968 gpmc_cs_get_memconf(cs
, &old_base
, &size
);
969 if (base
== old_base
)
972 ret
= gpmc_cs_delete_mem(cs
);
976 ret
= gpmc_cs_insert_mem(cs
, base
, size
);
980 ret
= gpmc_cs_set_memconf(cs
, base
, size
);
985 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
987 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
988 struct resource
*res
= &gpmc
->mem
;
991 if (cs
> gpmc_cs_num
) {
992 pr_err("%s: requested chip-select is disabled\n", __func__
);
995 size
= gpmc_mem_align(size
);
996 if (size
> (1 << GPMC_SECTION_SHIFT
))
999 spin_lock(&gpmc_mem_lock
);
1000 if (gpmc_cs_reserved(cs
)) {
1004 if (gpmc_cs_mem_enabled(cs
))
1005 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
1007 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
1012 /* Disable CS while changing base address and size mask */
1013 gpmc_cs_disable_mem(cs
);
1015 r
= gpmc_cs_set_memconf(cs
, res
->start
, resource_size(res
));
1017 release_resource(res
);
1022 gpmc_cs_enable_mem(cs
);
1024 gpmc_cs_set_reserved(cs
, 1);
1026 spin_unlock(&gpmc_mem_lock
);
1029 EXPORT_SYMBOL(gpmc_cs_request
);
1031 void gpmc_cs_free(int cs
)
1033 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
1034 struct resource
*res
= &gpmc
->mem
;
1036 spin_lock(&gpmc_mem_lock
);
1037 if (cs
>= gpmc_cs_num
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
1038 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
1040 spin_unlock(&gpmc_mem_lock
);
1043 gpmc_cs_disable_mem(cs
);
1045 release_resource(res
);
1046 gpmc_cs_set_reserved(cs
, 0);
1047 spin_unlock(&gpmc_mem_lock
);
1049 EXPORT_SYMBOL(gpmc_cs_free
);
1052 * gpmc_configure - write request to configure gpmc
1053 * @cmd: command type
1054 * @wval: value to write
1055 * @return status of the operation
1057 int gpmc_configure(int cmd
, int wval
)
1062 case GPMC_CONFIG_WP
:
1063 regval
= gpmc_read_reg(GPMC_CONFIG
);
1065 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
1067 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
1068 gpmc_write_reg(GPMC_CONFIG
, regval
);
1072 pr_err("%s: command not supported\n", __func__
);
1078 EXPORT_SYMBOL(gpmc_configure
);
1080 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
1084 reg
->gpmc_status
= NULL
; /* deprecated */
1085 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
1086 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
1087 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
1088 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
1089 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
1090 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
1091 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
1092 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
1093 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
1094 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
1095 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
1096 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
1097 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
1098 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
1100 for (i
= 0; i
< GPMC_BCH_NUM_REMAINDER
; i
++) {
1101 reg
->gpmc_bch_result0
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_0
+
1103 reg
->gpmc_bch_result1
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_1
+
1105 reg
->gpmc_bch_result2
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_2
+
1107 reg
->gpmc_bch_result3
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_3
+
1109 reg
->gpmc_bch_result4
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_4
+
1111 reg
->gpmc_bch_result5
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_5
+
1113 reg
->gpmc_bch_result6
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_6
+
1118 static bool gpmc_nand_writebuffer_empty(void)
1120 if (gpmc_read_reg(GPMC_STATUS
) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS
)
1126 static struct gpmc_nand_ops nand_ops
= {
1127 .nand_writebuffer_empty
= gpmc_nand_writebuffer_empty
,
1131 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1132 * @regs: the GPMC NAND register map exclusive for NAND use.
1133 * @cs: GPMC chip select number on which the NAND sits. The
1134 * register map returned will be specific to this chip select.
1136 * Returns NULL on error e.g. invalid cs.
1138 struct gpmc_nand_ops
*gpmc_omap_get_nand_ops(struct gpmc_nand_regs
*reg
, int cs
)
1140 if (cs
>= gpmc_cs_num
)
1143 gpmc_update_nand_reg(reg
, cs
);
1147 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops
);
1149 int gpmc_get_client_irq(unsigned irq_config
)
1151 if (!gpmc_irq_domain
) {
1152 pr_warn("%s called before GPMC IRQ domain available\n",
1157 /* we restrict this to NAND IRQs only */
1158 if (irq_config
>= GPMC_NR_NAND_IRQS
)
1161 return irq_create_mapping(gpmc_irq_domain
, irq_config
);
1164 static int gpmc_irq_endis(unsigned long hwirq
, bool endis
)
1168 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1169 if (hwirq
>= GPMC_NR_NAND_IRQS
)
1170 hwirq
+= 8 - GPMC_NR_NAND_IRQS
;
1172 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
1174 regval
|= BIT(hwirq
);
1176 regval
&= ~BIT(hwirq
);
1177 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
1182 static void gpmc_irq_disable(struct irq_data
*p
)
1184 gpmc_irq_endis(p
->hwirq
, false);
1187 static void gpmc_irq_enable(struct irq_data
*p
)
1189 gpmc_irq_endis(p
->hwirq
, true);
1192 static void gpmc_irq_mask(struct irq_data
*d
)
1194 gpmc_irq_endis(d
->hwirq
, false);
1197 static void gpmc_irq_unmask(struct irq_data
*d
)
1199 gpmc_irq_endis(d
->hwirq
, true);
1202 static void gpmc_irq_edge_config(unsigned long hwirq
, bool rising_edge
)
1206 /* NAND IRQs polarity is not configurable */
1207 if (hwirq
< GPMC_NR_NAND_IRQS
)
1210 /* WAITPIN starts at BIT 8 */
1211 hwirq
+= 8 - GPMC_NR_NAND_IRQS
;
1213 regval
= gpmc_read_reg(GPMC_CONFIG
);
1215 regval
&= ~BIT(hwirq
);
1217 regval
|= BIT(hwirq
);
1219 gpmc_write_reg(GPMC_CONFIG
, regval
);
1222 static void gpmc_irq_ack(struct irq_data
*d
)
1224 unsigned int hwirq
= d
->hwirq
;
1226 /* skip reserved bits */
1227 if (hwirq
>= GPMC_NR_NAND_IRQS
)
1228 hwirq
+= 8 - GPMC_NR_NAND_IRQS
;
1230 /* Setting bit to 1 clears (or Acks) the interrupt */
1231 gpmc_write_reg(GPMC_IRQSTATUS
, BIT(hwirq
));
1234 static int gpmc_irq_set_type(struct irq_data
*d
, unsigned int trigger
)
1236 /* can't set type for NAND IRQs */
1237 if (d
->hwirq
< GPMC_NR_NAND_IRQS
)
1240 /* We can support either rising or falling edge at a time */
1241 if (trigger
== IRQ_TYPE_EDGE_FALLING
)
1242 gpmc_irq_edge_config(d
->hwirq
, false);
1243 else if (trigger
== IRQ_TYPE_EDGE_RISING
)
1244 gpmc_irq_edge_config(d
->hwirq
, true);
1251 static int gpmc_irq_map(struct irq_domain
*d
, unsigned int virq
,
1254 struct gpmc_device
*gpmc
= d
->host_data
;
1256 irq_set_chip_data(virq
, gpmc
);
1257 if (hw
< GPMC_NR_NAND_IRQS
) {
1258 irq_modify_status(virq
, IRQ_NOREQUEST
, IRQ_NOAUTOEN
);
1259 irq_set_chip_and_handler(virq
, &gpmc
->irq_chip
,
1262 irq_set_chip_and_handler(virq
, &gpmc
->irq_chip
,
1269 static const struct irq_domain_ops gpmc_irq_domain_ops
= {
1270 .map
= gpmc_irq_map
,
1271 .xlate
= irq_domain_xlate_twocell
,
1274 static irqreturn_t
gpmc_handle_irq(int irq
, void *data
)
1277 u32 regval
, regvalx
;
1278 struct gpmc_device
*gpmc
= data
;
1280 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1286 for (hwirq
= 0; hwirq
< gpmc
->nirqs
; hwirq
++) {
1287 /* skip reserved status bits */
1288 if (hwirq
== GPMC_NR_NAND_IRQS
)
1289 regvalx
>>= 8 - GPMC_NR_NAND_IRQS
;
1291 if (regvalx
& BIT(hwirq
)) {
1292 virq
= irq_find_mapping(gpmc_irq_domain
, hwirq
);
1295 "spurious irq detected hwirq %d, virq %d\n",
1299 generic_handle_irq(virq
);
1303 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1308 static int gpmc_setup_irq(struct gpmc_device
*gpmc
)
1313 /* Disable interrupts */
1314 gpmc_write_reg(GPMC_IRQENABLE
, 0);
1316 /* clear interrupts */
1317 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1318 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1320 gpmc
->irq_chip
.name
= "gpmc";
1321 gpmc
->irq_chip
.irq_enable
= gpmc_irq_enable
;
1322 gpmc
->irq_chip
.irq_disable
= gpmc_irq_disable
;
1323 gpmc
->irq_chip
.irq_ack
= gpmc_irq_ack
;
1324 gpmc
->irq_chip
.irq_mask
= gpmc_irq_mask
;
1325 gpmc
->irq_chip
.irq_unmask
= gpmc_irq_unmask
;
1326 gpmc
->irq_chip
.irq_set_type
= gpmc_irq_set_type
;
1328 gpmc_irq_domain
= irq_domain_add_linear(gpmc
->dev
->of_node
,
1330 &gpmc_irq_domain_ops
,
1332 if (!gpmc_irq_domain
) {
1333 dev_err(gpmc
->dev
, "IRQ domain add failed\n");
1337 rc
= request_irq(gpmc
->irq
, gpmc_handle_irq
, 0, "gpmc", gpmc
);
1339 dev_err(gpmc
->dev
, "failed to request irq %d: %d\n",
1341 irq_domain_remove(gpmc_irq_domain
);
1342 gpmc_irq_domain
= NULL
;
1348 static int gpmc_free_irq(struct gpmc_device
*gpmc
)
1352 free_irq(gpmc
->irq
, gpmc
);
1354 for (hwirq
= 0; hwirq
< gpmc
->nirqs
; hwirq
++)
1355 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain
, hwirq
));
1357 irq_domain_remove(gpmc_irq_domain
);
1358 gpmc_irq_domain
= NULL
;
1363 static void gpmc_mem_exit(void)
1367 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
1368 if (!gpmc_cs_mem_enabled(cs
))
1370 gpmc_cs_delete_mem(cs
);
1375 static void gpmc_mem_init(void)
1379 gpmc_mem_root
.start
= GPMC_MEM_START
;
1380 gpmc_mem_root
.end
= GPMC_MEM_END
;
1382 /* Reserve all regions that has been set up by bootloader */
1383 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
1386 if (!gpmc_cs_mem_enabled(cs
))
1388 gpmc_cs_get_memconf(cs
, &base
, &size
);
1389 if (gpmc_cs_insert_mem(cs
, base
, size
)) {
1390 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1391 __func__
, cs
, base
, base
+ size
);
1392 gpmc_cs_disable_mem(cs
);
1397 static u32
gpmc_round_ps_to_sync_clk(u32 time_ps
, u32 sync_clk
)
1402 div
= gpmc_calc_divider(sync_clk
);
1403 temp
= gpmc_ps_to_ticks(time_ps
);
1404 temp
= (temp
+ div
- 1) / div
;
1405 return gpmc_ticks_to_ps(temp
* div
);
1408 /* XXX: can the cycles be avoided ? */
1409 static int gpmc_calc_sync_read_timings(struct gpmc_timings
*gpmc_t
,
1410 struct gpmc_device_timings
*dev_t
,
1416 temp
= dev_t
->t_avdp_r
;
1417 /* XXX: mux check required ? */
1419 /* XXX: t_avdp not to be required for sync, only added for tusb
1420 * this indirectly necessitates requirement of t_avdp_r and
1421 * t_avdp_w instead of having a single t_avdp
1423 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
1424 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1426 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
1429 temp
= dev_t
->t_oeasu
; /* XXX: remove this ? */
1431 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_ach
);
1432 temp
= max_t(u32
, temp
, gpmc_t
->adv_rd_off
+
1433 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_oe
));
1435 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
1438 /* XXX: any scope for improvement ?, by combining oe_on
1439 * and clk_activation, need to check whether
1440 * access = clk_activation + round to sync clk ?
1442 temp
= max_t(u32
, dev_t
->t_iaa
, dev_t
->cyc_iaa
* gpmc_t
->sync_clk
);
1443 temp
+= gpmc_t
->clk_activation
;
1445 temp
= max_t(u32
, temp
, gpmc_t
->oe_on
+
1446 gpmc_ticks_to_ps(dev_t
->cyc_oe
));
1447 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
1449 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
1450 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
1453 temp
= max_t(u32
, dev_t
->t_cez_r
, dev_t
->t_oez
);
1454 temp
= gpmc_round_ps_to_sync_clk(temp
, gpmc_t
->sync_clk
) +
1456 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1457 if (dev_t
->t_ce_rdyz
)
1458 temp
= max_t(u32
, temp
, gpmc_t
->cs_rd_off
+ dev_t
->t_ce_rdyz
);
1459 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
1464 static int gpmc_calc_sync_write_timings(struct gpmc_timings
*gpmc_t
,
1465 struct gpmc_device_timings
*dev_t
,
1471 temp
= dev_t
->t_avdp_w
;
1473 temp
= max_t(u32
, temp
,
1474 gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
1475 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1477 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
1479 /* wr_data_mux_bus */
1480 temp
= max_t(u32
, dev_t
->t_weasu
,
1481 gpmc_t
->clk_activation
+ dev_t
->t_rdyo
);
1482 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1483 * and in that case remember to handle we_on properly
1486 temp
= max_t(u32
, temp
,
1487 gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1488 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1489 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1491 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1494 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1495 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1497 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1500 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1501 gpmc_t
->wr_access
= gpmc_t
->access
;
1504 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1505 temp
= max_t(u32
, temp
,
1506 gpmc_t
->wr_access
+ gpmc_ticks_to_ps(1));
1507 temp
= max_t(u32
, temp
,
1508 gpmc_t
->we_on
+ gpmc_ticks_to_ps(dev_t
->cyc_wpl
));
1509 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1511 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1515 temp
= gpmc_round_ps_to_sync_clk(dev_t
->t_cez_w
, gpmc_t
->sync_clk
);
1516 temp
+= gpmc_t
->wr_access
;
1517 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1518 if (dev_t
->t_ce_rdyz
)
1519 temp
= max_t(u32
, temp
,
1520 gpmc_t
->cs_wr_off
+ dev_t
->t_ce_rdyz
);
1521 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1526 static int gpmc_calc_async_read_timings(struct gpmc_timings
*gpmc_t
,
1527 struct gpmc_device_timings
*dev_t
,
1533 temp
= dev_t
->t_avdp_r
;
1535 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1536 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
1539 temp
= dev_t
->t_oeasu
;
1541 temp
= max_t(u32
, temp
,
1542 gpmc_t
->adv_rd_off
+ dev_t
->t_aavdh
);
1543 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
1546 temp
= max_t(u32
, dev_t
->t_iaa
, /* XXX: remove t_iaa in async ? */
1547 gpmc_t
->oe_on
+ dev_t
->t_oe
);
1548 temp
= max_t(u32
, temp
,
1549 gpmc_t
->cs_on
+ dev_t
->t_ce
);
1550 temp
= max_t(u32
, temp
,
1551 gpmc_t
->adv_on
+ dev_t
->t_aa
);
1552 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
1554 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
1555 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
1558 temp
= max_t(u32
, dev_t
->t_rd_cycle
,
1559 gpmc_t
->cs_rd_off
+ dev_t
->t_cez_r
);
1560 temp
= max_t(u32
, temp
, gpmc_t
->oe_off
+ dev_t
->t_oez
);
1561 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
1566 static int gpmc_calc_async_write_timings(struct gpmc_timings
*gpmc_t
,
1567 struct gpmc_device_timings
*dev_t
,
1573 temp
= dev_t
->t_avdp_w
;
1575 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1576 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
1578 /* wr_data_mux_bus */
1579 temp
= dev_t
->t_weasu
;
1581 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1582 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1583 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1585 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1588 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1589 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1591 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1594 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1595 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1597 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1601 temp
= max_t(u32
, dev_t
->t_wr_cycle
,
1602 gpmc_t
->cs_wr_off
+ dev_t
->t_cez_w
);
1603 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1608 static int gpmc_calc_sync_common_timings(struct gpmc_timings
*gpmc_t
,
1609 struct gpmc_device_timings
*dev_t
)
1613 gpmc_t
->sync_clk
= gpmc_calc_divider(dev_t
->clk
) *
1614 gpmc_get_fclk_period();
1616 gpmc_t
->page_burst_access
= gpmc_round_ps_to_sync_clk(
1620 temp
= max_t(u32
, dev_t
->t_ces
, dev_t
->t_avds
);
1621 gpmc_t
->clk_activation
= gpmc_round_ps_to_ticks(temp
);
1623 if (gpmc_calc_divider(gpmc_t
->sync_clk
) != 1)
1626 if (dev_t
->ce_xdelay
)
1627 gpmc_t
->bool_timings
.cs_extra_delay
= true;
1628 if (dev_t
->avd_xdelay
)
1629 gpmc_t
->bool_timings
.adv_extra_delay
= true;
1630 if (dev_t
->oe_xdelay
)
1631 gpmc_t
->bool_timings
.oe_extra_delay
= true;
1632 if (dev_t
->we_xdelay
)
1633 gpmc_t
->bool_timings
.we_extra_delay
= true;
1638 static int gpmc_calc_common_timings(struct gpmc_timings
*gpmc_t
,
1639 struct gpmc_device_timings
*dev_t
,
1645 gpmc_t
->cs_on
= gpmc_round_ps_to_ticks(dev_t
->t_ceasu
);
1648 temp
= dev_t
->t_avdasu
;
1649 if (dev_t
->t_ce_avd
)
1650 temp
= max_t(u32
, temp
,
1651 gpmc_t
->cs_on
+ dev_t
->t_ce_avd
);
1652 gpmc_t
->adv_on
= gpmc_round_ps_to_ticks(temp
);
1655 gpmc_calc_sync_common_timings(gpmc_t
, dev_t
);
1660 /* TODO: remove this function once all peripherals are confirmed to
1661 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1662 * has to be modified to handle timings in ps instead of ns
1664 static void gpmc_convert_ps_to_ns(struct gpmc_timings
*t
)
1667 t
->cs_rd_off
/= 1000;
1668 t
->cs_wr_off
/= 1000;
1670 t
->adv_rd_off
/= 1000;
1671 t
->adv_wr_off
/= 1000;
1676 t
->page_burst_access
/= 1000;
1678 t
->rd_cycle
/= 1000;
1679 t
->wr_cycle
/= 1000;
1680 t
->bus_turnaround
/= 1000;
1681 t
->cycle2cycle_delay
/= 1000;
1682 t
->wait_monitoring
/= 1000;
1683 t
->clk_activation
/= 1000;
1684 t
->wr_access
/= 1000;
1685 t
->wr_data_mux_bus
/= 1000;
1688 int gpmc_calc_timings(struct gpmc_timings
*gpmc_t
,
1689 struct gpmc_settings
*gpmc_s
,
1690 struct gpmc_device_timings
*dev_t
)
1692 bool mux
= false, sync
= false;
1695 mux
= gpmc_s
->mux_add_data
? true : false;
1696 sync
= (gpmc_s
->sync_read
|| gpmc_s
->sync_write
);
1699 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1701 gpmc_calc_common_timings(gpmc_t
, dev_t
, sync
);
1703 if (gpmc_s
&& gpmc_s
->sync_read
)
1704 gpmc_calc_sync_read_timings(gpmc_t
, dev_t
, mux
);
1706 gpmc_calc_async_read_timings(gpmc_t
, dev_t
, mux
);
1708 if (gpmc_s
&& gpmc_s
->sync_write
)
1709 gpmc_calc_sync_write_timings(gpmc_t
, dev_t
, mux
);
1711 gpmc_calc_async_write_timings(gpmc_t
, dev_t
, mux
);
1713 /* TODO: remove, see function definition */
1714 gpmc_convert_ps_to_ns(gpmc_t
);
1720 * gpmc_cs_program_settings - programs non-timing related settings
1721 * @cs: GPMC chip-select to program
1722 * @p: pointer to GPMC settings structure
1724 * Programs non-timing related settings for a GPMC chip-select, such as
1725 * bus-width, burst configuration, etc. Function should be called once
1726 * for each chip-select that is being used and must be called before
1727 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1728 * register will be initialised to zero by this function. Returns 0 on
1729 * success and appropriate negative error code on failure.
1731 int gpmc_cs_program_settings(int cs
, struct gpmc_settings
*p
)
1735 if ((!p
->device_width
) || (p
->device_width
> GPMC_DEVWIDTH_16BIT
)) {
1736 pr_err("%s: invalid width %d!", __func__
, p
->device_width
);
1740 /* Address-data multiplexing not supported for NAND devices */
1741 if (p
->device_nand
&& p
->mux_add_data
) {
1742 pr_err("%s: invalid configuration!\n", __func__
);
1746 if ((p
->mux_add_data
> GPMC_MUX_AD
) ||
1747 ((p
->mux_add_data
== GPMC_MUX_AAD
) &&
1748 !(gpmc_capability
& GPMC_HAS_MUX_AAD
))) {
1749 pr_err("%s: invalid multiplex configuration!\n", __func__
);
1753 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1754 if (p
->burst_read
|| p
->burst_write
) {
1755 switch (p
->burst_len
) {
1761 pr_err("%s: invalid page/burst-length (%d)\n",
1762 __func__
, p
->burst_len
);
1767 if (p
->wait_pin
> gpmc_nr_waitpins
) {
1768 pr_err("%s: invalid wait-pin (%d)\n", __func__
, p
->wait_pin
);
1772 config1
= GPMC_CONFIG1_DEVICESIZE((p
->device_width
- 1));
1775 config1
|= GPMC_CONFIG1_READTYPE_SYNC
;
1777 config1
|= GPMC_CONFIG1_WRITETYPE_SYNC
;
1778 if (p
->wait_on_read
)
1779 config1
|= GPMC_CONFIG1_WAIT_READ_MON
;
1780 if (p
->wait_on_write
)
1781 config1
|= GPMC_CONFIG1_WAIT_WRITE_MON
;
1782 if (p
->wait_on_read
|| p
->wait_on_write
)
1783 config1
|= GPMC_CONFIG1_WAIT_PIN_SEL(p
->wait_pin
);
1785 config1
|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND
);
1786 if (p
->mux_add_data
)
1787 config1
|= GPMC_CONFIG1_MUXTYPE(p
->mux_add_data
);
1789 config1
|= GPMC_CONFIG1_READMULTIPLE_SUPP
;
1791 config1
|= GPMC_CONFIG1_WRITEMULTIPLE_SUPP
;
1792 if (p
->burst_read
|| p
->burst_write
) {
1793 config1
|= GPMC_CONFIG1_PAGE_LEN(p
->burst_len
>> 3);
1794 config1
|= p
->burst_wrap
? GPMC_CONFIG1_WRAPBURST_SUPP
: 0;
1797 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, config1
);
1803 static const struct of_device_id gpmc_dt_ids
[] = {
1804 { .compatible
= "ti,omap2420-gpmc" },
1805 { .compatible
= "ti,omap2430-gpmc" },
1806 { .compatible
= "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1807 { .compatible
= "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1808 { .compatible
= "ti,am3352-gpmc" }, /* am335x devices */
1811 MODULE_DEVICE_TABLE(of
, gpmc_dt_ids
);
1814 * gpmc_read_settings_dt - read gpmc settings from device-tree
1815 * @np: pointer to device-tree node for a gpmc child device
1816 * @p: pointer to gpmc settings structure
1818 * Reads the GPMC settings for a GPMC child device from device-tree and
1819 * stores them in the GPMC settings structure passed. The GPMC settings
1820 * structure is initialised to zero by this function and so any
1821 * previously stored settings will be cleared.
1823 void gpmc_read_settings_dt(struct device_node
*np
, struct gpmc_settings
*p
)
1825 memset(p
, 0, sizeof(struct gpmc_settings
));
1827 p
->sync_read
= of_property_read_bool(np
, "gpmc,sync-read");
1828 p
->sync_write
= of_property_read_bool(np
, "gpmc,sync-write");
1829 of_property_read_u32(np
, "gpmc,device-width", &p
->device_width
);
1830 of_property_read_u32(np
, "gpmc,mux-add-data", &p
->mux_add_data
);
1832 if (!of_property_read_u32(np
, "gpmc,burst-length", &p
->burst_len
)) {
1833 p
->burst_wrap
= of_property_read_bool(np
, "gpmc,burst-wrap");
1834 p
->burst_read
= of_property_read_bool(np
, "gpmc,burst-read");
1835 p
->burst_write
= of_property_read_bool(np
, "gpmc,burst-write");
1836 if (!p
->burst_read
&& !p
->burst_write
)
1837 pr_warn("%s: page/burst-length set but not used!\n",
1841 if (!of_property_read_u32(np
, "gpmc,wait-pin", &p
->wait_pin
)) {
1842 p
->wait_on_read
= of_property_read_bool(np
,
1843 "gpmc,wait-on-read");
1844 p
->wait_on_write
= of_property_read_bool(np
,
1845 "gpmc,wait-on-write");
1846 if (!p
->wait_on_read
&& !p
->wait_on_write
)
1847 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1852 static void __maybe_unused
gpmc_read_timings_dt(struct device_node
*np
,
1853 struct gpmc_timings
*gpmc_t
)
1855 struct gpmc_bool_timings
*p
;
1860 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1862 /* minimum clock period for syncronous mode */
1863 of_property_read_u32(np
, "gpmc,sync-clk-ps", &gpmc_t
->sync_clk
);
1865 /* chip select timtings */
1866 of_property_read_u32(np
, "gpmc,cs-on-ns", &gpmc_t
->cs_on
);
1867 of_property_read_u32(np
, "gpmc,cs-rd-off-ns", &gpmc_t
->cs_rd_off
);
1868 of_property_read_u32(np
, "gpmc,cs-wr-off-ns", &gpmc_t
->cs_wr_off
);
1870 /* ADV signal timings */
1871 of_property_read_u32(np
, "gpmc,adv-on-ns", &gpmc_t
->adv_on
);
1872 of_property_read_u32(np
, "gpmc,adv-rd-off-ns", &gpmc_t
->adv_rd_off
);
1873 of_property_read_u32(np
, "gpmc,adv-wr-off-ns", &gpmc_t
->adv_wr_off
);
1874 of_property_read_u32(np
, "gpmc,adv-aad-mux-on-ns",
1875 &gpmc_t
->adv_aad_mux_on
);
1876 of_property_read_u32(np
, "gpmc,adv-aad-mux-rd-off-ns",
1877 &gpmc_t
->adv_aad_mux_rd_off
);
1878 of_property_read_u32(np
, "gpmc,adv-aad-mux-wr-off-ns",
1879 &gpmc_t
->adv_aad_mux_wr_off
);
1881 /* WE signal timings */
1882 of_property_read_u32(np
, "gpmc,we-on-ns", &gpmc_t
->we_on
);
1883 of_property_read_u32(np
, "gpmc,we-off-ns", &gpmc_t
->we_off
);
1885 /* OE signal timings */
1886 of_property_read_u32(np
, "gpmc,oe-on-ns", &gpmc_t
->oe_on
);
1887 of_property_read_u32(np
, "gpmc,oe-off-ns", &gpmc_t
->oe_off
);
1888 of_property_read_u32(np
, "gpmc,oe-aad-mux-on-ns",
1889 &gpmc_t
->oe_aad_mux_on
);
1890 of_property_read_u32(np
, "gpmc,oe-aad-mux-off-ns",
1891 &gpmc_t
->oe_aad_mux_off
);
1893 /* access and cycle timings */
1894 of_property_read_u32(np
, "gpmc,page-burst-access-ns",
1895 &gpmc_t
->page_burst_access
);
1896 of_property_read_u32(np
, "gpmc,access-ns", &gpmc_t
->access
);
1897 of_property_read_u32(np
, "gpmc,rd-cycle-ns", &gpmc_t
->rd_cycle
);
1898 of_property_read_u32(np
, "gpmc,wr-cycle-ns", &gpmc_t
->wr_cycle
);
1899 of_property_read_u32(np
, "gpmc,bus-turnaround-ns",
1900 &gpmc_t
->bus_turnaround
);
1901 of_property_read_u32(np
, "gpmc,cycle2cycle-delay-ns",
1902 &gpmc_t
->cycle2cycle_delay
);
1903 of_property_read_u32(np
, "gpmc,wait-monitoring-ns",
1904 &gpmc_t
->wait_monitoring
);
1905 of_property_read_u32(np
, "gpmc,clk-activation-ns",
1906 &gpmc_t
->clk_activation
);
1908 /* only applicable to OMAP3+ */
1909 of_property_read_u32(np
, "gpmc,wr-access-ns", &gpmc_t
->wr_access
);
1910 of_property_read_u32(np
, "gpmc,wr-data-mux-bus-ns",
1911 &gpmc_t
->wr_data_mux_bus
);
1913 /* bool timing parameters */
1914 p
= &gpmc_t
->bool_timings
;
1916 p
->cycle2cyclediffcsen
=
1917 of_property_read_bool(np
, "gpmc,cycle2cycle-diffcsen");
1918 p
->cycle2cyclesamecsen
=
1919 of_property_read_bool(np
, "gpmc,cycle2cycle-samecsen");
1920 p
->we_extra_delay
= of_property_read_bool(np
, "gpmc,we-extra-delay");
1921 p
->oe_extra_delay
= of_property_read_bool(np
, "gpmc,oe-extra-delay");
1922 p
->adv_extra_delay
= of_property_read_bool(np
, "gpmc,adv-extra-delay");
1923 p
->cs_extra_delay
= of_property_read_bool(np
, "gpmc,cs-extra-delay");
1924 p
->time_para_granularity
=
1925 of_property_read_bool(np
, "gpmc,time-para-granularity");
1928 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1929 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1930 struct device_node
*child
)
1933 struct omap_onenand_platform_data
*gpmc_onenand_data
;
1935 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1936 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1941 gpmc_onenand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_onenand_data
),
1943 if (!gpmc_onenand_data
)
1946 gpmc_onenand_data
->cs
= val
;
1947 gpmc_onenand_data
->of_node
= child
;
1948 gpmc_onenand_data
->dma_channel
= -1;
1950 if (!of_property_read_u32(child
, "dma-channel", &val
))
1951 gpmc_onenand_data
->dma_channel
= val
;
1953 gpmc_onenand_init(gpmc_onenand_data
);
1958 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1959 struct device_node
*child
)
1966 * gpmc_probe_generic_child - configures the gpmc for a child device
1967 * @pdev: pointer to gpmc platform device
1968 * @child: pointer to device-tree node for child device
1970 * Allocates and configures a GPMC chip-select for a child device.
1971 * Returns 0 on success and appropriate negative error code on failure.
1973 static int gpmc_probe_generic_child(struct platform_device
*pdev
,
1974 struct device_node
*child
)
1976 struct gpmc_settings gpmc_s
;
1977 struct gpmc_timings gpmc_t
;
1978 struct resource res
;
1983 struct gpio_desc
*waitpin_desc
= NULL
;
1984 struct gpmc_device
*gpmc
= platform_get_drvdata(pdev
);
1986 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1987 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1992 if (of_address_to_resource(child
, 0, &res
) < 0) {
1993 dev_err(&pdev
->dev
, "%s has malformed 'reg' property\n",
1999 * Check if we have multiple instances of the same device
2000 * on a single chip select. If so, use the already initialized
2003 name
= gpmc_cs_get_name(cs
);
2004 if (name
&& child
->name
&& of_node_cmp(child
->name
, name
) == 0)
2007 ret
= gpmc_cs_request(cs
, resource_size(&res
), &base
);
2009 dev_err(&pdev
->dev
, "cannot request GPMC CS %d\n", cs
);
2012 gpmc_cs_set_name(cs
, child
->name
);
2014 gpmc_read_settings_dt(child
, &gpmc_s
);
2015 gpmc_read_timings_dt(child
, &gpmc_t
);
2018 * For some GPMC devices we still need to rely on the bootloader
2019 * timings because the devices can be connected via FPGA.
2020 * REVISIT: Add timing support from slls644g.pdf.
2022 if (!gpmc_t
.cs_rd_off
) {
2023 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2025 gpmc_cs_show_timings(cs
,
2026 "please add GPMC bootloader timings to .dts");
2030 /* CS must be disabled while making changes to gpmc configuration */
2031 gpmc_cs_disable_mem(cs
);
2034 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2035 * location in the gpmc address space. When booting with
2036 * device-tree we want the NOR flash to be mapped to the
2037 * location specified in the device-tree blob. So remap the
2038 * CS to this location. Once DT migration is complete should
2039 * just make gpmc_cs_request() map a specific address.
2041 ret
= gpmc_cs_remap(cs
, res
.start
);
2043 dev_err(&pdev
->dev
, "cannot remap GPMC CS %d to %pa\n",
2045 if (res
.start
< GPMC_MEM_START
) {
2046 dev_info(&pdev
->dev
,
2047 "GPMC CS %d start cannot be lesser than 0x%x\n",
2048 cs
, GPMC_MEM_START
);
2049 } else if (res
.end
> GPMC_MEM_END
) {
2050 dev_info(&pdev
->dev
,
2051 "GPMC CS %d end cannot be greater than 0x%x\n",
2057 if (of_node_cmp(child
->name
, "nand") == 0) {
2058 /* Warn about older DT blobs with no compatible property */
2059 if (!of_property_read_bool(child
, "compatible")) {
2060 dev_warn(&pdev
->dev
,
2061 "Incompatible NAND node: missing compatible");
2067 if (of_device_is_compatible(child
, "ti,omap2-nand")) {
2068 /* NAND specific setup */
2069 val
= of_get_nand_bus_width(child
);
2072 gpmc_s
.device_width
= GPMC_DEVWIDTH_8BIT
;
2075 gpmc_s
.device_width
= GPMC_DEVWIDTH_16BIT
;
2078 dev_err(&pdev
->dev
, "%s: invalid 'nand-bus-width'\n",
2084 /* disable write protect */
2085 gpmc_configure(GPMC_CONFIG_WP
, 0);
2086 gpmc_s
.device_nand
= true;
2088 ret
= of_property_read_u32(child
, "bank-width",
2089 &gpmc_s
.device_width
);
2094 /* Reserve wait pin if it is required and valid */
2095 if (gpmc_s
.wait_on_read
|| gpmc_s
.wait_on_write
) {
2096 unsigned int wait_pin
= gpmc_s
.wait_pin
;
2098 waitpin_desc
= gpiochip_request_own_desc(&gpmc
->gpio_chip
,
2099 wait_pin
, "WAITPIN");
2100 if (IS_ERR(waitpin_desc
)) {
2101 dev_err(&pdev
->dev
, "invalid wait-pin: %d\n", wait_pin
);
2102 ret
= PTR_ERR(waitpin_desc
);
2107 gpmc_cs_show_timings(cs
, "before gpmc_cs_program_settings");
2109 ret
= gpmc_cs_program_settings(cs
, &gpmc_s
);
2113 ret
= gpmc_cs_set_timings(cs
, &gpmc_t
, &gpmc_s
);
2115 dev_err(&pdev
->dev
, "failed to set gpmc timings for: %s\n",
2120 /* Clear limited address i.e. enable A26-A11 */
2121 val
= gpmc_read_reg(GPMC_CONFIG
);
2122 val
&= ~GPMC_CONFIG_LIMITEDADDRESS
;
2123 gpmc_write_reg(GPMC_CONFIG
, val
);
2125 /* Enable CS region */
2126 gpmc_cs_enable_mem(cs
);
2130 /* create platform device, NULL on error or when disabled */
2131 if (!of_platform_device_create(child
, NULL
, &pdev
->dev
))
2132 goto err_child_fail
;
2134 /* is child a common bus? */
2135 if (of_match_node(of_default_bus_match_table
, child
))
2136 /* create children and other common bus children */
2137 if (of_platform_populate(child
, of_default_bus_match_table
,
2139 goto err_child_fail
;
2145 dev_err(&pdev
->dev
, "failed to create gpmc child %s\n", child
->name
);
2150 gpiochip_free_own_desc(waitpin_desc
);
2158 static int gpmc_gpio_get_direction(struct gpio_chip
*chip
, unsigned int offset
)
2160 return 1; /* we're input only */
2163 static int gpmc_gpio_direction_input(struct gpio_chip
*chip
,
2164 unsigned int offset
)
2166 return 0; /* we're input only */
2169 static int gpmc_gpio_direction_output(struct gpio_chip
*chip
,
2170 unsigned int offset
, int value
)
2172 return -EINVAL
; /* we're input only */
2175 static void gpmc_gpio_set(struct gpio_chip
*chip
, unsigned int offset
,
2180 static int gpmc_gpio_get(struct gpio_chip
*chip
, unsigned int offset
)
2186 reg
= gpmc_read_reg(GPMC_STATUS
) & BIT(offset
);
2191 static int gpmc_gpio_init(struct gpmc_device
*gpmc
)
2195 gpmc
->gpio_chip
.parent
= gpmc
->dev
;
2196 gpmc
->gpio_chip
.owner
= THIS_MODULE
;
2197 gpmc
->gpio_chip
.label
= DEVICE_NAME
;
2198 gpmc
->gpio_chip
.ngpio
= gpmc_nr_waitpins
;
2199 gpmc
->gpio_chip
.get_direction
= gpmc_gpio_get_direction
;
2200 gpmc
->gpio_chip
.direction_input
= gpmc_gpio_direction_input
;
2201 gpmc
->gpio_chip
.direction_output
= gpmc_gpio_direction_output
;
2202 gpmc
->gpio_chip
.set
= gpmc_gpio_set
;
2203 gpmc
->gpio_chip
.get
= gpmc_gpio_get
;
2204 gpmc
->gpio_chip
.base
= -1;
2206 ret
= gpiochip_add(&gpmc
->gpio_chip
);
2208 dev_err(gpmc
->dev
, "could not register gpio chip: %d\n", ret
);
2215 static void gpmc_gpio_exit(struct gpmc_device
*gpmc
)
2217 gpiochip_remove(&gpmc
->gpio_chip
);
2220 static int gpmc_probe_dt(struct platform_device
*pdev
)
2223 const struct of_device_id
*of_id
=
2224 of_match_device(gpmc_dt_ids
, &pdev
->dev
);
2229 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-cs",
2232 pr_err("%s: number of chip-selects not defined\n", __func__
);
2234 } else if (gpmc_cs_num
< 1) {
2235 pr_err("%s: all chip-selects are disabled\n", __func__
);
2237 } else if (gpmc_cs_num
> GPMC_CS_NUM
) {
2238 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2239 __func__
, GPMC_CS_NUM
);
2243 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-waitpins",
2246 pr_err("%s: number of wait pins not found!\n", __func__
);
2253 static int gpmc_probe_dt_children(struct platform_device
*pdev
)
2256 struct device_node
*child
;
2258 for_each_available_child_of_node(pdev
->dev
.of_node
, child
) {
2263 if (of_node_cmp(child
->name
, "onenand") == 0)
2264 ret
= gpmc_probe_onenand_child(pdev
, child
);
2266 ret
= gpmc_probe_generic_child(pdev
, child
);
2275 static int gpmc_probe_dt(struct platform_device
*pdev
)
2280 static int gpmc_probe_dt_children(struct platform_device
*pdev
)
2286 static int gpmc_probe(struct platform_device
*pdev
)
2290 struct resource
*res
;
2291 struct gpmc_device
*gpmc
;
2293 gpmc
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc
), GFP_KERNEL
);
2297 gpmc
->dev
= &pdev
->dev
;
2298 platform_set_drvdata(pdev
, gpmc
);
2300 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2304 phys_base
= res
->start
;
2305 mem_size
= resource_size(res
);
2307 gpmc_base
= devm_ioremap_resource(&pdev
->dev
, res
);
2308 if (IS_ERR(gpmc_base
))
2309 return PTR_ERR(gpmc_base
);
2311 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2313 dev_err(&pdev
->dev
, "Failed to get resource: irq\n");
2317 gpmc
->irq
= res
->start
;
2319 gpmc_l3_clk
= devm_clk_get(&pdev
->dev
, "fck");
2320 if (IS_ERR(gpmc_l3_clk
)) {
2321 dev_err(&pdev
->dev
, "Failed to get GPMC fck\n");
2322 return PTR_ERR(gpmc_l3_clk
);
2325 if (!clk_get_rate(gpmc_l3_clk
)) {
2326 dev_err(&pdev
->dev
, "Invalid GPMC fck clock rate\n");
2330 if (pdev
->dev
.of_node
) {
2331 rc
= gpmc_probe_dt(pdev
);
2335 gpmc_cs_num
= GPMC_CS_NUM
;
2336 gpmc_nr_waitpins
= GPMC_NR_WAITPINS
;
2339 pm_runtime_enable(&pdev
->dev
);
2340 pm_runtime_get_sync(&pdev
->dev
);
2342 l
= gpmc_read_reg(GPMC_REVISION
);
2345 * FIXME: Once device-tree migration is complete the below flags
2346 * should be populated based upon the device-tree compatible
2347 * string. For now just use the IP revision. OMAP3+ devices have
2348 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2349 * devices support the addr-addr-data multiplex protocol.
2351 * GPMC IP revisions:
2354 * - OMAP44xx/54xx/AM335x = 6.0
2356 if (GPMC_REVISION_MAJOR(l
) > 0x4)
2357 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
2358 if (GPMC_REVISION_MAJOR(l
) > 0x5)
2359 gpmc_capability
|= GPMC_HAS_MUX_AAD
;
2360 dev_info(gpmc
->dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
2361 GPMC_REVISION_MINOR(l
));
2364 rc
= gpmc_gpio_init(gpmc
);
2366 goto gpio_init_failed
;
2368 gpmc
->nirqs
= GPMC_NR_NAND_IRQS
+ gpmc_nr_waitpins
;
2369 rc
= gpmc_setup_irq(gpmc
);
2371 dev_err(gpmc
->dev
, "gpmc_setup_irq failed\n");
2372 goto setup_irq_failed
;
2375 rc
= gpmc_probe_dt_children(pdev
);
2377 dev_err(gpmc
->dev
, "failed to probe DT children\n");
2378 goto dt_children_failed
;
2384 gpmc_free_irq(gpmc
);
2386 gpmc_gpio_exit(gpmc
);
2389 pm_runtime_put_sync(&pdev
->dev
);
2390 pm_runtime_disable(&pdev
->dev
);
2395 static int gpmc_remove(struct platform_device
*pdev
)
2397 struct gpmc_device
*gpmc
= platform_get_drvdata(pdev
);
2399 gpmc_free_irq(gpmc
);
2400 gpmc_gpio_exit(gpmc
);
2402 pm_runtime_put_sync(&pdev
->dev
);
2403 pm_runtime_disable(&pdev
->dev
);
2408 #ifdef CONFIG_PM_SLEEP
2409 static int gpmc_suspend(struct device
*dev
)
2411 omap3_gpmc_save_context();
2412 pm_runtime_put_sync(dev
);
2416 static int gpmc_resume(struct device
*dev
)
2418 pm_runtime_get_sync(dev
);
2419 omap3_gpmc_restore_context();
2424 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops
, gpmc_suspend
, gpmc_resume
);
2426 static struct platform_driver gpmc_driver
= {
2427 .probe
= gpmc_probe
,
2428 .remove
= gpmc_remove
,
2430 .name
= DEVICE_NAME
,
2431 .of_match_table
= of_match_ptr(gpmc_dt_ids
),
2436 static __init
int gpmc_init(void)
2438 return platform_driver_register(&gpmc_driver
);
2441 static __exit
void gpmc_exit(void)
2443 platform_driver_unregister(&gpmc_driver
);
2447 postcore_initcall(gpmc_init
);
2448 module_exit(gpmc_exit
);
2450 static struct omap3_gpmc_regs gpmc_context
;
2452 void omap3_gpmc_save_context(void)
2459 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
2460 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
2461 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
2462 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
2463 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
2464 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
2465 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
2466 for (i
= 0; i
< gpmc_cs_num
; i
++) {
2467 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
2468 if (gpmc_context
.cs_context
[i
].is_valid
) {
2469 gpmc_context
.cs_context
[i
].config1
=
2470 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
2471 gpmc_context
.cs_context
[i
].config2
=
2472 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
2473 gpmc_context
.cs_context
[i
].config3
=
2474 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
2475 gpmc_context
.cs_context
[i
].config4
=
2476 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
2477 gpmc_context
.cs_context
[i
].config5
=
2478 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
2479 gpmc_context
.cs_context
[i
].config6
=
2480 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
2481 gpmc_context
.cs_context
[i
].config7
=
2482 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
2487 void omap3_gpmc_restore_context(void)
2494 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
2495 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
2496 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
2497 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
2498 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
2499 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
2500 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
2501 for (i
= 0; i
< gpmc_cs_num
; i
++) {
2502 if (gpmc_context
.cs_context
[i
].is_valid
) {
2503 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
2504 gpmc_context
.cs_context
[i
].config1
);
2505 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
2506 gpmc_context
.cs_context
[i
].config2
);
2507 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
2508 gpmc_context
.cs_context
[i
].config3
);
2509 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
2510 gpmc_context
.cs_context
[i
].config4
);
2511 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
2512 gpmc_context
.cs_context
[i
].config5
);
2513 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
2514 gpmc_context
.cs_context
[i
].config6
);
2515 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
2516 gpmc_context
.cs_context
[i
].config7
);