2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
27 #include <linux/of_address.h>
28 #include <linux/of_mtd.h>
29 #include <linux/of_device.h>
30 #include <linux/of_platform.h>
31 #include <linux/omap-gpmc.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/pm_runtime.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
36 #include <linux/platform_data/mtd-onenand-omap2.h>
38 #include <asm/mach-types.h>
40 #define DEVICE_NAME "omap-gpmc"
42 /* GPMC register offsets */
43 #define GPMC_REVISION 0x00
44 #define GPMC_SYSCONFIG 0x10
45 #define GPMC_SYSSTATUS 0x14
46 #define GPMC_IRQSTATUS 0x18
47 #define GPMC_IRQENABLE 0x1c
48 #define GPMC_TIMEOUT_CONTROL 0x40
49 #define GPMC_ERR_ADDRESS 0x44
50 #define GPMC_ERR_TYPE 0x48
51 #define GPMC_CONFIG 0x50
52 #define GPMC_STATUS 0x54
53 #define GPMC_PREFETCH_CONFIG1 0x1e0
54 #define GPMC_PREFETCH_CONFIG2 0x1e4
55 #define GPMC_PREFETCH_CONTROL 0x1ec
56 #define GPMC_PREFETCH_STATUS 0x1f0
57 #define GPMC_ECC_CONFIG 0x1f4
58 #define GPMC_ECC_CONTROL 0x1f8
59 #define GPMC_ECC_SIZE_CONFIG 0x1fc
60 #define GPMC_ECC1_RESULT 0x200
61 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
69 /* GPMC ECC control settings */
70 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
71 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
72 #define GPMC_ECC_CTRL_ECCREG1 0x001
73 #define GPMC_ECC_CTRL_ECCREG2 0x002
74 #define GPMC_ECC_CTRL_ECCREG3 0x003
75 #define GPMC_ECC_CTRL_ECCREG4 0x004
76 #define GPMC_ECC_CTRL_ECCREG5 0x005
77 #define GPMC_ECC_CTRL_ECCREG6 0x006
78 #define GPMC_ECC_CTRL_ECCREG7 0x007
79 #define GPMC_ECC_CTRL_ECCREG8 0x008
80 #define GPMC_ECC_CTRL_ECCREG9 0x009
82 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
84 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
85 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
88 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
89 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91 #define GPMC_CS0_OFFSET 0x60
92 #define GPMC_CS_SIZE 0x30
93 #define GPMC_BCH_SIZE 0x10
95 #define GPMC_MEM_END 0x3FFFFFFF
97 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
98 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100 #define CS_NUM_SHIFT 24
101 #define ENABLE_PREFETCH (0x1 << 7)
102 #define DMA_MPU_MODE 2
104 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
105 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107 #define GPMC_HAS_WR_ACCESS 0x1
108 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
109 #define GPMC_HAS_MUX_AAD 0x4
111 #define GPMC_NR_WAITPINS 4
113 #define GPMC_CS_CONFIG1 0x00
114 #define GPMC_CS_CONFIG2 0x04
115 #define GPMC_CS_CONFIG3 0x08
116 #define GPMC_CS_CONFIG4 0x0c
117 #define GPMC_CS_CONFIG5 0x10
118 #define GPMC_CS_CONFIG6 0x14
119 #define GPMC_CS_CONFIG7 0x18
120 #define GPMC_CS_NAND_COMMAND 0x1c
121 #define GPMC_CS_NAND_ADDRESS 0x20
122 #define GPMC_CS_NAND_DATA 0x24
124 /* Control Commands */
125 #define GPMC_CONFIG_RDY_BSY 0x00000001
126 #define GPMC_CONFIG_DEV_SIZE 0x00000002
127 #define GPMC_CONFIG_DEV_TYPE 0x00000003
128 #define GPMC_SET_IRQ_STATUS 0x00000004
130 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
131 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
132 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
133 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
134 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
135 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
136 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
137 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
138 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
139 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
140 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
141 #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
142 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
143 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
144 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
145 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
146 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
147 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
148 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
149 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
150 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
151 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
152 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
153 #define GPMC_CONFIG7_CSVALID (1 << 6)
155 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
156 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
157 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
158 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
159 /* All CONFIG7 bits except reserved bits */
160 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
161 GPMC_CONFIG7_CSVALID_MASK | \
162 GPMC_CONFIG7_MASKADDRESS_MASK)
164 #define GPMC_DEVICETYPE_NOR 0
165 #define GPMC_DEVICETYPE_NAND 2
166 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
167 #define WR_RD_PIN_MONITORING 0x00600000
169 #define GPMC_ENABLE_IRQ 0x0000000d
172 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
173 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
174 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
176 /* XXX: Only NAND irq has been considered,currently these are the only ones used
178 #define GPMC_NR_IRQ 2
180 struct gpmc_cs_data
{
183 #define GPMC_CS_RESERVED (1 << 0)
189 struct gpmc_client_irq
{
194 /* Structure to save gpmc cs context */
195 struct gpmc_cs_config
{
207 * Structure to save/restore gpmc context
208 * to support core off on OMAP3
210 struct omap3_gpmc_regs
{
215 u32 prefetch_config1
;
216 u32 prefetch_config2
;
217 u32 prefetch_control
;
218 struct gpmc_cs_config cs_context
[GPMC_CS_NUM
];
221 static struct gpmc_client_irq gpmc_client_irq
[GPMC_NR_IRQ
];
222 static struct irq_chip gpmc_irq_chip
;
223 static int gpmc_irq_start
;
225 static struct resource gpmc_mem_root
;
226 static struct gpmc_cs_data gpmc_cs
[GPMC_CS_NUM
];
227 static DEFINE_SPINLOCK(gpmc_mem_lock
);
228 /* Define chip-selects as reserved by default until probe completes */
229 static unsigned int gpmc_cs_num
= GPMC_CS_NUM
;
230 static unsigned int gpmc_nr_waitpins
;
231 static struct device
*gpmc_dev
;
233 static resource_size_t phys_base
, mem_size
;
234 static unsigned gpmc_capability
;
235 static void __iomem
*gpmc_base
;
237 static struct clk
*gpmc_l3_clk
;
239 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
);
241 static void gpmc_write_reg(int idx
, u32 val
)
243 writel_relaxed(val
, gpmc_base
+ idx
);
246 static u32
gpmc_read_reg(int idx
)
248 return readl_relaxed(gpmc_base
+ idx
);
251 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
253 void __iomem
*reg_addr
;
255 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
256 writel_relaxed(val
, reg_addr
);
259 static u32
gpmc_cs_read_reg(int cs
, int idx
)
261 void __iomem
*reg_addr
;
263 reg_addr
= gpmc_base
+ GPMC_CS0_OFFSET
+ (cs
* GPMC_CS_SIZE
) + idx
;
264 return readl_relaxed(reg_addr
);
267 /* TODO: Add support for gpmc_fck to clock framework and use it */
268 static unsigned long gpmc_get_fclk_period(void)
270 unsigned long rate
= clk_get_rate(gpmc_l3_clk
);
273 rate
= 1000000000 / rate
; /* In picoseconds */
278 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
280 unsigned long tick_ps
;
282 /* Calculate in picosecs to yield more exact results */
283 tick_ps
= gpmc_get_fclk_period();
285 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
288 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps
)
290 unsigned long tick_ps
;
292 /* Calculate in picosecs to yield more exact results */
293 tick_ps
= gpmc_get_fclk_period();
295 return (time_ps
+ tick_ps
- 1) / tick_ps
;
298 unsigned int gpmc_ticks_to_ns(unsigned int ticks
)
300 return ticks
* gpmc_get_fclk_period() / 1000;
303 static unsigned int gpmc_ticks_to_ps(unsigned int ticks
)
305 return ticks
* gpmc_get_fclk_period();
308 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps
)
310 unsigned long ticks
= gpmc_ps_to_ticks(time_ps
);
312 return ticks
* gpmc_get_fclk_period();
315 static inline void gpmc_cs_modify_reg(int cs
, int reg
, u32 mask
, bool value
)
319 l
= gpmc_cs_read_reg(cs
, reg
);
324 gpmc_cs_write_reg(cs
, reg
, l
);
327 static void gpmc_cs_bool_timings(int cs
, const struct gpmc_bool_timings
*p
)
329 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG1
,
330 GPMC_CONFIG1_TIME_PARA_GRAN
,
331 p
->time_para_granularity
);
332 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG2
,
333 GPMC_CONFIG2_CSEXTRADELAY
, p
->cs_extra_delay
);
334 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG3
,
335 GPMC_CONFIG3_ADVEXTRADELAY
, p
->adv_extra_delay
);
336 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
337 GPMC_CONFIG4_OEEXTRADELAY
, p
->oe_extra_delay
);
338 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG4
,
339 GPMC_CONFIG4_OEEXTRADELAY
, p
->we_extra_delay
);
340 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
341 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
,
342 p
->cycle2cyclesamecsen
);
343 gpmc_cs_modify_reg(cs
, GPMC_CS_CONFIG6
,
344 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
,
345 p
->cycle2cyclediffcsen
);
350 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
351 * @cs: Chip Select Region
352 * @reg: GPMC_CS_CONFIGn register offset.
354 * @end_bit: End Bit. Must be >= @st_bit.
355 * @name: DTS node name, w/o "gpmc,"
356 * @raw: Raw Format Option.
357 * raw format: gpmc,name = <value>
358 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
359 * Where x ns -- y ns result in the same tick value.
360 * @noval: Parameter values equal to 0 are not printed.
361 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
362 * @return: Specified timing parameter (after optional @shift).
365 static int get_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
366 bool raw
, bool noval
, int shift
,
373 l
= gpmc_cs_read_reg(cs
, reg
);
374 nr_bits
= end_bit
- st_bit
+ 1;
375 mask
= (1 << nr_bits
) - 1;
376 l
= (l
>> st_bit
) & mask
;
379 if (noval
&& (l
== 0))
382 /* DTS tick format for timings in ns */
383 unsigned int time_ns
;
384 unsigned int time_ns_min
= 0;
387 time_ns_min
= gpmc_ticks_to_ns(l
- 1) + 1;
388 time_ns
= gpmc_ticks_to_ns(l
);
389 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks */\n",
390 name
, time_ns
, time_ns_min
, time_ns
, l
);
393 pr_info("gpmc,%s = <%u>\n", name
, l
);
399 #define GPMC_PRINT_CONFIG(cs, config) \
400 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
401 gpmc_cs_read_reg(cs, config))
402 #define GPMC_GET_RAW(reg, st, end, field) \
403 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
404 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
405 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
406 #define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
407 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
408 #define GPMC_GET_TICKS(reg, st, end, field) \
409 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
411 static void gpmc_show_regs(int cs
, const char *desc
)
413 pr_info("gpmc cs%i %s:\n", cs
, desc
);
414 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG1
);
415 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG2
);
416 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG3
);
417 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG4
);
418 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG5
);
419 GPMC_PRINT_CONFIG(cs
, GPMC_CS_CONFIG6
);
423 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
424 * see commit c9fb809.
426 static void gpmc_cs_show_timings(int cs
, const char *desc
)
428 gpmc_show_regs(cs
, desc
);
430 pr_info("gpmc cs%i access configuration:\n", cs
);
431 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 4, 4, "time-para-granularity");
432 GPMC_GET_RAW(GPMC_CS_CONFIG1
, 8, 9, "mux-add-data");
433 GPMC_GET_RAW(GPMC_CS_CONFIG1
, 12, 13, "device-width");
434 GPMC_GET_RAW(GPMC_CS_CONFIG1
, 16, 17, "wait-pin");
435 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 21, 21, "wait-on-write");
436 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 22, 22, "wait-on-read");
437 GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1
, 23, 24, 4, "burst-length");
438 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 27, 27, "sync-write");
439 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 28, 28, "burst-write");
440 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 29, 29, "gpmc,sync-read");
441 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 30, 30, "burst-read");
442 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1
, 31, 31, "burst-wrap");
444 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2
, 7, 7, "cs-extra-delay");
446 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3
, 7, 7, "adv-extra-delay");
448 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4
, 23, 23, "we-extra-delay");
449 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4
, 7, 7, "oe-extra-delay");
451 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6
, 7, 7, "cycle2cycle-samecsen");
452 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6
, 6, 6, "cycle2cycle-diffcsen");
454 pr_info("gpmc cs%i timings configuration:\n", cs
);
455 GPMC_GET_TICKS(GPMC_CS_CONFIG2
, 0, 3, "cs-on-ns");
456 GPMC_GET_TICKS(GPMC_CS_CONFIG2
, 8, 12, "cs-rd-off-ns");
457 GPMC_GET_TICKS(GPMC_CS_CONFIG2
, 16, 20, "cs-wr-off-ns");
459 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 0, 3, "adv-on-ns");
460 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 8, 12, "adv-rd-off-ns");
461 GPMC_GET_TICKS(GPMC_CS_CONFIG3
, 16, 20, "adv-wr-off-ns");
463 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 0, 3, "oe-on-ns");
464 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 8, 12, "oe-off-ns");
465 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 16, 19, "we-on-ns");
466 GPMC_GET_TICKS(GPMC_CS_CONFIG4
, 24, 28, "we-off-ns");
468 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 0, 4, "rd-cycle-ns");
469 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 8, 12, "wr-cycle-ns");
470 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 16, 20, "access-ns");
472 GPMC_GET_TICKS(GPMC_CS_CONFIG5
, 24, 27, "page-burst-access-ns");
474 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 0, 3, "bus-turnaround-ns");
475 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 8, 11, "cycle2cycle-delay-ns");
477 GPMC_GET_TICKS(GPMC_CS_CONFIG1
, 18, 19, "wait-monitoring-ns");
478 GPMC_GET_TICKS(GPMC_CS_CONFIG1
, 25, 26, "clk-activation-ns");
480 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 16, 19, "wr-data-mux-bus-ns");
481 GPMC_GET_TICKS(GPMC_CS_CONFIG6
, 24, 28, "wr-access-ns");
484 static inline void gpmc_cs_show_timings(int cs
, const char *desc
)
489 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
490 int time
, const char *name
)
493 int ticks
, mask
, nr_bits
;
498 ticks
= gpmc_ns_to_ticks(time
);
499 nr_bits
= end_bit
- st_bit
+ 1;
500 mask
= (1 << nr_bits
) - 1;
503 pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
504 __func__
, cs
, name
, time
, ticks
, mask
);
509 l
= gpmc_cs_read_reg(cs
, reg
);
512 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
513 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
514 (l
>> st_bit
) & mask
, time
);
516 l
&= ~(mask
<< st_bit
);
517 l
|= ticks
<< st_bit
;
518 gpmc_cs_write_reg(cs
, reg
, l
);
523 #define GPMC_SET_ONE(reg, st, end, field) \
524 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
525 t->field, #field) < 0) \
528 int gpmc_calc_divider(unsigned int sync_clk
)
533 l
= sync_clk
+ (gpmc_get_fclk_period() - 1);
534 div
= l
/ gpmc_get_fclk_period();
543 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
548 gpmc_cs_show_timings(cs
, "before gpmc_cs_set_timings");
549 div
= gpmc_calc_divider(t
->sync_clk
);
553 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
554 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
555 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
557 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
558 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
559 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
561 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
562 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
563 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
564 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
566 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
567 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
568 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
570 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
572 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 0, 3, bus_turnaround
);
573 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 8, 11, cycle2cycle_delay
);
575 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 18, 19, wait_monitoring
);
576 GPMC_SET_ONE(GPMC_CS_CONFIG1
, 25, 26, clk_activation
);
578 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
579 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 16, 19, wr_data_mux_bus
);
580 if (gpmc_capability
& GPMC_HAS_WR_ACCESS
)
581 GPMC_SET_ONE(GPMC_CS_CONFIG6
, 24, 28, wr_access
);
583 /* caller is expected to have initialized CONFIG1 to cover
584 * at least sync vs async
586 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
587 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
589 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
590 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
594 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
597 gpmc_cs_bool_timings(cs
, &t
->bool_timings
);
598 gpmc_cs_show_timings(cs
, "after gpmc_cs_set_timings");
603 static int gpmc_cs_set_memconf(int cs
, u32 base
, u32 size
)
609 * Ensure that base address is aligned on a
610 * boundary equal to or greater than size.
612 if (base
& (size
- 1))
615 base
>>= GPMC_CHUNK_SHIFT
;
616 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
617 mask
>>= GPMC_CHUNK_SHIFT
;
618 mask
<<= GPMC_CONFIG7_MASKADDRESS_OFFSET
;
620 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
621 l
&= ~GPMC_CONFIG7_MASK
;
622 l
|= base
& GPMC_CONFIG7_BASEADDRESS_MASK
;
623 l
|= mask
& GPMC_CONFIG7_MASKADDRESS_MASK
;
624 l
|= GPMC_CONFIG7_CSVALID
;
625 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
630 static void gpmc_cs_enable_mem(int cs
)
634 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
635 l
|= GPMC_CONFIG7_CSVALID
;
636 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
639 static void gpmc_cs_disable_mem(int cs
)
643 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
644 l
&= ~GPMC_CONFIG7_CSVALID
;
645 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
648 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
653 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
654 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
655 mask
= (l
>> 8) & 0x0f;
656 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
659 static int gpmc_cs_mem_enabled(int cs
)
663 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
664 return l
& GPMC_CONFIG7_CSVALID
;
667 static void gpmc_cs_set_reserved(int cs
, int reserved
)
669 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
671 gpmc
->flags
|= GPMC_CS_RESERVED
;
674 static bool gpmc_cs_reserved(int cs
)
676 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
678 return gpmc
->flags
& GPMC_CS_RESERVED
;
681 static void gpmc_cs_set_name(int cs
, const char *name
)
683 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
688 static const char *gpmc_cs_get_name(int cs
)
690 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
695 static unsigned long gpmc_mem_align(unsigned long size
)
699 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
700 order
= GPMC_CHUNK_SHIFT
- 1;
709 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
711 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
712 struct resource
*res
= &gpmc
->mem
;
715 size
= gpmc_mem_align(size
);
716 spin_lock(&gpmc_mem_lock
);
718 res
->end
= base
+ size
- 1;
719 r
= request_resource(&gpmc_mem_root
, res
);
720 spin_unlock(&gpmc_mem_lock
);
725 static int gpmc_cs_delete_mem(int cs
)
727 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
728 struct resource
*res
= &gpmc
->mem
;
731 spin_lock(&gpmc_mem_lock
);
732 r
= release_resource(res
);
735 spin_unlock(&gpmc_mem_lock
);
741 * gpmc_cs_remap - remaps a chip-select physical base address
742 * @cs: chip-select to remap
743 * @base: physical base address to re-map chip-select to
745 * Re-maps a chip-select to a new physical base address specified by
746 * "base". Returns 0 on success and appropriate negative error code
749 static int gpmc_cs_remap(int cs
, u32 base
)
754 if (cs
> gpmc_cs_num
) {
755 pr_err("%s: requested chip-select is disabled\n", __func__
);
760 * Make sure we ignore any device offsets from the GPMC partition
761 * allocated for the chip select and that the new base confirms
762 * to the GPMC 16MB minimum granularity.
764 base
&= ~(SZ_16M
- 1);
766 gpmc_cs_get_memconf(cs
, &old_base
, &size
);
767 if (base
== old_base
)
770 ret
= gpmc_cs_delete_mem(cs
);
774 ret
= gpmc_cs_insert_mem(cs
, base
, size
);
778 ret
= gpmc_cs_set_memconf(cs
, base
, size
);
783 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
785 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
786 struct resource
*res
= &gpmc
->mem
;
789 if (cs
> gpmc_cs_num
) {
790 pr_err("%s: requested chip-select is disabled\n", __func__
);
793 size
= gpmc_mem_align(size
);
794 if (size
> (1 << GPMC_SECTION_SHIFT
))
797 spin_lock(&gpmc_mem_lock
);
798 if (gpmc_cs_reserved(cs
)) {
802 if (gpmc_cs_mem_enabled(cs
))
803 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
805 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
810 /* Disable CS while changing base address and size mask */
811 gpmc_cs_disable_mem(cs
);
813 r
= gpmc_cs_set_memconf(cs
, res
->start
, resource_size(res
));
815 release_resource(res
);
820 gpmc_cs_enable_mem(cs
);
822 gpmc_cs_set_reserved(cs
, 1);
824 spin_unlock(&gpmc_mem_lock
);
827 EXPORT_SYMBOL(gpmc_cs_request
);
829 void gpmc_cs_free(int cs
)
831 struct gpmc_cs_data
*gpmc
= &gpmc_cs
[cs
];
832 struct resource
*res
= &gpmc
->mem
;
834 spin_lock(&gpmc_mem_lock
);
835 if (cs
>= gpmc_cs_num
|| cs
< 0 || !gpmc_cs_reserved(cs
)) {
836 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
838 spin_unlock(&gpmc_mem_lock
);
841 gpmc_cs_disable_mem(cs
);
843 release_resource(res
);
844 gpmc_cs_set_reserved(cs
, 0);
845 spin_unlock(&gpmc_mem_lock
);
847 EXPORT_SYMBOL(gpmc_cs_free
);
850 * gpmc_configure - write request to configure gpmc
852 * @wval: value to write
853 * @return status of the operation
855 int gpmc_configure(int cmd
, int wval
)
860 case GPMC_ENABLE_IRQ
:
861 gpmc_write_reg(GPMC_IRQENABLE
, wval
);
864 case GPMC_SET_IRQ_STATUS
:
865 gpmc_write_reg(GPMC_IRQSTATUS
, wval
);
869 regval
= gpmc_read_reg(GPMC_CONFIG
);
871 regval
&= ~GPMC_CONFIG_WRITEPROTECT
; /* WP is ON */
873 regval
|= GPMC_CONFIG_WRITEPROTECT
; /* WP is OFF */
874 gpmc_write_reg(GPMC_CONFIG
, regval
);
878 pr_err("%s: command not supported\n", __func__
);
884 EXPORT_SYMBOL(gpmc_configure
);
886 void gpmc_update_nand_reg(struct gpmc_nand_regs
*reg
, int cs
)
890 reg
->gpmc_status
= gpmc_base
+ GPMC_STATUS
;
891 reg
->gpmc_nand_command
= gpmc_base
+ GPMC_CS0_OFFSET
+
892 GPMC_CS_NAND_COMMAND
+ GPMC_CS_SIZE
* cs
;
893 reg
->gpmc_nand_address
= gpmc_base
+ GPMC_CS0_OFFSET
+
894 GPMC_CS_NAND_ADDRESS
+ GPMC_CS_SIZE
* cs
;
895 reg
->gpmc_nand_data
= gpmc_base
+ GPMC_CS0_OFFSET
+
896 GPMC_CS_NAND_DATA
+ GPMC_CS_SIZE
* cs
;
897 reg
->gpmc_prefetch_config1
= gpmc_base
+ GPMC_PREFETCH_CONFIG1
;
898 reg
->gpmc_prefetch_config2
= gpmc_base
+ GPMC_PREFETCH_CONFIG2
;
899 reg
->gpmc_prefetch_control
= gpmc_base
+ GPMC_PREFETCH_CONTROL
;
900 reg
->gpmc_prefetch_status
= gpmc_base
+ GPMC_PREFETCH_STATUS
;
901 reg
->gpmc_ecc_config
= gpmc_base
+ GPMC_ECC_CONFIG
;
902 reg
->gpmc_ecc_control
= gpmc_base
+ GPMC_ECC_CONTROL
;
903 reg
->gpmc_ecc_size_config
= gpmc_base
+ GPMC_ECC_SIZE_CONFIG
;
904 reg
->gpmc_ecc1_result
= gpmc_base
+ GPMC_ECC1_RESULT
;
906 for (i
= 0; i
< GPMC_BCH_NUM_REMAINDER
; i
++) {
907 reg
->gpmc_bch_result0
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_0
+
909 reg
->gpmc_bch_result1
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_1
+
911 reg
->gpmc_bch_result2
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_2
+
913 reg
->gpmc_bch_result3
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_3
+
915 reg
->gpmc_bch_result4
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_4
+
917 reg
->gpmc_bch_result5
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_5
+
919 reg
->gpmc_bch_result6
[i
] = gpmc_base
+ GPMC_ECC_BCH_RESULT_6
+
924 int gpmc_get_client_irq(unsigned irq_config
)
928 if (hweight32(irq_config
) > 1)
931 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
932 if (gpmc_client_irq
[i
].bitmask
& irq_config
)
933 return gpmc_client_irq
[i
].irq
;
938 static int gpmc_irq_endis(unsigned irq
, bool endis
)
943 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
944 if (irq
== gpmc_client_irq
[i
].irq
) {
945 regval
= gpmc_read_reg(GPMC_IRQENABLE
);
947 regval
|= gpmc_client_irq
[i
].bitmask
;
949 regval
&= ~gpmc_client_irq
[i
].bitmask
;
950 gpmc_write_reg(GPMC_IRQENABLE
, regval
);
957 static void gpmc_irq_disable(struct irq_data
*p
)
959 gpmc_irq_endis(p
->irq
, false);
962 static void gpmc_irq_enable(struct irq_data
*p
)
964 gpmc_irq_endis(p
->irq
, true);
967 static void gpmc_irq_noop(struct irq_data
*data
) { }
969 static unsigned int gpmc_irq_noop_ret(struct irq_data
*data
) { return 0; }
971 static int gpmc_setup_irq(void)
979 gpmc_irq_start
= irq_alloc_descs(-1, 0, GPMC_NR_IRQ
, 0);
980 if (gpmc_irq_start
< 0) {
981 pr_err("irq_alloc_descs failed\n");
982 return gpmc_irq_start
;
985 gpmc_irq_chip
.name
= "gpmc";
986 gpmc_irq_chip
.irq_startup
= gpmc_irq_noop_ret
;
987 gpmc_irq_chip
.irq_enable
= gpmc_irq_enable
;
988 gpmc_irq_chip
.irq_disable
= gpmc_irq_disable
;
989 gpmc_irq_chip
.irq_shutdown
= gpmc_irq_noop
;
990 gpmc_irq_chip
.irq_ack
= gpmc_irq_noop
;
991 gpmc_irq_chip
.irq_mask
= gpmc_irq_noop
;
992 gpmc_irq_chip
.irq_unmask
= gpmc_irq_noop
;
994 gpmc_client_irq
[0].bitmask
= GPMC_IRQ_FIFOEVENTENABLE
;
995 gpmc_client_irq
[1].bitmask
= GPMC_IRQ_COUNT_EVENT
;
997 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
998 gpmc_client_irq
[i
].irq
= gpmc_irq_start
+ i
;
999 irq_set_chip_and_handler(gpmc_client_irq
[i
].irq
,
1000 &gpmc_irq_chip
, handle_simple_irq
);
1001 set_irq_flags(gpmc_client_irq
[i
].irq
,
1002 IRQF_VALID
| IRQF_NOAUTOEN
);
1005 /* Disable interrupts */
1006 gpmc_write_reg(GPMC_IRQENABLE
, 0);
1008 /* clear interrupts */
1009 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
1010 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
1012 return request_irq(gpmc_irq
, gpmc_handle_irq
, 0, "gpmc", NULL
);
1015 static int gpmc_free_irq(void)
1020 free_irq(gpmc_irq
, NULL
);
1022 for (i
= 0; i
< GPMC_NR_IRQ
; i
++) {
1023 irq_set_handler(gpmc_client_irq
[i
].irq
, NULL
);
1024 irq_set_chip(gpmc_client_irq
[i
].irq
, &no_irq_chip
);
1025 irq_modify_status(gpmc_client_irq
[i
].irq
, 0, 0);
1028 irq_free_descs(gpmc_irq_start
, GPMC_NR_IRQ
);
1033 static void gpmc_mem_exit(void)
1037 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
1038 if (!gpmc_cs_mem_enabled(cs
))
1040 gpmc_cs_delete_mem(cs
);
1045 static void gpmc_mem_init(void)
1050 * The first 1MB of GPMC address space is typically mapped to
1051 * the internal ROM. Never allocate the first page, to
1052 * facilitate bug detection; even if we didn't boot from ROM.
1054 gpmc_mem_root
.start
= SZ_1M
;
1055 gpmc_mem_root
.end
= GPMC_MEM_END
;
1057 /* Reserve all regions that has been set up by bootloader */
1058 for (cs
= 0; cs
< gpmc_cs_num
; cs
++) {
1061 if (!gpmc_cs_mem_enabled(cs
))
1063 gpmc_cs_get_memconf(cs
, &base
, &size
);
1064 if (gpmc_cs_insert_mem(cs
, base
, size
)) {
1065 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1066 __func__
, cs
, base
, base
+ size
);
1067 gpmc_cs_disable_mem(cs
);
1072 static u32
gpmc_round_ps_to_sync_clk(u32 time_ps
, u32 sync_clk
)
1077 div
= gpmc_calc_divider(sync_clk
);
1078 temp
= gpmc_ps_to_ticks(time_ps
);
1079 temp
= (temp
+ div
- 1) / div
;
1080 return gpmc_ticks_to_ps(temp
* div
);
1083 /* XXX: can the cycles be avoided ? */
1084 static int gpmc_calc_sync_read_timings(struct gpmc_timings
*gpmc_t
,
1085 struct gpmc_device_timings
*dev_t
,
1091 temp
= dev_t
->t_avdp_r
;
1092 /* XXX: mux check required ? */
1094 /* XXX: t_avdp not to be required for sync, only added for tusb
1095 * this indirectly necessitates requirement of t_avdp_r and
1096 * t_avdp_w instead of having a single t_avdp
1098 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
1099 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1101 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
1104 temp
= dev_t
->t_oeasu
; /* XXX: remove this ? */
1106 temp
= max_t(u32
, temp
, gpmc_t
->clk_activation
+ dev_t
->t_ach
);
1107 temp
= max_t(u32
, temp
, gpmc_t
->adv_rd_off
+
1108 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_oe
));
1110 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
1113 /* XXX: any scope for improvement ?, by combining oe_on
1114 * and clk_activation, need to check whether
1115 * access = clk_activation + round to sync clk ?
1117 temp
= max_t(u32
, dev_t
->t_iaa
, dev_t
->cyc_iaa
* gpmc_t
->sync_clk
);
1118 temp
+= gpmc_t
->clk_activation
;
1120 temp
= max_t(u32
, temp
, gpmc_t
->oe_on
+
1121 gpmc_ticks_to_ps(dev_t
->cyc_oe
));
1122 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
1124 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
1125 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
1128 temp
= max_t(u32
, dev_t
->t_cez_r
, dev_t
->t_oez
);
1129 temp
= gpmc_round_ps_to_sync_clk(temp
, gpmc_t
->sync_clk
) +
1131 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1132 if (dev_t
->t_ce_rdyz
)
1133 temp
= max_t(u32
, temp
, gpmc_t
->cs_rd_off
+ dev_t
->t_ce_rdyz
);
1134 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
1139 static int gpmc_calc_sync_write_timings(struct gpmc_timings
*gpmc_t
,
1140 struct gpmc_device_timings
*dev_t
,
1146 temp
= dev_t
->t_avdp_w
;
1148 temp
= max_t(u32
, temp
,
1149 gpmc_t
->clk_activation
+ dev_t
->t_avdh
);
1150 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1152 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
1154 /* wr_data_mux_bus */
1155 temp
= max_t(u32
, dev_t
->t_weasu
,
1156 gpmc_t
->clk_activation
+ dev_t
->t_rdyo
);
1157 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1158 * and in that case remember to handle we_on properly
1161 temp
= max_t(u32
, temp
,
1162 gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1163 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1164 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1166 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1169 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1170 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1172 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1175 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1176 gpmc_t
->wr_access
= gpmc_t
->access
;
1179 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1180 temp
= max_t(u32
, temp
,
1181 gpmc_t
->wr_access
+ gpmc_ticks_to_ps(1));
1182 temp
= max_t(u32
, temp
,
1183 gpmc_t
->we_on
+ gpmc_ticks_to_ps(dev_t
->cyc_wpl
));
1184 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1186 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1190 temp
= gpmc_round_ps_to_sync_clk(dev_t
->t_cez_w
, gpmc_t
->sync_clk
);
1191 temp
+= gpmc_t
->wr_access
;
1192 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1193 if (dev_t
->t_ce_rdyz
)
1194 temp
= max_t(u32
, temp
,
1195 gpmc_t
->cs_wr_off
+ dev_t
->t_ce_rdyz
);
1196 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1201 static int gpmc_calc_async_read_timings(struct gpmc_timings
*gpmc_t
,
1202 struct gpmc_device_timings
*dev_t
,
1208 temp
= dev_t
->t_avdp_r
;
1210 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1211 gpmc_t
->adv_rd_off
= gpmc_round_ps_to_ticks(temp
);
1214 temp
= dev_t
->t_oeasu
;
1216 temp
= max_t(u32
, temp
,
1217 gpmc_t
->adv_rd_off
+ dev_t
->t_aavdh
);
1218 gpmc_t
->oe_on
= gpmc_round_ps_to_ticks(temp
);
1221 temp
= max_t(u32
, dev_t
->t_iaa
, /* XXX: remove t_iaa in async ? */
1222 gpmc_t
->oe_on
+ dev_t
->t_oe
);
1223 temp
= max_t(u32
, temp
,
1224 gpmc_t
->cs_on
+ dev_t
->t_ce
);
1225 temp
= max_t(u32
, temp
,
1226 gpmc_t
->adv_on
+ dev_t
->t_aa
);
1227 gpmc_t
->access
= gpmc_round_ps_to_ticks(temp
);
1229 gpmc_t
->oe_off
= gpmc_t
->access
+ gpmc_ticks_to_ps(1);
1230 gpmc_t
->cs_rd_off
= gpmc_t
->oe_off
;
1233 temp
= max_t(u32
, dev_t
->t_rd_cycle
,
1234 gpmc_t
->cs_rd_off
+ dev_t
->t_cez_r
);
1235 temp
= max_t(u32
, temp
, gpmc_t
->oe_off
+ dev_t
->t_oez
);
1236 gpmc_t
->rd_cycle
= gpmc_round_ps_to_ticks(temp
);
1241 static int gpmc_calc_async_write_timings(struct gpmc_timings
*gpmc_t
,
1242 struct gpmc_device_timings
*dev_t
,
1248 temp
= dev_t
->t_avdp_w
;
1250 temp
= max_t(u32
, gpmc_t
->adv_on
+ gpmc_ticks_to_ps(1), temp
);
1251 gpmc_t
->adv_wr_off
= gpmc_round_ps_to_ticks(temp
);
1253 /* wr_data_mux_bus */
1254 temp
= dev_t
->t_weasu
;
1256 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+ dev_t
->t_aavdh
);
1257 temp
= max_t(u32
, temp
, gpmc_t
->adv_wr_off
+
1258 gpmc_ticks_to_ps(dev_t
->cyc_aavdh_we
));
1260 gpmc_t
->wr_data_mux_bus
= gpmc_round_ps_to_ticks(temp
);
1263 if (gpmc_capability
& GPMC_HAS_WR_DATA_MUX_BUS
)
1264 gpmc_t
->we_on
= gpmc_round_ps_to_ticks(dev_t
->t_weasu
);
1266 gpmc_t
->we_on
= gpmc_t
->wr_data_mux_bus
;
1269 temp
= gpmc_t
->we_on
+ dev_t
->t_wpl
;
1270 gpmc_t
->we_off
= gpmc_round_ps_to_ticks(temp
);
1272 gpmc_t
->cs_wr_off
= gpmc_round_ps_to_ticks(gpmc_t
->we_off
+
1276 temp
= max_t(u32
, dev_t
->t_wr_cycle
,
1277 gpmc_t
->cs_wr_off
+ dev_t
->t_cez_w
);
1278 gpmc_t
->wr_cycle
= gpmc_round_ps_to_ticks(temp
);
1283 static int gpmc_calc_sync_common_timings(struct gpmc_timings
*gpmc_t
,
1284 struct gpmc_device_timings
*dev_t
)
1288 gpmc_t
->sync_clk
= gpmc_calc_divider(dev_t
->clk
) *
1289 gpmc_get_fclk_period();
1291 gpmc_t
->page_burst_access
= gpmc_round_ps_to_sync_clk(
1295 temp
= max_t(u32
, dev_t
->t_ces
, dev_t
->t_avds
);
1296 gpmc_t
->clk_activation
= gpmc_round_ps_to_ticks(temp
);
1298 if (gpmc_calc_divider(gpmc_t
->sync_clk
) != 1)
1301 if (dev_t
->ce_xdelay
)
1302 gpmc_t
->bool_timings
.cs_extra_delay
= true;
1303 if (dev_t
->avd_xdelay
)
1304 gpmc_t
->bool_timings
.adv_extra_delay
= true;
1305 if (dev_t
->oe_xdelay
)
1306 gpmc_t
->bool_timings
.oe_extra_delay
= true;
1307 if (dev_t
->we_xdelay
)
1308 gpmc_t
->bool_timings
.we_extra_delay
= true;
1313 static int gpmc_calc_common_timings(struct gpmc_timings
*gpmc_t
,
1314 struct gpmc_device_timings
*dev_t
,
1320 gpmc_t
->cs_on
= gpmc_round_ps_to_ticks(dev_t
->t_ceasu
);
1323 temp
= dev_t
->t_avdasu
;
1324 if (dev_t
->t_ce_avd
)
1325 temp
= max_t(u32
, temp
,
1326 gpmc_t
->cs_on
+ dev_t
->t_ce_avd
);
1327 gpmc_t
->adv_on
= gpmc_round_ps_to_ticks(temp
);
1330 gpmc_calc_sync_common_timings(gpmc_t
, dev_t
);
1335 /* TODO: remove this function once all peripherals are confirmed to
1336 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1337 * has to be modified to handle timings in ps instead of ns
1339 static void gpmc_convert_ps_to_ns(struct gpmc_timings
*t
)
1342 t
->cs_rd_off
/= 1000;
1343 t
->cs_wr_off
/= 1000;
1345 t
->adv_rd_off
/= 1000;
1346 t
->adv_wr_off
/= 1000;
1351 t
->page_burst_access
/= 1000;
1353 t
->rd_cycle
/= 1000;
1354 t
->wr_cycle
/= 1000;
1355 t
->bus_turnaround
/= 1000;
1356 t
->cycle2cycle_delay
/= 1000;
1357 t
->wait_monitoring
/= 1000;
1358 t
->clk_activation
/= 1000;
1359 t
->wr_access
/= 1000;
1360 t
->wr_data_mux_bus
/= 1000;
1363 int gpmc_calc_timings(struct gpmc_timings
*gpmc_t
,
1364 struct gpmc_settings
*gpmc_s
,
1365 struct gpmc_device_timings
*dev_t
)
1367 bool mux
= false, sync
= false;
1370 mux
= gpmc_s
->mux_add_data
? true : false;
1371 sync
= (gpmc_s
->sync_read
|| gpmc_s
->sync_write
);
1374 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1376 gpmc_calc_common_timings(gpmc_t
, dev_t
, sync
);
1378 if (gpmc_s
&& gpmc_s
->sync_read
)
1379 gpmc_calc_sync_read_timings(gpmc_t
, dev_t
, mux
);
1381 gpmc_calc_async_read_timings(gpmc_t
, dev_t
, mux
);
1383 if (gpmc_s
&& gpmc_s
->sync_write
)
1384 gpmc_calc_sync_write_timings(gpmc_t
, dev_t
, mux
);
1386 gpmc_calc_async_write_timings(gpmc_t
, dev_t
, mux
);
1388 /* TODO: remove, see function definition */
1389 gpmc_convert_ps_to_ns(gpmc_t
);
1395 * gpmc_cs_program_settings - programs non-timing related settings
1396 * @cs: GPMC chip-select to program
1397 * @p: pointer to GPMC settings structure
1399 * Programs non-timing related settings for a GPMC chip-select, such as
1400 * bus-width, burst configuration, etc. Function should be called once
1401 * for each chip-select that is being used and must be called before
1402 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1403 * register will be initialised to zero by this function. Returns 0 on
1404 * success and appropriate negative error code on failure.
1406 int gpmc_cs_program_settings(int cs
, struct gpmc_settings
*p
)
1410 if ((!p
->device_width
) || (p
->device_width
> GPMC_DEVWIDTH_16BIT
)) {
1411 pr_err("%s: invalid width %d!", __func__
, p
->device_width
);
1415 /* Address-data multiplexing not supported for NAND devices */
1416 if (p
->device_nand
&& p
->mux_add_data
) {
1417 pr_err("%s: invalid configuration!\n", __func__
);
1421 if ((p
->mux_add_data
> GPMC_MUX_AD
) ||
1422 ((p
->mux_add_data
== GPMC_MUX_AAD
) &&
1423 !(gpmc_capability
& GPMC_HAS_MUX_AAD
))) {
1424 pr_err("%s: invalid multiplex configuration!\n", __func__
);
1428 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1429 if (p
->burst_read
|| p
->burst_write
) {
1430 switch (p
->burst_len
) {
1436 pr_err("%s: invalid page/burst-length (%d)\n",
1437 __func__
, p
->burst_len
);
1442 if (p
->wait_pin
> gpmc_nr_waitpins
) {
1443 pr_err("%s: invalid wait-pin (%d)\n", __func__
, p
->wait_pin
);
1447 config1
= GPMC_CONFIG1_DEVICESIZE((p
->device_width
- 1));
1450 config1
|= GPMC_CONFIG1_READTYPE_SYNC
;
1452 config1
|= GPMC_CONFIG1_WRITETYPE_SYNC
;
1453 if (p
->wait_on_read
)
1454 config1
|= GPMC_CONFIG1_WAIT_READ_MON
;
1455 if (p
->wait_on_write
)
1456 config1
|= GPMC_CONFIG1_WAIT_WRITE_MON
;
1457 if (p
->wait_on_read
|| p
->wait_on_write
)
1458 config1
|= GPMC_CONFIG1_WAIT_PIN_SEL(p
->wait_pin
);
1460 config1
|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND
);
1461 if (p
->mux_add_data
)
1462 config1
|= GPMC_CONFIG1_MUXTYPE(p
->mux_add_data
);
1464 config1
|= GPMC_CONFIG1_READMULTIPLE_SUPP
;
1466 config1
|= GPMC_CONFIG1_WRITEMULTIPLE_SUPP
;
1467 if (p
->burst_read
|| p
->burst_write
) {
1468 config1
|= GPMC_CONFIG1_PAGE_LEN(p
->burst_len
>> 3);
1469 config1
|= p
->burst_wrap
? GPMC_CONFIG1_WRAPBURST_SUPP
: 0;
1472 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, config1
);
1478 static const struct of_device_id gpmc_dt_ids
[] = {
1479 { .compatible
= "ti,omap2420-gpmc" },
1480 { .compatible
= "ti,omap2430-gpmc" },
1481 { .compatible
= "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1482 { .compatible
= "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1483 { .compatible
= "ti,am3352-gpmc" }, /* am335x devices */
1486 MODULE_DEVICE_TABLE(of
, gpmc_dt_ids
);
1489 * gpmc_read_settings_dt - read gpmc settings from device-tree
1490 * @np: pointer to device-tree node for a gpmc child device
1491 * @p: pointer to gpmc settings structure
1493 * Reads the GPMC settings for a GPMC child device from device-tree and
1494 * stores them in the GPMC settings structure passed. The GPMC settings
1495 * structure is initialised to zero by this function and so any
1496 * previously stored settings will be cleared.
1498 void gpmc_read_settings_dt(struct device_node
*np
, struct gpmc_settings
*p
)
1500 memset(p
, 0, sizeof(struct gpmc_settings
));
1502 p
->sync_read
= of_property_read_bool(np
, "gpmc,sync-read");
1503 p
->sync_write
= of_property_read_bool(np
, "gpmc,sync-write");
1504 of_property_read_u32(np
, "gpmc,device-width", &p
->device_width
);
1505 of_property_read_u32(np
, "gpmc,mux-add-data", &p
->mux_add_data
);
1507 if (!of_property_read_u32(np
, "gpmc,burst-length", &p
->burst_len
)) {
1508 p
->burst_wrap
= of_property_read_bool(np
, "gpmc,burst-wrap");
1509 p
->burst_read
= of_property_read_bool(np
, "gpmc,burst-read");
1510 p
->burst_write
= of_property_read_bool(np
, "gpmc,burst-write");
1511 if (!p
->burst_read
&& !p
->burst_write
)
1512 pr_warn("%s: page/burst-length set but not used!\n",
1516 if (!of_property_read_u32(np
, "gpmc,wait-pin", &p
->wait_pin
)) {
1517 p
->wait_on_read
= of_property_read_bool(np
,
1518 "gpmc,wait-on-read");
1519 p
->wait_on_write
= of_property_read_bool(np
,
1520 "gpmc,wait-on-write");
1521 if (!p
->wait_on_read
&& !p
->wait_on_write
)
1522 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1527 static void __maybe_unused
gpmc_read_timings_dt(struct device_node
*np
,
1528 struct gpmc_timings
*gpmc_t
)
1530 struct gpmc_bool_timings
*p
;
1535 memset(gpmc_t
, 0, sizeof(*gpmc_t
));
1537 /* minimum clock period for syncronous mode */
1538 of_property_read_u32(np
, "gpmc,sync-clk-ps", &gpmc_t
->sync_clk
);
1540 /* chip select timtings */
1541 of_property_read_u32(np
, "gpmc,cs-on-ns", &gpmc_t
->cs_on
);
1542 of_property_read_u32(np
, "gpmc,cs-rd-off-ns", &gpmc_t
->cs_rd_off
);
1543 of_property_read_u32(np
, "gpmc,cs-wr-off-ns", &gpmc_t
->cs_wr_off
);
1545 /* ADV signal timings */
1546 of_property_read_u32(np
, "gpmc,adv-on-ns", &gpmc_t
->adv_on
);
1547 of_property_read_u32(np
, "gpmc,adv-rd-off-ns", &gpmc_t
->adv_rd_off
);
1548 of_property_read_u32(np
, "gpmc,adv-wr-off-ns", &gpmc_t
->adv_wr_off
);
1550 /* WE signal timings */
1551 of_property_read_u32(np
, "gpmc,we-on-ns", &gpmc_t
->we_on
);
1552 of_property_read_u32(np
, "gpmc,we-off-ns", &gpmc_t
->we_off
);
1554 /* OE signal timings */
1555 of_property_read_u32(np
, "gpmc,oe-on-ns", &gpmc_t
->oe_on
);
1556 of_property_read_u32(np
, "gpmc,oe-off-ns", &gpmc_t
->oe_off
);
1558 /* access and cycle timings */
1559 of_property_read_u32(np
, "gpmc,page-burst-access-ns",
1560 &gpmc_t
->page_burst_access
);
1561 of_property_read_u32(np
, "gpmc,access-ns", &gpmc_t
->access
);
1562 of_property_read_u32(np
, "gpmc,rd-cycle-ns", &gpmc_t
->rd_cycle
);
1563 of_property_read_u32(np
, "gpmc,wr-cycle-ns", &gpmc_t
->wr_cycle
);
1564 of_property_read_u32(np
, "gpmc,bus-turnaround-ns",
1565 &gpmc_t
->bus_turnaround
);
1566 of_property_read_u32(np
, "gpmc,cycle2cycle-delay-ns",
1567 &gpmc_t
->cycle2cycle_delay
);
1568 of_property_read_u32(np
, "gpmc,wait-monitoring-ns",
1569 &gpmc_t
->wait_monitoring
);
1570 of_property_read_u32(np
, "gpmc,clk-activation-ns",
1571 &gpmc_t
->clk_activation
);
1573 /* only applicable to OMAP3+ */
1574 of_property_read_u32(np
, "gpmc,wr-access-ns", &gpmc_t
->wr_access
);
1575 of_property_read_u32(np
, "gpmc,wr-data-mux-bus-ns",
1576 &gpmc_t
->wr_data_mux_bus
);
1578 /* bool timing parameters */
1579 p
= &gpmc_t
->bool_timings
;
1581 p
->cycle2cyclediffcsen
=
1582 of_property_read_bool(np
, "gpmc,cycle2cycle-diffcsen");
1583 p
->cycle2cyclesamecsen
=
1584 of_property_read_bool(np
, "gpmc,cycle2cycle-samecsen");
1585 p
->we_extra_delay
= of_property_read_bool(np
, "gpmc,we-extra-delay");
1586 p
->oe_extra_delay
= of_property_read_bool(np
, "gpmc,oe-extra-delay");
1587 p
->adv_extra_delay
= of_property_read_bool(np
, "gpmc,adv-extra-delay");
1588 p
->cs_extra_delay
= of_property_read_bool(np
, "gpmc,cs-extra-delay");
1589 p
->time_para_granularity
=
1590 of_property_read_bool(np
, "gpmc,time-para-granularity");
1593 #if IS_ENABLED(CONFIG_MTD_NAND)
1595 static const char * const nand_xfer_types
[] = {
1596 [NAND_OMAP_PREFETCH_POLLED
] = "prefetch-polled",
1597 [NAND_OMAP_POLLED
] = "polled",
1598 [NAND_OMAP_PREFETCH_DMA
] = "prefetch-dma",
1599 [NAND_OMAP_PREFETCH_IRQ
] = "prefetch-irq",
1602 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1603 struct device_node
*child
)
1607 struct gpmc_timings gpmc_t
;
1608 struct omap_nand_platform_data
*gpmc_nand_data
;
1610 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1611 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1616 gpmc_nand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_nand_data
),
1618 if (!gpmc_nand_data
)
1621 gpmc_nand_data
->cs
= val
;
1622 gpmc_nand_data
->of_node
= child
;
1624 /* Detect availability of ELM module */
1625 gpmc_nand_data
->elm_of_node
= of_parse_phandle(child
, "ti,elm-id", 0);
1626 if (gpmc_nand_data
->elm_of_node
== NULL
)
1627 gpmc_nand_data
->elm_of_node
=
1628 of_parse_phandle(child
, "elm_id", 0);
1630 /* select ecc-scheme for NAND */
1631 if (of_property_read_string(child
, "ti,nand-ecc-opt", &s
)) {
1632 pr_err("%s: ti,nand-ecc-opt not found\n", __func__
);
1636 if (!strcmp(s
, "sw"))
1637 gpmc_nand_data
->ecc_opt
= OMAP_ECC_HAM1_CODE_SW
;
1638 else if (!strcmp(s
, "ham1") ||
1639 !strcmp(s
, "hw") || !strcmp(s
, "hw-romcode"))
1640 gpmc_nand_data
->ecc_opt
=
1641 OMAP_ECC_HAM1_CODE_HW
;
1642 else if (!strcmp(s
, "bch4"))
1643 if (gpmc_nand_data
->elm_of_node
)
1644 gpmc_nand_data
->ecc_opt
=
1645 OMAP_ECC_BCH4_CODE_HW
;
1647 gpmc_nand_data
->ecc_opt
=
1648 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
;
1649 else if (!strcmp(s
, "bch8"))
1650 if (gpmc_nand_data
->elm_of_node
)
1651 gpmc_nand_data
->ecc_opt
=
1652 OMAP_ECC_BCH8_CODE_HW
;
1654 gpmc_nand_data
->ecc_opt
=
1655 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
;
1656 else if (!strcmp(s
, "bch16"))
1657 if (gpmc_nand_data
->elm_of_node
)
1658 gpmc_nand_data
->ecc_opt
=
1659 OMAP_ECC_BCH16_CODE_HW
;
1661 pr_err("%s: BCH16 requires ELM support\n", __func__
);
1663 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__
);
1665 /* select data transfer mode for NAND controller */
1666 if (!of_property_read_string(child
, "ti,nand-xfer-type", &s
))
1667 for (val
= 0; val
< ARRAY_SIZE(nand_xfer_types
); val
++)
1668 if (!strcasecmp(s
, nand_xfer_types
[val
])) {
1669 gpmc_nand_data
->xfer_type
= val
;
1673 gpmc_nand_data
->flash_bbt
= of_get_nand_on_flash_bbt(child
);
1675 val
= of_get_nand_bus_width(child
);
1677 gpmc_nand_data
->devsize
= NAND_BUSWIDTH_16
;
1679 gpmc_read_timings_dt(child
, &gpmc_t
);
1680 gpmc_nand_init(gpmc_nand_data
, &gpmc_t
);
1685 static int gpmc_probe_nand_child(struct platform_device
*pdev
,
1686 struct device_node
*child
)
1692 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1693 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1694 struct device_node
*child
)
1697 struct omap_onenand_platform_data
*gpmc_onenand_data
;
1699 if (of_property_read_u32(child
, "reg", &val
) < 0) {
1700 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1705 gpmc_onenand_data
= devm_kzalloc(&pdev
->dev
, sizeof(*gpmc_onenand_data
),
1707 if (!gpmc_onenand_data
)
1710 gpmc_onenand_data
->cs
= val
;
1711 gpmc_onenand_data
->of_node
= child
;
1712 gpmc_onenand_data
->dma_channel
= -1;
1714 if (!of_property_read_u32(child
, "dma-channel", &val
))
1715 gpmc_onenand_data
->dma_channel
= val
;
1717 gpmc_onenand_init(gpmc_onenand_data
);
1722 static int gpmc_probe_onenand_child(struct platform_device
*pdev
,
1723 struct device_node
*child
)
1730 * gpmc_probe_generic_child - configures the gpmc for a child device
1731 * @pdev: pointer to gpmc platform device
1732 * @child: pointer to device-tree node for child device
1734 * Allocates and configures a GPMC chip-select for a child device.
1735 * Returns 0 on success and appropriate negative error code on failure.
1737 static int gpmc_probe_generic_child(struct platform_device
*pdev
,
1738 struct device_node
*child
)
1740 struct gpmc_settings gpmc_s
;
1741 struct gpmc_timings gpmc_t
;
1742 struct resource res
;
1748 if (of_property_read_u32(child
, "reg", &cs
) < 0) {
1749 dev_err(&pdev
->dev
, "%s has no 'reg' property\n",
1754 if (of_address_to_resource(child
, 0, &res
) < 0) {
1755 dev_err(&pdev
->dev
, "%s has malformed 'reg' property\n",
1761 * Check if we have multiple instances of the same device
1762 * on a single chip select. If so, use the already initialized
1765 name
= gpmc_cs_get_name(cs
);
1766 if (name
&& child
->name
&& of_node_cmp(child
->name
, name
) == 0)
1769 ret
= gpmc_cs_request(cs
, resource_size(&res
), &base
);
1771 dev_err(&pdev
->dev
, "cannot request GPMC CS %d\n", cs
);
1774 gpmc_cs_set_name(cs
, child
->name
);
1776 gpmc_read_settings_dt(child
, &gpmc_s
);
1777 gpmc_read_timings_dt(child
, &gpmc_t
);
1780 * For some GPMC devices we still need to rely on the bootloader
1781 * timings because the devices can be connected via FPGA.
1782 * REVISIT: Add timing support from slls644g.pdf.
1784 if (!gpmc_t
.cs_rd_off
) {
1785 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1787 gpmc_cs_show_timings(cs
,
1788 "please add GPMC bootloader timings to .dts");
1792 /* CS must be disabled while making changes to gpmc configuration */
1793 gpmc_cs_disable_mem(cs
);
1796 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1797 * location in the gpmc address space. When booting with
1798 * device-tree we want the NOR flash to be mapped to the
1799 * location specified in the device-tree blob. So remap the
1800 * CS to this location. Once DT migration is complete should
1801 * just make gpmc_cs_request() map a specific address.
1803 ret
= gpmc_cs_remap(cs
, res
.start
);
1805 dev_err(&pdev
->dev
, "cannot remap GPMC CS %d to %pa\n",
1810 ret
= of_property_read_u32(child
, "bank-width", &gpmc_s
.device_width
);
1814 ret
= gpmc_cs_program_settings(cs
, &gpmc_s
);
1818 ret
= gpmc_cs_set_timings(cs
, &gpmc_t
);
1820 dev_err(&pdev
->dev
, "failed to set gpmc timings for: %s\n",
1825 /* Clear limited address i.e. enable A26-A11 */
1826 val
= gpmc_read_reg(GPMC_CONFIG
);
1827 val
&= ~GPMC_CONFIG_LIMITEDADDRESS
;
1828 gpmc_write_reg(GPMC_CONFIG
, val
);
1830 /* Enable CS region */
1831 gpmc_cs_enable_mem(cs
);
1835 /* create platform device, NULL on error or when disabled */
1836 if (!of_platform_device_create(child
, NULL
, &pdev
->dev
))
1837 goto err_child_fail
;
1839 /* is child a common bus? */
1840 if (of_match_node(of_default_bus_match_table
, child
))
1841 /* create children and other common bus children */
1842 if (of_platform_populate(child
, of_default_bus_match_table
,
1844 goto err_child_fail
;
1850 dev_err(&pdev
->dev
, "failed to create gpmc child %s\n", child
->name
);
1859 static int gpmc_probe_dt(struct platform_device
*pdev
)
1862 struct device_node
*child
;
1863 const struct of_device_id
*of_id
=
1864 of_match_device(gpmc_dt_ids
, &pdev
->dev
);
1869 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-cs",
1872 pr_err("%s: number of chip-selects not defined\n", __func__
);
1874 } else if (gpmc_cs_num
< 1) {
1875 pr_err("%s: all chip-selects are disabled\n", __func__
);
1877 } else if (gpmc_cs_num
> GPMC_CS_NUM
) {
1878 pr_err("%s: number of supported chip-selects cannot be > %d\n",
1879 __func__
, GPMC_CS_NUM
);
1883 ret
= of_property_read_u32(pdev
->dev
.of_node
, "gpmc,num-waitpins",
1886 pr_err("%s: number of wait pins not found!\n", __func__
);
1890 for_each_available_child_of_node(pdev
->dev
.of_node
, child
) {
1895 if (of_node_cmp(child
->name
, "nand") == 0)
1896 ret
= gpmc_probe_nand_child(pdev
, child
);
1897 else if (of_node_cmp(child
->name
, "onenand") == 0)
1898 ret
= gpmc_probe_onenand_child(pdev
, child
);
1899 else if (of_node_cmp(child
->name
, "ethernet") == 0 ||
1900 of_node_cmp(child
->name
, "nor") == 0 ||
1901 of_node_cmp(child
->name
, "uart") == 0)
1902 ret
= gpmc_probe_generic_child(pdev
, child
);
1904 if (WARN(ret
< 0, "%s: probing gpmc child %s failed\n",
1905 __func__
, child
->full_name
))
1912 static int gpmc_probe_dt(struct platform_device
*pdev
)
1918 static int gpmc_probe(struct platform_device
*pdev
)
1922 struct resource
*res
;
1924 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1928 phys_base
= res
->start
;
1929 mem_size
= resource_size(res
);
1931 gpmc_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1932 if (IS_ERR(gpmc_base
))
1933 return PTR_ERR(gpmc_base
);
1935 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1937 dev_warn(&pdev
->dev
, "Failed to get resource: irq\n");
1939 gpmc_irq
= res
->start
;
1941 gpmc_l3_clk
= devm_clk_get(&pdev
->dev
, "fck");
1942 if (IS_ERR(gpmc_l3_clk
)) {
1943 dev_err(&pdev
->dev
, "Failed to get GPMC fck\n");
1945 return PTR_ERR(gpmc_l3_clk
);
1948 if (!clk_get_rate(gpmc_l3_clk
)) {
1949 dev_err(&pdev
->dev
, "Invalid GPMC fck clock rate\n");
1953 pm_runtime_enable(&pdev
->dev
);
1954 pm_runtime_get_sync(&pdev
->dev
);
1956 gpmc_dev
= &pdev
->dev
;
1958 l
= gpmc_read_reg(GPMC_REVISION
);
1961 * FIXME: Once device-tree migration is complete the below flags
1962 * should be populated based upon the device-tree compatible
1963 * string. For now just use the IP revision. OMAP3+ devices have
1964 * the wr_access and wr_data_mux_bus register fields. OMAP4+
1965 * devices support the addr-addr-data multiplex protocol.
1967 * GPMC IP revisions:
1970 * - OMAP44xx/54xx/AM335x = 6.0
1972 if (GPMC_REVISION_MAJOR(l
) > 0x4)
1973 gpmc_capability
= GPMC_HAS_WR_ACCESS
| GPMC_HAS_WR_DATA_MUX_BUS
;
1974 if (GPMC_REVISION_MAJOR(l
) > 0x5)
1975 gpmc_capability
|= GPMC_HAS_MUX_AAD
;
1976 dev_info(gpmc_dev
, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l
),
1977 GPMC_REVISION_MINOR(l
));
1981 if (gpmc_setup_irq() < 0)
1982 dev_warn(gpmc_dev
, "gpmc_setup_irq failed\n");
1984 if (!pdev
->dev
.of_node
) {
1985 gpmc_cs_num
= GPMC_CS_NUM
;
1986 gpmc_nr_waitpins
= GPMC_NR_WAITPINS
;
1989 rc
= gpmc_probe_dt(pdev
);
1991 pm_runtime_put_sync(&pdev
->dev
);
1992 dev_err(gpmc_dev
, "failed to probe DT parameters\n");
1999 static int gpmc_remove(struct platform_device
*pdev
)
2003 pm_runtime_put_sync(&pdev
->dev
);
2004 pm_runtime_disable(&pdev
->dev
);
2009 #ifdef CONFIG_PM_SLEEP
2010 static int gpmc_suspend(struct device
*dev
)
2012 omap3_gpmc_save_context();
2013 pm_runtime_put_sync(dev
);
2017 static int gpmc_resume(struct device
*dev
)
2019 pm_runtime_get_sync(dev
);
2020 omap3_gpmc_restore_context();
2025 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops
, gpmc_suspend
, gpmc_resume
);
2027 static struct platform_driver gpmc_driver
= {
2028 .probe
= gpmc_probe
,
2029 .remove
= gpmc_remove
,
2031 .name
= DEVICE_NAME
,
2032 .of_match_table
= of_match_ptr(gpmc_dt_ids
),
2037 static __init
int gpmc_init(void)
2039 return platform_driver_register(&gpmc_driver
);
2042 static __exit
void gpmc_exit(void)
2044 platform_driver_unregister(&gpmc_driver
);
2048 postcore_initcall(gpmc_init
);
2049 module_exit(gpmc_exit
);
2051 static irqreturn_t
gpmc_handle_irq(int irq
, void *dev
)
2056 regval
= gpmc_read_reg(GPMC_IRQSTATUS
);
2061 for (i
= 0; i
< GPMC_NR_IRQ
; i
++)
2062 if (regval
& gpmc_client_irq
[i
].bitmask
)
2063 generic_handle_irq(gpmc_client_irq
[i
].irq
);
2065 gpmc_write_reg(GPMC_IRQSTATUS
, regval
);
2070 static struct omap3_gpmc_regs gpmc_context
;
2072 void omap3_gpmc_save_context(void)
2076 gpmc_context
.sysconfig
= gpmc_read_reg(GPMC_SYSCONFIG
);
2077 gpmc_context
.irqenable
= gpmc_read_reg(GPMC_IRQENABLE
);
2078 gpmc_context
.timeout_ctrl
= gpmc_read_reg(GPMC_TIMEOUT_CONTROL
);
2079 gpmc_context
.config
= gpmc_read_reg(GPMC_CONFIG
);
2080 gpmc_context
.prefetch_config1
= gpmc_read_reg(GPMC_PREFETCH_CONFIG1
);
2081 gpmc_context
.prefetch_config2
= gpmc_read_reg(GPMC_PREFETCH_CONFIG2
);
2082 gpmc_context
.prefetch_control
= gpmc_read_reg(GPMC_PREFETCH_CONTROL
);
2083 for (i
= 0; i
< gpmc_cs_num
; i
++) {
2084 gpmc_context
.cs_context
[i
].is_valid
= gpmc_cs_mem_enabled(i
);
2085 if (gpmc_context
.cs_context
[i
].is_valid
) {
2086 gpmc_context
.cs_context
[i
].config1
=
2087 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG1
);
2088 gpmc_context
.cs_context
[i
].config2
=
2089 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG2
);
2090 gpmc_context
.cs_context
[i
].config3
=
2091 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG3
);
2092 gpmc_context
.cs_context
[i
].config4
=
2093 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG4
);
2094 gpmc_context
.cs_context
[i
].config5
=
2095 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG5
);
2096 gpmc_context
.cs_context
[i
].config6
=
2097 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG6
);
2098 gpmc_context
.cs_context
[i
].config7
=
2099 gpmc_cs_read_reg(i
, GPMC_CS_CONFIG7
);
2104 void omap3_gpmc_restore_context(void)
2108 gpmc_write_reg(GPMC_SYSCONFIG
, gpmc_context
.sysconfig
);
2109 gpmc_write_reg(GPMC_IRQENABLE
, gpmc_context
.irqenable
);
2110 gpmc_write_reg(GPMC_TIMEOUT_CONTROL
, gpmc_context
.timeout_ctrl
);
2111 gpmc_write_reg(GPMC_CONFIG
, gpmc_context
.config
);
2112 gpmc_write_reg(GPMC_PREFETCH_CONFIG1
, gpmc_context
.prefetch_config1
);
2113 gpmc_write_reg(GPMC_PREFETCH_CONFIG2
, gpmc_context
.prefetch_config2
);
2114 gpmc_write_reg(GPMC_PREFETCH_CONTROL
, gpmc_context
.prefetch_control
);
2115 for (i
= 0; i
< gpmc_cs_num
; i
++) {
2116 if (gpmc_context
.cs_context
[i
].is_valid
) {
2117 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG1
,
2118 gpmc_context
.cs_context
[i
].config1
);
2119 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG2
,
2120 gpmc_context
.cs_context
[i
].config2
);
2121 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG3
,
2122 gpmc_context
.cs_context
[i
].config3
);
2123 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG4
,
2124 gpmc_context
.cs_context
[i
].config4
);
2125 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG5
,
2126 gpmc_context
.cs_context
[i
].config5
);
2127 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG6
,
2128 gpmc_context
.cs_context
[i
].config6
);
2129 gpmc_cs_write_reg(i
, GPMC_CS_CONFIG7
,
2130 gpmc_context
.cs_context
[i
].config7
);