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Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[deliverable/linux.git] / drivers / message / fusion / lsi / mpi_cnfg.h
1 /*
2 * Copyright (c) 2000-2005 LSI Logic Corporation.
3 *
4 *
5 * Name: mpi_cnfg.h
6 * Title: MPI Config message, structures, and Pages
7 * Creation Date: July 27, 2000
8 *
9 * mpi_cnfg.h Version: 01.05.11
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17 * 06-06-00 01.00.01 Update version number for 1.0 release.
18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20 * fields to FC_DEVICE_0 page, updated the page version.
21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23 * and updated the page versions.
24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25 * page and updated the page version.
26 * Added Information field and _INFO_PARAMS_NEGOTIATED
27 * definitionto SCSI_DEVICE_0 page.
28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
29 * page version.
30 * Added BucketsRemaining to LAN_1 page, redefined the
31 * state values, and updated the page version.
32 * Revised bus width definitions in SCSI_PORT_0,
33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
35 * version.
36 * Moved FC_DEVICE_0 PageAddress description to spec.
37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38 * widths in IOC_0 page and updated the page version.
39 * 11-02-00 01.01.01 Original release for post 1.0 work
40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41 * Port Page 2, FC Port Page 4, FC Port Page 5
42 * 11-15-00 01.01.02 Interim changes to match proposals
43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44 * 12-05-00 01.01.04 Modified config page actions.
45 * 01-09-01 01.01.05 Added defines for page address formats.
46 * Data size for Manufacturing pages 2 and 3 no longer
47 * defined here.
48 * Io Unit Page 2 size is fixed at 4 adapters and some
49 * flags were changed.
50 * SCSI Port Page 2 Device Settings modified.
51 * New fields added to FC Port Page 0 and some flags
52 * cleaned up.
53 * Removed impedance flash from FC Port Page 1.
54 * Added FC Port pages 6 and 7.
55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57 * Added some LinkType defines for FcPortPage0.
58 * 02-20-01 01.01.08 Started using MPI_POINTER.
59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61 * Added definitions and structures for IOC Page 2 and
62 * RAID Volume Page 2.
63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65 * Added VendorId and ProductRevLevel fields to
66 * RAIDVOL2_IM_PHYS_ID struct.
67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68 * defines to make them compatible to MPI version 1.0.
69 * Added structure offset comments.
70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71 * removed some obsolete ones.
72 * Added IO Unit Page 3.
73 * Modified defines for Scsi Port Page 2.
74 * Modified RAID Volume Pages.
75 * 08-08-01 01.02.01 Original release for v1.2 work.
76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77 * Added defines for the SEP bits in RVP2 VolumeSettings.
78 * Modified the DeviceSettings field in RVP2 to use the
79 * proper structure.
80 * Added defines for SES, SAF-TE, and cross channel for
81 * IOCPage2 CapabilitiesFlags.
82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
83 * Removed define for
84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96 * Added rejected bits to SCSI Device Page 0 Information.
97 * Increased size of ALPA array in FC Port Page 2 by one
98 * and removed a one byte reserved field.
99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101 * Added structures for Manufacturing Page 4, IO Unit
102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103 * RAID PhysDisk Page 0.
104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105 * Modified some of the new defines to make them 32
106 * character unique.
107 * Modified how variable length pages (arrays) are defined.
108 * Added generic defines for hot spare pools and RAID
109 * volume types.
110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112 * related define, and bumped the page version define.
113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114 * reserved byte and added a define.
115 * Added define for
116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117 * Added new config page: CONFIG_PAGE_IOC_5.
118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119 * fields to CONFIG_PAGE_FC_PORT_0.
120 * Added AltConnector and NumRequestedAliases fields to
121 * CONFIG_PAGE_FC_PORT_1.
122 * Added new config page: CONFIG_PAGE_FC_PORT_10.
123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
126 * Added define for
127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135 * CONFIG_PAGE_FC_PORT_1.
136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
137 * an alias.
138 * Added more device id defines.
139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140 * Added TargetConfig and IDConfig fields to
141 * CONFIG_PAGE_SCSI_PORT_1.
142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
143 * to control DV.
144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146 * with ADISCHardALPA.
147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
148 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
149 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
150 * Added define for
151 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
152 * Added new fields to the substructures of
153 * CONFIG_PAGE_FC_PORT_10.
154 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
155 * CONFIG_PAGE_SCSI_DEVICE_0, and
156 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
157 * these pages.
158 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
159 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
160 * pages.
161 * Added a new structure for extended config page header.
162 * Added new extended config pages types and structures for
163 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
164 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
165 * to add a Flags field.
166 * Two new Manufacturing config pages (5 and 6).
167 * Two new bits defined for IO Unit Page 1 Flags field.
168 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
169 * to specify the BIOS boot device.
170 * Four new Flags bits defined for IO Unit Page 2.
171 * Added IO Unit Page 4.
172 * Added EEDP Flags settings to IOC Page 1.
173 * Added new BIOS Page 1 config page.
174 * 10-05-04 01.05.02 Added define for
175 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
176 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
177 * associated defines.
178 * Added more defines for SAS IO Unit Page 0
179 * DiscoveryStatus field.
180 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
181 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
182 * Added defines for Physical Mapping Modes to SAS IO Unit
183 * Page 2.
184 * Added define for
185 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
186 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
187 * Added defines for MaxTargetSpinUp to BIOS Page 1.
188 * Added 5 new ControlFlags defines for SAS IO Unit
189 * Page 1.
190 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
191 * Page 2.
192 * Added AccessStatus field to SAS Device Page 0 and added
193 * new Flags bits for supported SATA features.
194 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
195 * Volume Page 1, and RAID Physical Disk Page 1.
196 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
197 * BootAdapterNum with reserved field.
198 * Added DataScrubRate and ResyncRate to RAID Volume
199 * Page 0.
200 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
201 * define.
202 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
203 * Flags field.
204 * Added Auto Port Config flag define for SAS IOUNIT
205 * Page 1 ControlFlags.
206 * Added Disabled bad Phy define to Expander Page 1
207 * Discovery Info field.
208 * Added SAS/SATA device support to SAS IOUnit Page 1
209 * ControlFlags.
210 * Added Unsupported device to SAS Dev Page 0 Flags field
211 * Added disable use SATA Hash Address for SAS IOUNIT
212 * page 1 in ControlFields.
213 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
214 * Manufacturing Page 4.
215 * Added new defines for BIOS Page 1 IOCSettings field.
216 * Added ExtDiskIdentifier field to RAID Physical Disk
217 * Page 0.
218 * Added new defines for SAS IO Unit Page 1 ControlFlags
219 * and to SAS Device Page 0 Flags to control SATA devices.
220 * Added defines and structures for the new Log Page 0, a
221 * new type of configuration page.
222 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
223 * Added WWID field to RAID Volume Page 1.
224 * Added PhysicalPort field to SAS Expander pages 0 and 1.
225 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
226 * Added Enclosure/Slot boot device format to BIOS Page 2.
227 * New status value for RAID Volume Page 0 VolumeStatus
228 * (VolumeState subfield).
229 * New value for RAID Physical Page 0 InactiveStatus.
230 * Added Inactive Volume Member flag RAID Physical Disk
231 * Page 0 PhysDiskStatus field.
232 * New physical mapping mode in SAS IO Unit Page 2.
233 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
234 * Added Slot and Enclosure fields to SAS Device Page 0.
235 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
236 * Added more RAID type defines to IOC Page 2.
237 * Added Port Enable Delay settings to BIOS Page 1.
238 * Added Bad Block Table Full define to RAID Volume Page 0.
239 * Added Previous State defines to RAID Physical Disk
240 * Page 0.
241 * Added Max Sata Targets define for DiscoveryStatus field
242 * of SAS IO Unit Page 0.
243 * Added Device Self Test to Control Flags of SAS IO Unit
244 * Page 1.
245 * Added Direct Attach Starting Slot Number define for SAS
246 * IO Unit Page 2.
247 * Added new fields in SAS Device Page 2 for enclosure
248 * mapping.
249 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
250 * Added IOC GPIO Flags define to SAS Enclosure Page 0.
251 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
252 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from
253 * Manufacturing Page 4.
254 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
255 * Added NumDevsPerEnclosure field to SAS IO Unit page 2.
256 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
257 * define.
258 * Added EnclosureHandle field to SAS Expander page 0.
259 * Removed redundant NumTableEntriesProg field from SAS
260 * Expander Page 1.
261 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for
262 * SAS1078.
263 * Added more defines for Manufacturing Page 4 Flags field.
264 * Added more defines for IOCSettings and added
265 * ExpanderSpinup field to Bios Page 1.
266 * Added postpone SATA Init bit to SAS IO Unit Page 1
267 * ControlFlags.
268 * Changed LogEntry format for Log Page 0.
269 * --------------------------------------------------------------------------
270 */
271
272 #ifndef MPI_CNFG_H
273 #define MPI_CNFG_H
274
275
276 /*****************************************************************************
277 *
278 * C o n f i g M e s s a g e a n d S t r u c t u r e s
279 *
280 *****************************************************************************/
281
282 typedef struct _CONFIG_PAGE_HEADER
283 {
284 U8 PageVersion; /* 00h */
285 U8 PageLength; /* 01h */
286 U8 PageNumber; /* 02h */
287 U8 PageType; /* 03h */
288 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
289 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
290
291 typedef union _CONFIG_PAGE_HEADER_UNION
292 {
293 ConfigPageHeader_t Struct;
294 U8 Bytes[4];
295 U16 Word16[2];
296 U32 Word32;
297 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
298 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
299
300 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
301 {
302 U8 PageVersion; /* 00h */
303 U8 Reserved1; /* 01h */
304 U8 PageNumber; /* 02h */
305 U8 PageType; /* 03h */
306 U16 ExtPageLength; /* 04h */
307 U8 ExtPageType; /* 06h */
308 U8 Reserved2; /* 07h */
309 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
310 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
311
312
313
314 /****************************************************************************
315 * PageType field values
316 ****************************************************************************/
317 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
318 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
319 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
320 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
321 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
322
323 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
324 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
325 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
326 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
327 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
328 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
329 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
330 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
331 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
332 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
333 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
334 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
335 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
336 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
337
338 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
339
340
341 /****************************************************************************
342 * ExtPageType field values
343 ****************************************************************************/
344 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
345 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
346 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
347 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
348 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
349 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
350
351
352 /****************************************************************************
353 * PageAddress field values
354 ****************************************************************************/
355 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
356
357 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
358 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
359 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
360 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
361 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
362 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
363 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
364 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
365 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
366 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
367 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
368 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
369 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
370
371 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
372 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
373 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
374 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
375 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
376 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
377
378 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
379 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
380 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
381 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
382 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
383 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
384 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
385 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
386 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
387 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
388 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
389 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
390 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
391
392 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
393 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
394
395 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
396 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
397 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
398 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
399 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
400 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
401 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
402 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
403 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
404 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
405 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
406 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
407 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
408
409 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
410 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
411 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
412 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
413 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
414 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
415 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
416 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
417 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
418 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
419 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
420 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
421 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
422
423 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
424 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
425 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
426 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
427 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
428 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
429 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
430 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
431
432 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
433 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
434 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
435 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
436 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
437 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
438 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
439 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
440
441
442
443 /****************************************************************************
444 * Config Request Message
445 ****************************************************************************/
446 typedef struct _MSG_CONFIG
447 {
448 U8 Action; /* 00h */
449 U8 Reserved; /* 01h */
450 U8 ChainOffset; /* 02h */
451 U8 Function; /* 03h */
452 U16 ExtPageLength; /* 04h */
453 U8 ExtPageType; /* 06h */
454 U8 MsgFlags; /* 07h */
455 U32 MsgContext; /* 08h */
456 U8 Reserved2[8]; /* 0Ch */
457 CONFIG_PAGE_HEADER Header; /* 14h */
458 U32 PageAddress; /* 18h */
459 SGE_IO_UNION PageBufferSGE; /* 1Ch */
460 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
461 Config_t, MPI_POINTER pConfig_t;
462
463
464 /****************************************************************************
465 * Action field values
466 ****************************************************************************/
467 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
468 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
469 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
470 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
471 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
472 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
473 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
474
475
476 /* Config Reply Message */
477 typedef struct _MSG_CONFIG_REPLY
478 {
479 U8 Action; /* 00h */
480 U8 Reserved; /* 01h */
481 U8 MsgLength; /* 02h */
482 U8 Function; /* 03h */
483 U16 ExtPageLength; /* 04h */
484 U8 ExtPageType; /* 06h */
485 U8 MsgFlags; /* 07h */
486 U32 MsgContext; /* 08h */
487 U8 Reserved2[2]; /* 0Ch */
488 U16 IOCStatus; /* 0Eh */
489 U32 IOCLogInfo; /* 10h */
490 CONFIG_PAGE_HEADER Header; /* 14h */
491 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
492 ConfigReply_t, MPI_POINTER pConfigReply_t;
493
494
495
496 /*****************************************************************************
497 *
498 * C o n f i g u r a t i o n P a g e s
499 *
500 *****************************************************************************/
501
502 /****************************************************************************
503 * Manufacturing Config pages
504 ****************************************************************************/
505 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
506 /* Fibre Channel */
507 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
508 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
509 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
510 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
511 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
512 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
513 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
514 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646)
515 /* SCSI */
516 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
517 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
518 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
519 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
520 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
521 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
522 /* SAS */
523 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
524 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
525 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
526 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
527 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
528 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
529 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
530 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062)
531
532
533 typedef struct _CONFIG_PAGE_MANUFACTURING_0
534 {
535 CONFIG_PAGE_HEADER Header; /* 00h */
536 U8 ChipName[16]; /* 04h */
537 U8 ChipRevision[8]; /* 14h */
538 U8 BoardName[16]; /* 1Ch */
539 U8 BoardAssembly[16]; /* 2Ch */
540 U8 BoardTracerNumber[16]; /* 3Ch */
541
542 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
543 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
544
545 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
546
547
548 typedef struct _CONFIG_PAGE_MANUFACTURING_1
549 {
550 CONFIG_PAGE_HEADER Header; /* 00h */
551 U8 VPD[256]; /* 04h */
552 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
553 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
554
555 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
556
557
558 typedef struct _MPI_CHIP_REVISION_ID
559 {
560 U16 DeviceID; /* 00h */
561 U8 PCIRevisionID; /* 02h */
562 U8 Reserved; /* 03h */
563 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
564 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
565
566
567 /*
568 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
569 * one and check Header.PageLength at runtime.
570 */
571 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
572 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
573 #endif
574
575 typedef struct _CONFIG_PAGE_MANUFACTURING_2
576 {
577 CONFIG_PAGE_HEADER Header; /* 00h */
578 MPI_CHIP_REVISION_ID ChipId; /* 04h */
579 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
580 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
581 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
582
583 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
584
585
586 /*
587 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
588 * one and check Header.PageLength at runtime.
589 */
590 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
591 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
592 #endif
593
594 typedef struct _CONFIG_PAGE_MANUFACTURING_3
595 {
596 CONFIG_PAGE_HEADER Header; /* 00h */
597 MPI_CHIP_REVISION_ID ChipId; /* 04h */
598 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
599 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
600 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
601
602 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
603
604
605 typedef struct _CONFIG_PAGE_MANUFACTURING_4
606 {
607 CONFIG_PAGE_HEADER Header; /* 00h */
608 U32 Reserved1; /* 04h */
609 U8 InfoOffset0; /* 08h */
610 U8 InfoSize0; /* 09h */
611 U8 InfoOffset1; /* 0Ah */
612 U8 InfoSize1; /* 0Bh */
613 U8 InquirySize; /* 0Ch */
614 U8 Flags; /* 0Dh */
615 U16 Reserved2; /* 0Eh */
616 U8 InquiryData[56]; /* 10h */
617 U32 ISVolumeSettings; /* 48h */
618 U32 IMEVolumeSettings; /* 4Ch */
619 U32 IMVolumeSettings; /* 50h */
620 U32 Reserved3; /* 54h */
621 U32 Reserved4; /* 58h */
622 U32 Reserved5; /* 5Ch */
623 U8 IMEDataScrubRate; /* 60h */
624 U8 IMEResyncRate; /* 61h */
625 U16 Reserved6; /* 62h */
626 U8 IMDataScrubRate; /* 64h */
627 U8 IMResyncRate; /* 65h */
628 U16 Reserved7; /* 66h */
629 U32 Reserved8; /* 68h */
630 U32 Reserved9; /* 6Ch */
631 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
632 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
633
634 #define MPI_MANUFACTURING4_PAGEVERSION (0x03)
635
636 /* defines for the Flags field */
637 #define MPI_MANPAGE4_IME_DISABLE (0x20)
638 #define MPI_MANPAGE4_IM_DISABLE (0x10)
639 #define MPI_MANPAGE4_IS_DISABLE (0x08)
640 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04)
641 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02)
642 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
643
644
645 typedef struct _CONFIG_PAGE_MANUFACTURING_5
646 {
647 CONFIG_PAGE_HEADER Header; /* 00h */
648 U64 BaseWWID; /* 04h */
649 U8 Flags; /* 0Ch */
650 U8 Reserved1; /* 0Dh */
651 U16 Reserved2; /* 0Eh */
652 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
653 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
654
655 #define MPI_MANUFACTURING5_PAGEVERSION (0x01)
656
657 /* defines for the Flags field */
658 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
659
660
661 typedef struct _CONFIG_PAGE_MANUFACTURING_6
662 {
663 CONFIG_PAGE_HEADER Header; /* 00h */
664 U32 ProductSpecificInfo;/* 04h */
665 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
666 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
667
668 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
669
670
671 /****************************************************************************
672 * IO Unit Config Pages
673 ****************************************************************************/
674
675 typedef struct _CONFIG_PAGE_IO_UNIT_0
676 {
677 CONFIG_PAGE_HEADER Header; /* 00h */
678 U64 UniqueValue; /* 04h */
679 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
680 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
681
682 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
683
684
685 typedef struct _CONFIG_PAGE_IO_UNIT_1
686 {
687 CONFIG_PAGE_HEADER Header; /* 00h */
688 U32 Flags; /* 04h */
689 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
690 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
691
692 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02)
693
694 /* IO Unit Page 1 Flags defines */
695 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
696 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
697 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
698 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
699 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
700 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
701 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
702 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
703 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
704 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)
705
706 typedef struct _MPI_ADAPTER_INFO
707 {
708 U8 PciBusNumber; /* 00h */
709 U8 PciDeviceAndFunctionNumber; /* 01h */
710 U16 AdapterFlags; /* 02h */
711 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
712 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
713
714 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
715 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
716
717 typedef struct _CONFIG_PAGE_IO_UNIT_2
718 {
719 CONFIG_PAGE_HEADER Header; /* 00h */
720 U32 Flags; /* 04h */
721 U32 BiosVersion; /* 08h */
722 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
723 U32 Reserved1; /* 1Ch */
724 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
725 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
726
727 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
728
729 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
730 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
731 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
732 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
733
734 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
735 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
736 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
737 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
738
739
740 /*
741 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
742 * one and check Header.PageLength at runtime.
743 */
744 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
745 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
746 #endif
747
748 typedef struct _CONFIG_PAGE_IO_UNIT_3
749 {
750 CONFIG_PAGE_HEADER Header; /* 00h */
751 U8 GPIOCount; /* 04h */
752 U8 Reserved1; /* 05h */
753 U16 Reserved2; /* 06h */
754 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
755 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
756 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
757
758 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
759
760 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
761 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
762 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
763 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
764
765
766 typedef struct _CONFIG_PAGE_IO_UNIT_4
767 {
768 CONFIG_PAGE_HEADER Header; /* 00h */
769 U32 Reserved1; /* 04h */
770 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
771 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
772 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
773
774 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
775
776
777 /****************************************************************************
778 * IOC Config Pages
779 ****************************************************************************/
780
781 typedef struct _CONFIG_PAGE_IOC_0
782 {
783 CONFIG_PAGE_HEADER Header; /* 00h */
784 U32 TotalNVStore; /* 04h */
785 U32 FreeNVStore; /* 08h */
786 U16 VendorID; /* 0Ch */
787 U16 DeviceID; /* 0Eh */
788 U8 RevisionID; /* 10h */
789 U8 Reserved[3]; /* 11h */
790 U32 ClassCode; /* 14h */
791 U16 SubsystemVendorID; /* 18h */
792 U16 SubsystemID; /* 1Ah */
793 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
794 IOCPage0_t, MPI_POINTER pIOCPage0_t;
795
796 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
797
798
799 typedef struct _CONFIG_PAGE_IOC_1
800 {
801 CONFIG_PAGE_HEADER Header; /* 00h */
802 U32 Flags; /* 04h */
803 U32 CoalescingTimeout; /* 08h */
804 U8 CoalescingDepth; /* 0Ch */
805 U8 PCISlotNum; /* 0Dh */
806 U8 Reserved[2]; /* 0Eh */
807 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
808 IOCPage1_t, MPI_POINTER pIOCPage1_t;
809
810 #define MPI_IOCPAGE1_PAGEVERSION (0x03)
811
812 /* defines for the Flags field */
813 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
814 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
815 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
816 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
817 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
818 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
819
820 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
821
822
823 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
824 {
825 U8 VolumeID; /* 00h */
826 U8 VolumeBus; /* 01h */
827 U8 VolumeIOC; /* 02h */
828 U8 VolumePageNumber; /* 03h */
829 U8 VolumeType; /* 04h */
830 U8 Flags; /* 05h */
831 U16 Reserved3; /* 06h */
832 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
833 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
834
835 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
836
837 #define MPI_RAID_VOL_TYPE_IS (0x00)
838 #define MPI_RAID_VOL_TYPE_IME (0x01)
839 #define MPI_RAID_VOL_TYPE_IM (0x02)
840 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
841 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
842 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
843 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
844 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
845
846 /* IOC Page 2 Volume Flags values */
847
848 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
849
850 /*
851 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
852 * one and check Header.PageLength at runtime.
853 */
854 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
855 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
856 #endif
857
858 typedef struct _CONFIG_PAGE_IOC_2
859 {
860 CONFIG_PAGE_HEADER Header; /* 00h */
861 U32 CapabilitiesFlags; /* 04h */
862 U8 NumActiveVolumes; /* 08h */
863 U8 MaxVolumes; /* 09h */
864 U8 NumActivePhysDisks; /* 0Ah */
865 U8 MaxPhysDisks; /* 0Bh */
866 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
867 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
868 IOCPage2_t, MPI_POINTER pIOCPage2_t;
869
870 #define MPI_IOCPAGE2_PAGEVERSION (0x03)
871
872 /* IOC Page 2 Capabilities flags */
873
874 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
875 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
876 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
877 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
878 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
879 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
880 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
881 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
882 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
883 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
884
885
886 typedef struct _IOC_3_PHYS_DISK
887 {
888 U8 PhysDiskID; /* 00h */
889 U8 PhysDiskBus; /* 01h */
890 U8 PhysDiskIOC; /* 02h */
891 U8 PhysDiskNum; /* 03h */
892 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
893 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
894
895 /*
896 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
897 * one and check Header.PageLength at runtime.
898 */
899 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
900 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
901 #endif
902
903 typedef struct _CONFIG_PAGE_IOC_3
904 {
905 CONFIG_PAGE_HEADER Header; /* 00h */
906 U8 NumPhysDisks; /* 04h */
907 U8 Reserved1; /* 05h */
908 U16 Reserved2; /* 06h */
909 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
910 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
911 IOCPage3_t, MPI_POINTER pIOCPage3_t;
912
913 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
914
915
916 typedef struct _IOC_4_SEP
917 {
918 U8 SEPTargetID; /* 00h */
919 U8 SEPBus; /* 01h */
920 U16 Reserved; /* 02h */
921 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
922 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
923
924 /*
925 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
926 * one and check Header.PageLength at runtime.
927 */
928 #ifndef MPI_IOC_PAGE_4_SEP_MAX
929 #define MPI_IOC_PAGE_4_SEP_MAX (1)
930 #endif
931
932 typedef struct _CONFIG_PAGE_IOC_4
933 {
934 CONFIG_PAGE_HEADER Header; /* 00h */
935 U8 ActiveSEP; /* 04h */
936 U8 MaxSEP; /* 05h */
937 U16 Reserved1; /* 06h */
938 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
939 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
940 IOCPage4_t, MPI_POINTER pIOCPage4_t;
941
942 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
943
944
945 typedef struct _IOC_5_HOT_SPARE
946 {
947 U8 PhysDiskNum; /* 00h */
948 U8 Reserved; /* 01h */
949 U8 HotSparePool; /* 02h */
950 U8 Flags; /* 03h */
951 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
952 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
953
954 /* IOC Page 5 HotSpare Flags */
955 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
956
957 /*
958 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
959 * one and check Header.PageLength at runtime.
960 */
961 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
962 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
963 #endif
964
965 typedef struct _CONFIG_PAGE_IOC_5
966 {
967 CONFIG_PAGE_HEADER Header; /* 00h */
968 U32 Reserved1; /* 04h */
969 U8 NumHotSpares; /* 08h */
970 U8 Reserved2; /* 09h */
971 U16 Reserved3; /* 0Ah */
972 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
973 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
974 IOCPage5_t, MPI_POINTER pIOCPage5_t;
975
976 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
977
978
979 /****************************************************************************
980 * BIOS Config Pages
981 ****************************************************************************/
982
983 typedef struct _CONFIG_PAGE_BIOS_1
984 {
985 CONFIG_PAGE_HEADER Header; /* 00h */
986 U32 BiosOptions; /* 04h */
987 U32 IOCSettings; /* 08h */
988 U32 Reserved1; /* 0Ch */
989 U32 DeviceSettings; /* 10h */
990 U16 NumberOfDevices; /* 14h */
991 U8 ExpanderSpinup; /* 16h */
992 U8 Reserved2; /* 17h */
993 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
994 U16 IOTimeoutSequential; /* 1Ah */
995 U16 IOTimeoutOther; /* 1Ch */
996 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
997 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
998 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
999
1000 #define MPI_BIOSPAGE1_PAGEVERSION (0x03)
1001
1002 /* values for the BiosOptions field */
1003 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
1004 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
1005 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
1006 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1007
1008 /* values for the IOCSettings field */
1009 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000)
1010 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1011
1012 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
1013 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
1014
1015 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000)
1016 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000)
1017
1018 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1019 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1020 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1021
1022 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
1023 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
1024
1025 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
1026 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
1027
1028 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1029 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1030 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1031 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1032
1033 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1034 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1035 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1036 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1037 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1038
1039 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1040
1041 /* values for the DeviceSettings field */
1042 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1043 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1044 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1045 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1046
1047 /* defines for the ExpanderSpinup field */
1048 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0)
1049 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4)
1050 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F)
1051
1052 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1053 {
1054 U32 Reserved1; /* 00h */
1055 U32 Reserved2; /* 04h */
1056 U32 Reserved3; /* 08h */
1057 U32 Reserved4; /* 0Ch */
1058 U32 Reserved5; /* 10h */
1059 U32 Reserved6; /* 14h */
1060 U32 Reserved7; /* 18h */
1061 U32 Reserved8; /* 1Ch */
1062 U32 Reserved9; /* 20h */
1063 U32 Reserved10; /* 24h */
1064 U32 Reserved11; /* 28h */
1065 U32 Reserved12; /* 2Ch */
1066 U32 Reserved13; /* 30h */
1067 U32 Reserved14; /* 34h */
1068 U32 Reserved15; /* 38h */
1069 U32 Reserved16; /* 3Ch */
1070 U32 Reserved17; /* 40h */
1071 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1072
1073 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1074 {
1075 U8 TargetID; /* 00h */
1076 U8 Bus; /* 01h */
1077 U8 AdapterNumber; /* 02h */
1078 U8 Reserved1; /* 03h */
1079 U32 Reserved2; /* 04h */
1080 U32 Reserved3; /* 08h */
1081 U32 Reserved4; /* 0Ch */
1082 U8 LUN[8]; /* 10h */
1083 U32 Reserved5; /* 18h */
1084 U32 Reserved6; /* 1Ch */
1085 U32 Reserved7; /* 20h */
1086 U32 Reserved8; /* 24h */
1087 U32 Reserved9; /* 28h */
1088 U32 Reserved10; /* 2Ch */
1089 U32 Reserved11; /* 30h */
1090 U32 Reserved12; /* 34h */
1091 U32 Reserved13; /* 38h */
1092 U32 Reserved14; /* 3Ch */
1093 U32 Reserved15; /* 40h */
1094 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1095
1096 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1097 {
1098 U8 TargetID; /* 00h */
1099 U8 Bus; /* 01h */
1100 U16 PCIAddress; /* 02h */
1101 U32 Reserved1; /* 04h */
1102 U32 Reserved2; /* 08h */
1103 U32 Reserved3; /* 0Ch */
1104 U8 LUN[8]; /* 10h */
1105 U32 Reserved4; /* 18h */
1106 U32 Reserved5; /* 1Ch */
1107 U32 Reserved6; /* 20h */
1108 U32 Reserved7; /* 24h */
1109 U32 Reserved8; /* 28h */
1110 U32 Reserved9; /* 2Ch */
1111 U32 Reserved10; /* 30h */
1112 U32 Reserved11; /* 34h */
1113 U32 Reserved12; /* 38h */
1114 U32 Reserved13; /* 3Ch */
1115 U32 Reserved14; /* 40h */
1116 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1117
1118 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1119 {
1120 U8 TargetID; /* 00h */
1121 U8 Bus; /* 01h */
1122 U8 PCISlotNumber; /* 02h */
1123 U8 Reserved1; /* 03h */
1124 U32 Reserved2; /* 04h */
1125 U32 Reserved3; /* 08h */
1126 U32 Reserved4; /* 0Ch */
1127 U8 LUN[8]; /* 10h */
1128 U32 Reserved5; /* 18h */
1129 U32 Reserved6; /* 1Ch */
1130 U32 Reserved7; /* 20h */
1131 U32 Reserved8; /* 24h */
1132 U32 Reserved9; /* 28h */
1133 U32 Reserved10; /* 2Ch */
1134 U32 Reserved11; /* 30h */
1135 U32 Reserved12; /* 34h */
1136 U32 Reserved13; /* 38h */
1137 U32 Reserved14; /* 3Ch */
1138 U32 Reserved15; /* 40h */
1139 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1140
1141 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1142 {
1143 U64 WWPN; /* 00h */
1144 U32 Reserved1; /* 08h */
1145 U32 Reserved2; /* 0Ch */
1146 U8 LUN[8]; /* 10h */
1147 U32 Reserved3; /* 18h */
1148 U32 Reserved4; /* 1Ch */
1149 U32 Reserved5; /* 20h */
1150 U32 Reserved6; /* 24h */
1151 U32 Reserved7; /* 28h */
1152 U32 Reserved8; /* 2Ch */
1153 U32 Reserved9; /* 30h */
1154 U32 Reserved10; /* 34h */
1155 U32 Reserved11; /* 38h */
1156 U32 Reserved12; /* 3Ch */
1157 U32 Reserved13; /* 40h */
1158 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1159
1160 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1161 {
1162 U64 SASAddress; /* 00h */
1163 U32 Reserved1; /* 08h */
1164 U32 Reserved2; /* 0Ch */
1165 U8 LUN[8]; /* 10h */
1166 U32 Reserved3; /* 18h */
1167 U32 Reserved4; /* 1Ch */
1168 U32 Reserved5; /* 20h */
1169 U32 Reserved6; /* 24h */
1170 U32 Reserved7; /* 28h */
1171 U32 Reserved8; /* 2Ch */
1172 U32 Reserved9; /* 30h */
1173 U32 Reserved10; /* 34h */
1174 U32 Reserved11; /* 38h */
1175 U32 Reserved12; /* 3Ch */
1176 U32 Reserved13; /* 40h */
1177 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1178
1179 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1180 {
1181 U64 EnclosureLogicalID; /* 00h */
1182 U32 Reserved1; /* 08h */
1183 U32 Reserved2; /* 0Ch */
1184 U8 LUN[8]; /* 10h */
1185 U16 SlotNumber; /* 18h */
1186 U16 Reserved3; /* 1Ah */
1187 U32 Reserved4; /* 1Ch */
1188 U32 Reserved5; /* 20h */
1189 U32 Reserved6; /* 24h */
1190 U32 Reserved7; /* 28h */
1191 U32 Reserved8; /* 2Ch */
1192 U32 Reserved9; /* 30h */
1193 U32 Reserved10; /* 34h */
1194 U32 Reserved11; /* 38h */
1195 U32 Reserved12; /* 3Ch */
1196 U32 Reserved13; /* 40h */
1197 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1198 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1199
1200 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1201 {
1202 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1203 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1204 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1205 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1206 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1207 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1208 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1209 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1210
1211 typedef struct _CONFIG_PAGE_BIOS_2
1212 {
1213 CONFIG_PAGE_HEADER Header; /* 00h */
1214 U32 Reserved1; /* 04h */
1215 U32 Reserved2; /* 08h */
1216 U32 Reserved3; /* 0Ch */
1217 U32 Reserved4; /* 10h */
1218 U32 Reserved5; /* 14h */
1219 U32 Reserved6; /* 18h */
1220 U8 BootDeviceForm; /* 1Ch */
1221 U8 Reserved7; /* 1Dh */
1222 U16 Reserved8; /* 1Eh */
1223 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1224 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1225 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1226
1227 #define MPI_BIOSPAGE2_PAGEVERSION (0x01)
1228
1229 #define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1230 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1231 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1232 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1233 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1234 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1235 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1236 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1237
1238
1239 /****************************************************************************
1240 * SCSI Port Config Pages
1241 ****************************************************************************/
1242
1243 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1244 {
1245 CONFIG_PAGE_HEADER Header; /* 00h */
1246 U32 Capabilities; /* 04h */
1247 U32 PhysicalInterface; /* 08h */
1248 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1249 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1250
1251 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
1252
1253 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1254 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1255 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1256 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1257 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1258 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1259 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1260 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1261 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1262 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1263 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1264 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1265 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1266
1267 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1268 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1269 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \
1270 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1271 )
1272 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1273 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1274 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1275 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \
1276 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1277 )
1278 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
1279 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1280 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1281
1282 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1283 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1284 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1285 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1286 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1287 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1288 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1289 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1290
1291
1292 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1293 {
1294 CONFIG_PAGE_HEADER Header; /* 00h */
1295 U32 Configuration; /* 04h */
1296 U32 OnBusTimerValue; /* 08h */
1297 U8 TargetConfig; /* 0Ch */
1298 U8 Reserved1; /* 0Dh */
1299 U16 IDConfig; /* 0Eh */
1300 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1301 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1302
1303 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1304
1305 /* Configuration values */
1306 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1307 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1308 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1309
1310 /* TargetConfig values */
1311 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1312 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1313
1314
1315 typedef struct _MPI_DEVICE_INFO
1316 {
1317 U8 Timeout; /* 00h */
1318 U8 SyncFactor; /* 01h */
1319 U16 DeviceFlags; /* 02h */
1320 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1321 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1322
1323 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1324 {
1325 CONFIG_PAGE_HEADER Header; /* 00h */
1326 U32 PortFlags; /* 04h */
1327 U32 PortSettings; /* 08h */
1328 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
1329 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1330 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1331
1332 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1333
1334 /* PortFlags values */
1335 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1336 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1337 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1338 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1339
1340 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1341 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1342 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1343 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1344
1345
1346 /* PortSettings values */
1347 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1348 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1349 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1350 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1351 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1352 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1353 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1354 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1355 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1356 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1357 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1358 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1359 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1360 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1361 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1362 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1363
1364 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1365 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1366 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1367 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1368 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1369 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1370
1371
1372 /****************************************************************************
1373 * SCSI Target Device Config Pages
1374 ****************************************************************************/
1375
1376 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1377 {
1378 CONFIG_PAGE_HEADER Header; /* 00h */
1379 U32 NegotiatedParameters; /* 04h */
1380 U32 Information; /* 08h */
1381 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1382 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1383
1384 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
1385
1386 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1387 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1388 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1389 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1390 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1391 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1392 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1393 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1394 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1395 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1396 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1397 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1398 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
1399 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1400 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1401
1402 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1403 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1404 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1405 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1406
1407
1408 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1409 {
1410 CONFIG_PAGE_HEADER Header; /* 00h */
1411 U32 RequestedParameters; /* 04h */
1412 U32 Reserved; /* 08h */
1413 U32 Configuration; /* 0Ch */
1414 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1415 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1416
1417 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
1418
1419 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1420 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1421 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1422 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1423 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1424 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1425 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1426 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1427 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1428 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1429 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1430 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1431 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
1432 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1433 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1434
1435 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1436 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1437 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1438 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1439
1440
1441 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1442 {
1443 CONFIG_PAGE_HEADER Header; /* 00h */
1444 U32 DomainValidation; /* 04h */
1445 U32 ParityPipeSelect; /* 08h */
1446 U32 DataPipeSelect; /* 0Ch */
1447 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1448 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1449
1450 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1451
1452 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1453 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1454 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1455 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1456 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1457 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1458 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1459 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1460 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1461
1462 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1463
1464 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1465 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1466 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1467 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1468 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1469 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1470 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1471 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1472 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1473 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1474 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1475 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1476 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1477 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1478 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1479 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1480
1481
1482 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1483 {
1484 CONFIG_PAGE_HEADER Header; /* 00h */
1485 U16 MsgRejectCount; /* 04h */
1486 U16 PhaseErrorCount; /* 06h */
1487 U16 ParityErrorCount; /* 08h */
1488 U16 Reserved; /* 0Ah */
1489 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1490 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1491
1492 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1493
1494 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1495 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1496
1497
1498 /****************************************************************************
1499 * FC Port Config Pages
1500 ****************************************************************************/
1501
1502 typedef struct _CONFIG_PAGE_FC_PORT_0
1503 {
1504 CONFIG_PAGE_HEADER Header; /* 00h */
1505 U32 Flags; /* 04h */
1506 U8 MPIPortNumber; /* 08h */
1507 U8 LinkType; /* 09h */
1508 U8 PortState; /* 0Ah */
1509 U8 Reserved; /* 0Bh */
1510 U32 PortIdentifier; /* 0Ch */
1511 U64 WWNN; /* 10h */
1512 U64 WWPN; /* 18h */
1513 U32 SupportedServiceClass; /* 20h */
1514 U32 SupportedSpeeds; /* 24h */
1515 U32 CurrentSpeed; /* 28h */
1516 U32 MaxFrameSize; /* 2Ch */
1517 U64 FabricWWNN; /* 30h */
1518 U64 FabricWWPN; /* 38h */
1519 U32 DiscoveredPortsCount; /* 40h */
1520 U32 MaxInitiators; /* 44h */
1521 U8 MaxAliasesSupported; /* 48h */
1522 U8 MaxHardAliasesSupported; /* 49h */
1523 U8 NumCurrentAliases; /* 4Ah */
1524 U8 Reserved1; /* 4Bh */
1525 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1526 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1527
1528 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1529
1530 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1531 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1532 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1533 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1534 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1535
1536 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1537 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1538 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1539
1540 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1541 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1542 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1543 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1544 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1545 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1546
1547 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1548 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1549 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1550 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1551 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1552 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1553 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1554 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1555 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1556 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1557 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1558 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1559 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1560 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1561 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1562 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1563
1564 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1565 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1566 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1567 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1568 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1569 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1570 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1571 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1572
1573 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1574 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1575 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1576
1577 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1578 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1579 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1580 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1581 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1582
1583 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1584 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1585 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1586 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1587 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1588 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1589
1590
1591 typedef struct _CONFIG_PAGE_FC_PORT_1
1592 {
1593 CONFIG_PAGE_HEADER Header; /* 00h */
1594 U32 Flags; /* 04h */
1595 U64 NoSEEPROMWWNN; /* 08h */
1596 U64 NoSEEPROMWWPN; /* 10h */
1597 U8 HardALPA; /* 18h */
1598 U8 LinkConfig; /* 19h */
1599 U8 TopologyConfig; /* 1Ah */
1600 U8 AltConnector; /* 1Bh */
1601 U8 NumRequestedAliases; /* 1Ch */
1602 U8 RR_TOV; /* 1Dh */
1603 U8 InitiatorDeviceTimeout; /* 1Eh */
1604 U8 InitiatorIoPendTimeout; /* 1Fh */
1605 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1606 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1607
1608 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1609
1610 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1611 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1612 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1613 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1614 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1615 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1616 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1617 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1618 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1619 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1620 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1621 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1622 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1623 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1624
1625 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1626 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1627 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1628 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1629 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1630 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1631
1632 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1633 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1634 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1635 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1636
1637 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1638
1639 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1640 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1641 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1642 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1643 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1644 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1645
1646 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1647 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1648 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1649 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1650
1651 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1652
1653 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1654 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
1655
1656
1657 typedef struct _CONFIG_PAGE_FC_PORT_2
1658 {
1659 CONFIG_PAGE_HEADER Header; /* 00h */
1660 U8 NumberActive; /* 04h */
1661 U8 ALPA[127]; /* 05h */
1662 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1663 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1664
1665 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1666
1667
1668 typedef struct _WWN_FORMAT
1669 {
1670 U64 WWNN; /* 00h */
1671 U64 WWPN; /* 08h */
1672 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1673 WWNFormat, MPI_POINTER pWWNFormat;
1674
1675 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1676 {
1677 WWN_FORMAT WWN;
1678 U32 Did;
1679 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1680 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1681
1682 typedef struct _FC_PORT_PERSISTENT
1683 {
1684 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1685 U8 TargetID; /* 10h */
1686 U8 Bus; /* 11h */
1687 U16 Flags; /* 12h */
1688 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1689 PersistentData_t, MPI_POINTER pPersistentData_t;
1690
1691 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1692 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1693 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1694 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1695 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1696 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1697
1698 /*
1699 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1700 * one and check Header.PageLength at runtime.
1701 */
1702 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1703 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1704 #endif
1705
1706 typedef struct _CONFIG_PAGE_FC_PORT_3
1707 {
1708 CONFIG_PAGE_HEADER Header; /* 00h */
1709 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1710 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1711 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1712
1713 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1714
1715
1716 typedef struct _CONFIG_PAGE_FC_PORT_4
1717 {
1718 CONFIG_PAGE_HEADER Header; /* 00h */
1719 U32 PortFlags; /* 04h */
1720 U32 PortSettings; /* 08h */
1721 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1722 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1723
1724 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1725
1726 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1727
1728 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1729 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1730 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1731 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1732 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1733 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1734 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1735
1736
1737 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1738 {
1739 U8 Flags; /* 00h */
1740 U8 AliasAlpa; /* 01h */
1741 U16 Reserved; /* 02h */
1742 U64 AliasWWNN; /* 04h */
1743 U64 AliasWWPN; /* 0Ch */
1744 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1745 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1746 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1747
1748 typedef struct _CONFIG_PAGE_FC_PORT_5
1749 {
1750 CONFIG_PAGE_HEADER Header; /* 00h */
1751 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1752 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1753 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1754
1755 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1756
1757 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1758 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1759 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1760 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1761 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1762
1763 typedef struct _CONFIG_PAGE_FC_PORT_6
1764 {
1765 CONFIG_PAGE_HEADER Header; /* 00h */
1766 U32 Reserved; /* 04h */
1767 U64 TimeSinceReset; /* 08h */
1768 U64 TxFrames; /* 10h */
1769 U64 RxFrames; /* 18h */
1770 U64 TxWords; /* 20h */
1771 U64 RxWords; /* 28h */
1772 U64 LipCount; /* 30h */
1773 U64 NosCount; /* 38h */
1774 U64 ErrorFrames; /* 40h */
1775 U64 DumpedFrames; /* 48h */
1776 U64 LinkFailureCount; /* 50h */
1777 U64 LossOfSyncCount; /* 58h */
1778 U64 LossOfSignalCount; /* 60h */
1779 U64 PrimativeSeqErrCount; /* 68h */
1780 U64 InvalidTxWordCount; /* 70h */
1781 U64 InvalidCrcCount; /* 78h */
1782 U64 FcpInitiatorIoCount; /* 80h */
1783 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1784 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1785
1786 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1787
1788
1789 typedef struct _CONFIG_PAGE_FC_PORT_7
1790 {
1791 CONFIG_PAGE_HEADER Header; /* 00h */
1792 U32 Reserved; /* 04h */
1793 U8 PortSymbolicName[256]; /* 08h */
1794 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1795 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1796
1797 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1798
1799
1800 typedef struct _CONFIG_PAGE_FC_PORT_8
1801 {
1802 CONFIG_PAGE_HEADER Header; /* 00h */
1803 U32 BitVector[8]; /* 04h */
1804 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1805 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1806
1807 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1808
1809
1810 typedef struct _CONFIG_PAGE_FC_PORT_9
1811 {
1812 CONFIG_PAGE_HEADER Header; /* 00h */
1813 U32 Reserved; /* 04h */
1814 U64 GlobalWWPN; /* 08h */
1815 U64 GlobalWWNN; /* 10h */
1816 U32 UnitType; /* 18h */
1817 U32 PhysicalPortNumber; /* 1Ch */
1818 U32 NumAttachedNodes; /* 20h */
1819 U16 IPVersion; /* 24h */
1820 U16 UDPPortNumber; /* 26h */
1821 U8 IPAddress[16]; /* 28h */
1822 U16 Reserved1; /* 38h */
1823 U16 TopologyDiscoveryFlags; /* 3Ah */
1824 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1825 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1826
1827 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1828
1829
1830 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1831 {
1832 U8 Id; /* 10h */
1833 U8 ExtId; /* 11h */
1834 U8 Connector; /* 12h */
1835 U8 Transceiver[8]; /* 13h */
1836 U8 Encoding; /* 1Bh */
1837 U8 BitRate_100mbs; /* 1Ch */
1838 U8 Reserved1; /* 1Dh */
1839 U8 Length9u_km; /* 1Eh */
1840 U8 Length9u_100m; /* 1Fh */
1841 U8 Length50u_10m; /* 20h */
1842 U8 Length62p5u_10m; /* 21h */
1843 U8 LengthCopper_m; /* 22h */
1844 U8 Reseverved2; /* 22h */
1845 U8 VendorName[16]; /* 24h */
1846 U8 Reserved3; /* 34h */
1847 U8 VendorOUI[3]; /* 35h */
1848 U8 VendorPN[16]; /* 38h */
1849 U8 VendorRev[4]; /* 48h */
1850 U16 Wavelength; /* 4Ch */
1851 U8 Reserved4; /* 4Eh */
1852 U8 CC_BASE; /* 4Fh */
1853 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1854 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1855 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1856
1857 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
1858 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
1859 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
1860 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
1861 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
1862 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
1863 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1864
1865 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
1866 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
1867 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
1868 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
1869 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
1870 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
1871 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
1872 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
1873 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1874
1875 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
1876 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
1877 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
1878 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
1879 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
1880 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
1881 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
1882 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
1883 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
1884 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
1885 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
1886 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
1887 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
1888 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
1889 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
1890 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
1891 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
1892 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
1893 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
1894
1895 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
1896 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
1897 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
1898 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
1899 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
1900
1901
1902 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
1903 {
1904 U8 Options[2]; /* 50h */
1905 U8 BitRateMax; /* 52h */
1906 U8 BitRateMin; /* 53h */
1907 U8 VendorSN[16]; /* 54h */
1908 U8 DateCode[8]; /* 64h */
1909 U8 DiagMonitoringType; /* 6Ch */
1910 U8 EnhancedOptions; /* 6Dh */
1911 U8 SFF8472Compliance; /* 6Eh */
1912 U8 CC_EXT; /* 6Fh */
1913 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1914 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1915 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
1916
1917 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
1918 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
1919 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
1920 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
1921 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
1922
1923
1924 typedef struct _CONFIG_PAGE_FC_PORT_10
1925 {
1926 CONFIG_PAGE_HEADER Header; /* 00h */
1927 U8 Flags; /* 04h */
1928 U8 Reserved1; /* 05h */
1929 U16 Reserved2; /* 06h */
1930 U32 HwConfig1; /* 08h */
1931 U32 HwConfig2; /* 0Ch */
1932 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
1933 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
1934 U8 VendorSpecific[32]; /* 70h */
1935 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
1936 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
1937
1938 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
1939
1940 /* standard MODDEF pin definitions (from GBIC spec.) */
1941 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
1942 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
1943 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
1944 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
1945 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
1946 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
1947 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
1948 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
1949 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
1950 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
1951 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
1952 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
1953
1954 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
1955 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
1956
1957
1958 /****************************************************************************
1959 * FC Device Config Pages
1960 ****************************************************************************/
1961
1962 typedef struct _CONFIG_PAGE_FC_DEVICE_0
1963 {
1964 CONFIG_PAGE_HEADER Header; /* 00h */
1965 U64 WWNN; /* 04h */
1966 U64 WWPN; /* 0Ch */
1967 U32 PortIdentifier; /* 14h */
1968 U8 Protocol; /* 18h */
1969 U8 Flags; /* 19h */
1970 U16 BBCredit; /* 1Ah */
1971 U16 MaxRxFrameSize; /* 1Ch */
1972 U8 ADISCHardALPA; /* 1Eh */
1973 U8 PortNumber; /* 1Fh */
1974 U8 FcPhLowestVersion; /* 20h */
1975 U8 FcPhHighestVersion; /* 21h */
1976 U8 CurrentTargetID; /* 22h */
1977 U8 CurrentBus; /* 23h */
1978 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1979 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1980
1981 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
1982
1983 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
1984 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
1985 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
1986
1987 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
1988 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
1989 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
1990 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
1991
1992 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
1993 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
1994 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
1995 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
1996 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
1997 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
1998 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
1999 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
2000
2001 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
2002
2003 /****************************************************************************
2004 * RAID Volume Config Pages
2005 ****************************************************************************/
2006
2007 typedef struct _RAID_VOL0_PHYS_DISK
2008 {
2009 U16 Reserved; /* 00h */
2010 U8 PhysDiskMap; /* 02h */
2011 U8 PhysDiskNum; /* 03h */
2012 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
2013 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
2014
2015 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
2016 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
2017
2018 typedef struct _RAID_VOL0_STATUS
2019 {
2020 U8 Flags; /* 00h */
2021 U8 State; /* 01h */
2022 U16 Reserved; /* 02h */
2023 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2024 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2025
2026 /* RAID Volume Page 0 VolumeStatus defines */
2027 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
2028 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
2029 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
2030 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
2031 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
2032
2033 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2034 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2035 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2036 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
2037
2038 typedef struct _RAID_VOL0_SETTINGS
2039 {
2040 U16 Settings; /* 00h */
2041 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2042 U8 Reserved; /* 02h */
2043 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2044 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2045
2046 /* RAID Volume Page 0 VolumeSettings defines */
2047 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2048 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2049 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2050 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2051 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
2052 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2053 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2054
2055 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2056 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2057 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2058 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2059 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
2060 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
2061 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
2062 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
2063 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
2064
2065 /*
2066 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2067 * one and check Header.PageLength at runtime.
2068 */
2069 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2070 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2071 #endif
2072
2073 typedef struct _CONFIG_PAGE_RAID_VOL_0
2074 {
2075 CONFIG_PAGE_HEADER Header; /* 00h */
2076 U8 VolumeID; /* 04h */
2077 U8 VolumeBus; /* 05h */
2078 U8 VolumeIOC; /* 06h */
2079 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2080 RAID_VOL0_STATUS VolumeStatus; /* 08h */
2081 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2082 U32 MaxLBA; /* 10h */
2083 U32 Reserved1; /* 14h */
2084 U32 StripeSize; /* 18h */
2085 U32 Reserved2; /* 1Ch */
2086 U32 Reserved3; /* 20h */
2087 U8 NumPhysDisks; /* 24h */
2088 U8 DataScrubRate; /* 25h */
2089 U8 ResyncRate; /* 26h */
2090 U8 InactiveStatus; /* 27h */
2091 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2092 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2093 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2094
2095 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x05)
2096
2097 /* values for RAID Volume Page 0 InactiveStatus field */
2098 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2099 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2100 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2101 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2102 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2103 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2104 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2105
2106
2107 typedef struct _CONFIG_PAGE_RAID_VOL_1
2108 {
2109 CONFIG_PAGE_HEADER Header; /* 00h */
2110 U8 VolumeID; /* 01h */
2111 U8 VolumeBus; /* 02h */
2112 U8 VolumeIOC; /* 03h */
2113 U8 Reserved0; /* 04h */
2114 U8 GUID[24]; /* 05h */
2115 U8 Name[32]; /* 20h */
2116 U64 WWID; /* 40h */
2117 U32 Reserved1; /* 48h */
2118 U32 Reserved2; /* 4Ch */
2119 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2120 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2121
2122 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2123
2124
2125 /****************************************************************************
2126 * RAID Physical Disk Config Pages
2127 ****************************************************************************/
2128
2129 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2130 {
2131 U8 ErrorCdbByte; /* 00h */
2132 U8 ErrorSenseKey; /* 01h */
2133 U16 Reserved; /* 02h */
2134 U16 ErrorCount; /* 04h */
2135 U8 ErrorASC; /* 06h */
2136 U8 ErrorASCQ; /* 07h */
2137 U16 SmartCount; /* 08h */
2138 U8 SmartASC; /* 0Ah */
2139 U8 SmartASCQ; /* 0Bh */
2140 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2141 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2142
2143 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2144 {
2145 U8 VendorID[8]; /* 00h */
2146 U8 ProductID[16]; /* 08h */
2147 U8 ProductRevLevel[4]; /* 18h */
2148 U8 Info[32]; /* 1Ch */
2149 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2150 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2151
2152 typedef struct _RAID_PHYS_DISK0_SETTINGS
2153 {
2154 U8 SepID; /* 00h */
2155 U8 SepBus; /* 01h */
2156 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2157 U8 PhysDiskSettings; /* 03h */
2158 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2159 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2160
2161 typedef struct _RAID_PHYS_DISK0_STATUS
2162 {
2163 U8 Flags; /* 00h */
2164 U8 State; /* 01h */
2165 U16 Reserved; /* 02h */
2166 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2167 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2168
2169 /* RAID Volume 2 IM Physical Disk DiskStatus flags */
2170
2171 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2172 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2173 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2174 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2175 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
2176
2177 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2178 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2179 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2180 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2181 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2182 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2183 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2184 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2185
2186 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2187 {
2188 CONFIG_PAGE_HEADER Header; /* 00h */
2189 U8 PhysDiskID; /* 04h */
2190 U8 PhysDiskBus; /* 05h */
2191 U8 PhysDiskIOC; /* 06h */
2192 U8 PhysDiskNum; /* 07h */
2193 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2194 U32 Reserved1; /* 0Ch */
2195 U8 ExtDiskIdentifier[8]; /* 10h */
2196 U8 DiskIdentifier[16]; /* 18h */
2197 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2198 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2199 U32 MaxLBA; /* 68h */
2200 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2201 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2202 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2203
2204 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
2205
2206
2207 typedef struct _RAID_PHYS_DISK1_PATH
2208 {
2209 U8 PhysDiskID; /* 00h */
2210 U8 PhysDiskBus; /* 01h */
2211 U16 Reserved1; /* 02h */
2212 U64 WWID; /* 04h */
2213 U64 OwnerWWID; /* 0Ch */
2214 U8 OwnerIdentifier; /* 14h */
2215 U8 Reserved2; /* 15h */
2216 U16 Flags; /* 16h */
2217 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2218 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2219
2220 /* RAID Physical Disk Page 1 Flags field defines */
2221 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2222 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2223
2224 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2225 {
2226 CONFIG_PAGE_HEADER Header; /* 00h */
2227 U8 NumPhysDiskPaths; /* 04h */
2228 U8 PhysDiskNum; /* 05h */
2229 U16 Reserved2; /* 06h */
2230 U32 Reserved1; /* 08h */
2231 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */
2232 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2233 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2234
2235 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2236
2237
2238 /****************************************************************************
2239 * LAN Config Pages
2240 ****************************************************************************/
2241
2242 typedef struct _CONFIG_PAGE_LAN_0
2243 {
2244 ConfigPageHeader_t Header; /* 00h */
2245 U16 TxRxModes; /* 04h */
2246 U16 Reserved; /* 06h */
2247 U32 PacketPrePad; /* 08h */
2248 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2249 LANPage0_t, MPI_POINTER pLANPage0_t;
2250
2251 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2252
2253 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2254 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2255 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2256
2257 typedef struct _CONFIG_PAGE_LAN_1
2258 {
2259 ConfigPageHeader_t Header; /* 00h */
2260 U16 Reserved; /* 04h */
2261 U8 CurrentDeviceState; /* 06h */
2262 U8 Reserved1; /* 07h */
2263 U32 MinPacketSize; /* 08h */
2264 U32 MaxPacketSize; /* 0Ch */
2265 U32 HardwareAddressLow; /* 10h */
2266 U32 HardwareAddressHigh; /* 14h */
2267 U32 MaxWireSpeedLow; /* 18h */
2268 U32 MaxWireSpeedHigh; /* 1Ch */
2269 U32 BucketsRemaining; /* 20h */
2270 U32 MaxReplySize; /* 24h */
2271 U32 NegWireSpeedLow; /* 28h */
2272 U32 NegWireSpeedHigh; /* 2Ch */
2273 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2274 LANPage1_t, MPI_POINTER pLANPage1_t;
2275
2276 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2277
2278 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2279 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2280
2281
2282 /****************************************************************************
2283 * Inband Config Pages
2284 ****************************************************************************/
2285
2286 typedef struct _CONFIG_PAGE_INBAND_0
2287 {
2288 CONFIG_PAGE_HEADER Header; /* 00h */
2289 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2290 U16 MaximumBuffers; /* 08h */
2291 U16 Reserved1; /* 0Ah */
2292 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2293 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2294
2295 #define MPI_INBAND_PAGEVERSION (0x00)
2296
2297
2298
2299 /****************************************************************************
2300 * SAS IO Unit Config Pages
2301 ****************************************************************************/
2302
2303 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2304 {
2305 U8 Port; /* 00h */
2306 U8 PortFlags; /* 01h */
2307 U8 PhyFlags; /* 02h */
2308 U8 NegotiatedLinkRate; /* 03h */
2309 U32 ControllerPhyDeviceInfo;/* 04h */
2310 U16 AttachedDeviceHandle; /* 08h */
2311 U16 ControllerDevHandle; /* 0Ah */
2312 U32 DiscoveryStatus; /* 0Ch */
2313 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2314 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2315
2316 /*
2317 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2318 * one and check Header.PageLength at runtime.
2319 */
2320 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2321 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
2322 #endif
2323
2324 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2325 {
2326 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2327 U32 Reserved1; /* 08h */
2328 U8 NumPhys; /* 0Ch */
2329 U8 Reserved2; /* 0Dh */
2330 U16 Reserved3; /* 0Eh */
2331 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2332 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2333 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2334
2335 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x03)
2336
2337 /* values for SAS IO Unit Page 0 PortFlags */
2338 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2339 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2340 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2341 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2342
2343 /* values for SAS IO Unit Page 0 PhyFlags */
2344 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2345 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2346 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2347
2348 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2349 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2350 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2351 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2352 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2353 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2354 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2355
2356 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2357
2358 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2359 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2360 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2361 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2362 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2363 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2364 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2365 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2366 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2367 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2368 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2369 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2370 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2371 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
2372
2373
2374 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2375 {
2376 U8 Port; /* 00h */
2377 U8 PortFlags; /* 01h */
2378 U8 PhyFlags; /* 02h */
2379 U8 MaxMinLinkRate; /* 03h */
2380 U32 ControllerPhyDeviceInfo;/* 04h */
2381 U32 Reserved1; /* 08h */
2382 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2383 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2384
2385 /*
2386 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2387 * one and check Header.PageLength at runtime.
2388 */
2389 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2390 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
2391 #endif
2392
2393 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2394 {
2395 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2396 U16 ControlFlags; /* 08h */
2397 U16 MaxNumSATATargets; /* 0Ah */
2398 U32 Reserved1; /* 0Ch */
2399 U8 NumPhys; /* 10h */
2400 U8 SATAMaxQDepth; /* 11h */
2401 U16 Reserved2; /* 12h */
2402 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2403 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2404 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2405
2406 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x05)
2407
2408 /* values for SAS IO Unit Page 1 ControlFlags */
2409 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2410 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2411 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2412 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2413 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2414
2415 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2416 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2417 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2418 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2419 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
2420
2421 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100)
2422 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2423 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2424 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2425 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2426 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2427 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2428 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2429 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2430
2431 /* values for SAS IO Unit Page 1 PortFlags */
2432 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2433 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2434 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2435
2436 /* values for SAS IO Unit Page 0 PhyFlags */
2437 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2438 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2439 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2440
2441 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2442 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2443 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2444 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2445 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2446 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2447 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2448
2449 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2450
2451
2452 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2453 {
2454 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2455 U8 NumDevsPerEnclosure; /* 08h */
2456 U8 Reserved1; /* 09h */
2457 U16 Reserved2; /* 0Ah */
2458 U16 MaxPersistentIDs; /* 0Ch */
2459 U16 NumPersistentIDsUsed; /* 0Eh */
2460 U8 Status; /* 10h */
2461 U8 Flags; /* 11h */
2462 U16 MaxNumPhysicalMappedIDs;/* 12h */
2463 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2464 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2465
2466 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x05)
2467
2468 /* values for SAS IO Unit Page 2 Status field */
2469 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2470 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2471
2472 /* values for SAS IO Unit Page 2 Flags field */
2473 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2474 /* Physical Mapping Modes */
2475 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2476 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2477 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2478 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2479 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2480 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)
2481
2482 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2483 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
2484
2485
2486 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2487 {
2488 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2489 U32 Reserved1; /* 08h */
2490 U32 MaxInvalidDwordCount; /* 0Ch */
2491 U32 InvalidDwordCountTime; /* 10h */
2492 U32 MaxRunningDisparityErrorCount; /* 14h */
2493 U32 RunningDisparityErrorTime; /* 18h */
2494 U32 MaxLossDwordSynchCount; /* 1Ch */
2495 U32 LossDwordSynchCountTime; /* 20h */
2496 U32 MaxPhyResetProblemCount; /* 24h */
2497 U32 PhyResetProblemTime; /* 28h */
2498 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2499 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2500
2501 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2502
2503
2504 /****************************************************************************
2505 * SAS Expander Config Pages
2506 ****************************************************************************/
2507
2508 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2509 {
2510 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2511 U8 PhysicalPort; /* 08h */
2512 U8 Reserved1; /* 09h */
2513 U16 EnclosureHandle; /* 0Ah */
2514 U64 SASAddress; /* 0Ch */
2515 U32 DiscoveryStatus; /* 14h */
2516 U16 DevHandle; /* 18h */
2517 U16 ParentDevHandle; /* 1Ah */
2518 U16 ExpanderChangeCount; /* 1Ch */
2519 U16 ExpanderRouteIndexes; /* 1Eh */
2520 U8 NumPhys; /* 20h */
2521 U8 SASLevel; /* 21h */
2522 U8 Flags; /* 22h */
2523 U8 Reserved3; /* 23h */
2524 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2525 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2526
2527 #define MPI_SASEXPANDER0_PAGEVERSION (0x03)
2528
2529 /* values for SAS Expander Page 0 DiscoveryStatus field */
2530 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2531 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2532 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2533 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2534 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2535 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2536 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2537 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2538 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2539 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2540 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2541 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2542
2543 /* values for SAS Expander Page 0 Flags field */
2544 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2545 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2546
2547
2548 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2549 {
2550 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2551 U8 PhysicalPort; /* 08h */
2552 U8 Reserved1; /* 09h */
2553 U16 Reserved2; /* 0Ah */
2554 U8 NumPhys; /* 0Ch */
2555 U8 Phy; /* 0Dh */
2556 U16 NumTableEntriesProgrammed; /* 0Eh */
2557 U8 ProgrammedLinkRate; /* 10h */
2558 U8 HwLinkRate; /* 11h */
2559 U16 AttachedDevHandle; /* 12h */
2560 U32 PhyInfo; /* 14h */
2561 U32 AttachedDeviceInfo; /* 18h */
2562 U16 OwnerDevHandle; /* 1Ch */
2563 U8 ChangeCount; /* 1Eh */
2564 U8 NegotiatedLinkRate; /* 1Fh */
2565 U8 PhyIdentifier; /* 20h */
2566 U8 AttachedPhyIdentifier; /* 21h */
2567 U8 Reserved3; /* 22h */
2568 U8 DiscoveryInfo; /* 23h */
2569 U32 Reserved4; /* 24h */
2570 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2571 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2572
2573 #define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2574
2575 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2576
2577 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2578
2579 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2580
2581 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2582
2583 /* values for SAS Expander Page 1 DiscoveryInfo field */
2584 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04)
2585 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2586 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2587
2588 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2589 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2590 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2591 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2592 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2593 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2594 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2595
2596
2597 /****************************************************************************
2598 * SAS Device Config Pages
2599 ****************************************************************************/
2600
2601 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2602 {
2603 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2604 U16 Slot; /* 08h */
2605 U16 EnclosureHandle; /* 0Ah */
2606 U64 SASAddress; /* 0Ch */
2607 U16 ParentDevHandle; /* 14h */
2608 U8 PhyNum; /* 16h */
2609 U8 AccessStatus; /* 17h */
2610 U16 DevHandle; /* 18h */
2611 U8 TargetID; /* 1Ah */
2612 U8 Bus; /* 1Bh */
2613 U32 DeviceInfo; /* 1Ch */
2614 U16 Flags; /* 20h */
2615 U8 PhysicalPort; /* 22h */
2616 U8 Reserved2; /* 23h */
2617 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2618 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2619
2620 #define MPI_SASDEVICE0_PAGEVERSION (0x04)
2621
2622 /* values for SAS Device Page 0 AccessStatus field */
2623 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2624 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2625 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2626
2627 /* values for SAS Device Page 0 Flags field */
2628 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2629 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2630 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2631 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2632 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2633 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2634 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2635 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2636 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2637 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2638
2639 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2640
2641
2642 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2643 {
2644 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2645 U32 Reserved1; /* 08h */
2646 U64 SASAddress; /* 0Ch */
2647 U32 Reserved2; /* 14h */
2648 U16 DevHandle; /* 18h */
2649 U8 TargetID; /* 1Ah */
2650 U8 Bus; /* 1Bh */
2651 U8 InitialRegDeviceFIS[20];/* 1Ch */
2652 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2653 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2654
2655 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2656
2657
2658 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2659 {
2660 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2661 U64 PhysicalIdentifier; /* 08h */
2662 U32 EnclosureMapping; /* 10h */
2663 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2664 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2665
2666 #define MPI_SASDEVICE2_PAGEVERSION (0x01)
2667
2668 /* defines for SAS Device Page 2 EnclosureMapping field */
2669 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2670 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2671 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2672 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2673 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2674 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
2675
2676
2677 /****************************************************************************
2678 * SAS PHY Config Pages
2679 ****************************************************************************/
2680
2681 typedef struct _CONFIG_PAGE_SAS_PHY_0
2682 {
2683 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2684 U16 OwnerDevHandle; /* 08h */
2685 U16 Reserved1; /* 0Ah */
2686 U64 SASAddress; /* 0Ch */
2687 U16 AttachedDevHandle; /* 14h */
2688 U8 AttachedPhyIdentifier; /* 16h */
2689 U8 Reserved2; /* 17h */
2690 U32 AttachedDeviceInfo; /* 18h */
2691 U8 ProgrammedLinkRate; /* 20h */
2692 U8 HwLinkRate; /* 21h */
2693 U8 ChangeCount; /* 22h */
2694 U8 Flags; /* 23h */
2695 U32 PhyInfo; /* 24h */
2696 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2697 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2698
2699 #define MPI_SASPHY0_PAGEVERSION (0x01)
2700
2701 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2702 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2703 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2704 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2705 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2706 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2707 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2708 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2709 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2710
2711 /* values for SAS PHY Page 0 HwLinkRate field */
2712 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2713 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2714 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2715 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2716 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2717 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2718
2719 /* values for SAS PHY Page 0 Flags field */
2720 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2721
2722 /* values for SAS PHY Page 0 PhyInfo field */
2723 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2724 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2725 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2726
2727 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2728 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2729
2730 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2731 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2732 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2733 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2734
2735 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2736 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2737 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2738 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
2739 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
2740 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
2741 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
2742
2743
2744 typedef struct _CONFIG_PAGE_SAS_PHY_1
2745 {
2746 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2747 U32 Reserved1; /* 08h */
2748 U32 InvalidDwordCount; /* 0Ch */
2749 U32 RunningDisparityErrorCount; /* 10h */
2750 U32 LossDwordSynchCount; /* 14h */
2751 U32 PhyResetProblemCount; /* 18h */
2752 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2753 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2754
2755 #define MPI_SASPHY1_PAGEVERSION (0x00)
2756
2757
2758 /****************************************************************************
2759 * SAS Enclosure Config Pages
2760 ****************************************************************************/
2761
2762 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2763 {
2764 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2765 U32 Reserved1; /* 08h */
2766 U64 EnclosureLogicalID; /* 0Ch */
2767 U16 Flags; /* 14h */
2768 U16 EnclosureHandle; /* 16h */
2769 U16 NumSlots; /* 18h */
2770 U16 StartSlot; /* 1Ah */
2771 U8 StartTargetID; /* 1Ch */
2772 U8 StartBus; /* 1Dh */
2773 U8 SEPTargetID; /* 1Eh */
2774 U8 SEPBus; /* 1Fh */
2775 U32 Reserved2; /* 20h */
2776 U32 Reserved3; /* 24h */
2777 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
2778 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
2779
2780 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
2781
2782 /* values for SAS Enclosure Page 0 Flags field */
2783 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
2784 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
2785
2786 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2787 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2788 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2789 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2790 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2791 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2792 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2793
2794
2795 /****************************************************************************
2796 * Log Config Pages
2797 ****************************************************************************/
2798 /*
2799 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2800 * one and check NumLogEntries at runtime.
2801 */
2802 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
2803 #define MPI_LOG_0_NUM_LOG_ENTRIES (1)
2804 #endif
2805
2806 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C)
2807
2808 typedef struct _MPI_LOG_0_ENTRY
2809 {
2810 U32 TimeStamp; /* 00h */
2811 U32 Reserved1; /* 04h */
2812 U16 LogSequence; /* 08h */
2813 U16 LogEntryQualifier; /* 0Ah */
2814 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */
2815 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
2816 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
2817
2818 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2819 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2820 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2821
2822 typedef struct _CONFIG_PAGE_LOG_0
2823 {
2824 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2825 U32 Reserved1; /* 08h */
2826 U32 Reserved2; /* 0Ch */
2827 U16 NumLogEntries; /* 10h */
2828 U16 Reserved3; /* 12h */
2829 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
2830 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
2831 LogPage0_t, MPI_POINTER pLogPage0_t;
2832
2833 #define MPI_LOG_0_PAGEVERSION (0x01)
2834
2835
2836 #endif
2837
Linux kernel - Deliverables
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