1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/module.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/mfd/rtsx_pci.h>
30 static u8
rtl8411_get_ic_version(struct rtsx_pcr
*pcr
)
34 rtsx_pci_read_register(pcr
, SYS_VER
, &val
);
38 static int rtl8411b_is_qfn48(struct rtsx_pcr
*pcr
)
42 rtsx_pci_read_register(pcr
, RTL8411B_PACKAGE_MODE
, &val
);
50 static void rtl8411_fetch_vendor_settings(struct rtsx_pcr
*pcr
)
55 rtsx_pci_read_config_dword(pcr
, PCR_SETTING_REG1
, ®1
);
56 dev_dbg(&(pcr
->pci
->dev
), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1
, reg1
);
58 if (!rtsx_vendor_setting_valid(reg1
))
61 pcr
->aspm_en
= rtsx_reg_to_aspm(reg1
);
62 pcr
->sd30_drive_sel_1v8
=
63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1
));
64 pcr
->card_drive_sel
&= 0x3F;
65 pcr
->card_drive_sel
|= rtsx_reg_to_card_drive_sel(reg1
);
67 rtsx_pci_read_config_byte(pcr
, PCR_SETTING_REG3
, ®3
);
68 dev_dbg(&(pcr
->pci
->dev
), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3
, reg3
);
69 pcr
->sd30_drive_sel_3v3
= rtl8411_reg_to_sd30_drive_sel_3v3(reg3
);
72 static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr
*pcr
)
76 rtsx_pci_read_config_dword(pcr
, PCR_SETTING_REG1
, ®
);
77 dev_dbg(&(pcr
->pci
->dev
), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1
, reg
);
79 if (!rtsx_vendor_setting_valid(reg
))
82 pcr
->aspm_en
= rtsx_reg_to_aspm(reg
);
83 pcr
->sd30_drive_sel_1v8
=
84 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg
));
85 pcr
->sd30_drive_sel_3v3
=
86 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg
));
89 static int rtl8411_extra_init_hw(struct rtsx_pcr
*pcr
)
91 rtsx_pci_init_cmd(pcr
);
93 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
94 0xFF, pcr
->sd30_drive_sel_3v3
);
95 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CD_PAD_CTL
,
96 CD_DISABLE_MASK
| CD_AUTO_DISABLE
, CD_ENABLE
);
98 return rtsx_pci_send_cmd(pcr
, 100);
101 static int rtl8411b_extra_init_hw(struct rtsx_pcr
*pcr
)
103 rtsx_pci_init_cmd(pcr
);
105 if (rtl8411b_is_qfn48(pcr
))
106 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
107 CARD_PULL_CTL3
, 0xFF, 0xF5);
108 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
109 0xFF, pcr
->sd30_drive_sel_3v3
);
110 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CD_PAD_CTL
,
111 CD_DISABLE_MASK
| CD_AUTO_DISABLE
, CD_ENABLE
);
113 return rtsx_pci_send_cmd(pcr
, 100);
116 static int rtl8411_turn_on_led(struct rtsx_pcr
*pcr
)
118 return rtsx_pci_write_register(pcr
, CARD_GPIO
, 0x01, 0x00);
121 static int rtl8411_turn_off_led(struct rtsx_pcr
*pcr
)
123 return rtsx_pci_write_register(pcr
, CARD_GPIO
, 0x01, 0x01);
126 static int rtl8411_enable_auto_blink(struct rtsx_pcr
*pcr
)
128 return rtsx_pci_write_register(pcr
, CARD_AUTO_BLINK
, 0xFF, 0x0D);
131 static int rtl8411_disable_auto_blink(struct rtsx_pcr
*pcr
)
133 return rtsx_pci_write_register(pcr
, CARD_AUTO_BLINK
, 0x08, 0x00);
136 static int rtl8411_card_power_on(struct rtsx_pcr
*pcr
, int card
)
140 rtsx_pci_init_cmd(pcr
);
141 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_PWR_CTL
,
142 BPP_POWER_MASK
, BPP_POWER_5_PERCENT_ON
);
143 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, LDO_CTL
,
144 BPP_LDO_POWB
, BPP_LDO_SUSPEND
);
145 err
= rtsx_pci_send_cmd(pcr
, 100);
149 /* To avoid too large in-rush current */
152 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
153 BPP_POWER_MASK
, BPP_POWER_10_PERCENT_ON
);
159 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
160 BPP_POWER_MASK
, BPP_POWER_15_PERCENT_ON
);
166 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
167 BPP_POWER_MASK
, BPP_POWER_ON
);
171 return rtsx_pci_write_register(pcr
, LDO_CTL
, BPP_LDO_POWB
, BPP_LDO_ON
);
174 static int rtl8411_card_power_off(struct rtsx_pcr
*pcr
, int card
)
178 err
= rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
179 BPP_POWER_MASK
, BPP_POWER_OFF
);
183 return rtsx_pci_write_register(pcr
, LDO_CTL
,
184 BPP_LDO_POWB
, BPP_LDO_SUSPEND
);
187 static int rtl8411_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
192 mask
= (BPP_REG_TUNED18
<< BPP_TUNED18_SHIFT_8411
) | BPP_PAD_MASK
;
193 if (voltage
== OUTPUT_3V3
) {
194 err
= rtsx_pci_write_register(pcr
,
195 SD30_DRIVE_SEL
, 0x07, pcr
->sd30_drive_sel_3v3
);
198 val
= (BPP_ASIC_3V3
<< BPP_TUNED18_SHIFT_8411
) | BPP_PAD_3V3
;
199 } else if (voltage
== OUTPUT_1V8
) {
200 err
= rtsx_pci_write_register(pcr
,
201 SD30_DRIVE_SEL
, 0x07, pcr
->sd30_drive_sel_1v8
);
204 val
= (BPP_ASIC_1V8
<< BPP_TUNED18_SHIFT_8411
) | BPP_PAD_1V8
;
209 return rtsx_pci_write_register(pcr
, LDO_CTL
, mask
, val
);
212 static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr
*pcr
)
214 unsigned int card_exist
;
216 card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
217 card_exist
&= CARD_EXIST
;
220 rtsx_pci_write_register(pcr
, CD_PAD_CTL
,
221 CD_DISABLE_MASK
, CD_ENABLE
);
222 /* Enable card interrupt */
223 rtsx_pci_write_register(pcr
, EFUSE_CONTENT
, 0xe0, 0x00);
227 if (hweight32(card_exist
) > 1) {
228 rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
229 BPP_POWER_MASK
, BPP_POWER_5_PERCENT_ON
);
232 card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
233 if (card_exist
& MS_EXIST
)
234 card_exist
= MS_EXIST
;
235 else if (card_exist
& SD_EXIST
)
236 card_exist
= SD_EXIST
;
240 rtsx_pci_write_register(pcr
, CARD_PWR_CTL
,
241 BPP_POWER_MASK
, BPP_POWER_OFF
);
243 dev_dbg(&(pcr
->pci
->dev
),
244 "After CD deglitch, card_exist = 0x%x\n",
248 if (card_exist
& MS_EXIST
) {
249 /* Disable SD interrupt */
250 rtsx_pci_write_register(pcr
, EFUSE_CONTENT
, 0xe0, 0x40);
251 rtsx_pci_write_register(pcr
, CD_PAD_CTL
,
252 CD_DISABLE_MASK
, MS_CD_EN_ONLY
);
253 } else if (card_exist
& SD_EXIST
) {
254 /* Disable MS interrupt */
255 rtsx_pci_write_register(pcr
, EFUSE_CONTENT
, 0xe0, 0x80);
256 rtsx_pci_write_register(pcr
, CD_PAD_CTL
,
257 CD_DISABLE_MASK
, SD_CD_EN_ONLY
);
263 static int rtl8411_conv_clk_and_div_n(int input
, int dir
)
267 if (dir
== CLK_TO_DIV_N
)
268 output
= input
* 4 / 5 - 2;
270 output
= (input
+ 2) * 5 / 4;
275 static const struct pcr_ops rtl8411_pcr_ops
= {
276 .fetch_vendor_settings
= rtl8411_fetch_vendor_settings
,
277 .extra_init_hw
= rtl8411_extra_init_hw
,
278 .optimize_phy
= NULL
,
279 .turn_on_led
= rtl8411_turn_on_led
,
280 .turn_off_led
= rtl8411_turn_off_led
,
281 .enable_auto_blink
= rtl8411_enable_auto_blink
,
282 .disable_auto_blink
= rtl8411_disable_auto_blink
,
283 .card_power_on
= rtl8411_card_power_on
,
284 .card_power_off
= rtl8411_card_power_off
,
285 .switch_output_voltage
= rtl8411_switch_output_voltage
,
286 .cd_deglitch
= rtl8411_cd_deglitch
,
287 .conv_clk_and_div_n
= rtl8411_conv_clk_and_div_n
,
290 static const struct pcr_ops rtl8411b_pcr_ops
= {
291 .fetch_vendor_settings
= rtl8411b_fetch_vendor_settings
,
292 .extra_init_hw
= rtl8411b_extra_init_hw
,
293 .optimize_phy
= NULL
,
294 .turn_on_led
= rtl8411_turn_on_led
,
295 .turn_off_led
= rtl8411_turn_off_led
,
296 .enable_auto_blink
= rtl8411_enable_auto_blink
,
297 .disable_auto_blink
= rtl8411_disable_auto_blink
,
298 .card_power_on
= rtl8411_card_power_on
,
299 .card_power_off
= rtl8411_card_power_off
,
300 .switch_output_voltage
= rtl8411_switch_output_voltage
,
301 .cd_deglitch
= rtl8411_cd_deglitch
,
302 .conv_clk_and_div_n
= rtl8411_conv_clk_and_div_n
,
305 /* SD Pull Control Enable:
306 * SD_DAT[3:0] ==> pull up
310 * SD_CLK ==> pull down
312 static const u32 rtl8411_sd_pull_ctl_enable_tbl
[] = {
313 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0xAA),
314 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0xAA),
315 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0xA9),
316 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09),
317 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x09),
318 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
322 /* SD Pull Control Disable:
323 * SD_DAT[3:0] ==> pull down
325 * SD_WP ==> pull down
326 * SD_CMD ==> pull down
327 * SD_CLK ==> pull down
329 static const u32 rtl8411_sd_pull_ctl_disable_tbl
[] = {
330 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
331 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
332 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x95),
333 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09),
334 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05),
335 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
339 /* MS Pull Control Enable:
341 * others ==> pull down
343 static const u32 rtl8411_ms_pull_ctl_enable_tbl
[] = {
344 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
345 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
346 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x95),
347 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x05),
348 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05),
349 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
353 /* MS Pull Control Disable:
355 * others ==> pull down
357 static const u32 rtl8411_ms_pull_ctl_disable_tbl
[] = {
358 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
359 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
360 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x95),
361 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09),
362 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05),
363 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04),
367 static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl
[] = {
368 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0xAA),
369 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0xAA),
370 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x09 | 0xD0),
371 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09 | 0x50),
372 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
373 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
377 static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl
[] = {
378 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0xAA),
379 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x69 | 0x90),
380 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x08 | 0x11),
384 static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl
[] = {
385 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
386 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
387 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x05 | 0xD0),
388 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09 | 0x50),
389 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
390 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
394 static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl
[] = {
395 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
396 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x65 | 0x90),
397 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
401 static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl
[] = {
402 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
403 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
404 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x05 | 0xD0),
405 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x05 | 0x50),
406 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
407 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
411 static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl
[] = {
412 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
413 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x65 | 0x90),
414 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
418 static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl
[] = {
419 RTSX_REG_PAIR(CARD_PULL_CTL1
, 0x65),
420 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
421 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x05 | 0xD0),
422 RTSX_REG_PAIR(CARD_PULL_CTL4
, 0x09 | 0x50),
423 RTSX_REG_PAIR(CARD_PULL_CTL5
, 0x05 | 0x50),
424 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
428 static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl
[] = {
429 RTSX_REG_PAIR(CARD_PULL_CTL2
, 0x55),
430 RTSX_REG_PAIR(CARD_PULL_CTL3
, 0x65 | 0x90),
431 RTSX_REG_PAIR(CARD_PULL_CTL6
, 0x04 | 0x11),
435 void rtl8411_init_params(struct rtsx_pcr
*pcr
)
437 pcr
->extra_caps
= EXTRA_CAPS_SD_SDR50
| EXTRA_CAPS_SD_SDR104
;
439 pcr
->ops
= &rtl8411_pcr_ops
;
442 pcr
->card_drive_sel
= RTL8411_CARD_DRIVE_DEFAULT
;
443 pcr
->sd30_drive_sel_1v8
= DRIVER_TYPE_B
;
444 pcr
->sd30_drive_sel_3v3
= DRIVER_TYPE_D
;
445 pcr
->aspm_en
= ASPM_L1_EN
;
447 pcr
->ic_version
= rtl8411_get_ic_version(pcr
);
448 pcr
->sd_pull_ctl_enable_tbl
= rtl8411_sd_pull_ctl_enable_tbl
;
449 pcr
->sd_pull_ctl_disable_tbl
= rtl8411_sd_pull_ctl_disable_tbl
;
450 pcr
->ms_pull_ctl_enable_tbl
= rtl8411_ms_pull_ctl_enable_tbl
;
451 pcr
->ms_pull_ctl_disable_tbl
= rtl8411_ms_pull_ctl_disable_tbl
;
454 void rtl8411b_init_params(struct rtsx_pcr
*pcr
)
456 pcr
->extra_caps
= EXTRA_CAPS_SD_SDR50
| EXTRA_CAPS_SD_SDR104
;
458 pcr
->ops
= &rtl8411b_pcr_ops
;
461 pcr
->card_drive_sel
= RTL8411_CARD_DRIVE_DEFAULT
;
462 pcr
->sd30_drive_sel_1v8
= DRIVER_TYPE_B
;
463 pcr
->sd30_drive_sel_3v3
= DRIVER_TYPE_D
;
464 pcr
->aspm_en
= ASPM_L1_EN
;
466 pcr
->ic_version
= rtl8411_get_ic_version(pcr
);
468 if (rtl8411b_is_qfn48(pcr
)) {
469 pcr
->sd_pull_ctl_enable_tbl
=
470 rtl8411b_qfn48_sd_pull_ctl_enable_tbl
;
471 pcr
->sd_pull_ctl_disable_tbl
=
472 rtl8411b_qfn48_sd_pull_ctl_disable_tbl
;
473 pcr
->ms_pull_ctl_enable_tbl
=
474 rtl8411b_qfn48_ms_pull_ctl_enable_tbl
;
475 pcr
->ms_pull_ctl_disable_tbl
=
476 rtl8411b_qfn48_ms_pull_ctl_disable_tbl
;
478 pcr
->sd_pull_ctl_enable_tbl
=
479 rtl8411b_qfn64_sd_pull_ctl_enable_tbl
;
480 pcr
->sd_pull_ctl_disable_tbl
=
481 rtl8411b_qfn64_sd_pull_ctl_disable_tbl
;
482 pcr
->ms_pull_ctl_enable_tbl
=
483 rtl8411b_qfn64_ms_pull_ctl_enable_tbl
;
484 pcr
->ms_pull_ctl_disable_tbl
=
485 rtl8411b_qfn64_ms_pull_ctl_disable_tbl
;