1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/pci.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/highmem.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/idr.h>
31 #include <linux/platform_device.h>
32 #include <linux/mfd/core.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
38 static bool msi_en
= true;
39 module_param(msi_en
, bool, S_IRUGO
| S_IWUSR
);
40 MODULE_PARM_DESC(msi_en
, "Enable MSI");
42 static DEFINE_IDR(rtsx_pci_idr
);
43 static DEFINE_SPINLOCK(rtsx_pci_lock
);
45 static struct mfd_cell rtsx_pcr_cells
[] = {
47 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
50 .name
= DRV_NAME_RTSX_PCI_MS
,
54 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids
) = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
62 MODULE_DEVICE_TABLE(pci
, rtsx_pci_ids
);
64 void rtsx_pci_start_run(struct rtsx_pcr
*pcr
)
66 /* If pci device removed, don't queue idle work any more */
70 if (pcr
->state
!= PDEV_STAT_RUN
) {
71 pcr
->state
= PDEV_STAT_RUN
;
72 if (pcr
->ops
->enable_auto_blink
)
73 pcr
->ops
->enable_auto_blink(pcr
);
76 mod_delayed_work(system_wq
, &pcr
->idle_work
, msecs_to_jiffies(200));
78 EXPORT_SYMBOL_GPL(rtsx_pci_start_run
);
80 int rtsx_pci_write_register(struct rtsx_pcr
*pcr
, u16 addr
, u8 mask
, u8 data
)
83 u32 val
= HAIMR_WRITE_START
;
85 val
|= (u32
)(addr
& 0x3FFF) << 16;
86 val
|= (u32
)mask
<< 8;
89 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
91 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
92 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
93 if ((val
& HAIMR_TRANS_END
) == 0) {
102 EXPORT_SYMBOL_GPL(rtsx_pci_write_register
);
104 int rtsx_pci_read_register(struct rtsx_pcr
*pcr
, u16 addr
, u8
*data
)
106 u32 val
= HAIMR_READ_START
;
109 val
|= (u32
)(addr
& 0x3FFF) << 16;
110 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
112 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
113 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
114 if ((val
& HAIMR_TRANS_END
) == 0)
118 if (i
>= MAX_RW_REG_CNT
)
122 *data
= (u8
)(val
& 0xFF);
126 EXPORT_SYMBOL_GPL(rtsx_pci_read_register
);
128 int rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
130 int err
, i
, finished
= 0;
133 rtsx_pci_init_cmd(pcr
);
135 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA0
, 0xFF, (u8
)val
);
136 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA1
, 0xFF, (u8
)(val
>> 8));
137 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
138 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x81);
140 err
= rtsx_pci_send_cmd(pcr
, 100);
144 for (i
= 0; i
< 100000; i
++) {
145 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
160 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register
);
162 int rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
164 int err
, i
, finished
= 0;
168 rtsx_pci_init_cmd(pcr
);
170 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
171 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x80);
173 err
= rtsx_pci_send_cmd(pcr
, 100);
177 for (i
= 0; i
< 100000; i
++) {
178 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
191 rtsx_pci_init_cmd(pcr
);
193 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA0
, 0, 0);
194 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA1
, 0, 0);
196 err
= rtsx_pci_send_cmd(pcr
, 100);
200 ptr
= rtsx_pci_get_cmd_data(pcr
);
201 data
= ((u16
)ptr
[1] << 8) | ptr
[0];
208 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register
);
210 void rtsx_pci_stop_cmd(struct rtsx_pcr
*pcr
)
212 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, STOP_CMD
);
213 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, STOP_DMA
);
215 rtsx_pci_write_register(pcr
, DMACTL
, 0x80, 0x80);
216 rtsx_pci_write_register(pcr
, RBCTL
, 0x80, 0x80);
218 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd
);
220 void rtsx_pci_add_cmd(struct rtsx_pcr
*pcr
,
221 u8 cmd_type
, u16 reg_addr
, u8 mask
, u8 data
)
225 u32
*ptr
= (u32
*)(pcr
->host_cmds_ptr
);
227 val
|= (u32
)(cmd_type
& 0x03) << 30;
228 val
|= (u32
)(reg_addr
& 0x3FFF) << 16;
229 val
|= (u32
)mask
<< 8;
232 spin_lock_irqsave(&pcr
->lock
, flags
);
234 if (pcr
->ci
< (HOST_CMDS_BUF_LEN
/ 4)) {
235 put_unaligned_le32(val
, ptr
);
239 spin_unlock_irqrestore(&pcr
->lock
, flags
);
241 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd
);
243 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr
*pcr
)
247 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
249 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
250 /* Hardware Auto Response */
252 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
254 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait
);
256 int rtsx_pci_send_cmd(struct rtsx_pcr
*pcr
, int timeout
)
258 struct completion trans_done
;
264 spin_lock_irqsave(&pcr
->lock
, flags
);
266 /* set up data structures for the wakeup system */
267 pcr
->done
= &trans_done
;
268 pcr
->trans_result
= TRANS_NOT_READY
;
269 init_completion(&trans_done
);
271 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
273 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
274 /* Hardware Auto Response */
276 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
278 spin_unlock_irqrestore(&pcr
->lock
, flags
);
280 /* Wait for TRANS_OK_INT */
281 timeleft
= wait_for_completion_interruptible_timeout(
282 &trans_done
, msecs_to_jiffies(timeout
));
284 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
287 goto finish_send_cmd
;
290 spin_lock_irqsave(&pcr
->lock
, flags
);
291 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
293 else if (pcr
->trans_result
== TRANS_RESULT_OK
)
295 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
297 spin_unlock_irqrestore(&pcr
->lock
, flags
);
300 spin_lock_irqsave(&pcr
->lock
, flags
);
302 spin_unlock_irqrestore(&pcr
->lock
, flags
);
304 if ((err
< 0) && (err
!= -ENODEV
))
305 rtsx_pci_stop_cmd(pcr
);
308 complete(pcr
->finish_me
);
312 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd
);
314 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr
*pcr
,
315 dma_addr_t addr
, unsigned int len
, int end
)
317 u64
*ptr
= (u64
*)(pcr
->host_sg_tbl_ptr
) + pcr
->sgi
;
319 u8 option
= SG_VALID
| SG_TRANS_DATA
;
321 dev_dbg(&(pcr
->pci
->dev
), "DMA addr: 0x%x, Len: 0x%x\n",
322 (unsigned int)addr
, len
);
326 val
= ((u64
)addr
<< 32) | ((u64
)len
<< 12) | option
;
328 put_unaligned_le64(val
, ptr
);
332 int rtsx_pci_transfer_data(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
333 int num_sg
, bool read
, int timeout
)
335 struct completion trans_done
;
337 int err
= 0, i
, count
;
340 struct scatterlist
*sg
;
341 enum dma_data_direction dma_dir
;
346 dev_dbg(&(pcr
->pci
->dev
), "--> %s: num_sg = %d\n", __func__
, num_sg
);
348 /* don't transfer data during abort processing */
352 if ((sglist
== NULL
) || (num_sg
<= 0))
356 dir
= DEVICE_TO_HOST
;
357 dma_dir
= DMA_FROM_DEVICE
;
359 dir
= HOST_TO_DEVICE
;
360 dma_dir
= DMA_TO_DEVICE
;
363 count
= dma_map_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dma_dir
);
365 dev_err(&(pcr
->pci
->dev
), "scatterlist map failed\n");
368 dev_dbg(&(pcr
->pci
->dev
), "DMA mapping count: %d\n", count
);
370 val
= ((u32
)(dir
& 0x01) << 29) | TRIG_DMA
| ADMA_MODE
;
372 for_each_sg(sglist
, sg
, count
, i
) {
373 addr
= sg_dma_address(sg
);
374 len
= sg_dma_len(sg
);
375 rtsx_pci_add_sg_tbl(pcr
, addr
, len
, i
== count
- 1);
378 spin_lock_irqsave(&pcr
->lock
, flags
);
380 pcr
->done
= &trans_done
;
381 pcr
->trans_result
= TRANS_NOT_READY
;
382 init_completion(&trans_done
);
383 rtsx_pci_writel(pcr
, RTSX_HDBAR
, pcr
->host_sg_tbl_addr
);
384 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, val
);
386 spin_unlock_irqrestore(&pcr
->lock
, flags
);
388 timeleft
= wait_for_completion_interruptible_timeout(
389 &trans_done
, msecs_to_jiffies(timeout
));
391 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
397 spin_lock_irqsave(&pcr
->lock
, flags
);
399 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
401 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
404 spin_unlock_irqrestore(&pcr
->lock
, flags
);
407 spin_lock_irqsave(&pcr
->lock
, flags
);
409 spin_unlock_irqrestore(&pcr
->lock
, flags
);
411 dma_unmap_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dma_dir
);
413 if ((err
< 0) && (err
!= -ENODEV
))
414 rtsx_pci_stop_cmd(pcr
);
417 complete(pcr
->finish_me
);
421 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data
);
423 int rtsx_pci_read_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
435 for (i
= 0; i
< buf_len
/ 256; i
++) {
436 rtsx_pci_init_cmd(pcr
);
438 for (j
= 0; j
< 256; j
++)
439 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
441 err
= rtsx_pci_send_cmd(pcr
, 250);
445 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), 256);
450 rtsx_pci_init_cmd(pcr
);
452 for (j
= 0; j
< buf_len
% 256; j
++)
453 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
455 err
= rtsx_pci_send_cmd(pcr
, 250);
460 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), buf_len
% 256);
464 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf
);
466 int rtsx_pci_write_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
478 for (i
= 0; i
< buf_len
/ 256; i
++) {
479 rtsx_pci_init_cmd(pcr
);
481 for (j
= 0; j
< 256; j
++) {
482 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
487 err
= rtsx_pci_send_cmd(pcr
, 250);
493 rtsx_pci_init_cmd(pcr
);
495 for (j
= 0; j
< buf_len
% 256; j
++) {
496 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
501 err
= rtsx_pci_send_cmd(pcr
, 250);
508 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf
);
510 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr
*pcr
, const u32
*tbl
)
514 rtsx_pci_init_cmd(pcr
);
516 while (*tbl
& 0xFFFF0000) {
517 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
518 (u16
)(*tbl
>> 16), 0xFF, (u8
)(*tbl
));
522 err
= rtsx_pci_send_cmd(pcr
, 100);
529 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr
*pcr
, int card
)
533 if (card
== RTSX_SD_CARD
)
534 tbl
= pcr
->sd_pull_ctl_enable_tbl
;
535 else if (card
== RTSX_MS_CARD
)
536 tbl
= pcr
->ms_pull_ctl_enable_tbl
;
540 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
542 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable
);
544 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr
*pcr
, int card
)
548 if (card
== RTSX_SD_CARD
)
549 tbl
= pcr
->sd_pull_ctl_disable_tbl
;
550 else if (card
== RTSX_MS_CARD
)
551 tbl
= pcr
->ms_pull_ctl_disable_tbl
;
556 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
558 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable
);
560 static void rtsx_pci_enable_bus_int(struct rtsx_pcr
*pcr
)
562 pcr
->bier
= TRANS_OK_INT_EN
| TRANS_FAIL_INT_EN
| SD_INT_EN
;
564 if (pcr
->num_slots
> 1)
565 pcr
->bier
|= MS_INT_EN
;
567 /* Enable Bus Interrupt */
568 rtsx_pci_writel(pcr
, RTSX_BIER
, pcr
->bier
);
570 dev_dbg(&(pcr
->pci
->dev
), "RTSX_BIER: 0x%08x\n", pcr
->bier
);
573 static inline u8
double_ssc_depth(u8 depth
)
575 return ((depth
> 1) ? (depth
- 1) : depth
);
578 static u8
revise_ssc_depth(u8 ssc_depth
, u8 div
)
580 if (div
> CLK_DIV_1
) {
581 if (ssc_depth
> (div
- 1))
582 ssc_depth
-= (div
- 1);
584 ssc_depth
= SSC_DEPTH_4M
;
590 int rtsx_pci_switch_clock(struct rtsx_pcr
*pcr
, unsigned int card_clock
,
591 u8 ssc_depth
, bool initial_mode
, bool double_clk
, bool vpclk
)
594 u8 n
, clk_divider
, mcu_cnt
, div
;
596 [RTSX_SSC_DEPTH_4M
] = SSC_DEPTH_4M
,
597 [RTSX_SSC_DEPTH_2M
] = SSC_DEPTH_2M
,
598 [RTSX_SSC_DEPTH_1M
] = SSC_DEPTH_1M
,
599 [RTSX_SSC_DEPTH_500K
] = SSC_DEPTH_500K
,
600 [RTSX_SSC_DEPTH_250K
] = SSC_DEPTH_250K
,
604 /* We use 250k(around) here, in initial stage */
605 clk_divider
= SD_CLK_DIVIDE_128
;
606 card_clock
= 30000000;
608 clk_divider
= SD_CLK_DIVIDE_0
;
610 err
= rtsx_pci_write_register(pcr
, SD_CFG1
,
611 SD_CLK_DIVIDE_MASK
, clk_divider
);
615 card_clock
/= 1000000;
616 dev_dbg(&(pcr
->pci
->dev
), "Switch card clock to %dMHz\n", card_clock
);
619 if (!initial_mode
&& double_clk
)
620 clk
= card_clock
* 2;
621 dev_dbg(&(pcr
->pci
->dev
),
622 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
623 clk
, pcr
->cur_clock
);
625 if (clk
== pcr
->cur_clock
)
628 if (pcr
->ops
->conv_clk_and_div_n
)
629 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(clk
, CLK_TO_DIV_N
);
632 if ((clk
<= 2) || (n
> MAX_DIV_N_PCR
))
635 mcu_cnt
= (u8
)(125/clk
+ 3);
639 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
641 while ((n
< MIN_DIV_N_PCR
) && (div
< CLK_DIV_8
)) {
642 if (pcr
->ops
->conv_clk_and_div_n
) {
643 int dbl_clk
= pcr
->ops
->conv_clk_and_div_n(n
,
645 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(dbl_clk
,
652 dev_dbg(&(pcr
->pci
->dev
), "n = %d, div = %d\n", n
, div
);
654 ssc_depth
= depth
[ssc_depth
];
656 ssc_depth
= double_ssc_depth(ssc_depth
);
658 ssc_depth
= revise_ssc_depth(ssc_depth
, div
);
659 dev_dbg(&(pcr
->pci
->dev
), "ssc_depth = %d\n", ssc_depth
);
661 rtsx_pci_init_cmd(pcr
);
662 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
663 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
664 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
,
665 0xFF, (div
<< 4) | mcu_cnt
);
666 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
667 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
,
668 SSC_DEPTH_MASK
, ssc_depth
);
669 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, n
);
670 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, SSC_RSTB
);
672 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
674 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
675 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
678 err
= rtsx_pci_send_cmd(pcr
, 2000);
682 /* Wait SSC clock stable */
684 err
= rtsx_pci_write_register(pcr
, CLK_CTL
, CLK_LOW_FREQ
, 0);
688 pcr
->cur_clock
= clk
;
691 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock
);
693 int rtsx_pci_card_power_on(struct rtsx_pcr
*pcr
, int card
)
695 if (pcr
->ops
->card_power_on
)
696 return pcr
->ops
->card_power_on(pcr
, card
);
700 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on
);
702 int rtsx_pci_card_power_off(struct rtsx_pcr
*pcr
, int card
)
704 if (pcr
->ops
->card_power_off
)
705 return pcr
->ops
->card_power_off(pcr
, card
);
709 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off
);
711 int rtsx_pci_card_exclusive_check(struct rtsx_pcr
*pcr
, int card
)
713 unsigned int cd_mask
[] = {
714 [RTSX_SD_CARD
] = SD_EXIST
,
715 [RTSX_MS_CARD
] = MS_EXIST
719 /* When using single PMOS, accessing card is not permitted
720 * if the existing card is not the designated one.
722 if (pcr
->card_exist
& (~cd_mask
[card
]))
728 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check
);
730 int rtsx_pci_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
732 if (pcr
->ops
->switch_output_voltage
)
733 return pcr
->ops
->switch_output_voltage(pcr
, voltage
);
737 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage
);
739 unsigned int rtsx_pci_card_exist(struct rtsx_pcr
*pcr
)
743 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
744 if (pcr
->ops
->cd_deglitch
)
745 val
= pcr
->ops
->cd_deglitch(pcr
);
749 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist
);
751 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr
*pcr
)
753 struct completion finish
;
755 pcr
->finish_me
= &finish
;
756 init_completion(&finish
);
761 if (!pcr
->remove_pci
)
762 rtsx_pci_stop_cmd(pcr
);
764 wait_for_completion_interruptible_timeout(&finish
,
765 msecs_to_jiffies(2));
766 pcr
->finish_me
= NULL
;
768 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer
);
770 static void rtsx_pci_card_detect(struct work_struct
*work
)
772 struct delayed_work
*dwork
;
773 struct rtsx_pcr
*pcr
;
775 unsigned int card_detect
= 0, card_inserted
, card_removed
;
778 dwork
= to_delayed_work(work
);
779 pcr
= container_of(dwork
, struct rtsx_pcr
, carddet_work
);
781 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
783 mutex_lock(&pcr
->pcr_mutex
);
784 spin_lock_irqsave(&pcr
->lock
, flags
);
786 irq_status
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
787 dev_dbg(&(pcr
->pci
->dev
), "irq_status: 0x%08x\n", irq_status
);
789 irq_status
&= CARD_EXIST
;
790 card_inserted
= pcr
->card_inserted
& irq_status
;
791 card_removed
= pcr
->card_removed
;
792 pcr
->card_inserted
= 0;
793 pcr
->card_removed
= 0;
795 spin_unlock_irqrestore(&pcr
->lock
, flags
);
797 if (card_inserted
|| card_removed
) {
798 dev_dbg(&(pcr
->pci
->dev
),
799 "card_inserted: 0x%x, card_removed: 0x%x\n",
800 card_inserted
, card_removed
);
802 if (pcr
->ops
->cd_deglitch
)
803 card_inserted
= pcr
->ops
->cd_deglitch(pcr
);
805 card_detect
= card_inserted
| card_removed
;
807 pcr
->card_exist
|= card_inserted
;
808 pcr
->card_exist
&= ~card_removed
;
811 mutex_unlock(&pcr
->pcr_mutex
);
813 if ((card_detect
& SD_EXIST
) && pcr
->slots
[RTSX_SD_CARD
].card_event
)
814 pcr
->slots
[RTSX_SD_CARD
].card_event(
815 pcr
->slots
[RTSX_SD_CARD
].p_dev
);
816 if ((card_detect
& MS_EXIST
) && pcr
->slots
[RTSX_MS_CARD
].card_event
)
817 pcr
->slots
[RTSX_MS_CARD
].card_event(
818 pcr
->slots
[RTSX_MS_CARD
].p_dev
);
821 static irqreturn_t
rtsx_pci_isr(int irq
, void *dev_id
)
823 struct rtsx_pcr
*pcr
= dev_id
;
829 spin_lock(&pcr
->lock
);
831 int_reg
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
832 /* Clear interrupt flag */
833 rtsx_pci_writel(pcr
, RTSX_BIPR
, int_reg
);
834 if ((int_reg
& pcr
->bier
) == 0) {
835 spin_unlock(&pcr
->lock
);
838 if (int_reg
== 0xFFFFFFFF) {
839 spin_unlock(&pcr
->lock
);
843 int_reg
&= (pcr
->bier
| 0x7FFFFF);
845 if (int_reg
& SD_INT
) {
846 if (int_reg
& SD_EXIST
) {
847 pcr
->card_inserted
|= SD_EXIST
;
849 pcr
->card_removed
|= SD_EXIST
;
850 pcr
->card_inserted
&= ~SD_EXIST
;
854 if (int_reg
& MS_INT
) {
855 if (int_reg
& MS_EXIST
) {
856 pcr
->card_inserted
|= MS_EXIST
;
858 pcr
->card_removed
|= MS_EXIST
;
859 pcr
->card_inserted
&= ~MS_EXIST
;
863 if (int_reg
& (NEED_COMPLETE_INT
| DELINK_INT
)) {
864 if (int_reg
& (TRANS_FAIL_INT
| DELINK_INT
)) {
865 pcr
->trans_result
= TRANS_RESULT_FAIL
;
868 } else if (int_reg
& TRANS_OK_INT
) {
869 pcr
->trans_result
= TRANS_RESULT_OK
;
875 if (pcr
->card_inserted
|| pcr
->card_removed
)
876 schedule_delayed_work(&pcr
->carddet_work
,
877 msecs_to_jiffies(200));
879 spin_unlock(&pcr
->lock
);
883 static int rtsx_pci_acquire_irq(struct rtsx_pcr
*pcr
)
885 dev_info(&(pcr
->pci
->dev
), "%s: pcr->msi_en = %d, pci->irq = %d\n",
886 __func__
, pcr
->msi_en
, pcr
->pci
->irq
);
888 if (request_irq(pcr
->pci
->irq
, rtsx_pci_isr
,
889 pcr
->msi_en
? 0 : IRQF_SHARED
,
890 DRV_NAME_RTSX_PCI
, pcr
)) {
891 dev_err(&(pcr
->pci
->dev
),
892 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
897 pcr
->irq
= pcr
->pci
->irq
;
898 pci_intx(pcr
->pci
, !pcr
->msi_en
);
903 static void rtsx_pci_idle_work(struct work_struct
*work
)
905 struct delayed_work
*dwork
= to_delayed_work(work
);
906 struct rtsx_pcr
*pcr
= container_of(dwork
, struct rtsx_pcr
, idle_work
);
908 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
910 mutex_lock(&pcr
->pcr_mutex
);
912 pcr
->state
= PDEV_STAT_IDLE
;
914 if (pcr
->ops
->disable_auto_blink
)
915 pcr
->ops
->disable_auto_blink(pcr
);
916 if (pcr
->ops
->turn_off_led
)
917 pcr
->ops
->turn_off_led(pcr
);
919 mutex_unlock(&pcr
->pcr_mutex
);
922 static int rtsx_pci_init_hw(struct rtsx_pcr
*pcr
)
926 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
928 rtsx_pci_enable_bus_int(pcr
);
931 err
= rtsx_pci_write_register(pcr
, FPDCTL
, SSC_POWER_DOWN
, 0);
935 /* Wait SSC power stable */
938 if (pcr
->ops
->optimize_phy
) {
939 err
= pcr
->ops
->optimize_phy(pcr
);
944 rtsx_pci_init_cmd(pcr
);
946 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
947 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
, 0x07, 0x07);
949 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, HOST_SLEEP_STATE
, 0x03, 0x00);
950 /* Disable card clock */
951 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, 0x1E, 0);
952 /* Reset ASPM state to default value */
953 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, ASPM_FORCE_CTL
, 0x3F, 0);
954 /* Reset delink mode */
955 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x0A, 0);
956 /* Card driving select */
957 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
958 0x07, DRIVER_TYPE_D
);
959 /* Enable SSC Clock */
960 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
,
961 0xFF, SSC_8X_EN
| SSC_SEL_4M
);
962 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
, 0xFF, 0x12);
963 /* Disable cd_pwr_save */
964 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x16, 0x10);
965 /* Clear Link Ready Interrupt */
966 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
967 LINK_RDY_INT
, LINK_RDY_INT
);
968 /* Enlarge the estimation window of PERST# glitch
969 * to reduce the chance of invalid card interrupt
971 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PERST_GLITCH_WIDTH
, 0xFF, 0x80);
972 /* Update RC oscillator to 400k
973 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
976 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, RCCTL
, 0x01, 0x00);
977 /* Set interrupt write clear
978 * bit 1: U_elbi_if_rd_clr_en
979 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
980 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
982 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, NFTS_TX_CTRL
, 0x02, 0);
983 /* Force CLKREQ# PIN to drive 0 to request clock */
984 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PETXCFG
, 0x08, 0x08);
986 err
= rtsx_pci_send_cmd(pcr
, 100);
990 /* Enable clk_request_n to enable clock power management */
991 rtsx_pci_write_config_byte(pcr
, 0x81, 1);
992 /* Enter L1 when host tx idle */
993 rtsx_pci_write_config_byte(pcr
, 0x70F, 0x5B);
995 if (pcr
->ops
->extra_init_hw
) {
996 err
= pcr
->ops
->extra_init_hw(pcr
);
1001 /* No CD interrupt if probing driver with card inserted.
1002 * So we need to initialize pcr->card_exist here.
1004 if (pcr
->ops
->cd_deglitch
)
1005 pcr
->card_exist
= pcr
->ops
->cd_deglitch(pcr
);
1007 pcr
->card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
) & CARD_EXIST
;
1012 static int rtsx_pci_init_chip(struct rtsx_pcr
*pcr
)
1016 spin_lock_init(&pcr
->lock
);
1017 mutex_init(&pcr
->pcr_mutex
);
1019 switch (PCI_PID(pcr
)) {
1022 rts5209_init_params(pcr
);
1026 rts5229_init_params(pcr
);
1030 rtl8411_init_params(pcr
);
1034 rts5227_init_params(pcr
);
1038 dev_dbg(&(pcr
->pci
->dev
), "PID: 0x%04x, IC version: 0x%02x\n",
1039 PCI_PID(pcr
), pcr
->ic_version
);
1041 pcr
->slots
= kcalloc(pcr
->num_slots
, sizeof(struct rtsx_slot
),
1046 pcr
->state
= PDEV_STAT_IDLE
;
1047 err
= rtsx_pci_init_hw(pcr
);
1056 static int rtsx_pci_probe(struct pci_dev
*pcidev
,
1057 const struct pci_device_id
*id
)
1059 struct rtsx_pcr
*pcr
;
1060 struct pcr_handle
*handle
;
1064 dev_dbg(&(pcidev
->dev
),
1065 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1066 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1067 (int)pcidev
->revision
);
1069 ret
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(32));
1073 ret
= pci_enable_device(pcidev
);
1077 ret
= pci_request_regions(pcidev
, DRV_NAME_RTSX_PCI
);
1081 pcr
= kzalloc(sizeof(*pcr
), GFP_KERNEL
);
1087 handle
= kzalloc(sizeof(*handle
), GFP_KERNEL
);
1094 idr_preload(GFP_KERNEL
);
1095 spin_lock(&rtsx_pci_lock
);
1096 ret
= idr_alloc(&rtsx_pci_idr
, pcr
, 0, 0, GFP_NOWAIT
);
1099 spin_unlock(&rtsx_pci_lock
);
1105 dev_set_drvdata(&pcidev
->dev
, handle
);
1107 len
= pci_resource_len(pcidev
, 0);
1108 base
= pci_resource_start(pcidev
, 0);
1109 pcr
->remap_addr
= ioremap_nocache(base
, len
);
1110 if (!pcr
->remap_addr
) {
1115 pcr
->rtsx_resv_buf
= dma_alloc_coherent(&(pcidev
->dev
),
1116 RTSX_RESV_BUF_LEN
, &(pcr
->rtsx_resv_buf_addr
),
1118 if (pcr
->rtsx_resv_buf
== NULL
) {
1122 pcr
->host_cmds_ptr
= pcr
->rtsx_resv_buf
;
1123 pcr
->host_cmds_addr
= pcr
->rtsx_resv_buf_addr
;
1124 pcr
->host_sg_tbl_ptr
= pcr
->rtsx_resv_buf
+ HOST_CMDS_BUF_LEN
;
1125 pcr
->host_sg_tbl_addr
= pcr
->rtsx_resv_buf_addr
+ HOST_CMDS_BUF_LEN
;
1127 pcr
->card_inserted
= 0;
1128 pcr
->card_removed
= 0;
1129 INIT_DELAYED_WORK(&pcr
->carddet_work
, rtsx_pci_card_detect
);
1130 INIT_DELAYED_WORK(&pcr
->idle_work
, rtsx_pci_idle_work
);
1132 pcr
->msi_en
= msi_en
;
1134 ret
= pci_enable_msi(pcidev
);
1136 pcr
->msi_en
= false;
1139 ret
= rtsx_pci_acquire_irq(pcr
);
1143 pci_set_master(pcidev
);
1144 synchronize_irq(pcr
->irq
);
1146 ret
= rtsx_pci_init_chip(pcr
);
1150 for (i
= 0; i
< ARRAY_SIZE(rtsx_pcr_cells
); i
++) {
1151 rtsx_pcr_cells
[i
].platform_data
= handle
;
1152 rtsx_pcr_cells
[i
].pdata_size
= sizeof(*handle
);
1154 ret
= mfd_add_devices(&pcidev
->dev
, pcr
->id
, rtsx_pcr_cells
,
1155 ARRAY_SIZE(rtsx_pcr_cells
), NULL
, 0, NULL
);
1159 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1164 free_irq(pcr
->irq
, (void *)pcr
);
1166 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1167 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1169 iounmap(pcr
->remap_addr
);
1171 dev_set_drvdata(&pcidev
->dev
, NULL
);
1177 pci_release_regions(pcidev
);
1179 pci_disable_device(pcidev
);
1184 static void rtsx_pci_remove(struct pci_dev
*pcidev
)
1186 struct pcr_handle
*handle
= pci_get_drvdata(pcidev
);
1187 struct rtsx_pcr
*pcr
= handle
->pcr
;
1189 pcr
->remove_pci
= true;
1191 cancel_delayed_work(&pcr
->carddet_work
);
1192 cancel_delayed_work(&pcr
->idle_work
);
1194 mfd_remove_devices(&pcidev
->dev
);
1196 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1197 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1198 free_irq(pcr
->irq
, (void *)pcr
);
1200 pci_disable_msi(pcr
->pci
);
1201 iounmap(pcr
->remap_addr
);
1203 dev_set_drvdata(&pcidev
->dev
, NULL
);
1204 pci_release_regions(pcidev
);
1205 pci_disable_device(pcidev
);
1207 spin_lock(&rtsx_pci_lock
);
1208 idr_remove(&rtsx_pci_idr
, pcr
->id
);
1209 spin_unlock(&rtsx_pci_lock
);
1215 dev_dbg(&(pcidev
->dev
),
1216 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1217 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1222 static int rtsx_pci_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1224 struct pcr_handle
*handle
;
1225 struct rtsx_pcr
*pcr
;
1228 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1230 handle
= pci_get_drvdata(pcidev
);
1233 cancel_delayed_work(&pcr
->carddet_work
);
1234 cancel_delayed_work(&pcr
->idle_work
);
1236 mutex_lock(&pcr
->pcr_mutex
);
1238 if (pcr
->ops
->turn_off_led
)
1239 pcr
->ops
->turn_off_led(pcr
);
1241 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
1244 rtsx_pci_write_register(pcr
, PETXCFG
, 0x08, 0x08);
1245 rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x02);
1247 pci_save_state(pcidev
);
1248 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1249 pci_disable_device(pcidev
);
1250 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1252 mutex_unlock(&pcr
->pcr_mutex
);
1256 static int rtsx_pci_resume(struct pci_dev
*pcidev
)
1258 struct pcr_handle
*handle
;
1259 struct rtsx_pcr
*pcr
;
1262 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1264 handle
= pci_get_drvdata(pcidev
);
1267 mutex_lock(&pcr
->pcr_mutex
);
1269 pci_set_power_state(pcidev
, PCI_D0
);
1270 pci_restore_state(pcidev
);
1271 ret
= pci_enable_device(pcidev
);
1274 pci_set_master(pcidev
);
1276 ret
= rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x00);
1280 ret
= rtsx_pci_init_hw(pcr
);
1284 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1287 mutex_unlock(&pcr
->pcr_mutex
);
1291 #else /* CONFIG_PM */
1293 #define rtsx_pci_suspend NULL
1294 #define rtsx_pci_resume NULL
1296 #endif /* CONFIG_PM */
1298 static struct pci_driver rtsx_pci_driver
= {
1299 .name
= DRV_NAME_RTSX_PCI
,
1300 .id_table
= rtsx_pci_ids
,
1301 .probe
= rtsx_pci_probe
,
1302 .remove
= rtsx_pci_remove
,
1303 .suspend
= rtsx_pci_suspend
,
1304 .resume
= rtsx_pci_resume
,
1306 module_pci_driver(rtsx_pci_driver
);
1308 MODULE_LICENSE("GPL");
1309 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1310 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");