1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
22 #include <linux/pci.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/highmem.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/idr.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/core.h>
32 #include <linux/mfd/rtsx_pci.h>
33 #include <asm/unaligned.h>
37 static bool msi_en
= true;
38 module_param(msi_en
, bool, S_IRUGO
| S_IWUSR
);
39 MODULE_PARM_DESC(msi_en
, "Enable MSI");
41 static DEFINE_IDR(rtsx_pci_idr
);
42 static DEFINE_SPINLOCK(rtsx_pci_lock
);
44 static struct mfd_cell rtsx_pcr_cells
[] = {
46 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
49 .name
= DRV_NAME_RTSX_PCI_MS
,
53 static const struct pci_device_id rtsx_pci_ids
[] = {
54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
64 MODULE_DEVICE_TABLE(pci
, rtsx_pci_ids
);
66 void rtsx_pci_start_run(struct rtsx_pcr
*pcr
)
68 /* If pci device removed, don't queue idle work any more */
72 if (pcr
->state
!= PDEV_STAT_RUN
) {
73 pcr
->state
= PDEV_STAT_RUN
;
74 if (pcr
->ops
->enable_auto_blink
)
75 pcr
->ops
->enable_auto_blink(pcr
);
78 rtsx_pci_write_config_byte(pcr
, LCTLR
, 0);
81 mod_delayed_work(system_wq
, &pcr
->idle_work
, msecs_to_jiffies(200));
83 EXPORT_SYMBOL_GPL(rtsx_pci_start_run
);
85 int rtsx_pci_write_register(struct rtsx_pcr
*pcr
, u16 addr
, u8 mask
, u8 data
)
88 u32 val
= HAIMR_WRITE_START
;
90 val
|= (u32
)(addr
& 0x3FFF) << 16;
91 val
|= (u32
)mask
<< 8;
94 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
96 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
97 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
98 if ((val
& HAIMR_TRANS_END
) == 0) {
107 EXPORT_SYMBOL_GPL(rtsx_pci_write_register
);
109 int rtsx_pci_read_register(struct rtsx_pcr
*pcr
, u16 addr
, u8
*data
)
111 u32 val
= HAIMR_READ_START
;
114 val
|= (u32
)(addr
& 0x3FFF) << 16;
115 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
117 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
118 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
119 if ((val
& HAIMR_TRANS_END
) == 0)
123 if (i
>= MAX_RW_REG_CNT
)
127 *data
= (u8
)(val
& 0xFF);
131 EXPORT_SYMBOL_GPL(rtsx_pci_read_register
);
133 int rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
135 int err
, i
, finished
= 0;
138 rtsx_pci_init_cmd(pcr
);
140 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA0
, 0xFF, (u8
)val
);
141 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA1
, 0xFF, (u8
)(val
>> 8));
142 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
143 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x81);
145 err
= rtsx_pci_send_cmd(pcr
, 100);
149 for (i
= 0; i
< 100000; i
++) {
150 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
165 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register
);
167 int rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
169 int err
, i
, finished
= 0;
173 rtsx_pci_init_cmd(pcr
);
175 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
176 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x80);
178 err
= rtsx_pci_send_cmd(pcr
, 100);
182 for (i
= 0; i
< 100000; i
++) {
183 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
196 rtsx_pci_init_cmd(pcr
);
198 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA0
, 0, 0);
199 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA1
, 0, 0);
201 err
= rtsx_pci_send_cmd(pcr
, 100);
205 ptr
= rtsx_pci_get_cmd_data(pcr
);
206 data
= ((u16
)ptr
[1] << 8) | ptr
[0];
213 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register
);
215 void rtsx_pci_stop_cmd(struct rtsx_pcr
*pcr
)
217 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, STOP_CMD
);
218 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, STOP_DMA
);
220 rtsx_pci_write_register(pcr
, DMACTL
, 0x80, 0x80);
221 rtsx_pci_write_register(pcr
, RBCTL
, 0x80, 0x80);
223 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd
);
225 void rtsx_pci_add_cmd(struct rtsx_pcr
*pcr
,
226 u8 cmd_type
, u16 reg_addr
, u8 mask
, u8 data
)
230 u32
*ptr
= (u32
*)(pcr
->host_cmds_ptr
);
232 val
|= (u32
)(cmd_type
& 0x03) << 30;
233 val
|= (u32
)(reg_addr
& 0x3FFF) << 16;
234 val
|= (u32
)mask
<< 8;
237 spin_lock_irqsave(&pcr
->lock
, flags
);
239 if (pcr
->ci
< (HOST_CMDS_BUF_LEN
/ 4)) {
240 put_unaligned_le32(val
, ptr
);
244 spin_unlock_irqrestore(&pcr
->lock
, flags
);
246 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd
);
248 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr
*pcr
)
252 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
254 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
255 /* Hardware Auto Response */
257 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
259 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait
);
261 int rtsx_pci_send_cmd(struct rtsx_pcr
*pcr
, int timeout
)
263 struct completion trans_done
;
269 spin_lock_irqsave(&pcr
->lock
, flags
);
271 /* set up data structures for the wakeup system */
272 pcr
->done
= &trans_done
;
273 pcr
->trans_result
= TRANS_NOT_READY
;
274 init_completion(&trans_done
);
276 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
278 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
279 /* Hardware Auto Response */
281 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
283 spin_unlock_irqrestore(&pcr
->lock
, flags
);
285 /* Wait for TRANS_OK_INT */
286 timeleft
= wait_for_completion_interruptible_timeout(
287 &trans_done
, msecs_to_jiffies(timeout
));
289 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
292 goto finish_send_cmd
;
295 spin_lock_irqsave(&pcr
->lock
, flags
);
296 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
298 else if (pcr
->trans_result
== TRANS_RESULT_OK
)
300 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
302 spin_unlock_irqrestore(&pcr
->lock
, flags
);
305 spin_lock_irqsave(&pcr
->lock
, flags
);
307 spin_unlock_irqrestore(&pcr
->lock
, flags
);
309 if ((err
< 0) && (err
!= -ENODEV
))
310 rtsx_pci_stop_cmd(pcr
);
313 complete(pcr
->finish_me
);
317 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd
);
319 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr
*pcr
,
320 dma_addr_t addr
, unsigned int len
, int end
)
322 u64
*ptr
= (u64
*)(pcr
->host_sg_tbl_ptr
) + pcr
->sgi
;
324 u8 option
= SG_VALID
| SG_TRANS_DATA
;
326 dev_dbg(&(pcr
->pci
->dev
), "DMA addr: 0x%x, Len: 0x%x\n",
327 (unsigned int)addr
, len
);
331 val
= ((u64
)addr
<< 32) | ((u64
)len
<< 12) | option
;
333 put_unaligned_le64(val
, ptr
);
337 int rtsx_pci_transfer_data(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
338 int num_sg
, bool read
, int timeout
)
340 struct completion trans_done
;
345 count
= rtsx_pci_dma_map_sg(pcr
, sglist
, num_sg
, read
);
347 dev_err(&(pcr
->pci
->dev
), "scatterlist map failed\n");
350 dev_dbg(&(pcr
->pci
->dev
), "DMA mapping count: %d\n", count
);
353 spin_lock_irqsave(&pcr
->lock
, flags
);
355 pcr
->done
= &trans_done
;
356 pcr
->trans_result
= TRANS_NOT_READY
;
357 init_completion(&trans_done
);
359 spin_unlock_irqrestore(&pcr
->lock
, flags
);
361 rtsx_pci_dma_transfer(pcr
, sglist
, count
, read
);
363 timeleft
= wait_for_completion_interruptible_timeout(
364 &trans_done
, msecs_to_jiffies(timeout
));
366 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
372 spin_lock_irqsave(&pcr
->lock
, flags
);
374 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
376 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
379 spin_unlock_irqrestore(&pcr
->lock
, flags
);
382 spin_lock_irqsave(&pcr
->lock
, flags
);
384 spin_unlock_irqrestore(&pcr
->lock
, flags
);
386 rtsx_pci_dma_unmap_sg(pcr
, sglist
, num_sg
, read
);
388 if ((err
< 0) && (err
!= -ENODEV
))
389 rtsx_pci_stop_cmd(pcr
);
392 complete(pcr
->finish_me
);
396 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data
);
398 int rtsx_pci_dma_map_sg(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
399 int num_sg
, bool read
)
401 enum dma_data_direction dir
= read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
406 if ((sglist
== NULL
) || num_sg
< 1)
409 return dma_map_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dir
);
411 EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg
);
413 int rtsx_pci_dma_unmap_sg(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
414 int num_sg
, bool read
)
416 enum dma_data_direction dir
= read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
421 if (sglist
== NULL
|| num_sg
< 1)
424 dma_unmap_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dir
);
427 EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg
);
429 int rtsx_pci_dma_transfer(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
430 int sg_count
, bool read
)
432 struct scatterlist
*sg
;
437 u8 dir
= read
? DEVICE_TO_HOST
: HOST_TO_DEVICE
;
443 if ((sglist
== NULL
) || (sg_count
< 1))
446 val
= ((u32
)(dir
& 0x01) << 29) | TRIG_DMA
| ADMA_MODE
;
448 for_each_sg(sglist
, sg
, sg_count
, i
) {
449 addr
= sg_dma_address(sg
);
450 len
= sg_dma_len(sg
);
451 rtsx_pci_add_sg_tbl(pcr
, addr
, len
, i
== sg_count
- 1);
454 spin_lock_irqsave(&pcr
->lock
, flags
);
456 rtsx_pci_writel(pcr
, RTSX_HDBAR
, pcr
->host_sg_tbl_addr
);
457 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, val
);
459 spin_unlock_irqrestore(&pcr
->lock
, flags
);
463 EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer
);
465 int rtsx_pci_read_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
477 for (i
= 0; i
< buf_len
/ 256; i
++) {
478 rtsx_pci_init_cmd(pcr
);
480 for (j
= 0; j
< 256; j
++)
481 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
483 err
= rtsx_pci_send_cmd(pcr
, 250);
487 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), 256);
492 rtsx_pci_init_cmd(pcr
);
494 for (j
= 0; j
< buf_len
% 256; j
++)
495 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
497 err
= rtsx_pci_send_cmd(pcr
, 250);
502 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), buf_len
% 256);
506 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf
);
508 int rtsx_pci_write_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
520 for (i
= 0; i
< buf_len
/ 256; i
++) {
521 rtsx_pci_init_cmd(pcr
);
523 for (j
= 0; j
< 256; j
++) {
524 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
529 err
= rtsx_pci_send_cmd(pcr
, 250);
535 rtsx_pci_init_cmd(pcr
);
537 for (j
= 0; j
< buf_len
% 256; j
++) {
538 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
543 err
= rtsx_pci_send_cmd(pcr
, 250);
550 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf
);
552 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr
*pcr
, const u32
*tbl
)
556 rtsx_pci_init_cmd(pcr
);
558 while (*tbl
& 0xFFFF0000) {
559 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
560 (u16
)(*tbl
>> 16), 0xFF, (u8
)(*tbl
));
564 err
= rtsx_pci_send_cmd(pcr
, 100);
571 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr
*pcr
, int card
)
575 if (card
== RTSX_SD_CARD
)
576 tbl
= pcr
->sd_pull_ctl_enable_tbl
;
577 else if (card
== RTSX_MS_CARD
)
578 tbl
= pcr
->ms_pull_ctl_enable_tbl
;
582 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
584 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable
);
586 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr
*pcr
, int card
)
590 if (card
== RTSX_SD_CARD
)
591 tbl
= pcr
->sd_pull_ctl_disable_tbl
;
592 else if (card
== RTSX_MS_CARD
)
593 tbl
= pcr
->ms_pull_ctl_disable_tbl
;
598 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
600 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable
);
602 static void rtsx_pci_enable_bus_int(struct rtsx_pcr
*pcr
)
604 pcr
->bier
= TRANS_OK_INT_EN
| TRANS_FAIL_INT_EN
| SD_INT_EN
;
606 if (pcr
->num_slots
> 1)
607 pcr
->bier
|= MS_INT_EN
;
609 /* Enable Bus Interrupt */
610 rtsx_pci_writel(pcr
, RTSX_BIER
, pcr
->bier
);
612 dev_dbg(&(pcr
->pci
->dev
), "RTSX_BIER: 0x%08x\n", pcr
->bier
);
615 static inline u8
double_ssc_depth(u8 depth
)
617 return ((depth
> 1) ? (depth
- 1) : depth
);
620 static u8
revise_ssc_depth(u8 ssc_depth
, u8 div
)
622 if (div
> CLK_DIV_1
) {
623 if (ssc_depth
> (div
- 1))
624 ssc_depth
-= (div
- 1);
626 ssc_depth
= SSC_DEPTH_4M
;
632 int rtsx_pci_switch_clock(struct rtsx_pcr
*pcr
, unsigned int card_clock
,
633 u8 ssc_depth
, bool initial_mode
, bool double_clk
, bool vpclk
)
636 u8 n
, clk_divider
, mcu_cnt
, div
;
638 [RTSX_SSC_DEPTH_4M
] = SSC_DEPTH_4M
,
639 [RTSX_SSC_DEPTH_2M
] = SSC_DEPTH_2M
,
640 [RTSX_SSC_DEPTH_1M
] = SSC_DEPTH_1M
,
641 [RTSX_SSC_DEPTH_500K
] = SSC_DEPTH_500K
,
642 [RTSX_SSC_DEPTH_250K
] = SSC_DEPTH_250K
,
646 /* We use 250k(around) here, in initial stage */
647 clk_divider
= SD_CLK_DIVIDE_128
;
648 card_clock
= 30000000;
650 clk_divider
= SD_CLK_DIVIDE_0
;
652 err
= rtsx_pci_write_register(pcr
, SD_CFG1
,
653 SD_CLK_DIVIDE_MASK
, clk_divider
);
657 card_clock
/= 1000000;
658 dev_dbg(&(pcr
->pci
->dev
), "Switch card clock to %dMHz\n", card_clock
);
661 if (!initial_mode
&& double_clk
)
662 clk
= card_clock
* 2;
663 dev_dbg(&(pcr
->pci
->dev
),
664 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
665 clk
, pcr
->cur_clock
);
667 if (clk
== pcr
->cur_clock
)
670 if (pcr
->ops
->conv_clk_and_div_n
)
671 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(clk
, CLK_TO_DIV_N
);
674 if ((clk
<= 2) || (n
> MAX_DIV_N_PCR
))
677 mcu_cnt
= (u8
)(125/clk
+ 3);
681 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
683 while ((n
< MIN_DIV_N_PCR
) && (div
< CLK_DIV_8
)) {
684 if (pcr
->ops
->conv_clk_and_div_n
) {
685 int dbl_clk
= pcr
->ops
->conv_clk_and_div_n(n
,
687 n
= (u8
)pcr
->ops
->conv_clk_and_div_n(dbl_clk
,
694 dev_dbg(&(pcr
->pci
->dev
), "n = %d, div = %d\n", n
, div
);
696 ssc_depth
= depth
[ssc_depth
];
698 ssc_depth
= double_ssc_depth(ssc_depth
);
700 ssc_depth
= revise_ssc_depth(ssc_depth
, div
);
701 dev_dbg(&(pcr
->pci
->dev
), "ssc_depth = %d\n", ssc_depth
);
703 rtsx_pci_init_cmd(pcr
);
704 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
705 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
706 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
,
707 0xFF, (div
<< 4) | mcu_cnt
);
708 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
709 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
,
710 SSC_DEPTH_MASK
, ssc_depth
);
711 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, n
);
712 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, SSC_RSTB
);
714 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
716 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
717 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
720 err
= rtsx_pci_send_cmd(pcr
, 2000);
724 /* Wait SSC clock stable */
726 err
= rtsx_pci_write_register(pcr
, CLK_CTL
, CLK_LOW_FREQ
, 0);
730 pcr
->cur_clock
= clk
;
733 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock
);
735 int rtsx_pci_card_power_on(struct rtsx_pcr
*pcr
, int card
)
737 if (pcr
->ops
->card_power_on
)
738 return pcr
->ops
->card_power_on(pcr
, card
);
742 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on
);
744 int rtsx_pci_card_power_off(struct rtsx_pcr
*pcr
, int card
)
746 if (pcr
->ops
->card_power_off
)
747 return pcr
->ops
->card_power_off(pcr
, card
);
751 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off
);
753 int rtsx_pci_card_exclusive_check(struct rtsx_pcr
*pcr
, int card
)
755 unsigned int cd_mask
[] = {
756 [RTSX_SD_CARD
] = SD_EXIST
,
757 [RTSX_MS_CARD
] = MS_EXIST
760 if (!(pcr
->flags
& PCR_MS_PMOS
)) {
761 /* When using single PMOS, accessing card is not permitted
762 * if the existing card is not the designated one.
764 if (pcr
->card_exist
& (~cd_mask
[card
]))
770 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check
);
772 int rtsx_pci_switch_output_voltage(struct rtsx_pcr
*pcr
, u8 voltage
)
774 if (pcr
->ops
->switch_output_voltage
)
775 return pcr
->ops
->switch_output_voltage(pcr
, voltage
);
779 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage
);
781 unsigned int rtsx_pci_card_exist(struct rtsx_pcr
*pcr
)
785 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
786 if (pcr
->ops
->cd_deglitch
)
787 val
= pcr
->ops
->cd_deglitch(pcr
);
791 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist
);
793 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr
*pcr
)
795 struct completion finish
;
797 pcr
->finish_me
= &finish
;
798 init_completion(&finish
);
803 if (!pcr
->remove_pci
)
804 rtsx_pci_stop_cmd(pcr
);
806 wait_for_completion_interruptible_timeout(&finish
,
807 msecs_to_jiffies(2));
808 pcr
->finish_me
= NULL
;
810 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer
);
812 static void rtsx_pci_card_detect(struct work_struct
*work
)
814 struct delayed_work
*dwork
;
815 struct rtsx_pcr
*pcr
;
817 unsigned int card_detect
= 0, card_inserted
, card_removed
;
820 dwork
= to_delayed_work(work
);
821 pcr
= container_of(dwork
, struct rtsx_pcr
, carddet_work
);
823 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
825 mutex_lock(&pcr
->pcr_mutex
);
826 spin_lock_irqsave(&pcr
->lock
, flags
);
828 irq_status
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
829 dev_dbg(&(pcr
->pci
->dev
), "irq_status: 0x%08x\n", irq_status
);
831 irq_status
&= CARD_EXIST
;
832 card_inserted
= pcr
->card_inserted
& irq_status
;
833 card_removed
= pcr
->card_removed
;
834 pcr
->card_inserted
= 0;
835 pcr
->card_removed
= 0;
837 spin_unlock_irqrestore(&pcr
->lock
, flags
);
839 if (card_inserted
|| card_removed
) {
840 dev_dbg(&(pcr
->pci
->dev
),
841 "card_inserted: 0x%x, card_removed: 0x%x\n",
842 card_inserted
, card_removed
);
844 if (pcr
->ops
->cd_deglitch
)
845 card_inserted
= pcr
->ops
->cd_deglitch(pcr
);
847 card_detect
= card_inserted
| card_removed
;
849 pcr
->card_exist
|= card_inserted
;
850 pcr
->card_exist
&= ~card_removed
;
853 mutex_unlock(&pcr
->pcr_mutex
);
855 if ((card_detect
& SD_EXIST
) && pcr
->slots
[RTSX_SD_CARD
].card_event
)
856 pcr
->slots
[RTSX_SD_CARD
].card_event(
857 pcr
->slots
[RTSX_SD_CARD
].p_dev
);
858 if ((card_detect
& MS_EXIST
) && pcr
->slots
[RTSX_MS_CARD
].card_event
)
859 pcr
->slots
[RTSX_MS_CARD
].card_event(
860 pcr
->slots
[RTSX_MS_CARD
].p_dev
);
863 static irqreturn_t
rtsx_pci_isr(int irq
, void *dev_id
)
865 struct rtsx_pcr
*pcr
= dev_id
;
871 spin_lock(&pcr
->lock
);
873 int_reg
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
874 /* Clear interrupt flag */
875 rtsx_pci_writel(pcr
, RTSX_BIPR
, int_reg
);
876 dev_dbg(&pcr
->pci
->dev
, "=========== BIPR 0x%8x ==========\n", int_reg
);
878 if ((int_reg
& pcr
->bier
) == 0) {
879 spin_unlock(&pcr
->lock
);
882 if (int_reg
== 0xFFFFFFFF) {
883 spin_unlock(&pcr
->lock
);
887 int_reg
&= (pcr
->bier
| 0x7FFFFF);
889 if (int_reg
& SD_INT
) {
890 if (int_reg
& SD_EXIST
) {
891 pcr
->card_inserted
|= SD_EXIST
;
893 pcr
->card_removed
|= SD_EXIST
;
894 pcr
->card_inserted
&= ~SD_EXIST
;
898 if (int_reg
& MS_INT
) {
899 if (int_reg
& MS_EXIST
) {
900 pcr
->card_inserted
|= MS_EXIST
;
902 pcr
->card_removed
|= MS_EXIST
;
903 pcr
->card_inserted
&= ~MS_EXIST
;
907 if (int_reg
& (NEED_COMPLETE_INT
| DELINK_INT
)) {
908 if (int_reg
& (TRANS_FAIL_INT
| DELINK_INT
))
909 pcr
->trans_result
= TRANS_RESULT_FAIL
;
910 else if (int_reg
& TRANS_OK_INT
)
911 pcr
->trans_result
= TRANS_RESULT_OK
;
916 if (int_reg
& SD_EXIST
) {
917 struct rtsx_slot
*slot
= &pcr
->slots
[RTSX_SD_CARD
];
918 if (slot
&& slot
->done_transfer
)
919 slot
->done_transfer(slot
->p_dev
);
922 if (int_reg
& MS_EXIST
) {
923 struct rtsx_slot
*slot
= &pcr
->slots
[RTSX_SD_CARD
];
924 if (slot
&& slot
->done_transfer
)
925 slot
->done_transfer(slot
->p_dev
);
930 if (pcr
->card_inserted
|| pcr
->card_removed
)
931 schedule_delayed_work(&pcr
->carddet_work
,
932 msecs_to_jiffies(200));
934 spin_unlock(&pcr
->lock
);
938 static int rtsx_pci_acquire_irq(struct rtsx_pcr
*pcr
)
940 dev_info(&(pcr
->pci
->dev
), "%s: pcr->msi_en = %d, pci->irq = %d\n",
941 __func__
, pcr
->msi_en
, pcr
->pci
->irq
);
943 if (request_irq(pcr
->pci
->irq
, rtsx_pci_isr
,
944 pcr
->msi_en
? 0 : IRQF_SHARED
,
945 DRV_NAME_RTSX_PCI
, pcr
)) {
946 dev_err(&(pcr
->pci
->dev
),
947 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
952 pcr
->irq
= pcr
->pci
->irq
;
953 pci_intx(pcr
->pci
, !pcr
->msi_en
);
958 static void rtsx_pci_idle_work(struct work_struct
*work
)
960 struct delayed_work
*dwork
= to_delayed_work(work
);
961 struct rtsx_pcr
*pcr
= container_of(dwork
, struct rtsx_pcr
, idle_work
);
963 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
965 mutex_lock(&pcr
->pcr_mutex
);
967 pcr
->state
= PDEV_STAT_IDLE
;
969 if (pcr
->ops
->disable_auto_blink
)
970 pcr
->ops
->disable_auto_blink(pcr
);
971 if (pcr
->ops
->turn_off_led
)
972 pcr
->ops
->turn_off_led(pcr
);
975 rtsx_pci_write_config_byte(pcr
, LCTLR
, pcr
->aspm_en
);
977 mutex_unlock(&pcr
->pcr_mutex
);
980 static void rtsx_pci_power_off(struct rtsx_pcr
*pcr
, u8 pm_state
)
982 if (pcr
->ops
->turn_off_led
)
983 pcr
->ops
->turn_off_led(pcr
);
985 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
988 rtsx_pci_write_register(pcr
, PETXCFG
, 0x08, 0x08);
989 rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, pm_state
);
991 if (pcr
->ops
->force_power_down
)
992 pcr
->ops
->force_power_down(pcr
, pm_state
);
995 static int rtsx_pci_init_hw(struct rtsx_pcr
*pcr
)
999 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
1001 rtsx_pci_enable_bus_int(pcr
);
1004 err
= rtsx_pci_write_register(pcr
, FPDCTL
, SSC_POWER_DOWN
, 0);
1008 /* Wait SSC power stable */
1011 if (pcr
->ops
->optimize_phy
) {
1012 err
= pcr
->ops
->optimize_phy(pcr
);
1017 rtsx_pci_init_cmd(pcr
);
1019 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1020 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
, 0x07, 0x07);
1022 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, HOST_SLEEP_STATE
, 0x03, 0x00);
1023 /* Disable card clock */
1024 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, 0x1E, 0);
1025 /* Reset delink mode */
1026 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x0A, 0);
1027 /* Card driving select */
1028 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_DRIVE_SEL
,
1029 0xFF, pcr
->card_drive_sel
);
1030 /* Enable SSC Clock */
1031 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
,
1032 0xFF, SSC_8X_EN
| SSC_SEL_4M
);
1033 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
, 0xFF, 0x12);
1034 /* Disable cd_pwr_save */
1035 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x16, 0x10);
1036 /* Clear Link Ready Interrupt */
1037 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
1038 LINK_RDY_INT
, LINK_RDY_INT
);
1039 /* Enlarge the estimation window of PERST# glitch
1040 * to reduce the chance of invalid card interrupt
1042 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PERST_GLITCH_WIDTH
, 0xFF, 0x80);
1043 /* Update RC oscillator to 400k
1044 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1047 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, RCCTL
, 0x01, 0x00);
1048 /* Set interrupt write clear
1049 * bit 1: U_elbi_if_rd_clr_en
1050 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1051 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1053 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, NFTS_TX_CTRL
, 0x02, 0);
1055 err
= rtsx_pci_send_cmd(pcr
, 100);
1059 rtsx_pci_write_config_byte(pcr
, LCTLR
, 0);
1061 /* Enable clk_request_n to enable clock power management */
1062 rtsx_pci_write_config_byte(pcr
, 0x81, 1);
1063 /* Enter L1 when host tx idle */
1064 rtsx_pci_write_config_byte(pcr
, 0x70F, 0x5B);
1066 if (pcr
->ops
->extra_init_hw
) {
1067 err
= pcr
->ops
->extra_init_hw(pcr
);
1072 /* No CD interrupt if probing driver with card inserted.
1073 * So we need to initialize pcr->card_exist here.
1075 if (pcr
->ops
->cd_deglitch
)
1076 pcr
->card_exist
= pcr
->ops
->cd_deglitch(pcr
);
1078 pcr
->card_exist
= rtsx_pci_readl(pcr
, RTSX_BIPR
) & CARD_EXIST
;
1083 static int rtsx_pci_init_chip(struct rtsx_pcr
*pcr
)
1087 spin_lock_init(&pcr
->lock
);
1088 mutex_init(&pcr
->pcr_mutex
);
1090 switch (PCI_PID(pcr
)) {
1093 rts5209_init_params(pcr
);
1097 rts5229_init_params(pcr
);
1101 rtl8411_init_params(pcr
);
1105 rts5227_init_params(pcr
);
1109 rts5249_init_params(pcr
);
1113 rtl8411b_init_params(pcr
);
1117 rtl8402_init_params(pcr
);
1121 dev_dbg(&(pcr
->pci
->dev
), "PID: 0x%04x, IC version: 0x%02x\n",
1122 PCI_PID(pcr
), pcr
->ic_version
);
1124 pcr
->slots
= kcalloc(pcr
->num_slots
, sizeof(struct rtsx_slot
),
1129 if (pcr
->ops
->fetch_vendor_settings
)
1130 pcr
->ops
->fetch_vendor_settings(pcr
);
1132 dev_dbg(&(pcr
->pci
->dev
), "pcr->aspm_en = 0x%x\n", pcr
->aspm_en
);
1133 dev_dbg(&(pcr
->pci
->dev
), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1134 pcr
->sd30_drive_sel_1v8
);
1135 dev_dbg(&(pcr
->pci
->dev
), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1136 pcr
->sd30_drive_sel_3v3
);
1137 dev_dbg(&(pcr
->pci
->dev
), "pcr->card_drive_sel = 0x%x\n",
1138 pcr
->card_drive_sel
);
1139 dev_dbg(&(pcr
->pci
->dev
), "pcr->flags = 0x%x\n", pcr
->flags
);
1141 pcr
->state
= PDEV_STAT_IDLE
;
1142 err
= rtsx_pci_init_hw(pcr
);
1151 static int rtsx_pci_probe(struct pci_dev
*pcidev
,
1152 const struct pci_device_id
*id
)
1154 struct rtsx_pcr
*pcr
;
1155 struct pcr_handle
*handle
;
1159 dev_dbg(&(pcidev
->dev
),
1160 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1161 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1162 (int)pcidev
->revision
);
1164 ret
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(32));
1168 ret
= pci_enable_device(pcidev
);
1172 ret
= pci_request_regions(pcidev
, DRV_NAME_RTSX_PCI
);
1176 pcr
= kzalloc(sizeof(*pcr
), GFP_KERNEL
);
1182 handle
= kzalloc(sizeof(*handle
), GFP_KERNEL
);
1189 idr_preload(GFP_KERNEL
);
1190 spin_lock(&rtsx_pci_lock
);
1191 ret
= idr_alloc(&rtsx_pci_idr
, pcr
, 0, 0, GFP_NOWAIT
);
1194 spin_unlock(&rtsx_pci_lock
);
1200 dev_set_drvdata(&pcidev
->dev
, handle
);
1202 len
= pci_resource_len(pcidev
, 0);
1203 base
= pci_resource_start(pcidev
, 0);
1204 pcr
->remap_addr
= ioremap_nocache(base
, len
);
1205 if (!pcr
->remap_addr
) {
1210 pcr
->rtsx_resv_buf
= dma_alloc_coherent(&(pcidev
->dev
),
1211 RTSX_RESV_BUF_LEN
, &(pcr
->rtsx_resv_buf_addr
),
1213 if (pcr
->rtsx_resv_buf
== NULL
) {
1217 pcr
->host_cmds_ptr
= pcr
->rtsx_resv_buf
;
1218 pcr
->host_cmds_addr
= pcr
->rtsx_resv_buf_addr
;
1219 pcr
->host_sg_tbl_ptr
= pcr
->rtsx_resv_buf
+ HOST_CMDS_BUF_LEN
;
1220 pcr
->host_sg_tbl_addr
= pcr
->rtsx_resv_buf_addr
+ HOST_CMDS_BUF_LEN
;
1222 pcr
->card_inserted
= 0;
1223 pcr
->card_removed
= 0;
1224 INIT_DELAYED_WORK(&pcr
->carddet_work
, rtsx_pci_card_detect
);
1225 INIT_DELAYED_WORK(&pcr
->idle_work
, rtsx_pci_idle_work
);
1227 pcr
->msi_en
= msi_en
;
1229 ret
= pci_enable_msi(pcidev
);
1231 pcr
->msi_en
= false;
1234 ret
= rtsx_pci_acquire_irq(pcr
);
1238 pci_set_master(pcidev
);
1239 synchronize_irq(pcr
->irq
);
1241 ret
= rtsx_pci_init_chip(pcr
);
1245 for (i
= 0; i
< ARRAY_SIZE(rtsx_pcr_cells
); i
++) {
1246 rtsx_pcr_cells
[i
].platform_data
= handle
;
1247 rtsx_pcr_cells
[i
].pdata_size
= sizeof(*handle
);
1249 ret
= mfd_add_devices(&pcidev
->dev
, pcr
->id
, rtsx_pcr_cells
,
1250 ARRAY_SIZE(rtsx_pcr_cells
), NULL
, 0, NULL
);
1254 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1259 free_irq(pcr
->irq
, (void *)pcr
);
1262 pci_disable_msi(pcr
->pci
);
1263 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1264 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1266 iounmap(pcr
->remap_addr
);
1272 pci_release_regions(pcidev
);
1274 pci_disable_device(pcidev
);
1279 static void rtsx_pci_remove(struct pci_dev
*pcidev
)
1281 struct pcr_handle
*handle
= pci_get_drvdata(pcidev
);
1282 struct rtsx_pcr
*pcr
= handle
->pcr
;
1284 pcr
->remove_pci
= true;
1286 /* Disable interrupts at the pcr level */
1287 spin_lock_irq(&pcr
->lock
);
1288 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
1290 spin_unlock_irq(&pcr
->lock
);
1292 cancel_delayed_work_sync(&pcr
->carddet_work
);
1293 cancel_delayed_work_sync(&pcr
->idle_work
);
1295 mfd_remove_devices(&pcidev
->dev
);
1297 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1298 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1299 free_irq(pcr
->irq
, (void *)pcr
);
1301 pci_disable_msi(pcr
->pci
);
1302 iounmap(pcr
->remap_addr
);
1304 pci_release_regions(pcidev
);
1305 pci_disable_device(pcidev
);
1307 spin_lock(&rtsx_pci_lock
);
1308 idr_remove(&rtsx_pci_idr
, pcr
->id
);
1309 spin_unlock(&rtsx_pci_lock
);
1315 dev_dbg(&(pcidev
->dev
),
1316 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1317 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1322 static int rtsx_pci_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1324 struct pcr_handle
*handle
;
1325 struct rtsx_pcr
*pcr
;
1327 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1329 handle
= pci_get_drvdata(pcidev
);
1332 cancel_delayed_work(&pcr
->carddet_work
);
1333 cancel_delayed_work(&pcr
->idle_work
);
1335 mutex_lock(&pcr
->pcr_mutex
);
1337 rtsx_pci_power_off(pcr
, HOST_ENTER_S3
);
1339 pci_save_state(pcidev
);
1340 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1341 pci_disable_device(pcidev
);
1342 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1344 mutex_unlock(&pcr
->pcr_mutex
);
1348 static int rtsx_pci_resume(struct pci_dev
*pcidev
)
1350 struct pcr_handle
*handle
;
1351 struct rtsx_pcr
*pcr
;
1354 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1356 handle
= pci_get_drvdata(pcidev
);
1359 mutex_lock(&pcr
->pcr_mutex
);
1361 pci_set_power_state(pcidev
, PCI_D0
);
1362 pci_restore_state(pcidev
);
1363 ret
= pci_enable_device(pcidev
);
1366 pci_set_master(pcidev
);
1368 ret
= rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x00);
1372 ret
= rtsx_pci_init_hw(pcr
);
1376 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1379 mutex_unlock(&pcr
->pcr_mutex
);
1383 static void rtsx_pci_shutdown(struct pci_dev
*pcidev
)
1385 struct pcr_handle
*handle
;
1386 struct rtsx_pcr
*pcr
;
1388 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1390 handle
= pci_get_drvdata(pcidev
);
1392 rtsx_pci_power_off(pcr
, HOST_ENTER_S1
);
1394 pci_disable_device(pcidev
);
1397 #else /* CONFIG_PM */
1399 #define rtsx_pci_suspend NULL
1400 #define rtsx_pci_resume NULL
1401 #define rtsx_pci_shutdown NULL
1403 #endif /* CONFIG_PM */
1405 static struct pci_driver rtsx_pci_driver
= {
1406 .name
= DRV_NAME_RTSX_PCI
,
1407 .id_table
= rtsx_pci_ids
,
1408 .probe
= rtsx_pci_probe
,
1409 .remove
= rtsx_pci_remove
,
1410 .suspend
= rtsx_pci_suspend
,
1411 .resume
= rtsx_pci_resume
,
1412 .shutdown
= rtsx_pci_shutdown
,
1414 module_pci_driver(rtsx_pci_driver
);
1416 MODULE_LICENSE("GPL");
1417 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1418 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");