drivers/misc/cxl/cxl.h

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #ifndef _CXL_H_
  11 #define _CXL_H_
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/semaphore.h>
  15 #include <linux/device.h>
  16 #include <linux/types.h>
  17 #include <linux/cdev.h>
  18 #include <linux/pid.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <linux/fs.h>
  22 #include <asm/cputable.h>
  23 #include <asm/mmu.h>
  24 #include <asm/reg.h>
  25 #include <misc/cxl-base.h>
  26
  27 #include <uapi/misc/cxl.h>
  28
  29 extern uint cxl_verbose;
  30
  31 #define CXL_TIMEOUT 5
  32
  33 /*
  34  * Bump version each time a user API change is made, whether it is
  35  * backwards compatible ot not.
  36  */
  37 #define CXL_API_VERSION 2
  38 #define CXL_API_VERSION_COMPATIBLE 1
  39
  40 /*
  41  * Opaque types to avoid accidentally passing registers for the wrong MMIO
  42  *
  43  * At the end of the day, I'm not married to using typedef here, but it might
  44  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  45  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  46  *
  47  * I'm quite happy if these are changed back to #defines before upstreaming, it
  48  * should be little more than a regexp search+replace operation in this file.
  49  */
  50 typedef struct {
  51         const int x;
  52 } cxl_p1_reg_t;
  53 typedef struct {
  54         const int x;
  55 } cxl_p1n_reg_t;
  56 typedef struct {
  57         const int x;
  58 } cxl_p2n_reg_t;
  59 #define cxl_reg_off(reg) \
  60         (reg.x)
  61
  62 /* Memory maps. Ref CXL Appendix A */
  63
  64 /* PSL Privilege 1 Memory Map */
  65 /* Configuration and Control area */
  66 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  67 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  68 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  69 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  70 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  71 /* Downloading */
  72 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  73 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  74
  75 /* PSL Lookaside Buffer Management Area */
  76 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  77 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  78 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  79 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  80 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  81 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  82
  83 /* 0x00C0:7EFF Implementation dependent area */
  84 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  85 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  86 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  87 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  88 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  89 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  90 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  91 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  92 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  93 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  94 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
  95 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
  96
  97 /* PSL Slice Privilege 1 Memory Map */
  98 /* Configuration Area */
  99 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 100 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 101 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 102 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 103 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 104 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 105 /* Memory Management and Lookaside Buffer Management */
 106 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 107 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 108 /* Pointer Area */
 109 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 110 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 111 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 112 /* Control Area */
 113 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 114 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 115 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 116 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 117 /* 0xC0:FF Implementation Dependent Area */
 118 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 119 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 120 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 121 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 122 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 123 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 124
 125 /* PSL Slice Privilege 2 Memory Map */
 126 /* Configuration and Control Area */
 127 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 128 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 129 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 130 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 131 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 132 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 133 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 134 /* Segment Lookaside Buffer Management */
 135 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 136 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 137 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 138 /* Interrupt Registers */
 139 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 140 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 141 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 142 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 143 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 144 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 145 /* AFU Registers */
 146 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 147 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 148 /* Work Element Descriptor */
 149 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 150 /* 0x0C0:FFF Implementation Dependent Area */
 151
 152 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 153 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 154 #define CXL_PSL_SPAP_Size_Shift 4
 155 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
 156
 157 /****** CXL_PSL_Control ****************************************************/
 158 #define CXL_PSL_Control_tb 0x0000000000000001ULL
 159
 160 /****** CXL_PSL_DLCNTL *****************************************************/
 161 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 162 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 163 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 164 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 165 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 166 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 167
 168 /****** CXL_PSL_SR_An ******************************************************/
 169 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 170 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 171 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 172 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 173 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 174 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 175 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 176 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 177 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 178 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 179 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 180
 181 /****** CXL_PSL_LLCMD_An ****************************************************/
 182 #define CXL_LLCMD_TERMINATE   0x0001000000000000ULL
 183 #define CXL_LLCMD_REMOVE      0x0002000000000000ULL
 184 #define CXL_LLCMD_SUSPEND     0x0003000000000000ULL
 185 #define CXL_LLCMD_RESUME      0x0004000000000000ULL
 186 #define CXL_LLCMD_ADD         0x0005000000000000ULL
 187 #define CXL_LLCMD_UPDATE      0x0006000000000000ULL
 188 #define CXL_LLCMD_HANDLE_MASK 0x000000000000ffffULL
 189
 190 /****** CXL_PSL_ID_An ****************************************************/
 191 #define CXL_PSL_ID_An_F (1ull << (63-31))
 192 #define CXL_PSL_ID_An_L (1ull << (63-30))
 193
 194 /****** CXL_PSL_SCNTL_An ****************************************************/
 195 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 196 /* Programming Modes: */
 197 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 198 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 199 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 200 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 201 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 202 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 203 /* Purge Status (ro) */
 204 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 205 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 206 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 207 /* Purge */
 208 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 209 /* Suspend Status (ro) */
 210 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 211 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 212 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 213 /* Suspend Control */
 214 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 215
 216 /* AFU Slice Enable Status (ro) */
 217 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 218 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 219 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 220 /* AFU Slice Enable */
 221 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 222 /* AFU Slice Reset status (ro) */
 223 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 224 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 225 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 226 /* AFU Slice Reset */
 227 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 228
 229 /****** CXL_SSTP0/1_An ******************************************************/
 230 /* These top bits are for the segment that CONTAINS the segment table */
 231 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 232 #define CXL_SSTP0_An_KS             (1ull << (63-2))
 233 #define CXL_SSTP0_An_KP             (1ull << (63-3))
 234 #define CXL_SSTP0_An_N              (1ull << (63-4))
 235 #define CXL_SSTP0_An_L              (1ull << (63-5))
 236 #define CXL_SSTP0_An_C              (1ull << (63-6))
 237 #define CXL_SSTP0_An_TA             (1ull << (63-7))
 238 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 239 /* And finally, the virtual address & size of the segment table: */
 240 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 241 #define CXL_SSTP0_An_SegTableSize_MASK \
 242         (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 243 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 244 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 245 #define CXL_SSTP1_An_V              (1ull << (63-63))
 246
 247 /****** CXL_PSL_SLBIE_[An] **************************************************/
 248 /* write: */
 249 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 250 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 251 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 252 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 253 /* read: */
 254 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 255 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 256
 257 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
 258 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 259
 260 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
 261 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 262 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 263 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 264
 265 /****** CXL_PSL_AFUSEL ******************************************************/
 266 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 267
 268 /****** CXL_PSL_DSISR_An ****************************************************/
 269 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 270 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 271 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 272 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 273 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 274 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 275 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 276 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 277 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 278 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 279 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 280 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 281 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 282 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 283 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 284
 285 /****** CXL_PSL_TFC_An ******************************************************/
 286 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 287 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 288 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 289 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 290
 291 /* cxl_process_element->software_status */
 292 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 293 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 294 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 295 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 296
 297 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 298  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 299  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 300  * of the hang pulse frequency.
 301  */
 302 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 303
 304 /* SPA->sw_command_status */
 305 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 306 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 307 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 308 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 309 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 310 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 311 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 312 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 313 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 314 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 315 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 316 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 317 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 318 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 319 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 320 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 321
 322 #define CXL_MAX_SLICES 4
 323 #define MAX_AFU_MMIO_REGS 3
 324
 325 #define CXL_MODE_TIME_SLICED 0x4
 326 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 327
 328 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
 329 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
 330 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
 331
 332 enum cxl_context_status {
 333         CLOSED,
 334         OPENED,
 335         STARTED
 336 };
 337
 338 enum prefault_modes {
 339         CXL_PREFAULT_NONE,
 340         CXL_PREFAULT_WED,
 341         CXL_PREFAULT_ALL,
 342 };
 343
 344 enum cxl_attrs {
 345         CXL_ADAPTER_ATTRS,
 346         CXL_AFU_MASTER_ATTRS,
 347         CXL_AFU_ATTRS,
 348 };
 349
 350 struct cxl_sste {
 351         __be64 esid_data;
 352         __be64 vsid_data;
 353 };
 354
 355 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 356 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 357
 358 struct cxl_afu_native {
 359         void __iomem *p1n_mmio;
 360         void __iomem *afu_desc_mmio;
 361         irq_hw_number_t psl_hwirq;
 362         unsigned int psl_virq;
 363         struct mutex spa_mutex;
 364         /*
 365          * Only the first part of the SPA is used for the process element
 366          * linked list. The only other part that software needs to worry about
 367          * is sw_command_status, which we store a separate pointer to.
 368          * Everything else in the SPA is only used by hardware
 369          */
 370         struct cxl_process_element *spa;
 371         __be64 *sw_command_status;
 372         unsigned int spa_size;
 373         int spa_order;
 374         int spa_max_procs;
 375         u64 pp_offset;
 376 };
 377
 378 struct cxl_afu_guest {
 379         u64 handle;
 380         phys_addr_t p2n_phys;
 381         u64 p2n_size;
 382         int max_ints;
 383         struct mutex recovery_lock;
 384         int previous_state;
 385 };
 386
 387 struct cxl_afu {
 388         struct cxl_afu_native *native;
 389         struct cxl_afu_guest *guest;
 390         irq_hw_number_t serr_hwirq;
 391         unsigned int serr_virq;
 392         char *psl_irq_name;
 393         char *err_irq_name;
 394         void __iomem *p2n_mmio;
 395         phys_addr_t psn_phys;
 396         u64 pp_size;
 397
 398         struct cxl *adapter;
 399         struct device dev;
 400         struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 401         struct device *chardev_s, *chardev_m, *chardev_d;
 402         struct idr contexts_idr;
 403         struct dentry *debugfs;
 404         struct mutex contexts_lock;
 405         spinlock_t afu_cntl_lock;
 406
 407         /* AFU error buffer fields and bin attribute for sysfs */
 408         u64 eb_len, eb_offset;
 409         struct bin_attribute attr_eb;
 410
 411         /* pointer to the vphb */
 412         struct pci_controller *phb;
 413
 414         int pp_irqs;
 415         int irqs_max;
 416         int num_procs;
 417         int max_procs_virtualised;
 418         int slice;
 419         int modes_supported;
 420         int current_mode;
 421         int crs_num;
 422         u64 crs_len;
 423         u64 crs_offset;
 424         struct list_head crs;
 425         enum prefault_modes prefault_mode;
 426         bool psa;
 427         bool pp_psa;
 428         bool enabled;
 429 };
 430
 431 /* AFU refcount management */
 432 static inline struct cxl_afu *cxl_afu_get(struct cxl_afu *afu)
 433 {
 434
 435         return (get_device(&afu->dev) == NULL) ? NULL : afu;
 436 }
 437
 438 static inline void  cxl_afu_put(struct cxl_afu *afu)
 439 {
 440         put_device(&afu->dev);
 441 }
 442
 443
 444 struct cxl_irq_name {
 445         struct list_head list;
 446         char *name;
 447 };
 448
 449 struct irq_avail {
 450         irq_hw_number_t offset;
 451         irq_hw_number_t range;
 452         unsigned long   *bitmap;
 453 };
 454
 455 /*
 456  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 457  * of these per AFU.  If in AFU directed there can be lots of these.
 458  */
 459 struct cxl_context {
 460         struct cxl_afu *afu;
 461
 462         /* Problem state MMIO */
 463         phys_addr_t psn_phys;
 464         u64 psn_size;
 465
 466         /* Used to unmap any mmaps when force detaching */
 467         struct address_space *mapping;
 468         struct mutex mapping_lock;
 469         struct page *ff_page;
 470         bool mmio_err_ff;
 471         bool kernelapi;
 472
 473         spinlock_t sste_lock; /* Protects segment table entries */
 474         struct cxl_sste *sstp;
 475         u64 sstp0, sstp1;
 476         unsigned int sst_size, sst_lru;
 477
 478         wait_queue_head_t wq;
 479         /* pid of the group leader associated with the pid */
 480         struct pid *glpid;
 481         /* use mm context associated with this pid for ds faults */
 482         struct pid *pid;
 483         spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 484         /* Only used in PR mode */
 485         u64 process_token;
 486
 487         unsigned long *irq_bitmap; /* Accessed from IRQ context */
 488         struct cxl_irq_ranges irqs;
 489         struct list_head irq_names;
 490         u64 fault_addr;
 491         u64 fault_dsisr;
 492         u64 afu_err;
 493
 494         /*
 495          * This status and it's lock pretects start and detach context
 496          * from racing.  It also prevents detach from racing with
 497          * itself
 498          */
 499         enum cxl_context_status status;
 500         struct mutex status_mutex;
 501
 502
 503         /* XXX: Is it possible to need multiple work items at once? */
 504         struct work_struct fault_work;
 505         u64 dsisr;
 506         u64 dar;
 507
 508         struct cxl_process_element *elem;
 509
 510         /*
 511          * pe is the process element handle, assigned by this driver when the
 512          * context is initialized.
 513          *
 514          * external_pe is the PE shown outside of cxl.
 515          * On bare-metal, pe=external_pe, because we decide what the handle is.
 516          * In a guest, we only find out about the pe used by pHyp when the
 517          * context is attached, and that's the value we want to report outside
 518          * of cxl.
 519          */
 520         int pe;
 521         int external_pe;
 522
 523         u32 irq_count;
 524         bool pe_inserted;
 525         bool master;
 526         bool kernel;
 527         bool pending_irq;
 528         bool pending_fault;
 529         bool pending_afu_err;
 530
 531         struct rcu_head rcu;
 532 };
 533
 534 struct cxl_native {
 535         u64 afu_desc_off;
 536         u64 afu_desc_size;
 537         void __iomem *p1_mmio;
 538         void __iomem *p2_mmio;
 539         irq_hw_number_t err_hwirq;
 540         unsigned int err_virq;
 541         u64 ps_off;
 542 };
 543
 544 struct cxl_guest {
 545         struct platform_device *pdev;
 546         int irq_nranges;
 547         struct cdev cdev;
 548         irq_hw_number_t irq_base_offset;
 549         struct irq_avail *irq_avail;
 550         spinlock_t irq_alloc_lock;
 551         u64 handle;
 552         char *status;
 553         u16 vendor;
 554         u16 device;
 555         u16 subsystem_vendor;
 556         u16 subsystem;
 557 };
 558
 559 struct cxl {
 560         struct cxl_native *native;
 561         struct cxl_guest *guest;
 562         spinlock_t afu_list_lock;
 563         struct cxl_afu *afu[CXL_MAX_SLICES];
 564         struct device dev;
 565         struct dentry *trace;
 566         struct dentry *psl_err_chk;
 567         struct dentry *debugfs;
 568         char *irq_name;
 569         struct bin_attribute cxl_attr;
 570         int adapter_num;
 571         int user_irqs;
 572         u64 ps_size;
 573         u16 psl_rev;
 574         u16 base_image;
 575         u8 vsec_status;
 576         u8 caia_major;
 577         u8 caia_minor;
 578         u8 slices;
 579         bool user_image_loaded;
 580         bool perst_loads_image;
 581         bool perst_select_user;
 582         bool perst_same_image;
 583 };
 584
 585 int cxl_pci_alloc_one_irq(struct cxl *adapter);
 586 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
 587 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 588 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 589 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 590 int cxl_update_image_control(struct cxl *adapter);
 591 int cxl_pci_reset(struct cxl *adapter);
 592 void cxl_pci_release_afu(struct device *dev);
 593 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 594
 595 /* common == phyp + powernv */
 596 struct cxl_process_element_common {
 597         __be32 tid;
 598         __be32 pid;
 599         __be64 csrp;
 600         __be64 aurp0;
 601         __be64 aurp1;
 602         __be64 sstp0;
 603         __be64 sstp1;
 604         __be64 amr;
 605         u8     reserved3[4];
 606         __be64 wed;
 607 } __packed;
 608
 609 /* just powernv */
 610 struct cxl_process_element {
 611         __be64 sr;
 612         __be64 SPOffset;
 613         __be64 sdr;
 614         __be64 haurp;
 615         __be32 ctxtime;
 616         __be16 ivte_offsets[4];
 617         __be16 ivte_ranges[4];
 618         __be32 lpid;
 619         struct cxl_process_element_common common;
 620         __be32 software_state;
 621 } __packed;
 622
 623 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
 624 {
 625         struct pci_dev *pdev;
 626
 627         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 628                 pdev = to_pci_dev(cxl->dev.parent);
 629                 return !pci_channel_offline(pdev);
 630         }
 631         return true;
 632 }
 633
 634 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 635 {
 636         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 637         return cxl->native->p1_mmio + cxl_reg_off(reg);
 638 }
 639
 640 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 641 {
 642         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 643                 out_be64(_cxl_p1_addr(cxl, reg), val);
 644 }
 645
 646 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 647 {
 648         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 649                 return in_be64(_cxl_p1_addr(cxl, reg));
 650         else
 651                 return ~0ULL;
 652 }
 653
 654 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 655 {
 656         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 657         return afu->native->p1n_mmio + cxl_reg_off(reg);
 658 }
 659
 660 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 661 {
 662         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 663                 out_be64(_cxl_p1n_addr(afu, reg), val);
 664 }
 665
 666 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 667 {
 668         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 669                 return in_be64(_cxl_p1n_addr(afu, reg));
 670         else
 671                 return ~0ULL;
 672 }
 673
 674 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 675 {
 676         return afu->p2n_mmio + cxl_reg_off(reg);
 677 }
 678
 679 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 680 {
 681         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 682                 out_be64(_cxl_p2n_addr(afu, reg), val);
 683 }
 684
 685 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 686 {
 687         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 688                 return in_be64(_cxl_p2n_addr(afu, reg));
 689         else
 690                 return ~0ULL;
 691 }
 692
 693 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 694                                 loff_t off, size_t count);
 695
 696
 697 struct cxl_calls {
 698         void (*cxl_slbia)(struct mm_struct *mm);
 699         struct module *owner;
 700 };
 701 int register_cxl_calls(struct cxl_calls *calls);
 702 void unregister_cxl_calls(struct cxl_calls *calls);
 703 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
 704
 705 void cxl_remove_adapter_nr(struct cxl *adapter);
 706
 707 int cxl_alloc_spa(struct cxl_afu *afu);
 708 void cxl_release_spa(struct cxl_afu *afu);
 709
 710 dev_t cxl_get_dev(void);
 711 int cxl_file_init(void);
 712 void cxl_file_exit(void);
 713 int cxl_register_adapter(struct cxl *adapter);
 714 int cxl_register_afu(struct cxl_afu *afu);
 715 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 716 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 717 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 718 void cxl_chardev_afu_remove(struct cxl_afu *afu);
 719
 720 void cxl_context_detach_all(struct cxl_afu *afu);
 721 void cxl_context_free(struct cxl_context *ctx);
 722 void cxl_context_detach(struct cxl_context *ctx);
 723
 724 int cxl_sysfs_adapter_add(struct cxl *adapter);
 725 void cxl_sysfs_adapter_remove(struct cxl *adapter);
 726 int cxl_sysfs_afu_add(struct cxl_afu *afu);
 727 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 728 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 729 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 730
 731 struct cxl *cxl_alloc_adapter(void);
 732 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
 733 int cxl_afu_select_best_mode(struct cxl_afu *afu);
 734
 735 int cxl_native_register_psl_irq(struct cxl_afu *afu);
 736 void cxl_native_release_psl_irq(struct cxl_afu *afu);
 737 int cxl_native_register_psl_err_irq(struct cxl *adapter);
 738 void cxl_native_release_psl_err_irq(struct cxl *adapter);
 739 int cxl_native_register_serr_irq(struct cxl_afu *afu);
 740 void cxl_native_release_serr_irq(struct cxl_afu *afu);
 741 int afu_register_irqs(struct cxl_context *ctx, u32 count);
 742 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 743 void afu_irq_name_free(struct cxl_context *ctx);
 744
 745 int cxl_debugfs_init(void);
 746 void cxl_debugfs_exit(void);
 747 int cxl_debugfs_adapter_add(struct cxl *adapter);
 748 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 749 int cxl_debugfs_afu_add(struct cxl_afu *afu);
 750 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 751
 752 void cxl_handle_fault(struct work_struct *work);
 753 void cxl_prefault(struct cxl_context *ctx, u64 wed);
 754
 755 struct cxl *get_cxl_adapter(int num);
 756 int cxl_alloc_sst(struct cxl_context *ctx);
 757 void cxl_dump_debug_buffer(void *addr, size_t size);
 758
 759 void init_cxl_native(void);
 760
 761 struct cxl_context *cxl_context_alloc(void);
 762 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
 763                      struct address_space *mapping);
 764 void cxl_context_free(struct cxl_context *ctx);
 765 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
 766 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
 767                          irq_handler_t handler, void *cookie, const char *name);
 768 void cxl_unmap_irq(unsigned int virq, void *cookie);
 769 int __detach_context(struct cxl_context *ctx);
 770
 771 /*
 772  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
 773  * in PAPR.
 774  * A word about endianness: a pointer to this structure is passed when
 775  * calling the hcall. However, it is not a block of memory filled up by
 776  * the hypervisor. The return values are found in registers, and copied
 777  * one by one when returning from the hcall. See the end of the call to
 778  * plpar_hcall9() in hvCall.S
 779  * As a consequence:
 780  * - we don't need to do any endianness conversion
 781  * - the pid and tid are an exception. They are 32-bit values returned in
 782  *   the same 64-bit register. So we do need to worry about byte ordering.
 783  */
 784 struct cxl_irq_info {
 785         u64 dsisr;
 786         u64 dar;
 787         u64 dsr;
 788 #ifndef CONFIG_CPU_LITTLE_ENDIAN
 789         u32 pid;
 790         u32 tid;
 791 #else
 792         u32 tid;
 793         u32 pid;
 794 #endif
 795         u64 afu_err;
 796         u64 errstat;
 797         u64 proc_handle;
 798         u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
 799 };
 800
 801 void cxl_assign_psn_space(struct cxl_context *ctx);
 802 irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 803 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
 804                         void *cookie, irq_hw_number_t *dest_hwirq,
 805                         unsigned int *dest_virq, const char *name);
 806
 807 int cxl_check_error(struct cxl_afu *afu);
 808 int cxl_afu_slbia(struct cxl_afu *afu);
 809 int cxl_tlb_slb_invalidate(struct cxl *adapter);
 810 int cxl_afu_disable(struct cxl_afu *afu);
 811 int cxl_psl_purge(struct cxl_afu *afu);
 812
 813 void cxl_stop_trace(struct cxl *cxl);
 814 int cxl_pci_vphb_add(struct cxl_afu *afu);
 815 void cxl_pci_vphb_remove(struct cxl_afu *afu);
 816
 817 extern struct pci_driver cxl_pci_driver;
 818 extern struct platform_driver cxl_of_driver;
 819 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
 820
 821 int afu_open(struct inode *inode, struct file *file);
 822 int afu_release(struct inode *inode, struct file *file);
 823 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 824 int afu_mmap(struct file *file, struct vm_area_struct *vm);
 825 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
 826 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
 827 extern const struct file_operations afu_fops;
 828
 829 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
 830 void cxl_guest_remove_adapter(struct cxl *adapter);
 831 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
 832 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
 833 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 834 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
 835 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
 836 void cxl_guest_remove_afu(struct cxl_afu *afu);
 837 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
 838 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
 839 int cxl_guest_add_chardev(struct cxl *adapter);
 840 void cxl_guest_remove_chardev(struct cxl *adapter);
 841 void cxl_guest_reload_module(struct cxl *adapter);
 842 int cxl_of_probe(struct platform_device *pdev);
 843
 844 struct cxl_backend_ops {
 845         struct module *module;
 846         int (*adapter_reset)(struct cxl *adapter);
 847         int (*alloc_one_irq)(struct cxl *adapter);
 848         void (*release_one_irq)(struct cxl *adapter, int hwirq);
 849         int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
 850                                 struct cxl *adapter, unsigned int num);
 851         void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
 852                                 struct cxl *adapter);
 853         int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
 854                         unsigned int virq);
 855         irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
 856                                         u64 dsisr, u64 errstat);
 857         irqreturn_t (*psl_interrupt)(int irq, void *data);
 858         int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
 859         void (*irq_wait)(struct cxl_context *ctx);
 860         int (*attach_process)(struct cxl_context *ctx, bool kernel,
 861                         u64 wed, u64 amr);
 862         int (*detach_process)(struct cxl_context *ctx);
 863         bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
 864         bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
 865         void (*release_afu)(struct device *dev);
 866         ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
 867                                 loff_t off, size_t count);
 868         int (*afu_check_and_enable)(struct cxl_afu *afu);
 869         int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
 870         int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
 871         int (*afu_reset)(struct cxl_afu *afu);
 872         int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
 873         int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
 874         int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
 875         int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
 876         int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
 877         int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
 878         int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
 879         ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
 880 };
 881 extern const struct cxl_backend_ops cxl_native_ops;
 882 extern const struct cxl_backend_ops cxl_guest_ops;
 883 extern const struct cxl_backend_ops *cxl_ops;
 884
 885 /* check if the given pci_dev is on the the cxl vphb bus */
 886 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
 887 #endif