drivers/misc/mei/hw-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16
  17 #include <linux/pci.h>
  18
  19 #include <linux/kthread.h>
  20 #include <linux/interrupt.h>
  21
  22 #include "mei_dev.h"
  23 #include "hw-me.h"
  24
  25 #include "hbm.h"
  26
  27
  28 /**
  29  * mei_reg_read - Reads 32bit data from the mei device
  30  *
  31  * @dev: the device structure
  32  * @offset: offset from which to read the data
  33  *
  34  * returns register value (u32)
  35  */
  36 static inline u32 mei_reg_read(const struct mei_me_hw *hw,
  37                                unsigned long offset)
  38 {
  39         return ioread32(hw->mem_addr + offset);
  40 }
  41
  42
  43 /**
  44  * mei_reg_write - Writes 32bit data to the mei device
  45  *
  46  * @dev: the device structure
  47  * @offset: offset from which to write the data
  48  * @value: register value to write (u32)
  49  */
  50 static inline void mei_reg_write(const struct mei_me_hw *hw,
  51                                  unsigned long offset, u32 value)
  52 {
  53         iowrite32(value, hw->mem_addr + offset);
  54 }
  55
  56 /**
  57  * mei_mecbrw_read - Reads 32bit data from ME circular buffer
  58  *  read window register
  59  *
  60  * @dev: the device structure
  61  *
  62  * returns ME_CB_RW register value (u32)
  63  */
  64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
  65 {
  66         return mei_reg_read(to_me_hw(dev), ME_CB_RW);
  67 }
  68 /**
  69  * mei_mecsr_read - Reads 32bit data from the ME CSR
  70  *
  71  * @dev: the device structure
  72  *
  73  * returns ME_CSR_HA register value (u32)
  74  */
  75 static inline u32 mei_mecsr_read(const struct mei_me_hw *hw)
  76 {
  77         return mei_reg_read(hw, ME_CSR_HA);
  78 }
  79
  80 /**
  81  * mei_hcsr_read - Reads 32bit data from the host CSR
  82  *
  83  * @dev: the device structure
  84  *
  85  * returns H_CSR register value (u32)
  86  */
  87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
  88 {
  89         return mei_reg_read(hw, H_CSR);
  90 }
  91
  92 /**
  93  * mei_hcsr_set - writes H_CSR register to the mei device,
  94  * and ignores the H_IS bit for it is write-one-to-zero.
  95  *
  96  * @dev: the device structure
  97  */
  98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
  99 {
 100         hcsr &= ~H_IS;
 101         mei_reg_write(hw, H_CSR, hcsr);
 102 }
 103
 104
 105 /**
 106  * me_hw_config - configure hw dependent settings
 107  *
 108  * @dev: mei device
 109  */
 110 static void mei_me_hw_config(struct mei_device *dev)
 111 {
 112         u32 hcsr = mei_hcsr_read(to_me_hw(dev));
 113         /* Doesn't change in runtime */
 114         dev->hbuf_depth = (hcsr & H_CBD) >> 24;
 115 }
 116 /**
 117  * mei_clear_interrupts - clear and stop interrupts
 118  *
 119  * @dev: the device structure
 120  */
 121 static void mei_me_intr_clear(struct mei_device *dev)
 122 {
 123         struct mei_me_hw *hw = to_me_hw(dev);
 124         u32 hcsr = mei_hcsr_read(hw);
 125         if ((hcsr & H_IS) == H_IS)
 126                 mei_reg_write(hw, H_CSR, hcsr);
 127 }
 128 /**
 129  * mei_me_intr_enable - enables mei device interrupts
 130  *
 131  * @dev: the device structure
 132  */
 133 static void mei_me_intr_enable(struct mei_device *dev)
 134 {
 135         struct mei_me_hw *hw = to_me_hw(dev);
 136         u32 hcsr = mei_hcsr_read(hw);
 137         hcsr |= H_IE;
 138         mei_hcsr_set(hw, hcsr);
 139 }
 140
 141 /**
 142  * mei_disable_interrupts - disables mei device interrupts
 143  *
 144  * @dev: the device structure
 145  */
 146 static void mei_me_intr_disable(struct mei_device *dev)
 147 {
 148         struct mei_me_hw *hw = to_me_hw(dev);
 149         u32 hcsr = mei_hcsr_read(hw);
 150         hcsr  &= ~H_IE;
 151         mei_hcsr_set(hw, hcsr);
 152 }
 153
 154 /**
 155  * mei_me_hw_reset - resets fw via mei csr register.
 156  *
 157  * @dev: the device structure
 158  * @interrupts_enabled: if interrupt should be enabled after reset.
 159  */
 160 static void mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
 161 {
 162         struct mei_me_hw *hw = to_me_hw(dev);
 163         u32 hcsr = mei_hcsr_read(hw);
 164
 165         dev_dbg(&dev->pdev->dev, "before reset HCSR = 0x%08x.\n", hcsr);
 166
 167         hcsr |= (H_RST | H_IG);
 168
 169         if (intr_enable)
 170                 hcsr |= H_IE;
 171         else
 172                 hcsr &= ~H_IE;
 173
 174         mei_hcsr_set(hw, hcsr);
 175
 176         hcsr = mei_hcsr_read(hw) | H_IG;
 177         hcsr &= ~H_RST;
 178
 179         mei_hcsr_set(hw, hcsr);
 180
 181         hcsr = mei_hcsr_read(hw);
 182
 183         dev_dbg(&dev->pdev->dev, "current HCSR = 0x%08x.\n", hcsr);
 184 }
 185
 186 /**
 187  * mei_me_host_set_ready - enable device
 188  *
 189  * @dev - mei device
 190  * returns bool
 191  */
 192
 193 static void mei_me_host_set_ready(struct mei_device *dev)
 194 {
 195         struct mei_me_hw *hw = to_me_hw(dev);
 196         hw->host_hw_state |= H_IE | H_IG | H_RDY;
 197         mei_hcsr_set(hw, hw->host_hw_state);
 198 }
 199 /**
 200  * mei_me_host_is_ready - check whether the host has turned ready
 201  *
 202  * @dev - mei device
 203  * returns bool
 204  */
 205 static bool mei_me_host_is_ready(struct mei_device *dev)
 206 {
 207         struct mei_me_hw *hw = to_me_hw(dev);
 208         hw->host_hw_state = mei_hcsr_read(hw);
 209         return (hw->host_hw_state & H_RDY) == H_RDY;
 210 }
 211
 212 /**
 213  * mei_me_hw_is_ready - check whether the me(hw) has turned ready
 214  *
 215  * @dev - mei device
 216  * returns bool
 217  */
 218 static bool mei_me_hw_is_ready(struct mei_device *dev)
 219 {
 220         struct mei_me_hw *hw = to_me_hw(dev);
 221         hw->me_hw_state = mei_mecsr_read(hw);
 222         return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
 223 }
 224
 225 /**
 226  * mei_hbuf_filled_slots - gets number of device filled buffer slots
 227  *
 228  * @dev: the device structure
 229  *
 230  * returns number of filled slots
 231  */
 232 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
 233 {
 234         struct mei_me_hw *hw = to_me_hw(dev);
 235         char read_ptr, write_ptr;
 236
 237         hw->host_hw_state = mei_hcsr_read(hw);
 238
 239         read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
 240         write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
 241
 242         return (unsigned char) (write_ptr - read_ptr);
 243 }
 244
 245 /**
 246  * mei_hbuf_is_empty - checks if host buffer is empty.
 247  *
 248  * @dev: the device structure
 249  *
 250  * returns true if empty, false - otherwise.
 251  */
 252 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
 253 {
 254         return mei_hbuf_filled_slots(dev) == 0;
 255 }
 256
 257 /**
 258  * mei_me_hbuf_empty_slots - counts write empty slots.
 259  *
 260  * @dev: the device structure
 261  *
 262  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
 263  */
 264 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
 265 {
 266         unsigned char filled_slots, empty_slots;
 267
 268         filled_slots = mei_hbuf_filled_slots(dev);
 269         empty_slots = dev->hbuf_depth - filled_slots;
 270
 271         /* check for overflow */
 272         if (filled_slots > dev->hbuf_depth)
 273                 return -EOVERFLOW;
 274
 275         return empty_slots;
 276 }
 277
 278 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
 279 {
 280         return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
 281 }
 282
 283
 284 /**
 285  * mei_write_message - writes a message to mei device.
 286  *
 287  * @dev: the device structure
 288  * @header: mei HECI header of message
 289  * @buf: message payload will be written
 290  *
 291  * This function returns -EIO if write has failed
 292  */
 293 static int mei_me_write_message(struct mei_device *dev,
 294                         struct mei_msg_hdr *header,
 295                         unsigned char *buf)
 296 {
 297         struct mei_me_hw *hw = to_me_hw(dev);
 298         unsigned long rem, dw_cnt;
 299         unsigned long length = header->length;
 300         u32 *reg_buf = (u32 *)buf;
 301         u32 hcsr;
 302         int i;
 303         int empty_slots;
 304
 305         dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 306
 307         empty_slots = mei_hbuf_empty_slots(dev);
 308         dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
 309
 310         dw_cnt = mei_data2slots(length);
 311         if (empty_slots < 0 || dw_cnt > empty_slots)
 312                 return -EIO;
 313
 314         mei_reg_write(hw, H_CB_WW, *((u32 *) header));
 315
 316         for (i = 0; i < length / 4; i++)
 317                 mei_reg_write(hw, H_CB_WW, reg_buf[i]);
 318
 319         rem = length & 0x3;
 320         if (rem > 0) {
 321                 u32 reg = 0;
 322                 memcpy(&reg, &buf[length - rem], rem);
 323                 mei_reg_write(hw, H_CB_WW, reg);
 324         }
 325
 326         hcsr = mei_hcsr_read(hw) | H_IG;
 327         mei_hcsr_set(hw, hcsr);
 328         if (!mei_me_hw_is_ready(dev))
 329                 return -EIO;
 330
 331         return 0;
 332 }
 333
 334 /**
 335  * mei_me_count_full_read_slots - counts read full slots.
 336  *
 337  * @dev: the device structure
 338  *
 339  * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
 340  */
 341 static int mei_me_count_full_read_slots(struct mei_device *dev)
 342 {
 343         struct mei_me_hw *hw = to_me_hw(dev);
 344         char read_ptr, write_ptr;
 345         unsigned char buffer_depth, filled_slots;
 346
 347         hw->me_hw_state = mei_mecsr_read(hw);
 348         buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
 349         read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
 350         write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
 351         filled_slots = (unsigned char) (write_ptr - read_ptr);
 352
 353         /* check for overflow */
 354         if (filled_slots > buffer_depth)
 355                 return -EOVERFLOW;
 356
 357         dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
 358         return (int)filled_slots;
 359 }
 360
 361 /**
 362  * mei_me_read_slots - reads a message from mei device.
 363  *
 364  * @dev: the device structure
 365  * @buffer: message buffer will be written
 366  * @buffer_length: message size will be read
 367  */
 368 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
 369                     unsigned long buffer_length)
 370 {
 371         struct mei_me_hw *hw = to_me_hw(dev);
 372         u32 *reg_buf = (u32 *)buffer;
 373         u32 hcsr;
 374
 375         for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
 376                 *reg_buf++ = mei_me_mecbrw_read(dev);
 377
 378         if (buffer_length > 0) {
 379                 u32 reg = mei_me_mecbrw_read(dev);
 380                 memcpy(reg_buf, &reg, buffer_length);
 381         }
 382
 383         hcsr = mei_hcsr_read(hw) | H_IG;
 384         mei_hcsr_set(hw, hcsr);
 385         return 0;
 386 }
 387
 388 /**
 389  * mei_me_irq_quick_handler - The ISR of the MEI device
 390  *
 391  * @irq: The irq number
 392  * @dev_id: pointer to the device structure
 393  *
 394  * returns irqreturn_t
 395  */
 396
 397 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
 398 {
 399         struct mei_device *dev = (struct mei_device *) dev_id;
 400         struct mei_me_hw *hw = to_me_hw(dev);
 401         u32 csr_reg = mei_hcsr_read(hw);
 402
 403         if ((csr_reg & H_IS) != H_IS)
 404                 return IRQ_NONE;
 405
 406         /* clear H_IS bit in H_CSR */
 407         mei_reg_write(hw, H_CSR, csr_reg);
 408
 409         return IRQ_WAKE_THREAD;
 410 }
 411
 412 /**
 413  * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
 414  * processing.
 415  *
 416  * @irq: The irq number
 417  * @dev_id: pointer to the device structure
 418  *
 419  * returns irqreturn_t
 420  *
 421  */
 422 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
 423 {
 424         struct mei_device *dev = (struct mei_device *) dev_id;
 425         struct mei_cl_cb complete_list;
 426         struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
 427         struct mei_cl *cl;
 428         s32 slots;
 429         int rets;
 430         bool  bus_message_received;
 431
 432
 433         dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
 434         /* initialize our complete list */
 435         mutex_lock(&dev->device_lock);
 436         mei_io_list_init(&complete_list);
 437
 438         /* Ack the interrupt here
 439          * In case of MSI we don't go through the quick handler */
 440         if (pci_dev_msi_enabled(dev->pdev))
 441                 mei_clear_interrupts(dev);
 442
 443         /* check if ME wants a reset */
 444         if (!mei_hw_is_ready(dev) &&
 445             dev->dev_state != MEI_DEV_RESETING &&
 446             dev->dev_state != MEI_DEV_INITIALIZING) {
 447                 dev_dbg(&dev->pdev->dev, "FW not ready.\n");
 448                 mei_reset(dev, 1);
 449                 mutex_unlock(&dev->device_lock);
 450                 return IRQ_HANDLED;
 451         }
 452
 453         /*  check if we need to start the dev */
 454         if (!mei_host_is_ready(dev)) {
 455                 if (mei_hw_is_ready(dev)) {
 456                         dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
 457
 458                         mei_host_set_ready(dev);
 459
 460                         dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
 461                         /* link is established * start sending messages.  */
 462
 463                         dev->dev_state = MEI_DEV_INIT_CLIENTS;
 464
 465                         mei_hbm_start_req(dev);
 466                         mutex_unlock(&dev->device_lock);
 467                         return IRQ_HANDLED;
 468                 } else {
 469                         dev_dbg(&dev->pdev->dev, "FW not ready.\n");
 470                         mutex_unlock(&dev->device_lock);
 471                         return IRQ_HANDLED;
 472                 }
 473         }
 474         /* check slots available for reading */
 475         slots = mei_count_full_read_slots(dev);
 476         while (slots > 0) {
 477                 /* we have urgent data to send so break the read */
 478                 if (dev->wr_ext_msg.hdr.length)
 479                         break;
 480                 dev_dbg(&dev->pdev->dev, "slots =%08x\n", slots);
 481                 dev_dbg(&dev->pdev->dev, "call mei_irq_read_handler.\n");
 482                 rets = mei_irq_read_handler(dev, &complete_list, &slots);
 483                 if (rets)
 484                         goto end;
 485         }
 486         rets = mei_irq_write_handler(dev, &complete_list);
 487 end:
 488         dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
 489         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
 490
 491         bus_message_received = false;
 492         if (dev->recvd_msg && waitqueue_active(&dev->wait_recvd_msg)) {
 493                 dev_dbg(&dev->pdev->dev, "received waiting bus message\n");
 494                 bus_message_received = true;
 495         }
 496         mutex_unlock(&dev->device_lock);
 497         if (bus_message_received) {
 498                 dev_dbg(&dev->pdev->dev, "wake up dev->wait_recvd_msg\n");
 499                 wake_up_interruptible(&dev->wait_recvd_msg);
 500                 bus_message_received = false;
 501         }
 502         if (list_empty(&complete_list.list))
 503                 return IRQ_HANDLED;
 504
 505
 506         list_for_each_entry_safe(cb_pos, cb_next, &complete_list.list, list) {
 507                 cl = cb_pos->cl;
 508                 list_del(&cb_pos->list);
 509                 if (cl) {
 510                         if (cl != &dev->iamthif_cl) {
 511                                 dev_dbg(&dev->pdev->dev, "completing call back.\n");
 512                                 mei_irq_complete_handler(cl, cb_pos);
 513                                 cb_pos = NULL;
 514                         } else if (cl == &dev->iamthif_cl) {
 515                                 mei_amthif_complete(dev, cb_pos);
 516                         }
 517                 }
 518         }
 519         return IRQ_HANDLED;
 520 }
 521 static const struct mei_hw_ops mei_me_hw_ops = {
 522
 523         .host_set_ready = mei_me_host_set_ready,
 524         .host_is_ready = mei_me_host_is_ready,
 525
 526         .hw_is_ready = mei_me_hw_is_ready,
 527         .hw_reset = mei_me_hw_reset,
 528         .hw_config  = mei_me_hw_config,
 529
 530         .intr_clear = mei_me_intr_clear,
 531         .intr_enable = mei_me_intr_enable,
 532         .intr_disable = mei_me_intr_disable,
 533
 534         .hbuf_free_slots = mei_me_hbuf_empty_slots,
 535         .hbuf_is_ready = mei_me_hbuf_is_empty,
 536         .hbuf_max_len = mei_me_hbuf_max_len,
 537
 538         .write = mei_me_write_message,
 539
 540         .rdbuf_full_slots = mei_me_count_full_read_slots,
 541         .read_hdr = mei_me_mecbrw_read,
 542         .read = mei_me_read_slots
 543 };
 544
 545 /**
 546  * init_mei_device - allocates and initializes the mei device structure
 547  *
 548  * @pdev: The pci device structure
 549  *
 550  * returns The mei_device_device pointer on success, NULL on failure.
 551  */
 552 struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
 553 {
 554         struct mei_device *dev;
 555
 556         dev = kzalloc(sizeof(struct mei_device) +
 557                          sizeof(struct mei_me_hw), GFP_KERNEL);
 558         if (!dev)
 559                 return NULL;
 560
 561         mei_device_init(dev);
 562
 563         INIT_LIST_HEAD(&dev->wd_cl.link);
 564         INIT_LIST_HEAD(&dev->iamthif_cl.link);
 565         mei_io_list_init(&dev->amthif_cmd_list);
 566         mei_io_list_init(&dev->amthif_rd_complete_list);
 567
 568         INIT_DELAYED_WORK(&dev->timer_work, mei_timer);
 569         INIT_WORK(&dev->init_work, mei_host_client_init);
 570
 571         dev->ops = &mei_me_hw_ops;
 572
 573         dev->pdev = pdev;
 574         return dev;
 575 }
 576