Merge tag 'char-misc-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[deliverable/linux.git] / drivers / misc / mei / hw.h
1 /*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17 #ifndef _MEI_HW_TYPES_H_
18 #define _MEI_HW_TYPES_H_
19
20 #include <linux/uuid.h>
21
22 /*
23 * Timeouts
24 */
25 #define MEI_INTEROP_TIMEOUT (HZ * 7)
26 #define MEI_CONNECT_TIMEOUT 3 /* at least 2 seconds */
27
28 #define CONNECT_TIMEOUT 15 /* HPS definition */
29 #define INIT_CLIENTS_TIMEOUT 15 /* HPS definition */
30
31 #define IAMTHIF_STALL_TIMER 12 /* seconds */
32 #define IAMTHIF_READ_TIMER 10000 /* ms */
33
34 /*
35 * Internal Clients Number
36 */
37 #define MEI_WD_HOST_CLIENT_ID 1
38 #define MEI_IAMTHIF_HOST_CLIENT_ID 2
39
40 /*
41 * MEI device IDs
42 */
43 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
44 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
45 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
46 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
47
48 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
49 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
50
51 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
52 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
53 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
54 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
55 #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
56
57 #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
58 #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
59 #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
60 #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
61 #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
62
63 #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
64 #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
65 #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
66 #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
67
68 #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
69 #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
70 #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
71 #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
72
73 #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
74 #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
75
76 #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */
77 #define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */
78
79 #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */
80 #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */
81 #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */
82
83 #define MEI_DEV_ID_LPT 0x8C3A /* Lynx Point */
84 #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */
85 /*
86 * MEI HW Section
87 */
88
89 /* MEI registers */
90 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
91 #define H_CB_WW 0
92 /* H_CSR - Host Control Status register */
93 #define H_CSR 4
94 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
95 #define ME_CB_RW 8
96 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
97 #define ME_CSR_HA 0xC
98
99
100 /* register bits of H_CSR (Host Control Status register) */
101 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
102 #define H_CBD 0xFF000000
103 /* Host Circular Buffer Write Pointer */
104 #define H_CBWP 0x00FF0000
105 /* Host Circular Buffer Read Pointer */
106 #define H_CBRP 0x0000FF00
107 /* Host Reset */
108 #define H_RST 0x00000010
109 /* Host Ready */
110 #define H_RDY 0x00000008
111 /* Host Interrupt Generate */
112 #define H_IG 0x00000004
113 /* Host Interrupt Status */
114 #define H_IS 0x00000002
115 /* Host Interrupt Enable */
116 #define H_IE 0x00000001
117
118
119 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
120 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
121 access to ME_CBD */
122 #define ME_CBD_HRA 0xFF000000
123 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
124 #define ME_CBWP_HRA 0x00FF0000
125 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
126 #define ME_CBRP_HRA 0x0000FF00
127 /* ME Reset HRA - host read only access to ME_RST */
128 #define ME_RST_HRA 0x00000010
129 /* ME Ready HRA - host read only access to ME_RDY */
130 #define ME_RDY_HRA 0x00000008
131 /* ME Interrupt Generate HRA - host read only access to ME_IG */
132 #define ME_IG_HRA 0x00000004
133 /* ME Interrupt Status HRA - host read only access to ME_IS */
134 #define ME_IS_HRA 0x00000002
135 /* ME Interrupt Enable HRA - host read only access to ME_IE */
136 #define ME_IE_HRA 0x00000001
137
138 /*
139 * MEI Version
140 */
141 #define HBM_MINOR_VERSION 0
142 #define HBM_MAJOR_VERSION 1
143 #define HBM_TIMEOUT 1 /* 1 second */
144
145 /* Host bus message command opcode */
146 #define MEI_HBM_CMD_OP_MSK 0x7f
147 /* Host bus message command RESPONSE */
148 #define MEI_HBM_CMD_RES_MSK 0x80
149
150 /*
151 * MEI Bus Message Command IDs
152 */
153 #define HOST_START_REQ_CMD 0x01
154 #define HOST_START_RES_CMD 0x81
155
156 #define HOST_STOP_REQ_CMD 0x02
157 #define HOST_STOP_RES_CMD 0x82
158
159 #define ME_STOP_REQ_CMD 0x03
160
161 #define HOST_ENUM_REQ_CMD 0x04
162 #define HOST_ENUM_RES_CMD 0x84
163
164 #define HOST_CLIENT_PROPERTIES_REQ_CMD 0x05
165 #define HOST_CLIENT_PROPERTIES_RES_CMD 0x85
166
167 #define CLIENT_CONNECT_REQ_CMD 0x06
168 #define CLIENT_CONNECT_RES_CMD 0x86
169
170 #define CLIENT_DISCONNECT_REQ_CMD 0x07
171 #define CLIENT_DISCONNECT_RES_CMD 0x87
172
173 #define MEI_FLOW_CONTROL_CMD 0x08
174
175 /*
176 * MEI Stop Reason
177 * used by hbm_host_stop_request.reason
178 */
179 enum mei_stop_reason_types {
180 DRIVER_STOP_REQUEST = 0x00,
181 DEVICE_D1_ENTRY = 0x01,
182 DEVICE_D2_ENTRY = 0x02,
183 DEVICE_D3_ENTRY = 0x03,
184 SYSTEM_S1_ENTRY = 0x04,
185 SYSTEM_S2_ENTRY = 0x05,
186 SYSTEM_S3_ENTRY = 0x06,
187 SYSTEM_S4_ENTRY = 0x07,
188 SYSTEM_S5_ENTRY = 0x08
189 };
190
191 /*
192 * Client Connect Status
193 * used by hbm_client_connect_response.status
194 */
195 enum client_connect_status_types {
196 CCS_SUCCESS = 0x00,
197 CCS_NOT_FOUND = 0x01,
198 CCS_ALREADY_STARTED = 0x02,
199 CCS_OUT_OF_RESOURCES = 0x03,
200 CCS_MESSAGE_SMALL = 0x04
201 };
202
203 /*
204 * Client Disconnect Status
205 */
206 enum client_disconnect_status_types {
207 CDS_SUCCESS = 0x00
208 };
209
210 /*
211 * MEI BUS Interface Section
212 */
213 struct mei_msg_hdr {
214 u32 me_addr:8;
215 u32 host_addr:8;
216 u32 length:9;
217 u32 reserved:6;
218 u32 msg_complete:1;
219 } __packed;
220
221
222 struct mei_bus_message {
223 u8 hbm_cmd;
224 u8 data[0];
225 } __packed;
226
227 struct hbm_version {
228 u8 minor_version;
229 u8 major_version;
230 } __packed;
231
232 struct hbm_host_version_request {
233 u8 hbm_cmd;
234 u8 reserved;
235 struct hbm_version host_version;
236 } __packed;
237
238 struct hbm_host_version_response {
239 u8 hbm_cmd;
240 u8 host_version_supported;
241 struct hbm_version me_max_version;
242 } __packed;
243
244 struct hbm_host_stop_request {
245 u8 hbm_cmd;
246 u8 reason;
247 u8 reserved[2];
248 } __packed;
249
250 struct hbm_host_stop_response {
251 u8 hbm_cmd;
252 u8 reserved[3];
253 } __packed;
254
255 struct hbm_me_stop_request {
256 u8 hbm_cmd;
257 u8 reason;
258 u8 reserved[2];
259 } __packed;
260
261 struct hbm_host_enum_request {
262 u8 hbm_cmd;
263 u8 reserved[3];
264 } __packed;
265
266 struct hbm_host_enum_response {
267 u8 hbm_cmd;
268 u8 reserved[3];
269 u8 valid_addresses[32];
270 } __packed;
271
272 struct mei_client_properties {
273 uuid_le protocol_name;
274 u8 protocol_version;
275 u8 max_number_of_connections;
276 u8 fixed_address;
277 u8 single_recv_buf;
278 u32 max_msg_length;
279 } __packed;
280
281 struct hbm_props_request {
282 u8 hbm_cmd;
283 u8 address;
284 u8 reserved[2];
285 } __packed;
286
287
288 struct hbm_props_response {
289 u8 hbm_cmd;
290 u8 address;
291 u8 status;
292 u8 reserved[1];
293 struct mei_client_properties client_properties;
294 } __packed;
295
296 struct hbm_client_connect_request {
297 u8 hbm_cmd;
298 u8 me_addr;
299 u8 host_addr;
300 u8 reserved;
301 } __packed;
302
303 struct hbm_client_connect_response {
304 u8 hbm_cmd;
305 u8 me_addr;
306 u8 host_addr;
307 u8 status;
308 } __packed;
309
310 struct hbm_client_disconnect_request {
311 u8 hbm_cmd;
312 u8 me_addr;
313 u8 host_addr;
314 u8 reserved[1];
315 } __packed;
316
317 #define MEI_FC_MESSAGE_RESERVED_LENGTH 5
318
319 struct hbm_flow_control {
320 u8 hbm_cmd;
321 u8 me_addr;
322 u8 host_addr;
323 u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
324 } __packed;
325
326 struct mei_me_client {
327 struct mei_client_properties props;
328 u8 client_id;
329 u8 mei_flow_ctrl_creds;
330 } __packed;
331
332
333 #endif
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