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mmc: at91_mci: add missing linux/highmem.h include
[deliverable/linux.git] / drivers / mmc / host / at91_mci.c
1 /*
2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
3 *
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
5 *
6 * Copyright (C) 2006 Malcolm Noyes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /*
14 This is the AT91 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
17
18 The three entry points are at91_mci_request, at91_mci_set_ios
19 and at91_mci_get_ro.
20
21 SET IOS
22 This configures the device to put it into the correct mode and clock speed
23 required.
24
25 MCI REQUEST
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
29
30 There are three main types of request, commands, reads and writes.
31
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
36
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
39
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
43
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
45
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
49
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
51
52 GET RO
53 Gets the status of the write protect pin, if available.
54 */
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/init.h>
59 #include <linux/ioport.h>
60 #include <linux/platform_device.h>
61 #include <linux/interrupt.h>
62 #include <linux/blkdev.h>
63 #include <linux/delay.h>
64 #include <linux/err.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/clk.h>
67 #include <linux/atmel_pdc.h>
68 #include <linux/gfp.h>
69 #include <linux/highmem.h>
70
71 #include <linux/mmc/host.h>
72
73 #include <asm/io.h>
74 #include <asm/irq.h>
75 #include <asm/gpio.h>
76
77 #include <mach/board.h>
78 #include <mach/cpu.h>
79 #include <mach/at91_mci.h>
80
81 #define DRIVER_NAME "at91_mci"
82
83 static inline int at91mci_is_mci1rev2xx(void)
84 {
85 return ( cpu_is_at91sam9260()
86 || cpu_is_at91sam9263()
87 || cpu_is_at91cap9()
88 || cpu_is_at91sam9rl()
89 || cpu_is_at91sam9g10()
90 || cpu_is_at91sam9g20()
91 );
92 }
93
94 #define FL_SENT_COMMAND (1 << 0)
95 #define FL_SENT_STOP (1 << 1)
96
97 #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
98 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
99 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
100
101 #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
102 #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
103
104 #define MCI_BLKSIZE 512
105 #define MCI_MAXBLKSIZE 4095
106 #define MCI_BLKATONCE 256
107 #define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE)
108
109 /*
110 * Low level type for this driver
111 */
112 struct at91mci_host
113 {
114 struct mmc_host *mmc;
115 struct mmc_command *cmd;
116 struct mmc_request *request;
117
118 void __iomem *baseaddr;
119 int irq;
120
121 struct at91_mmc_data *board;
122 int present;
123
124 struct clk *mci_clk;
125
126 /*
127 * Flag indicating when the command has been sent. This is used to
128 * work out whether or not to send the stop
129 */
130 unsigned int flags;
131 /* flag for current bus settings */
132 u32 bus_mode;
133
134 /* DMA buffer used for transmitting */
135 unsigned int* buffer;
136 dma_addr_t physical_address;
137 unsigned int total_length;
138
139 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
140 int in_use_index;
141
142 /* Latest in the scatterlist that has been enabled for transfer */
143 int transfer_index;
144
145 /* Timer for timeouts */
146 struct timer_list timer;
147 };
148
149 /*
150 * Reset the controller and restore most of the state
151 */
152 static void at91_reset_host(struct at91mci_host *host)
153 {
154 unsigned long flags;
155 u32 mr;
156 u32 sdcr;
157 u32 dtor;
158 u32 imr;
159
160 local_irq_save(flags);
161 imr = at91_mci_read(host, AT91_MCI_IMR);
162
163 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
164
165 /* save current state */
166 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
167 sdcr = at91_mci_read(host, AT91_MCI_SDCR);
168 dtor = at91_mci_read(host, AT91_MCI_DTOR);
169
170 /* reset the controller */
171 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
172
173 /* restore state */
174 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
175 at91_mci_write(host, AT91_MCI_MR, mr);
176 at91_mci_write(host, AT91_MCI_SDCR, sdcr);
177 at91_mci_write(host, AT91_MCI_DTOR, dtor);
178 at91_mci_write(host, AT91_MCI_IER, imr);
179
180 /* make sure sdio interrupts will fire */
181 at91_mci_read(host, AT91_MCI_SR);
182
183 local_irq_restore(flags);
184 }
185
186 static void at91_timeout_timer(unsigned long data)
187 {
188 struct at91mci_host *host;
189
190 host = (struct at91mci_host *)data;
191
192 if (host->request) {
193 dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
194
195 if (host->cmd && host->cmd->data) {
196 host->cmd->data->error = -ETIMEDOUT;
197 } else {
198 if (host->cmd)
199 host->cmd->error = -ETIMEDOUT;
200 else
201 host->request->cmd->error = -ETIMEDOUT;
202 }
203
204 at91_reset_host(host);
205 mmc_request_done(host->mmc, host->request);
206 }
207 }
208
209 /*
210 * Copy from sg to a dma block - used for transfers
211 */
212 static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
213 {
214 unsigned int len, i, size;
215 unsigned *dmabuf = host->buffer;
216
217 size = data->blksz * data->blocks;
218 len = data->sg_len;
219
220 /* MCI1 rev2xx Data Write Operation and number of bytes erratum */
221 if (at91mci_is_mci1rev2xx())
222 if (host->total_length == 12)
223 memset(dmabuf, 0, 12);
224
225 /*
226 * Just loop through all entries. Size might not
227 * be the entire list though so make sure that
228 * we do not transfer too much.
229 */
230 for (i = 0; i < len; i++) {
231 struct scatterlist *sg;
232 int amount;
233 unsigned int *sgbuffer;
234
235 sg = &data->sg[i];
236
237 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
238 amount = min(size, sg->length);
239 size -= amount;
240
241 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
242 int index;
243
244 for (index = 0; index < (amount / 4); index++)
245 *dmabuf++ = swab32(sgbuffer[index]);
246 } else {
247 char *tmpv = (char *)dmabuf;
248 memcpy(tmpv, sgbuffer, amount);
249 tmpv += amount;
250 dmabuf = (unsigned *)tmpv;
251 }
252
253 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
254
255 if (size == 0)
256 break;
257 }
258
259 /*
260 * Check that we didn't get a request to transfer
261 * more data than can fit into the SG list.
262 */
263 BUG_ON(size != 0);
264 }
265
266 /*
267 * Handle after a dma read
268 */
269 static void at91_mci_post_dma_read(struct at91mci_host *host)
270 {
271 struct mmc_command *cmd;
272 struct mmc_data *data;
273 unsigned int len, i, size;
274 unsigned *dmabuf = host->buffer;
275
276 pr_debug("post dma read\n");
277
278 cmd = host->cmd;
279 if (!cmd) {
280 pr_debug("no command\n");
281 return;
282 }
283
284 data = cmd->data;
285 if (!data) {
286 pr_debug("no data\n");
287 return;
288 }
289
290 size = data->blksz * data->blocks;
291 len = data->sg_len;
292
293 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
294 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
295
296 for (i = 0; i < len; i++) {
297 struct scatterlist *sg;
298 int amount;
299 unsigned int *sgbuffer;
300
301 sg = &data->sg[i];
302
303 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
304 amount = min(size, sg->length);
305 size -= amount;
306
307 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
308 int index;
309 for (index = 0; index < (amount / 4); index++)
310 sgbuffer[index] = swab32(*dmabuf++);
311 } else {
312 char *tmpv = (char *)dmabuf;
313 memcpy(sgbuffer, tmpv, amount);
314 tmpv += amount;
315 dmabuf = (unsigned *)tmpv;
316 }
317
318 flush_kernel_dcache_page(sg_page(sg));
319 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
320 data->bytes_xfered += amount;
321 if (size == 0)
322 break;
323 }
324
325 pr_debug("post dma read done\n");
326 }
327
328 /*
329 * Handle transmitted data
330 */
331 static void at91_mci_handle_transmitted(struct at91mci_host *host)
332 {
333 struct mmc_command *cmd;
334 struct mmc_data *data;
335
336 pr_debug("Handling the transmit\n");
337
338 /* Disable the transfer */
339 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
340
341 /* Now wait for cmd ready */
342 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
343
344 cmd = host->cmd;
345 if (!cmd) return;
346
347 data = cmd->data;
348 if (!data) return;
349
350 if (cmd->data->blocks > 1) {
351 pr_debug("multiple write : wait for BLKE...\n");
352 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
353 } else
354 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
355 }
356
357 /*
358 * Update bytes tranfered count during a write operation
359 */
360 static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
361 {
362 struct mmc_data *data;
363
364 /* always deal with the effective request (and not the current cmd) */
365
366 if (host->request->cmd && host->request->cmd->error != 0)
367 return;
368
369 if (host->request->data) {
370 data = host->request->data;
371 if (data->flags & MMC_DATA_WRITE) {
372 /* card is in IDLE mode now */
373 pr_debug("-> bytes_xfered %d, total_length = %d\n",
374 data->bytes_xfered, host->total_length);
375 data->bytes_xfered = data->blksz * data->blocks;
376 }
377 }
378 }
379
380
381 /*Handle after command sent ready*/
382 static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
383 {
384 if (!host->cmd)
385 return 1;
386 else if (!host->cmd->data) {
387 if (host->flags & FL_SENT_STOP) {
388 /*After multi block write, we must wait for NOTBUSY*/
389 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
390 } else return 1;
391 } else if (host->cmd->data->flags & MMC_DATA_WRITE) {
392 /*After sendding multi-block-write command, start DMA transfer*/
393 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
394 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
395 }
396
397 /* command not completed, have to wait */
398 return 0;
399 }
400
401
402 /*
403 * Enable the controller
404 */
405 static void at91_mci_enable(struct at91mci_host *host)
406 {
407 unsigned int mr;
408
409 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
410 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
411 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
412 mr = AT91_MCI_PDCMODE | 0x34a;
413
414 if (at91mci_is_mci1rev2xx())
415 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
416
417 at91_mci_write(host, AT91_MCI_MR, mr);
418
419 /* use Slot A or B (only one at same time) */
420 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
421 }
422
423 /*
424 * Disable the controller
425 */
426 static void at91_mci_disable(struct at91mci_host *host)
427 {
428 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
429 }
430
431 /*
432 * Send a command
433 */
434 static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
435 {
436 unsigned int cmdr, mr;
437 unsigned int block_length;
438 struct mmc_data *data = cmd->data;
439
440 unsigned int blocks;
441 unsigned int ier = 0;
442
443 host->cmd = cmd;
444
445 /* Needed for leaving busy state before CMD1 */
446 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
447 pr_debug("Clearing timeout\n");
448 at91_mci_write(host, AT91_MCI_ARGR, 0);
449 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
450 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
451 /* spin */
452 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
453 }
454 }
455
456 cmdr = cmd->opcode;
457
458 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
459 cmdr |= AT91_MCI_RSPTYP_NONE;
460 else {
461 /* if a response is expected then allow maximum response latancy */
462 cmdr |= AT91_MCI_MAXLAT;
463 /* set 136 bit response for R2, 48 bit response otherwise */
464 if (mmc_resp_type(cmd) == MMC_RSP_R2)
465 cmdr |= AT91_MCI_RSPTYP_136;
466 else
467 cmdr |= AT91_MCI_RSPTYP_48;
468 }
469
470 if (data) {
471
472 if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) {
473 if (data->blksz & 0x3) {
474 pr_debug("Unsupported block size\n");
475 cmd->error = -EINVAL;
476 mmc_request_done(host->mmc, host->request);
477 return;
478 }
479 if (data->flags & MMC_DATA_STREAM) {
480 pr_debug("Stream commands not supported\n");
481 cmd->error = -EINVAL;
482 mmc_request_done(host->mmc, host->request);
483 return;
484 }
485 }
486
487 block_length = data->blksz;
488 blocks = data->blocks;
489
490 /* always set data start - also set direction flag for read */
491 if (data->flags & MMC_DATA_READ)
492 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
493 else if (data->flags & MMC_DATA_WRITE)
494 cmdr |= AT91_MCI_TRCMD_START;
495
496 if (data->flags & MMC_DATA_STREAM)
497 cmdr |= AT91_MCI_TRTYP_STREAM;
498 if (data->blocks > 1)
499 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
500 }
501 else {
502 block_length = 0;
503 blocks = 0;
504 }
505
506 if (host->flags & FL_SENT_STOP)
507 cmdr |= AT91_MCI_TRCMD_STOP;
508
509 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
510 cmdr |= AT91_MCI_OPDCMD;
511
512 /*
513 * Set the arguments and send the command
514 */
515 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
516 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
517
518 if (!data) {
519 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
520 at91_mci_write(host, ATMEL_PDC_RPR, 0);
521 at91_mci_write(host, ATMEL_PDC_RCR, 0);
522 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
523 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
524 at91_mci_write(host, ATMEL_PDC_TPR, 0);
525 at91_mci_write(host, ATMEL_PDC_TCR, 0);
526 at91_mci_write(host, ATMEL_PDC_TNPR, 0);
527 at91_mci_write(host, ATMEL_PDC_TNCR, 0);
528 ier = AT91_MCI_CMDRDY;
529 } else {
530 /* zero block length and PDC mode */
531 mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff;
532 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
533 mr |= (block_length << 16);
534 mr |= AT91_MCI_PDCMODE;
535 at91_mci_write(host, AT91_MCI_MR, mr);
536
537 if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261()))
538 at91_mci_write(host, AT91_MCI_BLKR,
539 AT91_MCI_BLKR_BCNT(blocks) |
540 AT91_MCI_BLKR_BLKLEN(block_length));
541
542 /*
543 * Disable the PDC controller
544 */
545 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
546
547 if (cmdr & AT91_MCI_TRCMD_START) {
548 data->bytes_xfered = 0;
549 host->transfer_index = 0;
550 host->in_use_index = 0;
551 if (cmdr & AT91_MCI_TRDIR) {
552 /*
553 * Handle a read
554 */
555 host->total_length = 0;
556
557 at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address);
558 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ?
559 (blocks * block_length) : (blocks * block_length) / 4);
560 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
561 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
562
563 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
564 }
565 else {
566 /*
567 * Handle a write
568 */
569 host->total_length = block_length * blocks;
570 /*
571 * MCI1 rev2xx Data Write Operation and
572 * number of bytes erratum
573 */
574 if (at91mci_is_mci1rev2xx())
575 if (host->total_length < 12)
576 host->total_length = 12;
577
578 at91_mci_sg_to_dma(host, data);
579
580 pr_debug("Transmitting %d bytes\n", host->total_length);
581
582 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
583 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
584 host->total_length : host->total_length / 4);
585
586 ier = AT91_MCI_CMDRDY;
587 }
588 }
589 }
590
591 /*
592 * Send the command and then enable the PDC - not the other way round as
593 * the data sheet says
594 */
595
596 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
597 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
598
599 if (cmdr & AT91_MCI_TRCMD_START) {
600 if (cmdr & AT91_MCI_TRDIR)
601 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
602 }
603
604 /* Enable selected interrupts */
605 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
606 }
607
608 /*
609 * Process the next step in the request
610 */
611 static void at91_mci_process_next(struct at91mci_host *host)
612 {
613 if (!(host->flags & FL_SENT_COMMAND)) {
614 host->flags |= FL_SENT_COMMAND;
615 at91_mci_send_command(host, host->request->cmd);
616 }
617 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
618 host->flags |= FL_SENT_STOP;
619 at91_mci_send_command(host, host->request->stop);
620 } else {
621 del_timer(&host->timer);
622 /* the at91rm9200 mci controller hangs after some transfers,
623 * and the workaround is to reset it after each transfer.
624 */
625 if (cpu_is_at91rm9200())
626 at91_reset_host(host);
627 mmc_request_done(host->mmc, host->request);
628 }
629 }
630
631 /*
632 * Handle a command that has been completed
633 */
634 static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status)
635 {
636 struct mmc_command *cmd = host->cmd;
637 struct mmc_data *data = cmd->data;
638
639 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
640
641 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
642 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
643 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
644 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
645
646 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
647 status, at91_mci_read(host, AT91_MCI_SR),
648 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
649
650 if (status & AT91_MCI_ERRORS) {
651 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
652 cmd->error = 0;
653 }
654 else {
655 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) {
656 if (data) {
657 if (status & AT91_MCI_DTOE)
658 data->error = -ETIMEDOUT;
659 else if (status & AT91_MCI_DCRCE)
660 data->error = -EILSEQ;
661 }
662 } else {
663 if (status & AT91_MCI_RTOE)
664 cmd->error = -ETIMEDOUT;
665 else if (status & AT91_MCI_RCRCE)
666 cmd->error = -EILSEQ;
667 else
668 cmd->error = -EIO;
669 }
670
671 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n",
672 cmd->error, data ? data->error : 0,
673 cmd->opcode, cmd->retries);
674 }
675 }
676 else
677 cmd->error = 0;
678
679 at91_mci_process_next(host);
680 }
681
682 /*
683 * Handle an MMC request
684 */
685 static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
686 {
687 struct at91mci_host *host = mmc_priv(mmc);
688 host->request = mrq;
689 host->flags = 0;
690
691 /* more than 1s timeout needed with slow SD cards */
692 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
693
694 at91_mci_process_next(host);
695 }
696
697 /*
698 * Set the IOS
699 */
700 static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
701 {
702 int clkdiv;
703 struct at91mci_host *host = mmc_priv(mmc);
704 unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
705
706 host->bus_mode = ios->bus_mode;
707
708 if (ios->clock == 0) {
709 /* Disable the MCI controller */
710 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
711 clkdiv = 0;
712 }
713 else {
714 /* Enable the MCI controller */
715 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
716
717 if ((at91_master_clock % (ios->clock * 2)) == 0)
718 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
719 else
720 clkdiv = (at91_master_clock / ios->clock) / 2;
721
722 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
723 at91_master_clock / (2 * (clkdiv + 1)));
724 }
725 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
726 pr_debug("MMC: Setting controller bus width to 4\n");
727 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
728 }
729 else {
730 pr_debug("MMC: Setting controller bus width to 1\n");
731 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
732 }
733
734 /* Set the clock divider */
735 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
736
737 /* maybe switch power to the card */
738 if (host->board->vcc_pin) {
739 switch (ios->power_mode) {
740 case MMC_POWER_OFF:
741 gpio_set_value(host->board->vcc_pin, 0);
742 break;
743 case MMC_POWER_UP:
744 gpio_set_value(host->board->vcc_pin, 1);
745 break;
746 case MMC_POWER_ON:
747 break;
748 default:
749 WARN_ON(1);
750 }
751 }
752 }
753
754 /*
755 * Handle an interrupt
756 */
757 static irqreturn_t at91_mci_irq(int irq, void *devid)
758 {
759 struct at91mci_host *host = devid;
760 int completed = 0;
761 unsigned int int_status, int_mask;
762
763 int_status = at91_mci_read(host, AT91_MCI_SR);
764 int_mask = at91_mci_read(host, AT91_MCI_IMR);
765
766 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
767 int_status & int_mask);
768
769 int_status = int_status & int_mask;
770
771 if (int_status & AT91_MCI_ERRORS) {
772 completed = 1;
773
774 if (int_status & AT91_MCI_UNRE)
775 pr_debug("MMC: Underrun error\n");
776 if (int_status & AT91_MCI_OVRE)
777 pr_debug("MMC: Overrun error\n");
778 if (int_status & AT91_MCI_DTOE)
779 pr_debug("MMC: Data timeout\n");
780 if (int_status & AT91_MCI_DCRCE)
781 pr_debug("MMC: CRC error in data\n");
782 if (int_status & AT91_MCI_RTOE)
783 pr_debug("MMC: Response timeout\n");
784 if (int_status & AT91_MCI_RENDE)
785 pr_debug("MMC: Response end bit error\n");
786 if (int_status & AT91_MCI_RCRCE)
787 pr_debug("MMC: Response CRC error\n");
788 if (int_status & AT91_MCI_RDIRE)
789 pr_debug("MMC: Response direction error\n");
790 if (int_status & AT91_MCI_RINDE)
791 pr_debug("MMC: Response index error\n");
792 } else {
793 /* Only continue processing if no errors */
794
795 if (int_status & AT91_MCI_TXBUFE) {
796 pr_debug("TX buffer empty\n");
797 at91_mci_handle_transmitted(host);
798 }
799
800 if (int_status & AT91_MCI_ENDRX) {
801 pr_debug("ENDRX\n");
802 at91_mci_post_dma_read(host);
803 }
804
805 if (int_status & AT91_MCI_RXBUFF) {
806 pr_debug("RX buffer full\n");
807 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
808 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
809 completed = 1;
810 }
811
812 if (int_status & AT91_MCI_ENDTX)
813 pr_debug("Transmit has ended\n");
814
815 if (int_status & AT91_MCI_NOTBUSY) {
816 pr_debug("Card is ready\n");
817 at91_mci_update_bytes_xfered(host);
818 completed = 1;
819 }
820
821 if (int_status & AT91_MCI_DTIP)
822 pr_debug("Data transfer in progress\n");
823
824 if (int_status & AT91_MCI_BLKE) {
825 pr_debug("Block transfer has ended\n");
826 if (host->request->data && host->request->data->blocks > 1) {
827 /* multi block write : complete multi write
828 * command and send stop */
829 completed = 1;
830 } else {
831 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
832 }
833 }
834
835 if (int_status & AT91_MCI_SDIOIRQA)
836 mmc_signal_sdio_irq(host->mmc);
837
838 if (int_status & AT91_MCI_SDIOIRQB)
839 mmc_signal_sdio_irq(host->mmc);
840
841 if (int_status & AT91_MCI_TXRDY)
842 pr_debug("Ready to transmit\n");
843
844 if (int_status & AT91_MCI_RXRDY)
845 pr_debug("Ready to receive\n");
846
847 if (int_status & AT91_MCI_CMDRDY) {
848 pr_debug("Command ready\n");
849 completed = at91_mci_handle_cmdrdy(host);
850 }
851 }
852
853 if (completed) {
854 pr_debug("Completed command\n");
855 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
856 at91_mci_completed_command(host, int_status);
857 } else
858 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
859
860 return IRQ_HANDLED;
861 }
862
863 static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
864 {
865 struct at91mci_host *host = _host;
866 int present = !gpio_get_value(irq_to_gpio(irq));
867
868 /*
869 * we expect this irq on both insert and remove,
870 * and use a short delay to debounce.
871 */
872 if (present != host->present) {
873 host->present = present;
874 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
875 present ? "insert" : "remove");
876 if (!present) {
877 pr_debug("****** Resetting SD-card bus width ******\n");
878 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
879 }
880 /* 0.5s needed because of early card detect switch firing */
881 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
882 }
883 return IRQ_HANDLED;
884 }
885
886 static int at91_mci_get_ro(struct mmc_host *mmc)
887 {
888 struct at91mci_host *host = mmc_priv(mmc);
889
890 if (host->board->wp_pin)
891 return !!gpio_get_value(host->board->wp_pin);
892 /*
893 * Board doesn't support read only detection; let the mmc core
894 * decide what to do.
895 */
896 return -ENOSYS;
897 }
898
899 static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
900 {
901 struct at91mci_host *host = mmc_priv(mmc);
902
903 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc),
904 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable");
905 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR,
906 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA);
907
908 }
909
910 static const struct mmc_host_ops at91_mci_ops = {
911 .request = at91_mci_request,
912 .set_ios = at91_mci_set_ios,
913 .get_ro = at91_mci_get_ro,
914 .enable_sdio_irq = at91_mci_enable_sdio_irq,
915 };
916
917 /*
918 * Probe for the device
919 */
920 static int __init at91_mci_probe(struct platform_device *pdev)
921 {
922 struct mmc_host *mmc;
923 struct at91mci_host *host;
924 struct resource *res;
925 int ret;
926
927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
928 if (!res)
929 return -ENXIO;
930
931 if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME))
932 return -EBUSY;
933
934 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
935 if (!mmc) {
936 ret = -ENOMEM;
937 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
938 goto fail6;
939 }
940
941 mmc->ops = &at91_mci_ops;
942 mmc->f_min = 375000;
943 mmc->f_max = 25000000;
944 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
945 mmc->caps = 0;
946
947 mmc->max_blk_size = MCI_MAXBLKSIZE;
948 mmc->max_blk_count = MCI_BLKATONCE;
949 mmc->max_req_size = MCI_BUFSIZE;
950 mmc->max_phys_segs = MCI_BLKATONCE;
951 mmc->max_hw_segs = MCI_BLKATONCE;
952 mmc->max_seg_size = MCI_BUFSIZE;
953
954 host = mmc_priv(mmc);
955 host->mmc = mmc;
956 host->bus_mode = 0;
957 host->board = pdev->dev.platform_data;
958 if (host->board->wire4) {
959 if (at91mci_is_mci1rev2xx())
960 mmc->caps |= MMC_CAP_4_BIT_DATA;
961 else
962 dev_warn(&pdev->dev, "4 wire bus mode not supported"
963 " - using 1 wire\n");
964 }
965
966 host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE,
967 &host->physical_address, GFP_KERNEL);
968 if (!host->buffer) {
969 ret = -ENOMEM;
970 dev_err(&pdev->dev, "Can't allocate transmit buffer\n");
971 goto fail5;
972 }
973
974 /* Add SDIO capability when available */
975 if (at91mci_is_mci1rev2xx()) {
976 /* at91mci MCI1 rev2xx sdio interrupt erratum */
977 if (host->board->wire4 || !host->board->slot_b)
978 mmc->caps |= MMC_CAP_SDIO_IRQ;
979 }
980
981 /*
982 * Reserve GPIOs ... board init code makes sure these pins are set
983 * up as GPIOs with the right direction (input, except for vcc)
984 */
985 if (host->board->det_pin) {
986 ret = gpio_request(host->board->det_pin, "mmc_detect");
987 if (ret < 0) {
988 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
989 goto fail4b;
990 }
991 }
992 if (host->board->wp_pin) {
993 ret = gpio_request(host->board->wp_pin, "mmc_wp");
994 if (ret < 0) {
995 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
996 goto fail4;
997 }
998 }
999 if (host->board->vcc_pin) {
1000 ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
1001 if (ret < 0) {
1002 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
1003 goto fail3;
1004 }
1005 }
1006
1007 /*
1008 * Get Clock
1009 */
1010 host->mci_clk = clk_get(&pdev->dev, "mci_clk");
1011 if (IS_ERR(host->mci_clk)) {
1012 ret = -ENODEV;
1013 dev_dbg(&pdev->dev, "no mci_clk?\n");
1014 goto fail2;
1015 }
1016
1017 /*
1018 * Map I/O region
1019 */
1020 host->baseaddr = ioremap(res->start, res->end - res->start + 1);
1021 if (!host->baseaddr) {
1022 ret = -ENOMEM;
1023 goto fail1;
1024 }
1025
1026 /*
1027 * Reset hardware
1028 */
1029 clk_enable(host->mci_clk); /* Enable the peripheral clock */
1030 at91_mci_disable(host);
1031 at91_mci_enable(host);
1032
1033 /*
1034 * Allocate the MCI interrupt
1035 */
1036 host->irq = platform_get_irq(pdev, 0);
1037 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
1038 mmc_hostname(mmc), host);
1039 if (ret) {
1040 dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
1041 goto fail0;
1042 }
1043
1044 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);
1045
1046 platform_set_drvdata(pdev, mmc);
1047
1048 /*
1049 * Add host to MMC layer
1050 */
1051 if (host->board->det_pin) {
1052 host->present = !gpio_get_value(host->board->det_pin);
1053 }
1054 else
1055 host->present = -1;
1056
1057 mmc_add_host(mmc);
1058
1059 /*
1060 * monitor card insertion/removal if we can
1061 */
1062 if (host->board->det_pin) {
1063 ret = request_irq(gpio_to_irq(host->board->det_pin),
1064 at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
1065 if (ret)
1066 dev_warn(&pdev->dev, "request MMC detect irq failed\n");
1067 else
1068 device_init_wakeup(&pdev->dev, 1);
1069 }
1070
1071 pr_debug("Added MCI driver\n");
1072
1073 return 0;
1074
1075 fail0:
1076 clk_disable(host->mci_clk);
1077 iounmap(host->baseaddr);
1078 fail1:
1079 clk_put(host->mci_clk);
1080 fail2:
1081 if (host->board->vcc_pin)
1082 gpio_free(host->board->vcc_pin);
1083 fail3:
1084 if (host->board->wp_pin)
1085 gpio_free(host->board->wp_pin);
1086 fail4:
1087 if (host->board->det_pin)
1088 gpio_free(host->board->det_pin);
1089 fail4b:
1090 if (host->buffer)
1091 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1092 host->buffer, host->physical_address);
1093 fail5:
1094 mmc_free_host(mmc);
1095 fail6:
1096 release_mem_region(res->start, res->end - res->start + 1);
1097 dev_err(&pdev->dev, "probe failed, err %d\n", ret);
1098 return ret;
1099 }
1100
1101 /*
1102 * Remove a device
1103 */
1104 static int __exit at91_mci_remove(struct platform_device *pdev)
1105 {
1106 struct mmc_host *mmc = platform_get_drvdata(pdev);
1107 struct at91mci_host *host;
1108 struct resource *res;
1109
1110 if (!mmc)
1111 return -1;
1112
1113 host = mmc_priv(mmc);
1114
1115 if (host->buffer)
1116 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1117 host->buffer, host->physical_address);
1118
1119 if (host->board->det_pin) {
1120 if (device_can_wakeup(&pdev->dev))
1121 free_irq(gpio_to_irq(host->board->det_pin), host);
1122 device_init_wakeup(&pdev->dev, 0);
1123 gpio_free(host->board->det_pin);
1124 }
1125
1126 at91_mci_disable(host);
1127 del_timer_sync(&host->timer);
1128 mmc_remove_host(mmc);
1129 free_irq(host->irq, host);
1130
1131 clk_disable(host->mci_clk); /* Disable the peripheral clock */
1132 clk_put(host->mci_clk);
1133
1134 if (host->board->vcc_pin)
1135 gpio_free(host->board->vcc_pin);
1136 if (host->board->wp_pin)
1137 gpio_free(host->board->wp_pin);
1138
1139 iounmap(host->baseaddr);
1140 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1141 release_mem_region(res->start, res->end - res->start + 1);
1142
1143 mmc_free_host(mmc);
1144 platform_set_drvdata(pdev, NULL);
1145 pr_debug("MCI Removed\n");
1146
1147 return 0;
1148 }
1149
1150 #ifdef CONFIG_PM
1151 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
1152 {
1153 struct mmc_host *mmc = platform_get_drvdata(pdev);
1154 struct at91mci_host *host = mmc_priv(mmc);
1155 int ret = 0;
1156
1157 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1158 enable_irq_wake(host->board->det_pin);
1159
1160 if (mmc)
1161 ret = mmc_suspend_host(mmc);
1162
1163 return ret;
1164 }
1165
1166 static int at91_mci_resume(struct platform_device *pdev)
1167 {
1168 struct mmc_host *mmc = platform_get_drvdata(pdev);
1169 struct at91mci_host *host = mmc_priv(mmc);
1170 int ret = 0;
1171
1172 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1173 disable_irq_wake(host->board->det_pin);
1174
1175 if (mmc)
1176 ret = mmc_resume_host(mmc);
1177
1178 return ret;
1179 }
1180 #else
1181 #define at91_mci_suspend NULL
1182 #define at91_mci_resume NULL
1183 #endif
1184
1185 static struct platform_driver at91_mci_driver = {
1186 .remove = __exit_p(at91_mci_remove),
1187 .suspend = at91_mci_suspend,
1188 .resume = at91_mci_resume,
1189 .driver = {
1190 .name = DRIVER_NAME,
1191 .owner = THIS_MODULE,
1192 },
1193 };
1194
1195 static int __init at91_mci_init(void)
1196 {
1197 return platform_driver_probe(&at91_mci_driver, at91_mci_probe);
1198 }
1199
1200 static void __exit at91_mci_exit(void)
1201 {
1202 platform_driver_unregister(&at91_mci_driver);
1203 }
1204
1205 module_init(at91_mci_init);
1206 module_exit(at91_mci_exit);
1207
1208 MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
1209 MODULE_AUTHOR("Nick Randell");
1210 MODULE_LICENSE("GPL");
1211 MODULE_ALIAS("platform:at91_mci");
Linux kernel - Deliverables
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