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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / drivers / mmc / host / atmel-mci.c
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27 #include <linux/types.h>
28
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/sdio.h>
31
32 #include <mach/atmel-mci.h>
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
35
36 #include <asm/io.h>
37 #include <asm/unaligned.h>
38
39 #include <mach/cpu.h>
40 #include <mach/board.h>
41
42 #include "atmel-mci-regs.h"
43
44 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
45 #define ATMCI_DMA_THRESHOLD 16
46
47 enum {
48 EVENT_CMD_RDY = 0,
49 EVENT_XFER_COMPLETE,
50 EVENT_NOTBUSY,
51 EVENT_DATA_ERROR,
52 };
53
54 enum atmel_mci_state {
55 STATE_IDLE = 0,
56 STATE_SENDING_CMD,
57 STATE_DATA_XFER,
58 STATE_WAITING_NOTBUSY,
59 STATE_SENDING_STOP,
60 STATE_END_REQUEST,
61 };
62
63 enum atmci_xfer_dir {
64 XFER_RECEIVE = 0,
65 XFER_TRANSMIT,
66 };
67
68 enum atmci_pdc_buf {
69 PDC_FIRST_BUF = 0,
70 PDC_SECOND_BUF,
71 };
72
73 struct atmel_mci_caps {
74 bool has_dma;
75 bool has_pdc;
76 bool has_cfg_reg;
77 bool has_cstor_reg;
78 bool has_highspeed;
79 bool has_rwproof;
80 bool has_odd_clk_div;
81 bool has_bad_data_ordering;
82 bool need_reset_after_xfer;
83 bool need_blksz_mul_4;
84 };
85
86 struct atmel_mci_dma {
87 struct dma_chan *chan;
88 struct dma_async_tx_descriptor *data_desc;
89 };
90
91 /**
92 * struct atmel_mci - MMC controller state shared between all slots
93 * @lock: Spinlock protecting the queue and associated data.
94 * @regs: Pointer to MMIO registers.
95 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
96 * @pio_offset: Offset into the current scatterlist entry.
97 * @buffer: Buffer used if we don't have the r/w proof capability. We
98 * don't have the time to switch pdc buffers so we have to use only
99 * one buffer for the full transaction.
100 * @buf_size: size of the buffer.
101 * @phys_buf_addr: buffer address needed for pdc.
102 * @cur_slot: The slot which is currently using the controller.
103 * @mrq: The request currently being processed on @cur_slot,
104 * or NULL if the controller is idle.
105 * @cmd: The command currently being sent to the card, or NULL.
106 * @data: The data currently being transferred, or NULL if no data
107 * transfer is in progress.
108 * @data_size: just data->blocks * data->blksz.
109 * @dma: DMA client state.
110 * @data_chan: DMA channel being used for the current data transfer.
111 * @cmd_status: Snapshot of SR taken upon completion of the current
112 * command. Only valid when EVENT_CMD_COMPLETE is pending.
113 * @data_status: Snapshot of SR taken upon completion of the current
114 * data transfer. Only valid when EVENT_DATA_COMPLETE or
115 * EVENT_DATA_ERROR is pending.
116 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
117 * to be sent.
118 * @tasklet: Tasklet running the request state machine.
119 * @pending_events: Bitmask of events flagged by the interrupt handler
120 * to be processed by the tasklet.
121 * @completed_events: Bitmask of events which the state machine has
122 * processed.
123 * @state: Tasklet state.
124 * @queue: List of slots waiting for access to the controller.
125 * @need_clock_update: Update the clock rate before the next request.
126 * @need_reset: Reset controller before next request.
127 * @timer: Timer to balance the data timeout error flag which cannot rise.
128 * @mode_reg: Value of the MR register.
129 * @cfg_reg: Value of the CFG register.
130 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
131 * rate and timeout calculations.
132 * @mapbase: Physical address of the MMIO registers.
133 * @mck: The peripheral bus clock hooked up to the MMC controller.
134 * @pdev: Platform device associated with the MMC controller.
135 * @slot: Slots sharing this MMC controller.
136 * @caps: MCI capabilities depending on MCI version.
137 * @prepare_data: function to setup MCI before data transfer which
138 * depends on MCI capabilities.
139 * @submit_data: function to start data transfer which depends on MCI
140 * capabilities.
141 * @stop_transfer: function to stop data transfer which depends on MCI
142 * capabilities.
143 *
144 * Locking
145 * =======
146 *
147 * @lock is a softirq-safe spinlock protecting @queue as well as
148 * @cur_slot, @mrq and @state. These must always be updated
149 * at the same time while holding @lock.
150 *
151 * @lock also protects mode_reg and need_clock_update since these are
152 * used to synchronize mode register updates with the queue
153 * processing.
154 *
155 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
156 * and must always be written at the same time as the slot is added to
157 * @queue.
158 *
159 * @pending_events and @completed_events are accessed using atomic bit
160 * operations, so they don't need any locking.
161 *
162 * None of the fields touched by the interrupt handler need any
163 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
164 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
165 * interrupts must be disabled and @data_status updated with a
166 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
167 * CMDRDY interrupt must be disabled and @cmd_status updated with a
168 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
169 * bytes_xfered field of @data must be written. This is ensured by
170 * using barriers.
171 */
172 struct atmel_mci {
173 spinlock_t lock;
174 void __iomem *regs;
175
176 struct scatterlist *sg;
177 unsigned int pio_offset;
178 unsigned int *buffer;
179 unsigned int buf_size;
180 dma_addr_t buf_phys_addr;
181
182 struct atmel_mci_slot *cur_slot;
183 struct mmc_request *mrq;
184 struct mmc_command *cmd;
185 struct mmc_data *data;
186 unsigned int data_size;
187
188 struct atmel_mci_dma dma;
189 struct dma_chan *data_chan;
190 struct dma_slave_config dma_conf;
191
192 u32 cmd_status;
193 u32 data_status;
194 u32 stop_cmdr;
195
196 struct tasklet_struct tasklet;
197 unsigned long pending_events;
198 unsigned long completed_events;
199 enum atmel_mci_state state;
200 struct list_head queue;
201
202 bool need_clock_update;
203 bool need_reset;
204 struct timer_list timer;
205 u32 mode_reg;
206 u32 cfg_reg;
207 unsigned long bus_hz;
208 unsigned long mapbase;
209 struct clk *mck;
210 struct platform_device *pdev;
211
212 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
213
214 struct atmel_mci_caps caps;
215
216 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
217 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
218 void (*stop_transfer)(struct atmel_mci *host);
219 };
220
221 /**
222 * struct atmel_mci_slot - MMC slot state
223 * @mmc: The mmc_host representing this slot.
224 * @host: The MMC controller this slot is using.
225 * @sdc_reg: Value of SDCR to be written before using this slot.
226 * @sdio_irq: SDIO irq mask for this slot.
227 * @mrq: mmc_request currently being processed or waiting to be
228 * processed, or NULL when the slot is idle.
229 * @queue_node: List node for placing this node in the @queue list of
230 * &struct atmel_mci.
231 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
232 * @flags: Random state bits associated with the slot.
233 * @detect_pin: GPIO pin used for card detection, or negative if not
234 * available.
235 * @wp_pin: GPIO pin used for card write protect sending, or negative
236 * if not available.
237 * @detect_is_active_high: The state of the detect pin when it is active.
238 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
239 */
240 struct atmel_mci_slot {
241 struct mmc_host *mmc;
242 struct atmel_mci *host;
243
244 u32 sdc_reg;
245 u32 sdio_irq;
246
247 struct mmc_request *mrq;
248 struct list_head queue_node;
249
250 unsigned int clock;
251 unsigned long flags;
252 #define ATMCI_CARD_PRESENT 0
253 #define ATMCI_CARD_NEED_INIT 1
254 #define ATMCI_SHUTDOWN 2
255 #define ATMCI_SUSPENDED 3
256
257 int detect_pin;
258 int wp_pin;
259 bool detect_is_active_high;
260
261 struct timer_list detect_timer;
262 };
263
264 #define atmci_test_and_clear_pending(host, event) \
265 test_and_clear_bit(event, &host->pending_events)
266 #define atmci_set_completed(host, event) \
267 set_bit(event, &host->completed_events)
268 #define atmci_set_pending(host, event) \
269 set_bit(event, &host->pending_events)
270
271 /*
272 * The debugfs stuff below is mostly optimized away when
273 * CONFIG_DEBUG_FS is not set.
274 */
275 static int atmci_req_show(struct seq_file *s, void *v)
276 {
277 struct atmel_mci_slot *slot = s->private;
278 struct mmc_request *mrq;
279 struct mmc_command *cmd;
280 struct mmc_command *stop;
281 struct mmc_data *data;
282
283 /* Make sure we get a consistent snapshot */
284 spin_lock_bh(&slot->host->lock);
285 mrq = slot->mrq;
286
287 if (mrq) {
288 cmd = mrq->cmd;
289 data = mrq->data;
290 stop = mrq->stop;
291
292 if (cmd)
293 seq_printf(s,
294 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
295 cmd->opcode, cmd->arg, cmd->flags,
296 cmd->resp[0], cmd->resp[1], cmd->resp[2],
297 cmd->resp[3], cmd->error);
298 if (data)
299 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
300 data->bytes_xfered, data->blocks,
301 data->blksz, data->flags, data->error);
302 if (stop)
303 seq_printf(s,
304 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
305 stop->opcode, stop->arg, stop->flags,
306 stop->resp[0], stop->resp[1], stop->resp[2],
307 stop->resp[3], stop->error);
308 }
309
310 spin_unlock_bh(&slot->host->lock);
311
312 return 0;
313 }
314
315 static int atmci_req_open(struct inode *inode, struct file *file)
316 {
317 return single_open(file, atmci_req_show, inode->i_private);
318 }
319
320 static const struct file_operations atmci_req_fops = {
321 .owner = THIS_MODULE,
322 .open = atmci_req_open,
323 .read = seq_read,
324 .llseek = seq_lseek,
325 .release = single_release,
326 };
327
328 static void atmci_show_status_reg(struct seq_file *s,
329 const char *regname, u32 value)
330 {
331 static const char *sr_bit[] = {
332 [0] = "CMDRDY",
333 [1] = "RXRDY",
334 [2] = "TXRDY",
335 [3] = "BLKE",
336 [4] = "DTIP",
337 [5] = "NOTBUSY",
338 [6] = "ENDRX",
339 [7] = "ENDTX",
340 [8] = "SDIOIRQA",
341 [9] = "SDIOIRQB",
342 [12] = "SDIOWAIT",
343 [14] = "RXBUFF",
344 [15] = "TXBUFE",
345 [16] = "RINDE",
346 [17] = "RDIRE",
347 [18] = "RCRCE",
348 [19] = "RENDE",
349 [20] = "RTOE",
350 [21] = "DCRCE",
351 [22] = "DTOE",
352 [23] = "CSTOE",
353 [24] = "BLKOVRE",
354 [25] = "DMADONE",
355 [26] = "FIFOEMPTY",
356 [27] = "XFRDONE",
357 [30] = "OVRE",
358 [31] = "UNRE",
359 };
360 unsigned int i;
361
362 seq_printf(s, "%s:\t0x%08x", regname, value);
363 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
364 if (value & (1 << i)) {
365 if (sr_bit[i])
366 seq_printf(s, " %s", sr_bit[i]);
367 else
368 seq_puts(s, " UNKNOWN");
369 }
370 }
371 seq_putc(s, '\n');
372 }
373
374 static int atmci_regs_show(struct seq_file *s, void *v)
375 {
376 struct atmel_mci *host = s->private;
377 u32 *buf;
378
379 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
380 if (!buf)
381 return -ENOMEM;
382
383 /*
384 * Grab a more or less consistent snapshot. Note that we're
385 * not disabling interrupts, so IMR and SR may not be
386 * consistent.
387 */
388 spin_lock_bh(&host->lock);
389 clk_enable(host->mck);
390 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
391 clk_disable(host->mck);
392 spin_unlock_bh(&host->lock);
393
394 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
395 buf[ATMCI_MR / 4],
396 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
397 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
398 buf[ATMCI_MR / 4] & 0xff);
399 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
400 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
401 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
402 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
403 buf[ATMCI_BLKR / 4],
404 buf[ATMCI_BLKR / 4] & 0xffff,
405 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
406 if (host->caps.has_cstor_reg)
407 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
408
409 /* Don't read RSPR and RDR; it will consume the data there */
410
411 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
412 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
413
414 if (host->caps.has_dma) {
415 u32 val;
416
417 val = buf[ATMCI_DMA / 4];
418 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
419 val, val & 3,
420 ((val >> 4) & 3) ?
421 1 << (((val >> 4) & 3) + 1) : 1,
422 val & ATMCI_DMAEN ? " DMAEN" : "");
423 }
424 if (host->caps.has_cfg_reg) {
425 u32 val;
426
427 val = buf[ATMCI_CFG / 4];
428 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
429 val,
430 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
431 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
432 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
433 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
434 }
435
436 kfree(buf);
437
438 return 0;
439 }
440
441 static int atmci_regs_open(struct inode *inode, struct file *file)
442 {
443 return single_open(file, atmci_regs_show, inode->i_private);
444 }
445
446 static const struct file_operations atmci_regs_fops = {
447 .owner = THIS_MODULE,
448 .open = atmci_regs_open,
449 .read = seq_read,
450 .llseek = seq_lseek,
451 .release = single_release,
452 };
453
454 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
455 {
456 struct mmc_host *mmc = slot->mmc;
457 struct atmel_mci *host = slot->host;
458 struct dentry *root;
459 struct dentry *node;
460
461 root = mmc->debugfs_root;
462 if (!root)
463 return;
464
465 node = debugfs_create_file("regs", S_IRUSR, root, host,
466 &atmci_regs_fops);
467 if (IS_ERR(node))
468 return;
469 if (!node)
470 goto err;
471
472 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
473 if (!node)
474 goto err;
475
476 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
477 if (!node)
478 goto err;
479
480 node = debugfs_create_x32("pending_events", S_IRUSR, root,
481 (u32 *)&host->pending_events);
482 if (!node)
483 goto err;
484
485 node = debugfs_create_x32("completed_events", S_IRUSR, root,
486 (u32 *)&host->completed_events);
487 if (!node)
488 goto err;
489
490 return;
491
492 err:
493 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
494 }
495
496 static inline unsigned int atmci_get_version(struct atmel_mci *host)
497 {
498 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
499 }
500
501 static void atmci_timeout_timer(unsigned long data)
502 {
503 struct atmel_mci *host;
504
505 host = (struct atmel_mci *)data;
506
507 dev_dbg(&host->pdev->dev, "software timeout\n");
508
509 if (host->mrq->cmd->data) {
510 host->mrq->cmd->data->error = -ETIMEDOUT;
511 host->data = NULL;
512 } else {
513 host->mrq->cmd->error = -ETIMEDOUT;
514 host->cmd = NULL;
515 }
516 host->need_reset = 1;
517 host->state = STATE_END_REQUEST;
518 smp_wmb();
519 tasklet_schedule(&host->tasklet);
520 }
521
522 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
523 unsigned int ns)
524 {
525 /*
526 * It is easier here to use us instead of ns for the timeout,
527 * it prevents from overflows during calculation.
528 */
529 unsigned int us = DIV_ROUND_UP(ns, 1000);
530
531 /* Maximum clock frequency is host->bus_hz/2 */
532 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
533 }
534
535 static void atmci_set_timeout(struct atmel_mci *host,
536 struct atmel_mci_slot *slot, struct mmc_data *data)
537 {
538 static unsigned dtomul_to_shift[] = {
539 0, 4, 7, 8, 10, 12, 16, 20
540 };
541 unsigned timeout;
542 unsigned dtocyc;
543 unsigned dtomul;
544
545 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
546 + data->timeout_clks;
547
548 for (dtomul = 0; dtomul < 8; dtomul++) {
549 unsigned shift = dtomul_to_shift[dtomul];
550 dtocyc = (timeout + (1 << shift) - 1) >> shift;
551 if (dtocyc < 15)
552 break;
553 }
554
555 if (dtomul >= 8) {
556 dtomul = 7;
557 dtocyc = 15;
558 }
559
560 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
561 dtocyc << dtomul_to_shift[dtomul]);
562 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
563 }
564
565 /*
566 * Return mask with command flags to be enabled for this command.
567 */
568 static u32 atmci_prepare_command(struct mmc_host *mmc,
569 struct mmc_command *cmd)
570 {
571 struct mmc_data *data;
572 u32 cmdr;
573
574 cmd->error = -EINPROGRESS;
575
576 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
577
578 if (cmd->flags & MMC_RSP_PRESENT) {
579 if (cmd->flags & MMC_RSP_136)
580 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
581 else
582 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
583 }
584
585 /*
586 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
587 * it's too difficult to determine whether this is an ACMD or
588 * not. Better make it 64.
589 */
590 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
591
592 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
593 cmdr |= ATMCI_CMDR_OPDCMD;
594
595 data = cmd->data;
596 if (data) {
597 cmdr |= ATMCI_CMDR_START_XFER;
598
599 if (cmd->opcode == SD_IO_RW_EXTENDED) {
600 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
601 } else {
602 if (data->flags & MMC_DATA_STREAM)
603 cmdr |= ATMCI_CMDR_STREAM;
604 else if (data->blocks > 1)
605 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
606 else
607 cmdr |= ATMCI_CMDR_BLOCK;
608 }
609
610 if (data->flags & MMC_DATA_READ)
611 cmdr |= ATMCI_CMDR_TRDIR_READ;
612 }
613
614 return cmdr;
615 }
616
617 static void atmci_send_command(struct atmel_mci *host,
618 struct mmc_command *cmd, u32 cmd_flags)
619 {
620 WARN_ON(host->cmd);
621 host->cmd = cmd;
622
623 dev_vdbg(&host->pdev->dev,
624 "start command: ARGR=0x%08x CMDR=0x%08x\n",
625 cmd->arg, cmd_flags);
626
627 atmci_writel(host, ATMCI_ARGR, cmd->arg);
628 atmci_writel(host, ATMCI_CMDR, cmd_flags);
629 }
630
631 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
632 {
633 dev_dbg(&host->pdev->dev, "send stop command\n");
634 atmci_send_command(host, data->stop, host->stop_cmdr);
635 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
636 }
637
638 /*
639 * Configure given PDC buffer taking care of alignement issues.
640 * Update host->data_size and host->sg.
641 */
642 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
643 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
644 {
645 u32 pointer_reg, counter_reg;
646 unsigned int buf_size;
647
648 if (dir == XFER_RECEIVE) {
649 pointer_reg = ATMEL_PDC_RPR;
650 counter_reg = ATMEL_PDC_RCR;
651 } else {
652 pointer_reg = ATMEL_PDC_TPR;
653 counter_reg = ATMEL_PDC_TCR;
654 }
655
656 if (buf_nb == PDC_SECOND_BUF) {
657 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
658 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
659 }
660
661 if (!host->caps.has_rwproof) {
662 buf_size = host->buf_size;
663 atmci_writel(host, pointer_reg, host->buf_phys_addr);
664 } else {
665 buf_size = sg_dma_len(host->sg);
666 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
667 }
668
669 if (host->data_size <= buf_size) {
670 if (host->data_size & 0x3) {
671 /* If size is different from modulo 4, transfer bytes */
672 atmci_writel(host, counter_reg, host->data_size);
673 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
674 } else {
675 /* Else transfer 32-bits words */
676 atmci_writel(host, counter_reg, host->data_size / 4);
677 }
678 host->data_size = 0;
679 } else {
680 /* We assume the size of a page is 32-bits aligned */
681 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
682 host->data_size -= sg_dma_len(host->sg);
683 if (host->data_size)
684 host->sg = sg_next(host->sg);
685 }
686 }
687
688 /*
689 * Configure PDC buffer according to the data size ie configuring one or two
690 * buffers. Don't use this function if you want to configure only the second
691 * buffer. In this case, use atmci_pdc_set_single_buf.
692 */
693 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
694 {
695 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
696 if (host->data_size)
697 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
698 }
699
700 /*
701 * Unmap sg lists, called when transfer is finished.
702 */
703 static void atmci_pdc_cleanup(struct atmel_mci *host)
704 {
705 struct mmc_data *data = host->data;
706
707 if (data)
708 dma_unmap_sg(&host->pdev->dev,
709 data->sg, data->sg_len,
710 ((data->flags & MMC_DATA_WRITE)
711 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
712 }
713
714 /*
715 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
716 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
717 * interrupt needed for both transfer directions.
718 */
719 static void atmci_pdc_complete(struct atmel_mci *host)
720 {
721 int transfer_size = host->data->blocks * host->data->blksz;
722 int i;
723
724 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
725
726 if ((!host->caps.has_rwproof)
727 && (host->data->flags & MMC_DATA_READ)) {
728 if (host->caps.has_bad_data_ordering)
729 for (i = 0; i < transfer_size; i++)
730 host->buffer[i] = swab32(host->buffer[i]);
731 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
732 host->buffer, transfer_size);
733 }
734
735 atmci_pdc_cleanup(host);
736
737 /*
738 * If the card was removed, data will be NULL. No point trying
739 * to send the stop command or waiting for NBUSY in this case.
740 */
741 if (host->data) {
742 dev_dbg(&host->pdev->dev,
743 "(%s) set pending xfer complete\n", __func__);
744 atmci_set_pending(host, EVENT_XFER_COMPLETE);
745 tasklet_schedule(&host->tasklet);
746 }
747 }
748
749 static void atmci_dma_cleanup(struct atmel_mci *host)
750 {
751 struct mmc_data *data = host->data;
752
753 if (data)
754 dma_unmap_sg(host->dma.chan->device->dev,
755 data->sg, data->sg_len,
756 ((data->flags & MMC_DATA_WRITE)
757 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
758 }
759
760 /*
761 * This function is called by the DMA driver from tasklet context.
762 */
763 static void atmci_dma_complete(void *arg)
764 {
765 struct atmel_mci *host = arg;
766 struct mmc_data *data = host->data;
767
768 dev_vdbg(&host->pdev->dev, "DMA complete\n");
769
770 if (host->caps.has_dma)
771 /* Disable DMA hardware handshaking on MCI */
772 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
773
774 atmci_dma_cleanup(host);
775
776 /*
777 * If the card was removed, data will be NULL. No point trying
778 * to send the stop command or waiting for NBUSY in this case.
779 */
780 if (data) {
781 dev_dbg(&host->pdev->dev,
782 "(%s) set pending xfer complete\n", __func__);
783 atmci_set_pending(host, EVENT_XFER_COMPLETE);
784 tasklet_schedule(&host->tasklet);
785
786 /*
787 * Regardless of what the documentation says, we have
788 * to wait for NOTBUSY even after block read
789 * operations.
790 *
791 * When the DMA transfer is complete, the controller
792 * may still be reading the CRC from the card, i.e.
793 * the data transfer is still in progress and we
794 * haven't seen all the potential error bits yet.
795 *
796 * The interrupt handler will schedule a different
797 * tasklet to finish things up when the data transfer
798 * is completely done.
799 *
800 * We may not complete the mmc request here anyway
801 * because the mmc layer may call back and cause us to
802 * violate the "don't submit new operations from the
803 * completion callback" rule of the dma engine
804 * framework.
805 */
806 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
807 }
808 }
809
810 /*
811 * Returns a mask of interrupt flags to be enabled after the whole
812 * request has been prepared.
813 */
814 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
815 {
816 u32 iflags;
817
818 data->error = -EINPROGRESS;
819
820 host->sg = data->sg;
821 host->data = data;
822 host->data_chan = NULL;
823
824 iflags = ATMCI_DATA_ERROR_FLAGS;
825
826 /*
827 * Errata: MMC data write operation with less than 12
828 * bytes is impossible.
829 *
830 * Errata: MCI Transmit Data Register (TDR) FIFO
831 * corruption when length is not multiple of 4.
832 */
833 if (data->blocks * data->blksz < 12
834 || (data->blocks * data->blksz) & 3)
835 host->need_reset = true;
836
837 host->pio_offset = 0;
838 if (data->flags & MMC_DATA_READ)
839 iflags |= ATMCI_RXRDY;
840 else
841 iflags |= ATMCI_TXRDY;
842
843 return iflags;
844 }
845
846 /*
847 * Set interrupt flags and set block length into the MCI mode register even
848 * if this value is also accessible in the MCI block register. It seems to be
849 * necessary before the High Speed MCI version. It also map sg and configure
850 * PDC registers.
851 */
852 static u32
853 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
854 {
855 u32 iflags, tmp;
856 unsigned int sg_len;
857 enum dma_data_direction dir;
858 int i;
859
860 data->error = -EINPROGRESS;
861
862 host->data = data;
863 host->sg = data->sg;
864 iflags = ATMCI_DATA_ERROR_FLAGS;
865
866 /* Enable pdc mode */
867 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
868
869 if (data->flags & MMC_DATA_READ) {
870 dir = DMA_FROM_DEVICE;
871 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
872 } else {
873 dir = DMA_TO_DEVICE;
874 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
875 }
876
877 /* Set BLKLEN */
878 tmp = atmci_readl(host, ATMCI_MR);
879 tmp &= 0x0000ffff;
880 tmp |= ATMCI_BLKLEN(data->blksz);
881 atmci_writel(host, ATMCI_MR, tmp);
882
883 /* Configure PDC */
884 host->data_size = data->blocks * data->blksz;
885 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
886
887 if ((!host->caps.has_rwproof)
888 && (host->data->flags & MMC_DATA_WRITE)) {
889 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
890 host->buffer, host->data_size);
891 if (host->caps.has_bad_data_ordering)
892 for (i = 0; i < host->data_size; i++)
893 host->buffer[i] = swab32(host->buffer[i]);
894 }
895
896 if (host->data_size)
897 atmci_pdc_set_both_buf(host,
898 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
899
900 return iflags;
901 }
902
903 static u32
904 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
905 {
906 struct dma_chan *chan;
907 struct dma_async_tx_descriptor *desc;
908 struct scatterlist *sg;
909 unsigned int i;
910 enum dma_data_direction direction;
911 enum dma_transfer_direction slave_dirn;
912 unsigned int sglen;
913 u32 iflags;
914
915 data->error = -EINPROGRESS;
916
917 WARN_ON(host->data);
918 host->sg = NULL;
919 host->data = data;
920
921 iflags = ATMCI_DATA_ERROR_FLAGS;
922
923 /*
924 * We don't do DMA on "complex" transfers, i.e. with
925 * non-word-aligned buffers or lengths. Also, we don't bother
926 * with all the DMA setup overhead for short transfers.
927 */
928 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
929 return atmci_prepare_data(host, data);
930 if (data->blksz & 3)
931 return atmci_prepare_data(host, data);
932
933 for_each_sg(data->sg, sg, data->sg_len, i) {
934 if (sg->offset & 3 || sg->length & 3)
935 return atmci_prepare_data(host, data);
936 }
937
938 /* If we don't have a channel, we can't do DMA */
939 chan = host->dma.chan;
940 if (chan)
941 host->data_chan = chan;
942
943 if (!chan)
944 return -ENODEV;
945
946 if (host->caps.has_dma)
947 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
948
949 if (data->flags & MMC_DATA_READ) {
950 direction = DMA_FROM_DEVICE;
951 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
952 } else {
953 direction = DMA_TO_DEVICE;
954 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
955 }
956
957 sglen = dma_map_sg(chan->device->dev, data->sg,
958 data->sg_len, direction);
959
960 dmaengine_slave_config(chan, &host->dma_conf);
961 desc = dmaengine_prep_slave_sg(chan,
962 data->sg, sglen, slave_dirn,
963 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
964 if (!desc)
965 goto unmap_exit;
966
967 host->dma.data_desc = desc;
968 desc->callback = atmci_dma_complete;
969 desc->callback_param = host;
970
971 return iflags;
972 unmap_exit:
973 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
974 return -ENOMEM;
975 }
976
977 static void
978 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
979 {
980 return;
981 }
982
983 /*
984 * Start PDC according to transfer direction.
985 */
986 static void
987 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
988 {
989 if (data->flags & MMC_DATA_READ)
990 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
991 else
992 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
993 }
994
995 static void
996 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
997 {
998 struct dma_chan *chan = host->data_chan;
999 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1000
1001 if (chan) {
1002 dmaengine_submit(desc);
1003 dma_async_issue_pending(chan);
1004 }
1005 }
1006
1007 static void atmci_stop_transfer(struct atmel_mci *host)
1008 {
1009 dev_dbg(&host->pdev->dev,
1010 "(%s) set pending xfer complete\n", __func__);
1011 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1012 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1013 }
1014
1015 /*
1016 * Stop data transfer because error(s) occured.
1017 */
1018 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1019 {
1020 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1021 }
1022
1023 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1024 {
1025 struct dma_chan *chan = host->data_chan;
1026
1027 if (chan) {
1028 dmaengine_terminate_all(chan);
1029 atmci_dma_cleanup(host);
1030 } else {
1031 /* Data transfer was stopped by the interrupt handler */
1032 dev_dbg(&host->pdev->dev,
1033 "(%s) set pending xfer complete\n", __func__);
1034 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1035 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1036 }
1037 }
1038
1039 /*
1040 * Start a request: prepare data if needed, prepare the command and activate
1041 * interrupts.
1042 */
1043 static void atmci_start_request(struct atmel_mci *host,
1044 struct atmel_mci_slot *slot)
1045 {
1046 struct mmc_request *mrq;
1047 struct mmc_command *cmd;
1048 struct mmc_data *data;
1049 u32 iflags;
1050 u32 cmdflags;
1051
1052 mrq = slot->mrq;
1053 host->cur_slot = slot;
1054 host->mrq = mrq;
1055
1056 host->pending_events = 0;
1057 host->completed_events = 0;
1058 host->cmd_status = 0;
1059 host->data_status = 0;
1060
1061 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1062
1063 if (host->need_reset || host->caps.need_reset_after_xfer) {
1064 iflags = atmci_readl(host, ATMCI_IMR);
1065 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1066 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1067 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1068 atmci_writel(host, ATMCI_MR, host->mode_reg);
1069 if (host->caps.has_cfg_reg)
1070 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1071 atmci_writel(host, ATMCI_IER, iflags);
1072 host->need_reset = false;
1073 }
1074 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1075
1076 iflags = atmci_readl(host, ATMCI_IMR);
1077 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1078 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1079 iflags);
1080
1081 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1082 /* Send init sequence (74 clock cycles) */
1083 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1084 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1085 cpu_relax();
1086 }
1087 iflags = 0;
1088 data = mrq->data;
1089 if (data) {
1090 atmci_set_timeout(host, slot, data);
1091
1092 /* Must set block count/size before sending command */
1093 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1094 | ATMCI_BLKLEN(data->blksz));
1095 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1096 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1097
1098 iflags |= host->prepare_data(host, data);
1099 }
1100
1101 iflags |= ATMCI_CMDRDY;
1102 cmd = mrq->cmd;
1103 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1104 atmci_send_command(host, cmd, cmdflags);
1105
1106 if (data)
1107 host->submit_data(host, data);
1108
1109 if (mrq->stop) {
1110 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1111 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1112 if (!(data->flags & MMC_DATA_WRITE))
1113 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1114 if (data->flags & MMC_DATA_STREAM)
1115 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1116 else
1117 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1118 }
1119
1120 /*
1121 * We could have enabled interrupts earlier, but I suspect
1122 * that would open up a nice can of interesting race
1123 * conditions (e.g. command and data complete, but stop not
1124 * prepared yet.)
1125 */
1126 atmci_writel(host, ATMCI_IER, iflags);
1127
1128 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1129 }
1130
1131 static void atmci_queue_request(struct atmel_mci *host,
1132 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1133 {
1134 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1135 host->state);
1136
1137 spin_lock_bh(&host->lock);
1138 slot->mrq = mrq;
1139 if (host->state == STATE_IDLE) {
1140 host->state = STATE_SENDING_CMD;
1141 atmci_start_request(host, slot);
1142 } else {
1143 dev_dbg(&host->pdev->dev, "queue request\n");
1144 list_add_tail(&slot->queue_node, &host->queue);
1145 }
1146 spin_unlock_bh(&host->lock);
1147 }
1148
1149 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1150 {
1151 struct atmel_mci_slot *slot = mmc_priv(mmc);
1152 struct atmel_mci *host = slot->host;
1153 struct mmc_data *data;
1154
1155 WARN_ON(slot->mrq);
1156 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1157
1158 /*
1159 * We may "know" the card is gone even though there's still an
1160 * electrical connection. If so, we really need to communicate
1161 * this to the MMC core since there won't be any more
1162 * interrupts as the card is completely removed. Otherwise,
1163 * the MMC core might believe the card is still there even
1164 * though the card was just removed very slowly.
1165 */
1166 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1167 mrq->cmd->error = -ENOMEDIUM;
1168 mmc_request_done(mmc, mrq);
1169 return;
1170 }
1171
1172 /* We don't support multiple blocks of weird lengths. */
1173 data = mrq->data;
1174 if (data && data->blocks > 1 && data->blksz & 3) {
1175 mrq->cmd->error = -EINVAL;
1176 mmc_request_done(mmc, mrq);
1177 }
1178
1179 atmci_queue_request(host, slot, mrq);
1180 }
1181
1182 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1183 {
1184 struct atmel_mci_slot *slot = mmc_priv(mmc);
1185 struct atmel_mci *host = slot->host;
1186 unsigned int i;
1187
1188 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1189 switch (ios->bus_width) {
1190 case MMC_BUS_WIDTH_1:
1191 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1192 break;
1193 case MMC_BUS_WIDTH_4:
1194 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1195 break;
1196 }
1197
1198 if (ios->clock) {
1199 unsigned int clock_min = ~0U;
1200 u32 clkdiv;
1201
1202 spin_lock_bh(&host->lock);
1203 if (!host->mode_reg) {
1204 clk_enable(host->mck);
1205 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1206 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1207 if (host->caps.has_cfg_reg)
1208 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1209 }
1210
1211 /*
1212 * Use mirror of ios->clock to prevent race with mmc
1213 * core ios update when finding the minimum.
1214 */
1215 slot->clock = ios->clock;
1216 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1217 if (host->slot[i] && host->slot[i]->clock
1218 && host->slot[i]->clock < clock_min)
1219 clock_min = host->slot[i]->clock;
1220 }
1221
1222 /* Calculate clock divider */
1223 if (host->caps.has_odd_clk_div) {
1224 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1225 if (clkdiv > 511) {
1226 dev_warn(&mmc->class_dev,
1227 "clock %u too slow; using %lu\n",
1228 clock_min, host->bus_hz / (511 + 2));
1229 clkdiv = 511;
1230 }
1231 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1232 | ATMCI_MR_CLKODD(clkdiv & 1);
1233 } else {
1234 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1235 if (clkdiv > 255) {
1236 dev_warn(&mmc->class_dev,
1237 "clock %u too slow; using %lu\n",
1238 clock_min, host->bus_hz / (2 * 256));
1239 clkdiv = 255;
1240 }
1241 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1242 }
1243
1244 /*
1245 * WRPROOF and RDPROOF prevent overruns/underruns by
1246 * stopping the clock when the FIFO is full/empty.
1247 * This state is not expected to last for long.
1248 */
1249 if (host->caps.has_rwproof)
1250 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1251
1252 if (host->caps.has_cfg_reg) {
1253 /* setup High Speed mode in relation with card capacity */
1254 if (ios->timing == MMC_TIMING_SD_HS)
1255 host->cfg_reg |= ATMCI_CFG_HSMODE;
1256 else
1257 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1258 }
1259
1260 if (list_empty(&host->queue)) {
1261 atmci_writel(host, ATMCI_MR, host->mode_reg);
1262 if (host->caps.has_cfg_reg)
1263 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1264 } else {
1265 host->need_clock_update = true;
1266 }
1267
1268 spin_unlock_bh(&host->lock);
1269 } else {
1270 bool any_slot_active = false;
1271
1272 spin_lock_bh(&host->lock);
1273 slot->clock = 0;
1274 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1275 if (host->slot[i] && host->slot[i]->clock) {
1276 any_slot_active = true;
1277 break;
1278 }
1279 }
1280 if (!any_slot_active) {
1281 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1282 if (host->mode_reg) {
1283 atmci_readl(host, ATMCI_MR);
1284 clk_disable(host->mck);
1285 }
1286 host->mode_reg = 0;
1287 }
1288 spin_unlock_bh(&host->lock);
1289 }
1290
1291 switch (ios->power_mode) {
1292 case MMC_POWER_UP:
1293 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1294 break;
1295 default:
1296 /*
1297 * TODO: None of the currently available AVR32-based
1298 * boards allow MMC power to be turned off. Implement
1299 * power control when this can be tested properly.
1300 *
1301 * We also need to hook this into the clock management
1302 * somehow so that newly inserted cards aren't
1303 * subjected to a fast clock before we have a chance
1304 * to figure out what the maximum rate is. Currently,
1305 * there's no way to avoid this, and there never will
1306 * be for boards that don't support power control.
1307 */
1308 break;
1309 }
1310 }
1311
1312 static int atmci_get_ro(struct mmc_host *mmc)
1313 {
1314 int read_only = -ENOSYS;
1315 struct atmel_mci_slot *slot = mmc_priv(mmc);
1316
1317 if (gpio_is_valid(slot->wp_pin)) {
1318 read_only = gpio_get_value(slot->wp_pin);
1319 dev_dbg(&mmc->class_dev, "card is %s\n",
1320 read_only ? "read-only" : "read-write");
1321 }
1322
1323 return read_only;
1324 }
1325
1326 static int atmci_get_cd(struct mmc_host *mmc)
1327 {
1328 int present = -ENOSYS;
1329 struct atmel_mci_slot *slot = mmc_priv(mmc);
1330
1331 if (gpio_is_valid(slot->detect_pin)) {
1332 present = !(gpio_get_value(slot->detect_pin) ^
1333 slot->detect_is_active_high);
1334 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1335 present ? "" : "not ");
1336 }
1337
1338 return present;
1339 }
1340
1341 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1342 {
1343 struct atmel_mci_slot *slot = mmc_priv(mmc);
1344 struct atmel_mci *host = slot->host;
1345
1346 if (enable)
1347 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1348 else
1349 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1350 }
1351
1352 static const struct mmc_host_ops atmci_ops = {
1353 .request = atmci_request,
1354 .set_ios = atmci_set_ios,
1355 .get_ro = atmci_get_ro,
1356 .get_cd = atmci_get_cd,
1357 .enable_sdio_irq = atmci_enable_sdio_irq,
1358 };
1359
1360 /* Called with host->lock held */
1361 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1362 __releases(&host->lock)
1363 __acquires(&host->lock)
1364 {
1365 struct atmel_mci_slot *slot = NULL;
1366 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1367
1368 WARN_ON(host->cmd || host->data);
1369
1370 /*
1371 * Update the MMC clock rate if necessary. This may be
1372 * necessary if set_ios() is called when a different slot is
1373 * busy transferring data.
1374 */
1375 if (host->need_clock_update) {
1376 atmci_writel(host, ATMCI_MR, host->mode_reg);
1377 if (host->caps.has_cfg_reg)
1378 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1379 }
1380
1381 host->cur_slot->mrq = NULL;
1382 host->mrq = NULL;
1383 if (!list_empty(&host->queue)) {
1384 slot = list_entry(host->queue.next,
1385 struct atmel_mci_slot, queue_node);
1386 list_del(&slot->queue_node);
1387 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1388 mmc_hostname(slot->mmc));
1389 host->state = STATE_SENDING_CMD;
1390 atmci_start_request(host, slot);
1391 } else {
1392 dev_vdbg(&host->pdev->dev, "list empty\n");
1393 host->state = STATE_IDLE;
1394 }
1395
1396 del_timer(&host->timer);
1397
1398 spin_unlock(&host->lock);
1399 mmc_request_done(prev_mmc, mrq);
1400 spin_lock(&host->lock);
1401 }
1402
1403 static void atmci_command_complete(struct atmel_mci *host,
1404 struct mmc_command *cmd)
1405 {
1406 u32 status = host->cmd_status;
1407
1408 /* Read the response from the card (up to 16 bytes) */
1409 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1410 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1411 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1412 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1413
1414 if (status & ATMCI_RTOE)
1415 cmd->error = -ETIMEDOUT;
1416 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1417 cmd->error = -EILSEQ;
1418 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1419 cmd->error = -EIO;
1420 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1421 if (host->caps.need_blksz_mul_4) {
1422 cmd->error = -EINVAL;
1423 host->need_reset = 1;
1424 }
1425 } else
1426 cmd->error = 0;
1427 }
1428
1429 static void atmci_detect_change(unsigned long data)
1430 {
1431 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1432 bool present;
1433 bool present_old;
1434
1435 /*
1436 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1437 * freeing the interrupt. We must not re-enable the interrupt
1438 * if it has been freed, and if we're shutting down, it
1439 * doesn't really matter whether the card is present or not.
1440 */
1441 smp_rmb();
1442 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1443 return;
1444
1445 enable_irq(gpio_to_irq(slot->detect_pin));
1446 present = !(gpio_get_value(slot->detect_pin) ^
1447 slot->detect_is_active_high);
1448 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1449
1450 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1451 present, present_old);
1452
1453 if (present != present_old) {
1454 struct atmel_mci *host = slot->host;
1455 struct mmc_request *mrq;
1456
1457 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1458 present ? "inserted" : "removed");
1459
1460 spin_lock(&host->lock);
1461
1462 if (!present)
1463 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1464 else
1465 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1466
1467 /* Clean up queue if present */
1468 mrq = slot->mrq;
1469 if (mrq) {
1470 if (mrq == host->mrq) {
1471 /*
1472 * Reset controller to terminate any ongoing
1473 * commands or data transfers.
1474 */
1475 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1476 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1477 atmci_writel(host, ATMCI_MR, host->mode_reg);
1478 if (host->caps.has_cfg_reg)
1479 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1480
1481 host->data = NULL;
1482 host->cmd = NULL;
1483
1484 switch (host->state) {
1485 case STATE_IDLE:
1486 break;
1487 case STATE_SENDING_CMD:
1488 mrq->cmd->error = -ENOMEDIUM;
1489 if (mrq->data)
1490 host->stop_transfer(host);
1491 break;
1492 case STATE_DATA_XFER:
1493 mrq->data->error = -ENOMEDIUM;
1494 host->stop_transfer(host);
1495 break;
1496 case STATE_WAITING_NOTBUSY:
1497 mrq->data->error = -ENOMEDIUM;
1498 break;
1499 case STATE_SENDING_STOP:
1500 mrq->stop->error = -ENOMEDIUM;
1501 break;
1502 case STATE_END_REQUEST:
1503 break;
1504 }
1505
1506 atmci_request_end(host, mrq);
1507 } else {
1508 list_del(&slot->queue_node);
1509 mrq->cmd->error = -ENOMEDIUM;
1510 if (mrq->data)
1511 mrq->data->error = -ENOMEDIUM;
1512 if (mrq->stop)
1513 mrq->stop->error = -ENOMEDIUM;
1514
1515 spin_unlock(&host->lock);
1516 mmc_request_done(slot->mmc, mrq);
1517 spin_lock(&host->lock);
1518 }
1519 }
1520 spin_unlock(&host->lock);
1521
1522 mmc_detect_change(slot->mmc, 0);
1523 }
1524 }
1525
1526 static void atmci_tasklet_func(unsigned long priv)
1527 {
1528 struct atmel_mci *host = (struct atmel_mci *)priv;
1529 struct mmc_request *mrq = host->mrq;
1530 struct mmc_data *data = host->data;
1531 enum atmel_mci_state state = host->state;
1532 enum atmel_mci_state prev_state;
1533 u32 status;
1534
1535 spin_lock(&host->lock);
1536
1537 state = host->state;
1538
1539 dev_vdbg(&host->pdev->dev,
1540 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1541 state, host->pending_events, host->completed_events,
1542 atmci_readl(host, ATMCI_IMR));
1543
1544 do {
1545 prev_state = state;
1546 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1547
1548 switch (state) {
1549 case STATE_IDLE:
1550 break;
1551
1552 case STATE_SENDING_CMD:
1553 /*
1554 * Command has been sent, we are waiting for command
1555 * ready. Then we have three next states possible:
1556 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1557 * command needing it or DATA_XFER if there is data.
1558 */
1559 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1560 if (!atmci_test_and_clear_pending(host,
1561 EVENT_CMD_RDY))
1562 break;
1563
1564 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1565 host->cmd = NULL;
1566 atmci_set_completed(host, EVENT_CMD_RDY);
1567 atmci_command_complete(host, mrq->cmd);
1568 if (mrq->data) {
1569 dev_dbg(&host->pdev->dev,
1570 "command with data transfer");
1571 /*
1572 * If there is a command error don't start
1573 * data transfer.
1574 */
1575 if (mrq->cmd->error) {
1576 host->stop_transfer(host);
1577 host->data = NULL;
1578 atmci_writel(host, ATMCI_IDR,
1579 ATMCI_TXRDY | ATMCI_RXRDY
1580 | ATMCI_DATA_ERROR_FLAGS);
1581 state = STATE_END_REQUEST;
1582 } else
1583 state = STATE_DATA_XFER;
1584 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1585 dev_dbg(&host->pdev->dev,
1586 "command response need waiting notbusy");
1587 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1588 state = STATE_WAITING_NOTBUSY;
1589 } else
1590 state = STATE_END_REQUEST;
1591
1592 break;
1593
1594 case STATE_DATA_XFER:
1595 if (atmci_test_and_clear_pending(host,
1596 EVENT_DATA_ERROR)) {
1597 dev_dbg(&host->pdev->dev, "set completed data error\n");
1598 atmci_set_completed(host, EVENT_DATA_ERROR);
1599 state = STATE_END_REQUEST;
1600 break;
1601 }
1602
1603 /*
1604 * A data transfer is in progress. The event expected
1605 * to move to the next state depends of data transfer
1606 * type (PDC or DMA). Once transfer done we can move
1607 * to the next step which is WAITING_NOTBUSY in write
1608 * case and directly SENDING_STOP in read case.
1609 */
1610 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1611 if (!atmci_test_and_clear_pending(host,
1612 EVENT_XFER_COMPLETE))
1613 break;
1614
1615 dev_dbg(&host->pdev->dev,
1616 "(%s) set completed xfer complete\n",
1617 __func__);
1618 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1619
1620 if (host->data->flags & MMC_DATA_WRITE) {
1621 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1622 state = STATE_WAITING_NOTBUSY;
1623 } else if (host->mrq->stop) {
1624 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1625 atmci_send_stop_cmd(host, data);
1626 state = STATE_SENDING_STOP;
1627 } else {
1628 host->data = NULL;
1629 data->bytes_xfered = data->blocks * data->blksz;
1630 data->error = 0;
1631 state = STATE_END_REQUEST;
1632 }
1633 break;
1634
1635 case STATE_WAITING_NOTBUSY:
1636 /*
1637 * We can be in the state for two reasons: a command
1638 * requiring waiting not busy signal (stop command
1639 * included) or a write operation. In the latest case,
1640 * we need to send a stop command.
1641 */
1642 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1643 if (!atmci_test_and_clear_pending(host,
1644 EVENT_NOTBUSY))
1645 break;
1646
1647 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1648 atmci_set_completed(host, EVENT_NOTBUSY);
1649
1650 if (host->data) {
1651 /*
1652 * For some commands such as CMD53, even if
1653 * there is data transfer, there is no stop
1654 * command to send.
1655 */
1656 if (host->mrq->stop) {
1657 atmci_writel(host, ATMCI_IER,
1658 ATMCI_CMDRDY);
1659 atmci_send_stop_cmd(host, data);
1660 state = STATE_SENDING_STOP;
1661 } else {
1662 host->data = NULL;
1663 data->bytes_xfered = data->blocks
1664 * data->blksz;
1665 data->error = 0;
1666 state = STATE_END_REQUEST;
1667 }
1668 } else
1669 state = STATE_END_REQUEST;
1670 break;
1671
1672 case STATE_SENDING_STOP:
1673 /*
1674 * In this state, it is important to set host->data to
1675 * NULL (which is tested in the waiting notbusy state)
1676 * in order to go to the end request state instead of
1677 * sending stop again.
1678 */
1679 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1680 if (!atmci_test_and_clear_pending(host,
1681 EVENT_CMD_RDY))
1682 break;
1683
1684 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1685 host->cmd = NULL;
1686 host->data = NULL;
1687 data->bytes_xfered = data->blocks * data->blksz;
1688 data->error = 0;
1689 atmci_command_complete(host, mrq->stop);
1690 if (mrq->stop->error) {
1691 host->stop_transfer(host);
1692 atmci_writel(host, ATMCI_IDR,
1693 ATMCI_TXRDY | ATMCI_RXRDY
1694 | ATMCI_DATA_ERROR_FLAGS);
1695 state = STATE_END_REQUEST;
1696 } else {
1697 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1698 state = STATE_WAITING_NOTBUSY;
1699 }
1700 break;
1701
1702 case STATE_END_REQUEST:
1703 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1704 | ATMCI_DATA_ERROR_FLAGS);
1705 status = host->data_status;
1706 if (unlikely(status)) {
1707 host->stop_transfer(host);
1708 host->data = NULL;
1709 if (status & ATMCI_DTOE) {
1710 data->error = -ETIMEDOUT;
1711 } else if (status & ATMCI_DCRCE) {
1712 data->error = -EILSEQ;
1713 } else {
1714 data->error = -EIO;
1715 }
1716 }
1717
1718 atmci_request_end(host, host->mrq);
1719 state = STATE_IDLE;
1720 break;
1721 }
1722 } while (state != prev_state);
1723
1724 host->state = state;
1725
1726 spin_unlock(&host->lock);
1727 }
1728
1729 static void atmci_read_data_pio(struct atmel_mci *host)
1730 {
1731 struct scatterlist *sg = host->sg;
1732 void *buf = sg_virt(sg);
1733 unsigned int offset = host->pio_offset;
1734 struct mmc_data *data = host->data;
1735 u32 value;
1736 u32 status;
1737 unsigned int nbytes = 0;
1738
1739 do {
1740 value = atmci_readl(host, ATMCI_RDR);
1741 if (likely(offset + 4 <= sg->length)) {
1742 put_unaligned(value, (u32 *)(buf + offset));
1743
1744 offset += 4;
1745 nbytes += 4;
1746
1747 if (offset == sg->length) {
1748 flush_dcache_page(sg_page(sg));
1749 host->sg = sg = sg_next(sg);
1750 if (!sg)
1751 goto done;
1752
1753 offset = 0;
1754 buf = sg_virt(sg);
1755 }
1756 } else {
1757 unsigned int remaining = sg->length - offset;
1758 memcpy(buf + offset, &value, remaining);
1759 nbytes += remaining;
1760
1761 flush_dcache_page(sg_page(sg));
1762 host->sg = sg = sg_next(sg);
1763 if (!sg)
1764 goto done;
1765
1766 offset = 4 - remaining;
1767 buf = sg_virt(sg);
1768 memcpy(buf, (u8 *)&value + remaining, offset);
1769 nbytes += offset;
1770 }
1771
1772 status = atmci_readl(host, ATMCI_SR);
1773 if (status & ATMCI_DATA_ERROR_FLAGS) {
1774 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1775 | ATMCI_DATA_ERROR_FLAGS));
1776 host->data_status = status;
1777 data->bytes_xfered += nbytes;
1778 return;
1779 }
1780 } while (status & ATMCI_RXRDY);
1781
1782 host->pio_offset = offset;
1783 data->bytes_xfered += nbytes;
1784
1785 return;
1786
1787 done:
1788 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1789 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1790 data->bytes_xfered += nbytes;
1791 smp_wmb();
1792 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1793 }
1794
1795 static void atmci_write_data_pio(struct atmel_mci *host)
1796 {
1797 struct scatterlist *sg = host->sg;
1798 void *buf = sg_virt(sg);
1799 unsigned int offset = host->pio_offset;
1800 struct mmc_data *data = host->data;
1801 u32 value;
1802 u32 status;
1803 unsigned int nbytes = 0;
1804
1805 do {
1806 if (likely(offset + 4 <= sg->length)) {
1807 value = get_unaligned((u32 *)(buf + offset));
1808 atmci_writel(host, ATMCI_TDR, value);
1809
1810 offset += 4;
1811 nbytes += 4;
1812 if (offset == sg->length) {
1813 host->sg = sg = sg_next(sg);
1814 if (!sg)
1815 goto done;
1816
1817 offset = 0;
1818 buf = sg_virt(sg);
1819 }
1820 } else {
1821 unsigned int remaining = sg->length - offset;
1822
1823 value = 0;
1824 memcpy(&value, buf + offset, remaining);
1825 nbytes += remaining;
1826
1827 host->sg = sg = sg_next(sg);
1828 if (!sg) {
1829 atmci_writel(host, ATMCI_TDR, value);
1830 goto done;
1831 }
1832
1833 offset = 4 - remaining;
1834 buf = sg_virt(sg);
1835 memcpy((u8 *)&value + remaining, buf, offset);
1836 atmci_writel(host, ATMCI_TDR, value);
1837 nbytes += offset;
1838 }
1839
1840 status = atmci_readl(host, ATMCI_SR);
1841 if (status & ATMCI_DATA_ERROR_FLAGS) {
1842 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1843 | ATMCI_DATA_ERROR_FLAGS));
1844 host->data_status = status;
1845 data->bytes_xfered += nbytes;
1846 return;
1847 }
1848 } while (status & ATMCI_TXRDY);
1849
1850 host->pio_offset = offset;
1851 data->bytes_xfered += nbytes;
1852
1853 return;
1854
1855 done:
1856 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1857 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1858 data->bytes_xfered += nbytes;
1859 smp_wmb();
1860 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1861 }
1862
1863 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1864 {
1865 int i;
1866
1867 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1868 struct atmel_mci_slot *slot = host->slot[i];
1869 if (slot && (status & slot->sdio_irq)) {
1870 mmc_signal_sdio_irq(slot->mmc);
1871 }
1872 }
1873 }
1874
1875
1876 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1877 {
1878 struct atmel_mci *host = dev_id;
1879 u32 status, mask, pending;
1880 unsigned int pass_count = 0;
1881
1882 do {
1883 status = atmci_readl(host, ATMCI_SR);
1884 mask = atmci_readl(host, ATMCI_IMR);
1885 pending = status & mask;
1886 if (!pending)
1887 break;
1888
1889 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1890 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
1891 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1892 | ATMCI_RXRDY | ATMCI_TXRDY
1893 | ATMCI_ENDRX | ATMCI_ENDTX
1894 | ATMCI_RXBUFF | ATMCI_TXBUFE);
1895
1896 host->data_status = status;
1897 dev_dbg(&host->pdev->dev, "set pending data error\n");
1898 smp_wmb();
1899 atmci_set_pending(host, EVENT_DATA_ERROR);
1900 tasklet_schedule(&host->tasklet);
1901 }
1902
1903 if (pending & ATMCI_TXBUFE) {
1904 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
1905 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1906 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1907 /*
1908 * We can receive this interruption before having configured
1909 * the second pdc buffer, so we need to reconfigure first and
1910 * second buffers again
1911 */
1912 if (host->data_size) {
1913 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1914 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1915 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1916 } else {
1917 atmci_pdc_complete(host);
1918 }
1919 } else if (pending & ATMCI_ENDTX) {
1920 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
1921 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1922
1923 if (host->data_size) {
1924 atmci_pdc_set_single_buf(host,
1925 XFER_TRANSMIT, PDC_SECOND_BUF);
1926 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1927 }
1928 }
1929
1930 if (pending & ATMCI_RXBUFF) {
1931 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
1932 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
1933 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1934 /*
1935 * We can receive this interruption before having configured
1936 * the second pdc buffer, so we need to reconfigure first and
1937 * second buffers again
1938 */
1939 if (host->data_size) {
1940 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
1941 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1942 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1943 } else {
1944 atmci_pdc_complete(host);
1945 }
1946 } else if (pending & ATMCI_ENDRX) {
1947 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
1948 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1949
1950 if (host->data_size) {
1951 atmci_pdc_set_single_buf(host,
1952 XFER_RECEIVE, PDC_SECOND_BUF);
1953 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1954 }
1955 }
1956
1957 /*
1958 * First mci IPs, so mainly the ones having pdc, have some
1959 * issues with the notbusy signal. You can't get it after
1960 * data transmission if you have not sent a stop command.
1961 * The appropriate workaround is to use the BLKE signal.
1962 */
1963 if (pending & ATMCI_BLKE) {
1964 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
1965 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
1966 smp_wmb();
1967 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
1968 atmci_set_pending(host, EVENT_NOTBUSY);
1969 tasklet_schedule(&host->tasklet);
1970 }
1971
1972 if (pending & ATMCI_NOTBUSY) {
1973 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
1974 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
1975 smp_wmb();
1976 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
1977 atmci_set_pending(host, EVENT_NOTBUSY);
1978 tasklet_schedule(&host->tasklet);
1979 }
1980
1981 if (pending & ATMCI_RXRDY)
1982 atmci_read_data_pio(host);
1983 if (pending & ATMCI_TXRDY)
1984 atmci_write_data_pio(host);
1985
1986 if (pending & ATMCI_CMDRDY) {
1987 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
1988 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
1989 host->cmd_status = status;
1990 smp_wmb();
1991 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
1992 atmci_set_pending(host, EVENT_CMD_RDY);
1993 tasklet_schedule(&host->tasklet);
1994 }
1995
1996 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1997 atmci_sdio_interrupt(host, status);
1998
1999 } while (pass_count++ < 5);
2000
2001 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2002 }
2003
2004 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2005 {
2006 struct atmel_mci_slot *slot = dev_id;
2007
2008 /*
2009 * Disable interrupts until the pin has stabilized and check
2010 * the state then. Use mod_timer() since we may be in the
2011 * middle of the timer routine when this interrupt triggers.
2012 */
2013 disable_irq_nosync(irq);
2014 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2015
2016 return IRQ_HANDLED;
2017 }
2018
2019 static int __init atmci_init_slot(struct atmel_mci *host,
2020 struct mci_slot_pdata *slot_data, unsigned int id,
2021 u32 sdc_reg, u32 sdio_irq)
2022 {
2023 struct mmc_host *mmc;
2024 struct atmel_mci_slot *slot;
2025
2026 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2027 if (!mmc)
2028 return -ENOMEM;
2029
2030 slot = mmc_priv(mmc);
2031 slot->mmc = mmc;
2032 slot->host = host;
2033 slot->detect_pin = slot_data->detect_pin;
2034 slot->wp_pin = slot_data->wp_pin;
2035 slot->detect_is_active_high = slot_data->detect_is_active_high;
2036 slot->sdc_reg = sdc_reg;
2037 slot->sdio_irq = sdio_irq;
2038
2039 mmc->ops = &atmci_ops;
2040 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2041 mmc->f_max = host->bus_hz / 2;
2042 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2043 if (sdio_irq)
2044 mmc->caps |= MMC_CAP_SDIO_IRQ;
2045 if (host->caps.has_highspeed)
2046 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2047 /*
2048 * Without the read/write proof capability, it is strongly suggested to
2049 * use only one bit for data to prevent fifo underruns and overruns
2050 * which will corrupt data.
2051 */
2052 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2053 mmc->caps |= MMC_CAP_4_BIT_DATA;
2054
2055 if (atmci_get_version(host) < 0x200) {
2056 mmc->max_segs = 256;
2057 mmc->max_blk_size = 4095;
2058 mmc->max_blk_count = 256;
2059 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2060 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2061 } else {
2062 mmc->max_segs = 64;
2063 mmc->max_req_size = 32768 * 512;
2064 mmc->max_blk_size = 32768;
2065 mmc->max_blk_count = 512;
2066 }
2067
2068 /* Assume card is present initially */
2069 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2070 if (gpio_is_valid(slot->detect_pin)) {
2071 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2072 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2073 slot->detect_pin = -EBUSY;
2074 } else if (gpio_get_value(slot->detect_pin) ^
2075 slot->detect_is_active_high) {
2076 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2077 }
2078 }
2079
2080 if (!gpio_is_valid(slot->detect_pin))
2081 mmc->caps |= MMC_CAP_NEEDS_POLL;
2082
2083 if (gpio_is_valid(slot->wp_pin)) {
2084 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2085 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2086 slot->wp_pin = -EBUSY;
2087 }
2088 }
2089
2090 host->slot[id] = slot;
2091 mmc_add_host(mmc);
2092
2093 if (gpio_is_valid(slot->detect_pin)) {
2094 int ret;
2095
2096 setup_timer(&slot->detect_timer, atmci_detect_change,
2097 (unsigned long)slot);
2098
2099 ret = request_irq(gpio_to_irq(slot->detect_pin),
2100 atmci_detect_interrupt,
2101 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2102 "mmc-detect", slot);
2103 if (ret) {
2104 dev_dbg(&mmc->class_dev,
2105 "could not request IRQ %d for detect pin\n",
2106 gpio_to_irq(slot->detect_pin));
2107 gpio_free(slot->detect_pin);
2108 slot->detect_pin = -EBUSY;
2109 }
2110 }
2111
2112 atmci_init_debugfs(slot);
2113
2114 return 0;
2115 }
2116
2117 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2118 unsigned int id)
2119 {
2120 /* Debugfs stuff is cleaned up by mmc core */
2121
2122 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2123 smp_wmb();
2124
2125 mmc_remove_host(slot->mmc);
2126
2127 if (gpio_is_valid(slot->detect_pin)) {
2128 int pin = slot->detect_pin;
2129
2130 free_irq(gpio_to_irq(pin), slot);
2131 del_timer_sync(&slot->detect_timer);
2132 gpio_free(pin);
2133 }
2134 if (gpio_is_valid(slot->wp_pin))
2135 gpio_free(slot->wp_pin);
2136
2137 slot->host->slot[id] = NULL;
2138 mmc_free_host(slot->mmc);
2139 }
2140
2141 static bool atmci_filter(struct dma_chan *chan, void *slave)
2142 {
2143 struct mci_dma_data *sl = slave;
2144
2145 if (sl && find_slave_dev(sl) == chan->device->dev) {
2146 chan->private = slave_data_ptr(sl);
2147 return true;
2148 } else {
2149 return false;
2150 }
2151 }
2152
2153 static bool atmci_configure_dma(struct atmel_mci *host)
2154 {
2155 struct mci_platform_data *pdata;
2156
2157 if (host == NULL)
2158 return false;
2159
2160 pdata = host->pdev->dev.platform_data;
2161
2162 if (pdata && find_slave_dev(pdata->dma_slave)) {
2163 dma_cap_mask_t mask;
2164
2165 /* Try to grab a DMA channel */
2166 dma_cap_zero(mask);
2167 dma_cap_set(DMA_SLAVE, mask);
2168 host->dma.chan =
2169 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
2170 }
2171 if (!host->dma.chan) {
2172 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2173 return false;
2174 } else {
2175 dev_info(&host->pdev->dev,
2176 "using %s for DMA transfers\n",
2177 dma_chan_name(host->dma.chan));
2178
2179 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2180 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2181 host->dma_conf.src_maxburst = 1;
2182 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2183 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2184 host->dma_conf.dst_maxburst = 1;
2185 host->dma_conf.device_fc = false;
2186 return true;
2187 }
2188 }
2189
2190 /*
2191 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2192 * HSMCI provides DMA support and a new config register but no more supports
2193 * PDC.
2194 */
2195 static void __init atmci_get_cap(struct atmel_mci *host)
2196 {
2197 unsigned int version;
2198
2199 version = atmci_get_version(host);
2200 dev_info(&host->pdev->dev,
2201 "version: 0x%x\n", version);
2202
2203 host->caps.has_dma = 0;
2204 host->caps.has_pdc = 1;
2205 host->caps.has_cfg_reg = 0;
2206 host->caps.has_cstor_reg = 0;
2207 host->caps.has_highspeed = 0;
2208 host->caps.has_rwproof = 0;
2209 host->caps.has_odd_clk_div = 0;
2210 host->caps.has_bad_data_ordering = 1;
2211 host->caps.need_reset_after_xfer = 1;
2212 host->caps.need_blksz_mul_4 = 1;
2213
2214 /* keep only major version number */
2215 switch (version & 0xf00) {
2216 case 0x500:
2217 host->caps.has_odd_clk_div = 1;
2218 case 0x400:
2219 case 0x300:
2220 #ifdef CONFIG_AT_HDMAC
2221 host->caps.has_dma = 1;
2222 #else
2223 dev_info(&host->pdev->dev,
2224 "has dma capability but dma engine is not selected, then use pio\n");
2225 #endif
2226 host->caps.has_pdc = 0;
2227 host->caps.has_cfg_reg = 1;
2228 host->caps.has_cstor_reg = 1;
2229 host->caps.has_highspeed = 1;
2230 case 0x200:
2231 host->caps.has_rwproof = 1;
2232 host->caps.need_blksz_mul_4 = 0;
2233 case 0x100:
2234 host->caps.has_bad_data_ordering = 0;
2235 host->caps.need_reset_after_xfer = 0;
2236 case 0x0:
2237 break;
2238 default:
2239 host->caps.has_pdc = 0;
2240 dev_warn(&host->pdev->dev,
2241 "Unmanaged mci version, set minimum capabilities\n");
2242 break;
2243 }
2244 }
2245
2246 static int __init atmci_probe(struct platform_device *pdev)
2247 {
2248 struct mci_platform_data *pdata;
2249 struct atmel_mci *host;
2250 struct resource *regs;
2251 unsigned int nr_slots;
2252 int irq;
2253 int ret;
2254
2255 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2256 if (!regs)
2257 return -ENXIO;
2258 pdata = pdev->dev.platform_data;
2259 if (!pdata)
2260 return -ENXIO;
2261 irq = platform_get_irq(pdev, 0);
2262 if (irq < 0)
2263 return irq;
2264
2265 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2266 if (!host)
2267 return -ENOMEM;
2268
2269 host->pdev = pdev;
2270 spin_lock_init(&host->lock);
2271 INIT_LIST_HEAD(&host->queue);
2272
2273 host->mck = clk_get(&pdev->dev, "mci_clk");
2274 if (IS_ERR(host->mck)) {
2275 ret = PTR_ERR(host->mck);
2276 goto err_clk_get;
2277 }
2278
2279 ret = -ENOMEM;
2280 host->regs = ioremap(regs->start, resource_size(regs));
2281 if (!host->regs)
2282 goto err_ioremap;
2283
2284 clk_enable(host->mck);
2285 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2286 host->bus_hz = clk_get_rate(host->mck);
2287 clk_disable(host->mck);
2288
2289 host->mapbase = regs->start;
2290
2291 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2292
2293 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2294 if (ret)
2295 goto err_request_irq;
2296
2297 /* Get MCI capabilities and set operations according to it */
2298 atmci_get_cap(host);
2299 if (host->caps.has_dma && atmci_configure_dma(host)) {
2300 host->prepare_data = &atmci_prepare_data_dma;
2301 host->submit_data = &atmci_submit_data_dma;
2302 host->stop_transfer = &atmci_stop_transfer_dma;
2303 } else if (host->caps.has_pdc) {
2304 dev_info(&pdev->dev, "using PDC\n");
2305 host->prepare_data = &atmci_prepare_data_pdc;
2306 host->submit_data = &atmci_submit_data_pdc;
2307 host->stop_transfer = &atmci_stop_transfer_pdc;
2308 } else {
2309 dev_info(&pdev->dev, "using PIO\n");
2310 host->prepare_data = &atmci_prepare_data;
2311 host->submit_data = &atmci_submit_data;
2312 host->stop_transfer = &atmci_stop_transfer;
2313 }
2314
2315 platform_set_drvdata(pdev, host);
2316
2317 /* We need at least one slot to succeed */
2318 nr_slots = 0;
2319 ret = -ENODEV;
2320 if (pdata->slot[0].bus_width) {
2321 ret = atmci_init_slot(host, &pdata->slot[0],
2322 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2323 if (!ret) {
2324 nr_slots++;
2325 host->buf_size = host->slot[0]->mmc->max_req_size;
2326 }
2327 }
2328 if (pdata->slot[1].bus_width) {
2329 ret = atmci_init_slot(host, &pdata->slot[1],
2330 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2331 if (!ret) {
2332 nr_slots++;
2333 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2334 host->buf_size =
2335 host->slot[1]->mmc->max_req_size;
2336 }
2337 }
2338
2339 if (!nr_slots) {
2340 dev_err(&pdev->dev, "init failed: no slot defined\n");
2341 goto err_init_slot;
2342 }
2343
2344 if (!host->caps.has_rwproof) {
2345 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2346 &host->buf_phys_addr,
2347 GFP_KERNEL);
2348 if (!host->buffer) {
2349 ret = -ENOMEM;
2350 dev_err(&pdev->dev, "buffer allocation failed\n");
2351 goto err_init_slot;
2352 }
2353 }
2354
2355 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2356
2357 dev_info(&pdev->dev,
2358 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2359 host->mapbase, irq, nr_slots);
2360
2361 return 0;
2362
2363 err_init_slot:
2364 if (host->dma.chan)
2365 dma_release_channel(host->dma.chan);
2366 free_irq(irq, host);
2367 err_request_irq:
2368 iounmap(host->regs);
2369 err_ioremap:
2370 clk_put(host->mck);
2371 err_clk_get:
2372 kfree(host);
2373 return ret;
2374 }
2375
2376 static int __exit atmci_remove(struct platform_device *pdev)
2377 {
2378 struct atmel_mci *host = platform_get_drvdata(pdev);
2379 unsigned int i;
2380
2381 platform_set_drvdata(pdev, NULL);
2382
2383 if (host->buffer)
2384 dma_free_coherent(&pdev->dev, host->buf_size,
2385 host->buffer, host->buf_phys_addr);
2386
2387 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2388 if (host->slot[i])
2389 atmci_cleanup_slot(host->slot[i], i);
2390 }
2391
2392 clk_enable(host->mck);
2393 atmci_writel(host, ATMCI_IDR, ~0UL);
2394 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2395 atmci_readl(host, ATMCI_SR);
2396 clk_disable(host->mck);
2397
2398 #ifdef CONFIG_MMC_ATMELMCI_DMA
2399 if (host->dma.chan)
2400 dma_release_channel(host->dma.chan);
2401 #endif
2402
2403 free_irq(platform_get_irq(pdev, 0), host);
2404 iounmap(host->regs);
2405
2406 clk_put(host->mck);
2407 kfree(host);
2408
2409 return 0;
2410 }
2411
2412 #ifdef CONFIG_PM
2413 static int atmci_suspend(struct device *dev)
2414 {
2415 struct atmel_mci *host = dev_get_drvdata(dev);
2416 int i;
2417
2418 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2419 struct atmel_mci_slot *slot = host->slot[i];
2420 int ret;
2421
2422 if (!slot)
2423 continue;
2424 ret = mmc_suspend_host(slot->mmc);
2425 if (ret < 0) {
2426 while (--i >= 0) {
2427 slot = host->slot[i];
2428 if (slot
2429 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2430 mmc_resume_host(host->slot[i]->mmc);
2431 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2432 }
2433 }
2434 return ret;
2435 } else {
2436 set_bit(ATMCI_SUSPENDED, &slot->flags);
2437 }
2438 }
2439
2440 return 0;
2441 }
2442
2443 static int atmci_resume(struct device *dev)
2444 {
2445 struct atmel_mci *host = dev_get_drvdata(dev);
2446 int i;
2447 int ret = 0;
2448
2449 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2450 struct atmel_mci_slot *slot = host->slot[i];
2451 int err;
2452
2453 slot = host->slot[i];
2454 if (!slot)
2455 continue;
2456 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2457 continue;
2458 err = mmc_resume_host(slot->mmc);
2459 if (err < 0)
2460 ret = err;
2461 else
2462 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2463 }
2464
2465 return ret;
2466 }
2467 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2468 #define ATMCI_PM_OPS (&atmci_pm)
2469 #else
2470 #define ATMCI_PM_OPS NULL
2471 #endif
2472
2473 static struct platform_driver atmci_driver = {
2474 .remove = __exit_p(atmci_remove),
2475 .driver = {
2476 .name = "atmel_mci",
2477 .pm = ATMCI_PM_OPS,
2478 },
2479 };
2480
2481 static int __init atmci_init(void)
2482 {
2483 return platform_driver_probe(&atmci_driver, atmci_probe);
2484 }
2485
2486 static void __exit atmci_exit(void)
2487 {
2488 platform_driver_unregister(&atmci_driver);
2489 }
2490
2491 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2492 module_exit(atmci_exit);
2493
2494 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2495 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2496 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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