2 * Atmel MultiMedia Card Interface driver
4 * Copyright (C) 2004-2008 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27 #include <linux/types.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/sdio.h>
32 #include <mach/atmel-mci.h>
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
37 #include <asm/unaligned.h>
40 #include <mach/board.h>
42 #include "atmel-mci-regs.h"
44 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
45 #define ATMCI_DMA_THRESHOLD 16
54 enum atmel_mci_state
{
58 STATE_WAITING_NOTBUSY
,
73 struct atmel_mci_caps
{
81 bool has_bad_data_ordering
;
82 bool need_reset_after_xfer
;
83 bool need_blksz_mul_4
;
86 struct atmel_mci_dma
{
87 struct dma_chan
*chan
;
88 struct dma_async_tx_descriptor
*data_desc
;
92 * struct atmel_mci - MMC controller state shared between all slots
93 * @lock: Spinlock protecting the queue and associated data.
94 * @regs: Pointer to MMIO registers.
95 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
96 * @pio_offset: Offset into the current scatterlist entry.
97 * @buffer: Buffer used if we don't have the r/w proof capability. We
98 * don't have the time to switch pdc buffers so we have to use only
99 * one buffer for the full transaction.
100 * @buf_size: size of the buffer.
101 * @phys_buf_addr: buffer address needed for pdc.
102 * @cur_slot: The slot which is currently using the controller.
103 * @mrq: The request currently being processed on @cur_slot,
104 * or NULL if the controller is idle.
105 * @cmd: The command currently being sent to the card, or NULL.
106 * @data: The data currently being transferred, or NULL if no data
107 * transfer is in progress.
108 * @data_size: just data->blocks * data->blksz.
109 * @dma: DMA client state.
110 * @data_chan: DMA channel being used for the current data transfer.
111 * @cmd_status: Snapshot of SR taken upon completion of the current
112 * command. Only valid when EVENT_CMD_COMPLETE is pending.
113 * @data_status: Snapshot of SR taken upon completion of the current
114 * data transfer. Only valid when EVENT_DATA_COMPLETE or
115 * EVENT_DATA_ERROR is pending.
116 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
118 * @tasklet: Tasklet running the request state machine.
119 * @pending_events: Bitmask of events flagged by the interrupt handler
120 * to be processed by the tasklet.
121 * @completed_events: Bitmask of events which the state machine has
123 * @state: Tasklet state.
124 * @queue: List of slots waiting for access to the controller.
125 * @need_clock_update: Update the clock rate before the next request.
126 * @need_reset: Reset controller before next request.
127 * @timer: Timer to balance the data timeout error flag which cannot rise.
128 * @mode_reg: Value of the MR register.
129 * @cfg_reg: Value of the CFG register.
130 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
131 * rate and timeout calculations.
132 * @mapbase: Physical address of the MMIO registers.
133 * @mck: The peripheral bus clock hooked up to the MMC controller.
134 * @pdev: Platform device associated with the MMC controller.
135 * @slot: Slots sharing this MMC controller.
136 * @caps: MCI capabilities depending on MCI version.
137 * @prepare_data: function to setup MCI before data transfer which
138 * depends on MCI capabilities.
139 * @submit_data: function to start data transfer which depends on MCI
141 * @stop_transfer: function to stop data transfer which depends on MCI
147 * @lock is a softirq-safe spinlock protecting @queue as well as
148 * @cur_slot, @mrq and @state. These must always be updated
149 * at the same time while holding @lock.
151 * @lock also protects mode_reg and need_clock_update since these are
152 * used to synchronize mode register updates with the queue
155 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
156 * and must always be written at the same time as the slot is added to
159 * @pending_events and @completed_events are accessed using atomic bit
160 * operations, so they don't need any locking.
162 * None of the fields touched by the interrupt handler need any
163 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
164 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
165 * interrupts must be disabled and @data_status updated with a
166 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
167 * CMDRDY interrupt must be disabled and @cmd_status updated with a
168 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
169 * bytes_xfered field of @data must be written. This is ensured by
176 struct scatterlist
*sg
;
177 unsigned int pio_offset
;
178 unsigned int *buffer
;
179 unsigned int buf_size
;
180 dma_addr_t buf_phys_addr
;
182 struct atmel_mci_slot
*cur_slot
;
183 struct mmc_request
*mrq
;
184 struct mmc_command
*cmd
;
185 struct mmc_data
*data
;
186 unsigned int data_size
;
188 struct atmel_mci_dma dma
;
189 struct dma_chan
*data_chan
;
190 struct dma_slave_config dma_conf
;
196 struct tasklet_struct tasklet
;
197 unsigned long pending_events
;
198 unsigned long completed_events
;
199 enum atmel_mci_state state
;
200 struct list_head queue
;
202 bool need_clock_update
;
204 struct timer_list timer
;
207 unsigned long bus_hz
;
208 unsigned long mapbase
;
210 struct platform_device
*pdev
;
212 struct atmel_mci_slot
*slot
[ATMCI_MAX_NR_SLOTS
];
214 struct atmel_mci_caps caps
;
216 u32 (*prepare_data
)(struct atmel_mci
*host
, struct mmc_data
*data
);
217 void (*submit_data
)(struct atmel_mci
*host
, struct mmc_data
*data
);
218 void (*stop_transfer
)(struct atmel_mci
*host
);
222 * struct atmel_mci_slot - MMC slot state
223 * @mmc: The mmc_host representing this slot.
224 * @host: The MMC controller this slot is using.
225 * @sdc_reg: Value of SDCR to be written before using this slot.
226 * @sdio_irq: SDIO irq mask for this slot.
227 * @mrq: mmc_request currently being processed or waiting to be
228 * processed, or NULL when the slot is idle.
229 * @queue_node: List node for placing this node in the @queue list of
231 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
232 * @flags: Random state bits associated with the slot.
233 * @detect_pin: GPIO pin used for card detection, or negative if not
235 * @wp_pin: GPIO pin used for card write protect sending, or negative
237 * @detect_is_active_high: The state of the detect pin when it is active.
238 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
240 struct atmel_mci_slot
{
241 struct mmc_host
*mmc
;
242 struct atmel_mci
*host
;
247 struct mmc_request
*mrq
;
248 struct list_head queue_node
;
252 #define ATMCI_CARD_PRESENT 0
253 #define ATMCI_CARD_NEED_INIT 1
254 #define ATMCI_SHUTDOWN 2
255 #define ATMCI_SUSPENDED 3
259 bool detect_is_active_high
;
261 struct timer_list detect_timer
;
264 #define atmci_test_and_clear_pending(host, event) \
265 test_and_clear_bit(event, &host->pending_events)
266 #define atmci_set_completed(host, event) \
267 set_bit(event, &host->completed_events)
268 #define atmci_set_pending(host, event) \
269 set_bit(event, &host->pending_events)
272 * The debugfs stuff below is mostly optimized away when
273 * CONFIG_DEBUG_FS is not set.
275 static int atmci_req_show(struct seq_file
*s
, void *v
)
277 struct atmel_mci_slot
*slot
= s
->private;
278 struct mmc_request
*mrq
;
279 struct mmc_command
*cmd
;
280 struct mmc_command
*stop
;
281 struct mmc_data
*data
;
283 /* Make sure we get a consistent snapshot */
284 spin_lock_bh(&slot
->host
->lock
);
294 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
295 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
296 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
297 cmd
->resp
[3], cmd
->error
);
299 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
300 data
->bytes_xfered
, data
->blocks
,
301 data
->blksz
, data
->flags
, data
->error
);
304 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
305 stop
->opcode
, stop
->arg
, stop
->flags
,
306 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
307 stop
->resp
[3], stop
->error
);
310 spin_unlock_bh(&slot
->host
->lock
);
315 static int atmci_req_open(struct inode
*inode
, struct file
*file
)
317 return single_open(file
, atmci_req_show
, inode
->i_private
);
320 static const struct file_operations atmci_req_fops
= {
321 .owner
= THIS_MODULE
,
322 .open
= atmci_req_open
,
325 .release
= single_release
,
328 static void atmci_show_status_reg(struct seq_file
*s
,
329 const char *regname
, u32 value
)
331 static const char *sr_bit
[] = {
362 seq_printf(s
, "%s:\t0x%08x", regname
, value
);
363 for (i
= 0; i
< ARRAY_SIZE(sr_bit
); i
++) {
364 if (value
& (1 << i
)) {
366 seq_printf(s
, " %s", sr_bit
[i
]);
368 seq_puts(s
, " UNKNOWN");
374 static int atmci_regs_show(struct seq_file
*s
, void *v
)
376 struct atmel_mci
*host
= s
->private;
379 buf
= kmalloc(ATMCI_REGS_SIZE
, GFP_KERNEL
);
384 * Grab a more or less consistent snapshot. Note that we're
385 * not disabling interrupts, so IMR and SR may not be
388 spin_lock_bh(&host
->lock
);
389 clk_enable(host
->mck
);
390 memcpy_fromio(buf
, host
->regs
, ATMCI_REGS_SIZE
);
391 clk_disable(host
->mck
);
392 spin_unlock_bh(&host
->lock
);
394 seq_printf(s
, "MR:\t0x%08x%s%s CLKDIV=%u\n",
396 buf
[ATMCI_MR
/ 4] & ATMCI_MR_RDPROOF
? " RDPROOF" : "",
397 buf
[ATMCI_MR
/ 4] & ATMCI_MR_WRPROOF
? " WRPROOF" : "",
398 buf
[ATMCI_MR
/ 4] & 0xff);
399 seq_printf(s
, "DTOR:\t0x%08x\n", buf
[ATMCI_DTOR
/ 4]);
400 seq_printf(s
, "SDCR:\t0x%08x\n", buf
[ATMCI_SDCR
/ 4]);
401 seq_printf(s
, "ARGR:\t0x%08x\n", buf
[ATMCI_ARGR
/ 4]);
402 seq_printf(s
, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
404 buf
[ATMCI_BLKR
/ 4] & 0xffff,
405 (buf
[ATMCI_BLKR
/ 4] >> 16) & 0xffff);
406 if (host
->caps
.has_cstor_reg
)
407 seq_printf(s
, "CSTOR:\t0x%08x\n", buf
[ATMCI_CSTOR
/ 4]);
409 /* Don't read RSPR and RDR; it will consume the data there */
411 atmci_show_status_reg(s
, "SR", buf
[ATMCI_SR
/ 4]);
412 atmci_show_status_reg(s
, "IMR", buf
[ATMCI_IMR
/ 4]);
414 if (host
->caps
.has_dma
) {
417 val
= buf
[ATMCI_DMA
/ 4];
418 seq_printf(s
, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
421 1 << (((val
>> 4) & 3) + 1) : 1,
422 val
& ATMCI_DMAEN
? " DMAEN" : "");
424 if (host
->caps
.has_cfg_reg
) {
427 val
= buf
[ATMCI_CFG
/ 4];
428 seq_printf(s
, "CFG:\t0x%08x%s%s%s%s\n",
430 val
& ATMCI_CFG_FIFOMODE_1DATA
? " FIFOMODE_ONE_DATA" : "",
431 val
& ATMCI_CFG_FERRCTRL_COR
? " FERRCTRL_CLEAR_ON_READ" : "",
432 val
& ATMCI_CFG_HSMODE
? " HSMODE" : "",
433 val
& ATMCI_CFG_LSYNC
? " LSYNC" : "");
441 static int atmci_regs_open(struct inode
*inode
, struct file
*file
)
443 return single_open(file
, atmci_regs_show
, inode
->i_private
);
446 static const struct file_operations atmci_regs_fops
= {
447 .owner
= THIS_MODULE
,
448 .open
= atmci_regs_open
,
451 .release
= single_release
,
454 static void atmci_init_debugfs(struct atmel_mci_slot
*slot
)
456 struct mmc_host
*mmc
= slot
->mmc
;
457 struct atmel_mci
*host
= slot
->host
;
461 root
= mmc
->debugfs_root
;
465 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
472 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
, &atmci_req_fops
);
476 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
480 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
481 (u32
*)&host
->pending_events
);
485 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
486 (u32
*)&host
->completed_events
);
493 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
496 static inline unsigned int atmci_get_version(struct atmel_mci
*host
)
498 return atmci_readl(host
, ATMCI_VERSION
) & 0x00000fff;
501 static void atmci_timeout_timer(unsigned long data
)
503 struct atmel_mci
*host
;
505 host
= (struct atmel_mci
*)data
;
507 dev_dbg(&host
->pdev
->dev
, "software timeout\n");
509 if (host
->mrq
->cmd
->data
) {
510 host
->mrq
->cmd
->data
->error
= -ETIMEDOUT
;
513 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
516 host
->need_reset
= 1;
517 host
->state
= STATE_END_REQUEST
;
519 tasklet_schedule(&host
->tasklet
);
522 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci
*host
,
526 * It is easier here to use us instead of ns for the timeout,
527 * it prevents from overflows during calculation.
529 unsigned int us
= DIV_ROUND_UP(ns
, 1000);
531 /* Maximum clock frequency is host->bus_hz/2 */
532 return us
* (DIV_ROUND_UP(host
->bus_hz
, 2000000));
535 static void atmci_set_timeout(struct atmel_mci
*host
,
536 struct atmel_mci_slot
*slot
, struct mmc_data
*data
)
538 static unsigned dtomul_to_shift
[] = {
539 0, 4, 7, 8, 10, 12, 16, 20
545 timeout
= atmci_ns_to_clocks(host
, data
->timeout_ns
)
546 + data
->timeout_clks
;
548 for (dtomul
= 0; dtomul
< 8; dtomul
++) {
549 unsigned shift
= dtomul_to_shift
[dtomul
];
550 dtocyc
= (timeout
+ (1 << shift
) - 1) >> shift
;
560 dev_vdbg(&slot
->mmc
->class_dev
, "setting timeout to %u cycles\n",
561 dtocyc
<< dtomul_to_shift
[dtomul
]);
562 atmci_writel(host
, ATMCI_DTOR
, (ATMCI_DTOMUL(dtomul
) | ATMCI_DTOCYC(dtocyc
)));
566 * Return mask with command flags to be enabled for this command.
568 static u32
atmci_prepare_command(struct mmc_host
*mmc
,
569 struct mmc_command
*cmd
)
571 struct mmc_data
*data
;
574 cmd
->error
= -EINPROGRESS
;
576 cmdr
= ATMCI_CMDR_CMDNB(cmd
->opcode
);
578 if (cmd
->flags
& MMC_RSP_PRESENT
) {
579 if (cmd
->flags
& MMC_RSP_136
)
580 cmdr
|= ATMCI_CMDR_RSPTYP_136BIT
;
582 cmdr
|= ATMCI_CMDR_RSPTYP_48BIT
;
586 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
587 * it's too difficult to determine whether this is an ACMD or
588 * not. Better make it 64.
590 cmdr
|= ATMCI_CMDR_MAXLAT_64CYC
;
592 if (mmc
->ios
.bus_mode
== MMC_BUSMODE_OPENDRAIN
)
593 cmdr
|= ATMCI_CMDR_OPDCMD
;
597 cmdr
|= ATMCI_CMDR_START_XFER
;
599 if (cmd
->opcode
== SD_IO_RW_EXTENDED
) {
600 cmdr
|= ATMCI_CMDR_SDIO_BLOCK
;
602 if (data
->flags
& MMC_DATA_STREAM
)
603 cmdr
|= ATMCI_CMDR_STREAM
;
604 else if (data
->blocks
> 1)
605 cmdr
|= ATMCI_CMDR_MULTI_BLOCK
;
607 cmdr
|= ATMCI_CMDR_BLOCK
;
610 if (data
->flags
& MMC_DATA_READ
)
611 cmdr
|= ATMCI_CMDR_TRDIR_READ
;
617 static void atmci_send_command(struct atmel_mci
*host
,
618 struct mmc_command
*cmd
, u32 cmd_flags
)
623 dev_vdbg(&host
->pdev
->dev
,
624 "start command: ARGR=0x%08x CMDR=0x%08x\n",
625 cmd
->arg
, cmd_flags
);
627 atmci_writel(host
, ATMCI_ARGR
, cmd
->arg
);
628 atmci_writel(host
, ATMCI_CMDR
, cmd_flags
);
631 static void atmci_send_stop_cmd(struct atmel_mci
*host
, struct mmc_data
*data
)
633 dev_dbg(&host
->pdev
->dev
, "send stop command\n");
634 atmci_send_command(host
, data
->stop
, host
->stop_cmdr
);
635 atmci_writel(host
, ATMCI_IER
, ATMCI_CMDRDY
);
639 * Configure given PDC buffer taking care of alignement issues.
640 * Update host->data_size and host->sg.
642 static void atmci_pdc_set_single_buf(struct atmel_mci
*host
,
643 enum atmci_xfer_dir dir
, enum atmci_pdc_buf buf_nb
)
645 u32 pointer_reg
, counter_reg
;
646 unsigned int buf_size
;
648 if (dir
== XFER_RECEIVE
) {
649 pointer_reg
= ATMEL_PDC_RPR
;
650 counter_reg
= ATMEL_PDC_RCR
;
652 pointer_reg
= ATMEL_PDC_TPR
;
653 counter_reg
= ATMEL_PDC_TCR
;
656 if (buf_nb
== PDC_SECOND_BUF
) {
657 pointer_reg
+= ATMEL_PDC_SCND_BUF_OFF
;
658 counter_reg
+= ATMEL_PDC_SCND_BUF_OFF
;
661 if (!host
->caps
.has_rwproof
) {
662 buf_size
= host
->buf_size
;
663 atmci_writel(host
, pointer_reg
, host
->buf_phys_addr
);
665 buf_size
= sg_dma_len(host
->sg
);
666 atmci_writel(host
, pointer_reg
, sg_dma_address(host
->sg
));
669 if (host
->data_size
<= buf_size
) {
670 if (host
->data_size
& 0x3) {
671 /* If size is different from modulo 4, transfer bytes */
672 atmci_writel(host
, counter_reg
, host
->data_size
);
673 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
| ATMCI_MR_PDCFBYTE
);
675 /* Else transfer 32-bits words */
676 atmci_writel(host
, counter_reg
, host
->data_size
/ 4);
680 /* We assume the size of a page is 32-bits aligned */
681 atmci_writel(host
, counter_reg
, sg_dma_len(host
->sg
) / 4);
682 host
->data_size
-= sg_dma_len(host
->sg
);
684 host
->sg
= sg_next(host
->sg
);
689 * Configure PDC buffer according to the data size ie configuring one or two
690 * buffers. Don't use this function if you want to configure only the second
691 * buffer. In this case, use atmci_pdc_set_single_buf.
693 static void atmci_pdc_set_both_buf(struct atmel_mci
*host
, int dir
)
695 atmci_pdc_set_single_buf(host
, dir
, PDC_FIRST_BUF
);
697 atmci_pdc_set_single_buf(host
, dir
, PDC_SECOND_BUF
);
701 * Unmap sg lists, called when transfer is finished.
703 static void atmci_pdc_cleanup(struct atmel_mci
*host
)
705 struct mmc_data
*data
= host
->data
;
708 dma_unmap_sg(&host
->pdev
->dev
,
709 data
->sg
, data
->sg_len
,
710 ((data
->flags
& MMC_DATA_WRITE
)
711 ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
));
715 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
716 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
717 * interrupt needed for both transfer directions.
719 static void atmci_pdc_complete(struct atmel_mci
*host
)
721 int transfer_size
= host
->data
->blocks
* host
->data
->blksz
;
724 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_RXTDIS
| ATMEL_PDC_TXTDIS
);
726 if ((!host
->caps
.has_rwproof
)
727 && (host
->data
->flags
& MMC_DATA_READ
)) {
728 if (host
->caps
.has_bad_data_ordering
)
729 for (i
= 0; i
< transfer_size
; i
++)
730 host
->buffer
[i
] = swab32(host
->buffer
[i
]);
731 sg_copy_from_buffer(host
->data
->sg
, host
->data
->sg_len
,
732 host
->buffer
, transfer_size
);
735 atmci_pdc_cleanup(host
);
738 * If the card was removed, data will be NULL. No point trying
739 * to send the stop command or waiting for NBUSY in this case.
742 dev_dbg(&host
->pdev
->dev
,
743 "(%s) set pending xfer complete\n", __func__
);
744 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
745 tasklet_schedule(&host
->tasklet
);
749 static void atmci_dma_cleanup(struct atmel_mci
*host
)
751 struct mmc_data
*data
= host
->data
;
754 dma_unmap_sg(host
->dma
.chan
->device
->dev
,
755 data
->sg
, data
->sg_len
,
756 ((data
->flags
& MMC_DATA_WRITE
)
757 ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
));
761 * This function is called by the DMA driver from tasklet context.
763 static void atmci_dma_complete(void *arg
)
765 struct atmel_mci
*host
= arg
;
766 struct mmc_data
*data
= host
->data
;
768 dev_vdbg(&host
->pdev
->dev
, "DMA complete\n");
770 if (host
->caps
.has_dma
)
771 /* Disable DMA hardware handshaking on MCI */
772 atmci_writel(host
, ATMCI_DMA
, atmci_readl(host
, ATMCI_DMA
) & ~ATMCI_DMAEN
);
774 atmci_dma_cleanup(host
);
777 * If the card was removed, data will be NULL. No point trying
778 * to send the stop command or waiting for NBUSY in this case.
781 dev_dbg(&host
->pdev
->dev
,
782 "(%s) set pending xfer complete\n", __func__
);
783 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
784 tasklet_schedule(&host
->tasklet
);
787 * Regardless of what the documentation says, we have
788 * to wait for NOTBUSY even after block read
791 * When the DMA transfer is complete, the controller
792 * may still be reading the CRC from the card, i.e.
793 * the data transfer is still in progress and we
794 * haven't seen all the potential error bits yet.
796 * The interrupt handler will schedule a different
797 * tasklet to finish things up when the data transfer
798 * is completely done.
800 * We may not complete the mmc request here anyway
801 * because the mmc layer may call back and cause us to
802 * violate the "don't submit new operations from the
803 * completion callback" rule of the dma engine
806 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
811 * Returns a mask of interrupt flags to be enabled after the whole
812 * request has been prepared.
814 static u32
atmci_prepare_data(struct atmel_mci
*host
, struct mmc_data
*data
)
818 data
->error
= -EINPROGRESS
;
822 host
->data_chan
= NULL
;
824 iflags
= ATMCI_DATA_ERROR_FLAGS
;
827 * Errata: MMC data write operation with less than 12
828 * bytes is impossible.
830 * Errata: MCI Transmit Data Register (TDR) FIFO
831 * corruption when length is not multiple of 4.
833 if (data
->blocks
* data
->blksz
< 12
834 || (data
->blocks
* data
->blksz
) & 3)
835 host
->need_reset
= true;
837 host
->pio_offset
= 0;
838 if (data
->flags
& MMC_DATA_READ
)
839 iflags
|= ATMCI_RXRDY
;
841 iflags
|= ATMCI_TXRDY
;
847 * Set interrupt flags and set block length into the MCI mode register even
848 * if this value is also accessible in the MCI block register. It seems to be
849 * necessary before the High Speed MCI version. It also map sg and configure
853 atmci_prepare_data_pdc(struct atmel_mci
*host
, struct mmc_data
*data
)
857 enum dma_data_direction dir
;
860 data
->error
= -EINPROGRESS
;
864 iflags
= ATMCI_DATA_ERROR_FLAGS
;
866 /* Enable pdc mode */
867 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
| ATMCI_MR_PDCMODE
);
869 if (data
->flags
& MMC_DATA_READ
) {
870 dir
= DMA_FROM_DEVICE
;
871 iflags
|= ATMCI_ENDRX
| ATMCI_RXBUFF
;
874 iflags
|= ATMCI_ENDTX
| ATMCI_TXBUFE
| ATMCI_BLKE
;
878 tmp
= atmci_readl(host
, ATMCI_MR
);
880 tmp
|= ATMCI_BLKLEN(data
->blksz
);
881 atmci_writel(host
, ATMCI_MR
, tmp
);
884 host
->data_size
= data
->blocks
* data
->blksz
;
885 sg_len
= dma_map_sg(&host
->pdev
->dev
, data
->sg
, data
->sg_len
, dir
);
887 if ((!host
->caps
.has_rwproof
)
888 && (host
->data
->flags
& MMC_DATA_WRITE
)) {
889 sg_copy_to_buffer(host
->data
->sg
, host
->data
->sg_len
,
890 host
->buffer
, host
->data_size
);
891 if (host
->caps
.has_bad_data_ordering
)
892 for (i
= 0; i
< host
->data_size
; i
++)
893 host
->buffer
[i
] = swab32(host
->buffer
[i
]);
897 atmci_pdc_set_both_buf(host
,
898 ((dir
== DMA_FROM_DEVICE
) ? XFER_RECEIVE
: XFER_TRANSMIT
));
904 atmci_prepare_data_dma(struct atmel_mci
*host
, struct mmc_data
*data
)
906 struct dma_chan
*chan
;
907 struct dma_async_tx_descriptor
*desc
;
908 struct scatterlist
*sg
;
910 enum dma_data_direction direction
;
911 enum dma_transfer_direction slave_dirn
;
916 data
->error
= -EINPROGRESS
;
922 iflags
= ATMCI_DATA_ERROR_FLAGS
;
925 * We don't do DMA on "complex" transfers, i.e. with
926 * non-word-aligned buffers or lengths. Also, we don't bother
927 * with all the DMA setup overhead for short transfers.
929 if (data
->blocks
* data
->blksz
< ATMCI_DMA_THRESHOLD
)
930 return atmci_prepare_data(host
, data
);
932 return atmci_prepare_data(host
, data
);
934 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
935 if (sg
->offset
& 3 || sg
->length
& 3)
936 return atmci_prepare_data(host
, data
);
939 /* If we don't have a channel, we can't do DMA */
940 chan
= host
->dma
.chan
;
942 host
->data_chan
= chan
;
947 if (data
->flags
& MMC_DATA_READ
) {
948 direction
= DMA_FROM_DEVICE
;
949 host
->dma_conf
.direction
= slave_dirn
= DMA_DEV_TO_MEM
;
950 maxburst
= atmci_convert_chksize(host
->dma_conf
.src_maxburst
);
952 direction
= DMA_TO_DEVICE
;
953 host
->dma_conf
.direction
= slave_dirn
= DMA_MEM_TO_DEV
;
954 maxburst
= atmci_convert_chksize(host
->dma_conf
.dst_maxburst
);
957 atmci_writel(host
, ATMCI_DMA
, ATMCI_DMA_CHKSIZE(maxburst
) | ATMCI_DMAEN
);
959 sglen
= dma_map_sg(chan
->device
->dev
, data
->sg
,
960 data
->sg_len
, direction
);
962 dmaengine_slave_config(chan
, &host
->dma_conf
);
963 desc
= dmaengine_prep_slave_sg(chan
,
964 data
->sg
, sglen
, slave_dirn
,
965 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
969 host
->dma
.data_desc
= desc
;
970 desc
->callback
= atmci_dma_complete
;
971 desc
->callback_param
= host
;
975 dma_unmap_sg(chan
->device
->dev
, data
->sg
, data
->sg_len
, direction
);
980 atmci_submit_data(struct atmel_mci
*host
, struct mmc_data
*data
)
986 * Start PDC according to transfer direction.
989 atmci_submit_data_pdc(struct atmel_mci
*host
, struct mmc_data
*data
)
991 if (data
->flags
& MMC_DATA_READ
)
992 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_RXTEN
);
994 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_TXTEN
);
998 atmci_submit_data_dma(struct atmel_mci
*host
, struct mmc_data
*data
)
1000 struct dma_chan
*chan
= host
->data_chan
;
1001 struct dma_async_tx_descriptor
*desc
= host
->dma
.data_desc
;
1004 dmaengine_submit(desc
);
1005 dma_async_issue_pending(chan
);
1009 static void atmci_stop_transfer(struct atmel_mci
*host
)
1011 dev_dbg(&host
->pdev
->dev
,
1012 "(%s) set pending xfer complete\n", __func__
);
1013 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1014 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1018 * Stop data transfer because error(s) occured.
1020 static void atmci_stop_transfer_pdc(struct atmel_mci
*host
)
1022 atmci_writel(host
, ATMEL_PDC_PTCR
, ATMEL_PDC_RXTDIS
| ATMEL_PDC_TXTDIS
);
1025 static void atmci_stop_transfer_dma(struct atmel_mci
*host
)
1027 struct dma_chan
*chan
= host
->data_chan
;
1030 dmaengine_terminate_all(chan
);
1031 atmci_dma_cleanup(host
);
1033 /* Data transfer was stopped by the interrupt handler */
1034 dev_dbg(&host
->pdev
->dev
,
1035 "(%s) set pending xfer complete\n", __func__
);
1036 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1037 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1042 * Start a request: prepare data if needed, prepare the command and activate
1045 static void atmci_start_request(struct atmel_mci
*host
,
1046 struct atmel_mci_slot
*slot
)
1048 struct mmc_request
*mrq
;
1049 struct mmc_command
*cmd
;
1050 struct mmc_data
*data
;
1055 host
->cur_slot
= slot
;
1058 host
->pending_events
= 0;
1059 host
->completed_events
= 0;
1060 host
->cmd_status
= 0;
1061 host
->data_status
= 0;
1063 dev_dbg(&host
->pdev
->dev
, "start request: cmd %u\n", mrq
->cmd
->opcode
);
1065 if (host
->need_reset
|| host
->caps
.need_reset_after_xfer
) {
1066 iflags
= atmci_readl(host
, ATMCI_IMR
);
1067 iflags
&= (ATMCI_SDIOIRQA
| ATMCI_SDIOIRQB
);
1068 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
1069 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIEN
);
1070 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1071 if (host
->caps
.has_cfg_reg
)
1072 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1073 atmci_writel(host
, ATMCI_IER
, iflags
);
1074 host
->need_reset
= false;
1076 atmci_writel(host
, ATMCI_SDCR
, slot
->sdc_reg
);
1078 iflags
= atmci_readl(host
, ATMCI_IMR
);
1079 if (iflags
& ~(ATMCI_SDIOIRQA
| ATMCI_SDIOIRQB
))
1080 dev_dbg(&slot
->mmc
->class_dev
, "WARNING: IMR=0x%08x\n",
1083 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT
, &slot
->flags
))) {
1084 /* Send init sequence (74 clock cycles) */
1085 atmci_writel(host
, ATMCI_CMDR
, ATMCI_CMDR_SPCMD_INIT
);
1086 while (!(atmci_readl(host
, ATMCI_SR
) & ATMCI_CMDRDY
))
1092 atmci_set_timeout(host
, slot
, data
);
1094 /* Must set block count/size before sending command */
1095 atmci_writel(host
, ATMCI_BLKR
, ATMCI_BCNT(data
->blocks
)
1096 | ATMCI_BLKLEN(data
->blksz
));
1097 dev_vdbg(&slot
->mmc
->class_dev
, "BLKR=0x%08x\n",
1098 ATMCI_BCNT(data
->blocks
) | ATMCI_BLKLEN(data
->blksz
));
1100 iflags
|= host
->prepare_data(host
, data
);
1103 iflags
|= ATMCI_CMDRDY
;
1105 cmdflags
= atmci_prepare_command(slot
->mmc
, cmd
);
1106 atmci_send_command(host
, cmd
, cmdflags
);
1109 host
->submit_data(host
, data
);
1112 host
->stop_cmdr
= atmci_prepare_command(slot
->mmc
, mrq
->stop
);
1113 host
->stop_cmdr
|= ATMCI_CMDR_STOP_XFER
;
1114 if (!(data
->flags
& MMC_DATA_WRITE
))
1115 host
->stop_cmdr
|= ATMCI_CMDR_TRDIR_READ
;
1116 if (data
->flags
& MMC_DATA_STREAM
)
1117 host
->stop_cmdr
|= ATMCI_CMDR_STREAM
;
1119 host
->stop_cmdr
|= ATMCI_CMDR_MULTI_BLOCK
;
1123 * We could have enabled interrupts earlier, but I suspect
1124 * that would open up a nice can of interesting race
1125 * conditions (e.g. command and data complete, but stop not
1128 atmci_writel(host
, ATMCI_IER
, iflags
);
1130 mod_timer(&host
->timer
, jiffies
+ msecs_to_jiffies(2000));
1133 static void atmci_queue_request(struct atmel_mci
*host
,
1134 struct atmel_mci_slot
*slot
, struct mmc_request
*mrq
)
1136 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
1139 spin_lock_bh(&host
->lock
);
1141 if (host
->state
== STATE_IDLE
) {
1142 host
->state
= STATE_SENDING_CMD
;
1143 atmci_start_request(host
, slot
);
1145 dev_dbg(&host
->pdev
->dev
, "queue request\n");
1146 list_add_tail(&slot
->queue_node
, &host
->queue
);
1148 spin_unlock_bh(&host
->lock
);
1151 static void atmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1153 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1154 struct atmel_mci
*host
= slot
->host
;
1155 struct mmc_data
*data
;
1158 dev_dbg(&host
->pdev
->dev
, "MRQ: cmd %u\n", mrq
->cmd
->opcode
);
1161 * We may "know" the card is gone even though there's still an
1162 * electrical connection. If so, we really need to communicate
1163 * this to the MMC core since there won't be any more
1164 * interrupts as the card is completely removed. Otherwise,
1165 * the MMC core might believe the card is still there even
1166 * though the card was just removed very slowly.
1168 if (!test_bit(ATMCI_CARD_PRESENT
, &slot
->flags
)) {
1169 mrq
->cmd
->error
= -ENOMEDIUM
;
1170 mmc_request_done(mmc
, mrq
);
1174 /* We don't support multiple blocks of weird lengths. */
1176 if (data
&& data
->blocks
> 1 && data
->blksz
& 3) {
1177 mrq
->cmd
->error
= -EINVAL
;
1178 mmc_request_done(mmc
, mrq
);
1181 atmci_queue_request(host
, slot
, mrq
);
1184 static void atmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1186 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1187 struct atmel_mci
*host
= slot
->host
;
1190 slot
->sdc_reg
&= ~ATMCI_SDCBUS_MASK
;
1191 switch (ios
->bus_width
) {
1192 case MMC_BUS_WIDTH_1
:
1193 slot
->sdc_reg
|= ATMCI_SDCBUS_1BIT
;
1195 case MMC_BUS_WIDTH_4
:
1196 slot
->sdc_reg
|= ATMCI_SDCBUS_4BIT
;
1201 unsigned int clock_min
= ~0U;
1204 spin_lock_bh(&host
->lock
);
1205 if (!host
->mode_reg
) {
1206 clk_enable(host
->mck
);
1207 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
1208 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIEN
);
1209 if (host
->caps
.has_cfg_reg
)
1210 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1214 * Use mirror of ios->clock to prevent race with mmc
1215 * core ios update when finding the minimum.
1217 slot
->clock
= ios
->clock
;
1218 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
1219 if (host
->slot
[i
] && host
->slot
[i
]->clock
1220 && host
->slot
[i
]->clock
< clock_min
)
1221 clock_min
= host
->slot
[i
]->clock
;
1224 /* Calculate clock divider */
1225 if (host
->caps
.has_odd_clk_div
) {
1226 clkdiv
= DIV_ROUND_UP(host
->bus_hz
, clock_min
) - 2;
1228 dev_warn(&mmc
->class_dev
,
1229 "clock %u too slow; using %lu\n",
1230 clock_min
, host
->bus_hz
/ (511 + 2));
1233 host
->mode_reg
= ATMCI_MR_CLKDIV(clkdiv
>> 1)
1234 | ATMCI_MR_CLKODD(clkdiv
& 1);
1236 clkdiv
= DIV_ROUND_UP(host
->bus_hz
, 2 * clock_min
) - 1;
1238 dev_warn(&mmc
->class_dev
,
1239 "clock %u too slow; using %lu\n",
1240 clock_min
, host
->bus_hz
/ (2 * 256));
1243 host
->mode_reg
= ATMCI_MR_CLKDIV(clkdiv
);
1247 * WRPROOF and RDPROOF prevent overruns/underruns by
1248 * stopping the clock when the FIFO is full/empty.
1249 * This state is not expected to last for long.
1251 if (host
->caps
.has_rwproof
)
1252 host
->mode_reg
|= (ATMCI_MR_WRPROOF
| ATMCI_MR_RDPROOF
);
1254 if (host
->caps
.has_cfg_reg
) {
1255 /* setup High Speed mode in relation with card capacity */
1256 if (ios
->timing
== MMC_TIMING_SD_HS
)
1257 host
->cfg_reg
|= ATMCI_CFG_HSMODE
;
1259 host
->cfg_reg
&= ~ATMCI_CFG_HSMODE
;
1262 if (list_empty(&host
->queue
)) {
1263 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1264 if (host
->caps
.has_cfg_reg
)
1265 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1267 host
->need_clock_update
= true;
1270 spin_unlock_bh(&host
->lock
);
1272 bool any_slot_active
= false;
1274 spin_lock_bh(&host
->lock
);
1276 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
1277 if (host
->slot
[i
] && host
->slot
[i
]->clock
) {
1278 any_slot_active
= true;
1282 if (!any_slot_active
) {
1283 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIDIS
);
1284 if (host
->mode_reg
) {
1285 atmci_readl(host
, ATMCI_MR
);
1286 clk_disable(host
->mck
);
1290 spin_unlock_bh(&host
->lock
);
1293 switch (ios
->power_mode
) {
1295 set_bit(ATMCI_CARD_NEED_INIT
, &slot
->flags
);
1299 * TODO: None of the currently available AVR32-based
1300 * boards allow MMC power to be turned off. Implement
1301 * power control when this can be tested properly.
1303 * We also need to hook this into the clock management
1304 * somehow so that newly inserted cards aren't
1305 * subjected to a fast clock before we have a chance
1306 * to figure out what the maximum rate is. Currently,
1307 * there's no way to avoid this, and there never will
1308 * be for boards that don't support power control.
1314 static int atmci_get_ro(struct mmc_host
*mmc
)
1316 int read_only
= -ENOSYS
;
1317 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1319 if (gpio_is_valid(slot
->wp_pin
)) {
1320 read_only
= gpio_get_value(slot
->wp_pin
);
1321 dev_dbg(&mmc
->class_dev
, "card is %s\n",
1322 read_only
? "read-only" : "read-write");
1328 static int atmci_get_cd(struct mmc_host
*mmc
)
1330 int present
= -ENOSYS
;
1331 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1333 if (gpio_is_valid(slot
->detect_pin
)) {
1334 present
= !(gpio_get_value(slot
->detect_pin
) ^
1335 slot
->detect_is_active_high
);
1336 dev_dbg(&mmc
->class_dev
, "card is %spresent\n",
1337 present
? "" : "not ");
1343 static void atmci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1345 struct atmel_mci_slot
*slot
= mmc_priv(mmc
);
1346 struct atmel_mci
*host
= slot
->host
;
1349 atmci_writel(host
, ATMCI_IER
, slot
->sdio_irq
);
1351 atmci_writel(host
, ATMCI_IDR
, slot
->sdio_irq
);
1354 static const struct mmc_host_ops atmci_ops
= {
1355 .request
= atmci_request
,
1356 .set_ios
= atmci_set_ios
,
1357 .get_ro
= atmci_get_ro
,
1358 .get_cd
= atmci_get_cd
,
1359 .enable_sdio_irq
= atmci_enable_sdio_irq
,
1362 /* Called with host->lock held */
1363 static void atmci_request_end(struct atmel_mci
*host
, struct mmc_request
*mrq
)
1364 __releases(&host
->lock
)
1365 __acquires(&host
->lock
)
1367 struct atmel_mci_slot
*slot
= NULL
;
1368 struct mmc_host
*prev_mmc
= host
->cur_slot
->mmc
;
1370 WARN_ON(host
->cmd
|| host
->data
);
1373 * Update the MMC clock rate if necessary. This may be
1374 * necessary if set_ios() is called when a different slot is
1375 * busy transferring data.
1377 if (host
->need_clock_update
) {
1378 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1379 if (host
->caps
.has_cfg_reg
)
1380 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1383 host
->cur_slot
->mrq
= NULL
;
1385 if (!list_empty(&host
->queue
)) {
1386 slot
= list_entry(host
->queue
.next
,
1387 struct atmel_mci_slot
, queue_node
);
1388 list_del(&slot
->queue_node
);
1389 dev_vdbg(&host
->pdev
->dev
, "list not empty: %s is next\n",
1390 mmc_hostname(slot
->mmc
));
1391 host
->state
= STATE_SENDING_CMD
;
1392 atmci_start_request(host
, slot
);
1394 dev_vdbg(&host
->pdev
->dev
, "list empty\n");
1395 host
->state
= STATE_IDLE
;
1398 del_timer(&host
->timer
);
1400 spin_unlock(&host
->lock
);
1401 mmc_request_done(prev_mmc
, mrq
);
1402 spin_lock(&host
->lock
);
1405 static void atmci_command_complete(struct atmel_mci
*host
,
1406 struct mmc_command
*cmd
)
1408 u32 status
= host
->cmd_status
;
1410 /* Read the response from the card (up to 16 bytes) */
1411 cmd
->resp
[0] = atmci_readl(host
, ATMCI_RSPR
);
1412 cmd
->resp
[1] = atmci_readl(host
, ATMCI_RSPR
);
1413 cmd
->resp
[2] = atmci_readl(host
, ATMCI_RSPR
);
1414 cmd
->resp
[3] = atmci_readl(host
, ATMCI_RSPR
);
1416 if (status
& ATMCI_RTOE
)
1417 cmd
->error
= -ETIMEDOUT
;
1418 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& ATMCI_RCRCE
))
1419 cmd
->error
= -EILSEQ
;
1420 else if (status
& (ATMCI_RINDE
| ATMCI_RDIRE
| ATMCI_RENDE
))
1422 else if (host
->mrq
->data
&& (host
->mrq
->data
->blksz
& 3)) {
1423 if (host
->caps
.need_blksz_mul_4
) {
1424 cmd
->error
= -EINVAL
;
1425 host
->need_reset
= 1;
1431 static void atmci_detect_change(unsigned long data
)
1433 struct atmel_mci_slot
*slot
= (struct atmel_mci_slot
*)data
;
1438 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1439 * freeing the interrupt. We must not re-enable the interrupt
1440 * if it has been freed, and if we're shutting down, it
1441 * doesn't really matter whether the card is present or not.
1444 if (test_bit(ATMCI_SHUTDOWN
, &slot
->flags
))
1447 enable_irq(gpio_to_irq(slot
->detect_pin
));
1448 present
= !(gpio_get_value(slot
->detect_pin
) ^
1449 slot
->detect_is_active_high
);
1450 present_old
= test_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
1452 dev_vdbg(&slot
->mmc
->class_dev
, "detect change: %d (was %d)\n",
1453 present
, present_old
);
1455 if (present
!= present_old
) {
1456 struct atmel_mci
*host
= slot
->host
;
1457 struct mmc_request
*mrq
;
1459 dev_dbg(&slot
->mmc
->class_dev
, "card %s\n",
1460 present
? "inserted" : "removed");
1462 spin_lock(&host
->lock
);
1465 clear_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
1467 set_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
1469 /* Clean up queue if present */
1472 if (mrq
== host
->mrq
) {
1474 * Reset controller to terminate any ongoing
1475 * commands or data transfers.
1477 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
1478 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIEN
);
1479 atmci_writel(host
, ATMCI_MR
, host
->mode_reg
);
1480 if (host
->caps
.has_cfg_reg
)
1481 atmci_writel(host
, ATMCI_CFG
, host
->cfg_reg
);
1486 switch (host
->state
) {
1489 case STATE_SENDING_CMD
:
1490 mrq
->cmd
->error
= -ENOMEDIUM
;
1492 host
->stop_transfer(host
);
1494 case STATE_DATA_XFER
:
1495 mrq
->data
->error
= -ENOMEDIUM
;
1496 host
->stop_transfer(host
);
1498 case STATE_WAITING_NOTBUSY
:
1499 mrq
->data
->error
= -ENOMEDIUM
;
1501 case STATE_SENDING_STOP
:
1502 mrq
->stop
->error
= -ENOMEDIUM
;
1504 case STATE_END_REQUEST
:
1508 atmci_request_end(host
, mrq
);
1510 list_del(&slot
->queue_node
);
1511 mrq
->cmd
->error
= -ENOMEDIUM
;
1513 mrq
->data
->error
= -ENOMEDIUM
;
1515 mrq
->stop
->error
= -ENOMEDIUM
;
1517 spin_unlock(&host
->lock
);
1518 mmc_request_done(slot
->mmc
, mrq
);
1519 spin_lock(&host
->lock
);
1522 spin_unlock(&host
->lock
);
1524 mmc_detect_change(slot
->mmc
, 0);
1528 static void atmci_tasklet_func(unsigned long priv
)
1530 struct atmel_mci
*host
= (struct atmel_mci
*)priv
;
1531 struct mmc_request
*mrq
= host
->mrq
;
1532 struct mmc_data
*data
= host
->data
;
1533 enum atmel_mci_state state
= host
->state
;
1534 enum atmel_mci_state prev_state
;
1537 spin_lock(&host
->lock
);
1539 state
= host
->state
;
1541 dev_vdbg(&host
->pdev
->dev
,
1542 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1543 state
, host
->pending_events
, host
->completed_events
,
1544 atmci_readl(host
, ATMCI_IMR
));
1548 dev_dbg(&host
->pdev
->dev
, "FSM: state=%d\n", state
);
1554 case STATE_SENDING_CMD
:
1556 * Command has been sent, we are waiting for command
1557 * ready. Then we have three next states possible:
1558 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1559 * command needing it or DATA_XFER if there is data.
1561 dev_dbg(&host
->pdev
->dev
, "FSM: cmd ready?\n");
1562 if (!atmci_test_and_clear_pending(host
,
1566 dev_dbg(&host
->pdev
->dev
, "set completed cmd ready\n");
1568 atmci_set_completed(host
, EVENT_CMD_RDY
);
1569 atmci_command_complete(host
, mrq
->cmd
);
1571 dev_dbg(&host
->pdev
->dev
,
1572 "command with data transfer");
1574 * If there is a command error don't start
1577 if (mrq
->cmd
->error
) {
1578 host
->stop_transfer(host
);
1580 atmci_writel(host
, ATMCI_IDR
,
1581 ATMCI_TXRDY
| ATMCI_RXRDY
1582 | ATMCI_DATA_ERROR_FLAGS
);
1583 state
= STATE_END_REQUEST
;
1585 state
= STATE_DATA_XFER
;
1586 } else if ((!mrq
->data
) && (mrq
->cmd
->flags
& MMC_RSP_BUSY
)) {
1587 dev_dbg(&host
->pdev
->dev
,
1588 "command response need waiting notbusy");
1589 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1590 state
= STATE_WAITING_NOTBUSY
;
1592 state
= STATE_END_REQUEST
;
1596 case STATE_DATA_XFER
:
1597 if (atmci_test_and_clear_pending(host
,
1598 EVENT_DATA_ERROR
)) {
1599 dev_dbg(&host
->pdev
->dev
, "set completed data error\n");
1600 atmci_set_completed(host
, EVENT_DATA_ERROR
);
1601 state
= STATE_END_REQUEST
;
1606 * A data transfer is in progress. The event expected
1607 * to move to the next state depends of data transfer
1608 * type (PDC or DMA). Once transfer done we can move
1609 * to the next step which is WAITING_NOTBUSY in write
1610 * case and directly SENDING_STOP in read case.
1612 dev_dbg(&host
->pdev
->dev
, "FSM: xfer complete?\n");
1613 if (!atmci_test_and_clear_pending(host
,
1614 EVENT_XFER_COMPLETE
))
1617 dev_dbg(&host
->pdev
->dev
,
1618 "(%s) set completed xfer complete\n",
1620 atmci_set_completed(host
, EVENT_XFER_COMPLETE
);
1622 if (host
->data
->flags
& MMC_DATA_WRITE
) {
1623 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1624 state
= STATE_WAITING_NOTBUSY
;
1625 } else if (host
->mrq
->stop
) {
1626 atmci_writel(host
, ATMCI_IER
, ATMCI_CMDRDY
);
1627 atmci_send_stop_cmd(host
, data
);
1628 state
= STATE_SENDING_STOP
;
1631 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1633 state
= STATE_END_REQUEST
;
1637 case STATE_WAITING_NOTBUSY
:
1639 * We can be in the state for two reasons: a command
1640 * requiring waiting not busy signal (stop command
1641 * included) or a write operation. In the latest case,
1642 * we need to send a stop command.
1644 dev_dbg(&host
->pdev
->dev
, "FSM: not busy?\n");
1645 if (!atmci_test_and_clear_pending(host
,
1649 dev_dbg(&host
->pdev
->dev
, "set completed not busy\n");
1650 atmci_set_completed(host
, EVENT_NOTBUSY
);
1654 * For some commands such as CMD53, even if
1655 * there is data transfer, there is no stop
1658 if (host
->mrq
->stop
) {
1659 atmci_writel(host
, ATMCI_IER
,
1661 atmci_send_stop_cmd(host
, data
);
1662 state
= STATE_SENDING_STOP
;
1665 data
->bytes_xfered
= data
->blocks
1668 state
= STATE_END_REQUEST
;
1671 state
= STATE_END_REQUEST
;
1674 case STATE_SENDING_STOP
:
1676 * In this state, it is important to set host->data to
1677 * NULL (which is tested in the waiting notbusy state)
1678 * in order to go to the end request state instead of
1679 * sending stop again.
1681 dev_dbg(&host
->pdev
->dev
, "FSM: cmd ready?\n");
1682 if (!atmci_test_and_clear_pending(host
,
1686 dev_dbg(&host
->pdev
->dev
, "FSM: cmd ready\n");
1689 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1691 atmci_command_complete(host
, mrq
->stop
);
1692 if (mrq
->stop
->error
) {
1693 host
->stop_transfer(host
);
1694 atmci_writel(host
, ATMCI_IDR
,
1695 ATMCI_TXRDY
| ATMCI_RXRDY
1696 | ATMCI_DATA_ERROR_FLAGS
);
1697 state
= STATE_END_REQUEST
;
1699 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1700 state
= STATE_WAITING_NOTBUSY
;
1704 case STATE_END_REQUEST
:
1705 atmci_writel(host
, ATMCI_IDR
, ATMCI_TXRDY
| ATMCI_RXRDY
1706 | ATMCI_DATA_ERROR_FLAGS
);
1707 status
= host
->data_status
;
1708 if (unlikely(status
)) {
1709 host
->stop_transfer(host
);
1711 if (status
& ATMCI_DTOE
) {
1712 data
->error
= -ETIMEDOUT
;
1713 } else if (status
& ATMCI_DCRCE
) {
1714 data
->error
= -EILSEQ
;
1720 atmci_request_end(host
, host
->mrq
);
1724 } while (state
!= prev_state
);
1726 host
->state
= state
;
1728 spin_unlock(&host
->lock
);
1731 static void atmci_read_data_pio(struct atmel_mci
*host
)
1733 struct scatterlist
*sg
= host
->sg
;
1734 void *buf
= sg_virt(sg
);
1735 unsigned int offset
= host
->pio_offset
;
1736 struct mmc_data
*data
= host
->data
;
1739 unsigned int nbytes
= 0;
1742 value
= atmci_readl(host
, ATMCI_RDR
);
1743 if (likely(offset
+ 4 <= sg
->length
)) {
1744 put_unaligned(value
, (u32
*)(buf
+ offset
));
1749 if (offset
== sg
->length
) {
1750 flush_dcache_page(sg_page(sg
));
1751 host
->sg
= sg
= sg_next(sg
);
1759 unsigned int remaining
= sg
->length
- offset
;
1760 memcpy(buf
+ offset
, &value
, remaining
);
1761 nbytes
+= remaining
;
1763 flush_dcache_page(sg_page(sg
));
1764 host
->sg
= sg
= sg_next(sg
);
1768 offset
= 4 - remaining
;
1770 memcpy(buf
, (u8
*)&value
+ remaining
, offset
);
1774 status
= atmci_readl(host
, ATMCI_SR
);
1775 if (status
& ATMCI_DATA_ERROR_FLAGS
) {
1776 atmci_writel(host
, ATMCI_IDR
, (ATMCI_NOTBUSY
| ATMCI_RXRDY
1777 | ATMCI_DATA_ERROR_FLAGS
));
1778 host
->data_status
= status
;
1779 data
->bytes_xfered
+= nbytes
;
1782 } while (status
& ATMCI_RXRDY
);
1784 host
->pio_offset
= offset
;
1785 data
->bytes_xfered
+= nbytes
;
1790 atmci_writel(host
, ATMCI_IDR
, ATMCI_RXRDY
);
1791 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1792 data
->bytes_xfered
+= nbytes
;
1794 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1797 static void atmci_write_data_pio(struct atmel_mci
*host
)
1799 struct scatterlist
*sg
= host
->sg
;
1800 void *buf
= sg_virt(sg
);
1801 unsigned int offset
= host
->pio_offset
;
1802 struct mmc_data
*data
= host
->data
;
1805 unsigned int nbytes
= 0;
1808 if (likely(offset
+ 4 <= sg
->length
)) {
1809 value
= get_unaligned((u32
*)(buf
+ offset
));
1810 atmci_writel(host
, ATMCI_TDR
, value
);
1814 if (offset
== sg
->length
) {
1815 host
->sg
= sg
= sg_next(sg
);
1823 unsigned int remaining
= sg
->length
- offset
;
1826 memcpy(&value
, buf
+ offset
, remaining
);
1827 nbytes
+= remaining
;
1829 host
->sg
= sg
= sg_next(sg
);
1831 atmci_writel(host
, ATMCI_TDR
, value
);
1835 offset
= 4 - remaining
;
1837 memcpy((u8
*)&value
+ remaining
, buf
, offset
);
1838 atmci_writel(host
, ATMCI_TDR
, value
);
1842 status
= atmci_readl(host
, ATMCI_SR
);
1843 if (status
& ATMCI_DATA_ERROR_FLAGS
) {
1844 atmci_writel(host
, ATMCI_IDR
, (ATMCI_NOTBUSY
| ATMCI_TXRDY
1845 | ATMCI_DATA_ERROR_FLAGS
));
1846 host
->data_status
= status
;
1847 data
->bytes_xfered
+= nbytes
;
1850 } while (status
& ATMCI_TXRDY
);
1852 host
->pio_offset
= offset
;
1853 data
->bytes_xfered
+= nbytes
;
1858 atmci_writel(host
, ATMCI_IDR
, ATMCI_TXRDY
);
1859 atmci_writel(host
, ATMCI_IER
, ATMCI_NOTBUSY
);
1860 data
->bytes_xfered
+= nbytes
;
1862 atmci_set_pending(host
, EVENT_XFER_COMPLETE
);
1865 static void atmci_sdio_interrupt(struct atmel_mci
*host
, u32 status
)
1869 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
1870 struct atmel_mci_slot
*slot
= host
->slot
[i
];
1871 if (slot
&& (status
& slot
->sdio_irq
)) {
1872 mmc_signal_sdio_irq(slot
->mmc
);
1878 static irqreturn_t
atmci_interrupt(int irq
, void *dev_id
)
1880 struct atmel_mci
*host
= dev_id
;
1881 u32 status
, mask
, pending
;
1882 unsigned int pass_count
= 0;
1885 status
= atmci_readl(host
, ATMCI_SR
);
1886 mask
= atmci_readl(host
, ATMCI_IMR
);
1887 pending
= status
& mask
;
1891 if (pending
& ATMCI_DATA_ERROR_FLAGS
) {
1892 dev_dbg(&host
->pdev
->dev
, "IRQ: data error\n");
1893 atmci_writel(host
, ATMCI_IDR
, ATMCI_DATA_ERROR_FLAGS
1894 | ATMCI_RXRDY
| ATMCI_TXRDY
1895 | ATMCI_ENDRX
| ATMCI_ENDTX
1896 | ATMCI_RXBUFF
| ATMCI_TXBUFE
);
1898 host
->data_status
= status
;
1899 dev_dbg(&host
->pdev
->dev
, "set pending data error\n");
1901 atmci_set_pending(host
, EVENT_DATA_ERROR
);
1902 tasklet_schedule(&host
->tasklet
);
1905 if (pending
& ATMCI_TXBUFE
) {
1906 dev_dbg(&host
->pdev
->dev
, "IRQ: tx buffer empty\n");
1907 atmci_writel(host
, ATMCI_IDR
, ATMCI_TXBUFE
);
1908 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDTX
);
1910 * We can receive this interruption before having configured
1911 * the second pdc buffer, so we need to reconfigure first and
1912 * second buffers again
1914 if (host
->data_size
) {
1915 atmci_pdc_set_both_buf(host
, XFER_TRANSMIT
);
1916 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDTX
);
1917 atmci_writel(host
, ATMCI_IER
, ATMCI_TXBUFE
);
1919 atmci_pdc_complete(host
);
1921 } else if (pending
& ATMCI_ENDTX
) {
1922 dev_dbg(&host
->pdev
->dev
, "IRQ: end of tx buffer\n");
1923 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDTX
);
1925 if (host
->data_size
) {
1926 atmci_pdc_set_single_buf(host
,
1927 XFER_TRANSMIT
, PDC_SECOND_BUF
);
1928 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDTX
);
1932 if (pending
& ATMCI_RXBUFF
) {
1933 dev_dbg(&host
->pdev
->dev
, "IRQ: rx buffer full\n");
1934 atmci_writel(host
, ATMCI_IDR
, ATMCI_RXBUFF
);
1935 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDRX
);
1937 * We can receive this interruption before having configured
1938 * the second pdc buffer, so we need to reconfigure first and
1939 * second buffers again
1941 if (host
->data_size
) {
1942 atmci_pdc_set_both_buf(host
, XFER_RECEIVE
);
1943 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDRX
);
1944 atmci_writel(host
, ATMCI_IER
, ATMCI_RXBUFF
);
1946 atmci_pdc_complete(host
);
1948 } else if (pending
& ATMCI_ENDRX
) {
1949 dev_dbg(&host
->pdev
->dev
, "IRQ: end of rx buffer\n");
1950 atmci_writel(host
, ATMCI_IDR
, ATMCI_ENDRX
);
1952 if (host
->data_size
) {
1953 atmci_pdc_set_single_buf(host
,
1954 XFER_RECEIVE
, PDC_SECOND_BUF
);
1955 atmci_writel(host
, ATMCI_IER
, ATMCI_ENDRX
);
1960 * First mci IPs, so mainly the ones having pdc, have some
1961 * issues with the notbusy signal. You can't get it after
1962 * data transmission if you have not sent a stop command.
1963 * The appropriate workaround is to use the BLKE signal.
1965 if (pending
& ATMCI_BLKE
) {
1966 dev_dbg(&host
->pdev
->dev
, "IRQ: blke\n");
1967 atmci_writel(host
, ATMCI_IDR
, ATMCI_BLKE
);
1969 dev_dbg(&host
->pdev
->dev
, "set pending notbusy\n");
1970 atmci_set_pending(host
, EVENT_NOTBUSY
);
1971 tasklet_schedule(&host
->tasklet
);
1974 if (pending
& ATMCI_NOTBUSY
) {
1975 dev_dbg(&host
->pdev
->dev
, "IRQ: not_busy\n");
1976 atmci_writel(host
, ATMCI_IDR
, ATMCI_NOTBUSY
);
1978 dev_dbg(&host
->pdev
->dev
, "set pending notbusy\n");
1979 atmci_set_pending(host
, EVENT_NOTBUSY
);
1980 tasklet_schedule(&host
->tasklet
);
1983 if (pending
& ATMCI_RXRDY
)
1984 atmci_read_data_pio(host
);
1985 if (pending
& ATMCI_TXRDY
)
1986 atmci_write_data_pio(host
);
1988 if (pending
& ATMCI_CMDRDY
) {
1989 dev_dbg(&host
->pdev
->dev
, "IRQ: cmd ready\n");
1990 atmci_writel(host
, ATMCI_IDR
, ATMCI_CMDRDY
);
1991 host
->cmd_status
= status
;
1993 dev_dbg(&host
->pdev
->dev
, "set pending cmd rdy\n");
1994 atmci_set_pending(host
, EVENT_CMD_RDY
);
1995 tasklet_schedule(&host
->tasklet
);
1998 if (pending
& (ATMCI_SDIOIRQA
| ATMCI_SDIOIRQB
))
1999 atmci_sdio_interrupt(host
, status
);
2001 } while (pass_count
++ < 5);
2003 return pass_count
? IRQ_HANDLED
: IRQ_NONE
;
2006 static irqreturn_t
atmci_detect_interrupt(int irq
, void *dev_id
)
2008 struct atmel_mci_slot
*slot
= dev_id
;
2011 * Disable interrupts until the pin has stabilized and check
2012 * the state then. Use mod_timer() since we may be in the
2013 * middle of the timer routine when this interrupt triggers.
2015 disable_irq_nosync(irq
);
2016 mod_timer(&slot
->detect_timer
, jiffies
+ msecs_to_jiffies(20));
2021 static int __init
atmci_init_slot(struct atmel_mci
*host
,
2022 struct mci_slot_pdata
*slot_data
, unsigned int id
,
2023 u32 sdc_reg
, u32 sdio_irq
)
2025 struct mmc_host
*mmc
;
2026 struct atmel_mci_slot
*slot
;
2028 mmc
= mmc_alloc_host(sizeof(struct atmel_mci_slot
), &host
->pdev
->dev
);
2032 slot
= mmc_priv(mmc
);
2035 slot
->detect_pin
= slot_data
->detect_pin
;
2036 slot
->wp_pin
= slot_data
->wp_pin
;
2037 slot
->detect_is_active_high
= slot_data
->detect_is_active_high
;
2038 slot
->sdc_reg
= sdc_reg
;
2039 slot
->sdio_irq
= sdio_irq
;
2041 mmc
->ops
= &atmci_ops
;
2042 mmc
->f_min
= DIV_ROUND_UP(host
->bus_hz
, 512);
2043 mmc
->f_max
= host
->bus_hz
/ 2;
2044 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
2046 mmc
->caps
|= MMC_CAP_SDIO_IRQ
;
2047 if (host
->caps
.has_highspeed
)
2048 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
;
2050 * Without the read/write proof capability, it is strongly suggested to
2051 * use only one bit for data to prevent fifo underruns and overruns
2052 * which will corrupt data.
2054 if ((slot_data
->bus_width
>= 4) && host
->caps
.has_rwproof
)
2055 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2057 if (atmci_get_version(host
) < 0x200) {
2058 mmc
->max_segs
= 256;
2059 mmc
->max_blk_size
= 4095;
2060 mmc
->max_blk_count
= 256;
2061 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
2062 mmc
->max_seg_size
= mmc
->max_blk_size
* mmc
->max_segs
;
2065 mmc
->max_req_size
= 32768 * 512;
2066 mmc
->max_blk_size
= 32768;
2067 mmc
->max_blk_count
= 512;
2070 /* Assume card is present initially */
2071 set_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
2072 if (gpio_is_valid(slot
->detect_pin
)) {
2073 if (gpio_request(slot
->detect_pin
, "mmc_detect")) {
2074 dev_dbg(&mmc
->class_dev
, "no detect pin available\n");
2075 slot
->detect_pin
= -EBUSY
;
2076 } else if (gpio_get_value(slot
->detect_pin
) ^
2077 slot
->detect_is_active_high
) {
2078 clear_bit(ATMCI_CARD_PRESENT
, &slot
->flags
);
2082 if (!gpio_is_valid(slot
->detect_pin
))
2083 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
2085 if (gpio_is_valid(slot
->wp_pin
)) {
2086 if (gpio_request(slot
->wp_pin
, "mmc_wp")) {
2087 dev_dbg(&mmc
->class_dev
, "no WP pin available\n");
2088 slot
->wp_pin
= -EBUSY
;
2092 host
->slot
[id
] = slot
;
2095 if (gpio_is_valid(slot
->detect_pin
)) {
2098 setup_timer(&slot
->detect_timer
, atmci_detect_change
,
2099 (unsigned long)slot
);
2101 ret
= request_irq(gpio_to_irq(slot
->detect_pin
),
2102 atmci_detect_interrupt
,
2103 IRQF_TRIGGER_FALLING
| IRQF_TRIGGER_RISING
,
2104 "mmc-detect", slot
);
2106 dev_dbg(&mmc
->class_dev
,
2107 "could not request IRQ %d for detect pin\n",
2108 gpio_to_irq(slot
->detect_pin
));
2109 gpio_free(slot
->detect_pin
);
2110 slot
->detect_pin
= -EBUSY
;
2114 atmci_init_debugfs(slot
);
2119 static void __exit
atmci_cleanup_slot(struct atmel_mci_slot
*slot
,
2122 /* Debugfs stuff is cleaned up by mmc core */
2124 set_bit(ATMCI_SHUTDOWN
, &slot
->flags
);
2127 mmc_remove_host(slot
->mmc
);
2129 if (gpio_is_valid(slot
->detect_pin
)) {
2130 int pin
= slot
->detect_pin
;
2132 free_irq(gpio_to_irq(pin
), slot
);
2133 del_timer_sync(&slot
->detect_timer
);
2136 if (gpio_is_valid(slot
->wp_pin
))
2137 gpio_free(slot
->wp_pin
);
2139 slot
->host
->slot
[id
] = NULL
;
2140 mmc_free_host(slot
->mmc
);
2143 static bool atmci_filter(struct dma_chan
*chan
, void *slave
)
2145 struct mci_dma_data
*sl
= slave
;
2147 if (sl
&& find_slave_dev(sl
) == chan
->device
->dev
) {
2148 chan
->private = slave_data_ptr(sl
);
2155 static bool atmci_configure_dma(struct atmel_mci
*host
)
2157 struct mci_platform_data
*pdata
;
2162 pdata
= host
->pdev
->dev
.platform_data
;
2164 if (pdata
&& find_slave_dev(pdata
->dma_slave
)) {
2165 dma_cap_mask_t mask
;
2167 /* Try to grab a DMA channel */
2169 dma_cap_set(DMA_SLAVE
, mask
);
2171 dma_request_channel(mask
, atmci_filter
, pdata
->dma_slave
);
2173 if (!host
->dma
.chan
) {
2174 dev_warn(&host
->pdev
->dev
, "no DMA channel available\n");
2177 dev_info(&host
->pdev
->dev
,
2178 "using %s for DMA transfers\n",
2179 dma_chan_name(host
->dma
.chan
));
2181 host
->dma_conf
.src_addr
= host
->mapbase
+ ATMCI_RDR
;
2182 host
->dma_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
2183 host
->dma_conf
.src_maxburst
= 1;
2184 host
->dma_conf
.dst_addr
= host
->mapbase
+ ATMCI_TDR
;
2185 host
->dma_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
2186 host
->dma_conf
.dst_maxburst
= 1;
2187 host
->dma_conf
.device_fc
= false;
2193 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2194 * HSMCI provides DMA support and a new config register but no more supports
2197 static void __init
atmci_get_cap(struct atmel_mci
*host
)
2199 unsigned int version
;
2201 version
= atmci_get_version(host
);
2202 dev_info(&host
->pdev
->dev
,
2203 "version: 0x%x\n", version
);
2205 host
->caps
.has_dma
= 0;
2206 host
->caps
.has_pdc
= 1;
2207 host
->caps
.has_cfg_reg
= 0;
2208 host
->caps
.has_cstor_reg
= 0;
2209 host
->caps
.has_highspeed
= 0;
2210 host
->caps
.has_rwproof
= 0;
2211 host
->caps
.has_odd_clk_div
= 0;
2212 host
->caps
.has_bad_data_ordering
= 1;
2213 host
->caps
.need_reset_after_xfer
= 1;
2214 host
->caps
.need_blksz_mul_4
= 1;
2216 /* keep only major version number */
2217 switch (version
& 0xf00) {
2219 host
->caps
.has_odd_clk_div
= 1;
2222 #ifdef CONFIG_AT_HDMAC
2223 host
->caps
.has_dma
= 1;
2225 dev_info(&host
->pdev
->dev
,
2226 "has dma capability but dma engine is not selected, then use pio\n");
2228 host
->caps
.has_pdc
= 0;
2229 host
->caps
.has_cfg_reg
= 1;
2230 host
->caps
.has_cstor_reg
= 1;
2231 host
->caps
.has_highspeed
= 1;
2233 host
->caps
.has_rwproof
= 1;
2234 host
->caps
.need_blksz_mul_4
= 0;
2236 host
->caps
.has_bad_data_ordering
= 0;
2237 host
->caps
.need_reset_after_xfer
= 0;
2241 host
->caps
.has_pdc
= 0;
2242 dev_warn(&host
->pdev
->dev
,
2243 "Unmanaged mci version, set minimum capabilities\n");
2248 static int __init
atmci_probe(struct platform_device
*pdev
)
2250 struct mci_platform_data
*pdata
;
2251 struct atmel_mci
*host
;
2252 struct resource
*regs
;
2253 unsigned int nr_slots
;
2257 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2260 pdata
= pdev
->dev
.platform_data
;
2263 irq
= platform_get_irq(pdev
, 0);
2267 host
= kzalloc(sizeof(struct atmel_mci
), GFP_KERNEL
);
2272 spin_lock_init(&host
->lock
);
2273 INIT_LIST_HEAD(&host
->queue
);
2275 host
->mck
= clk_get(&pdev
->dev
, "mci_clk");
2276 if (IS_ERR(host
->mck
)) {
2277 ret
= PTR_ERR(host
->mck
);
2282 host
->regs
= ioremap(regs
->start
, resource_size(regs
));
2286 clk_enable(host
->mck
);
2287 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_SWRST
);
2288 host
->bus_hz
= clk_get_rate(host
->mck
);
2289 clk_disable(host
->mck
);
2291 host
->mapbase
= regs
->start
;
2293 tasklet_init(&host
->tasklet
, atmci_tasklet_func
, (unsigned long)host
);
2295 ret
= request_irq(irq
, atmci_interrupt
, 0, dev_name(&pdev
->dev
), host
);
2297 goto err_request_irq
;
2299 /* Get MCI capabilities and set operations according to it */
2300 atmci_get_cap(host
);
2301 if (host
->caps
.has_dma
&& atmci_configure_dma(host
)) {
2302 host
->prepare_data
= &atmci_prepare_data_dma
;
2303 host
->submit_data
= &atmci_submit_data_dma
;
2304 host
->stop_transfer
= &atmci_stop_transfer_dma
;
2305 } else if (host
->caps
.has_pdc
) {
2306 dev_info(&pdev
->dev
, "using PDC\n");
2307 host
->prepare_data
= &atmci_prepare_data_pdc
;
2308 host
->submit_data
= &atmci_submit_data_pdc
;
2309 host
->stop_transfer
= &atmci_stop_transfer_pdc
;
2311 dev_info(&pdev
->dev
, "using PIO\n");
2312 host
->prepare_data
= &atmci_prepare_data
;
2313 host
->submit_data
= &atmci_submit_data
;
2314 host
->stop_transfer
= &atmci_stop_transfer
;
2317 platform_set_drvdata(pdev
, host
);
2319 setup_timer(&host
->timer
, atmci_timeout_timer
, (unsigned long)host
);
2321 /* We need at least one slot to succeed */
2324 if (pdata
->slot
[0].bus_width
) {
2325 ret
= atmci_init_slot(host
, &pdata
->slot
[0],
2326 0, ATMCI_SDCSEL_SLOT_A
, ATMCI_SDIOIRQA
);
2329 host
->buf_size
= host
->slot
[0]->mmc
->max_req_size
;
2332 if (pdata
->slot
[1].bus_width
) {
2333 ret
= atmci_init_slot(host
, &pdata
->slot
[1],
2334 1, ATMCI_SDCSEL_SLOT_B
, ATMCI_SDIOIRQB
);
2337 if (host
->slot
[1]->mmc
->max_req_size
> host
->buf_size
)
2339 host
->slot
[1]->mmc
->max_req_size
;
2344 dev_err(&pdev
->dev
, "init failed: no slot defined\n");
2348 if (!host
->caps
.has_rwproof
) {
2349 host
->buffer
= dma_alloc_coherent(&pdev
->dev
, host
->buf_size
,
2350 &host
->buf_phys_addr
,
2352 if (!host
->buffer
) {
2354 dev_err(&pdev
->dev
, "buffer allocation failed\n");
2359 dev_info(&pdev
->dev
,
2360 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2361 host
->mapbase
, irq
, nr_slots
);
2367 dma_release_channel(host
->dma
.chan
);
2368 free_irq(irq
, host
);
2370 iounmap(host
->regs
);
2378 static int __exit
atmci_remove(struct platform_device
*pdev
)
2380 struct atmel_mci
*host
= platform_get_drvdata(pdev
);
2383 platform_set_drvdata(pdev
, NULL
);
2386 dma_free_coherent(&pdev
->dev
, host
->buf_size
,
2387 host
->buffer
, host
->buf_phys_addr
);
2389 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
2391 atmci_cleanup_slot(host
->slot
[i
], i
);
2394 clk_enable(host
->mck
);
2395 atmci_writel(host
, ATMCI_IDR
, ~0UL);
2396 atmci_writel(host
, ATMCI_CR
, ATMCI_CR_MCIDIS
);
2397 atmci_readl(host
, ATMCI_SR
);
2398 clk_disable(host
->mck
);
2400 #ifdef CONFIG_MMC_ATMELMCI_DMA
2402 dma_release_channel(host
->dma
.chan
);
2405 free_irq(platform_get_irq(pdev
, 0), host
);
2406 iounmap(host
->regs
);
2415 static int atmci_suspend(struct device
*dev
)
2417 struct atmel_mci
*host
= dev_get_drvdata(dev
);
2420 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
2421 struct atmel_mci_slot
*slot
= host
->slot
[i
];
2426 ret
= mmc_suspend_host(slot
->mmc
);
2429 slot
= host
->slot
[i
];
2431 && test_bit(ATMCI_SUSPENDED
, &slot
->flags
)) {
2432 mmc_resume_host(host
->slot
[i
]->mmc
);
2433 clear_bit(ATMCI_SUSPENDED
, &slot
->flags
);
2438 set_bit(ATMCI_SUSPENDED
, &slot
->flags
);
2445 static int atmci_resume(struct device
*dev
)
2447 struct atmel_mci
*host
= dev_get_drvdata(dev
);
2451 for (i
= 0; i
< ATMCI_MAX_NR_SLOTS
; i
++) {
2452 struct atmel_mci_slot
*slot
= host
->slot
[i
];
2455 slot
= host
->slot
[i
];
2458 if (!test_bit(ATMCI_SUSPENDED
, &slot
->flags
))
2460 err
= mmc_resume_host(slot
->mmc
);
2464 clear_bit(ATMCI_SUSPENDED
, &slot
->flags
);
2469 static SIMPLE_DEV_PM_OPS(atmci_pm
, atmci_suspend
, atmci_resume
);
2470 #define ATMCI_PM_OPS (&atmci_pm)
2472 #define ATMCI_PM_OPS NULL
2475 static struct platform_driver atmci_driver
= {
2476 .remove
= __exit_p(atmci_remove
),
2478 .name
= "atmel_mci",
2483 static int __init
atmci_init(void)
2485 return platform_driver_probe(&atmci_driver
, atmci_probe
);
2488 static void __exit
atmci_exit(void)
2490 platform_driver_unregister(&atmci_driver
);
2493 late_initcall(atmci_init
); /* try to load after dma driver when built-in */
2494 module_exit(atmci_exit
);
2496 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2497 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2498 MODULE_LICENSE("GPL v2");