2 * bfin_sdh.c - Analog Devices Blackfin SDH Controller
4 * Copyright (C) 2007-2009 Analog Device Inc.
6 * Licensed under the GPL-2 or later.
9 #define DRIVER_NAME "bfin-sdh"
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/mmc/host.h>
19 #include <linux/proc_fs.h>
21 #include <asm/cacheflush.h>
23 #include <asm/portmux.h>
24 #include <asm/bfin_sdh.h>
26 #if defined(CONFIG_BF51x)
27 #define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CTL
28 #define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CTL
29 #define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CTL
30 #define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CTL
31 #define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
32 #define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
33 #define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
34 #define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
35 #define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
36 #define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
37 #define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
38 #define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
39 #define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CTL
40 #define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CTL
41 #define bfin_read_SDH_DATA_CNT bfin_read_RSI_DATA_CNT
42 #define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUS_CLR
43 #define bfin_read_SDH_E_STATUS bfin_read_RSI_E_STATUS
44 #define bfin_write_SDH_E_STATUS bfin_write_RSI_E_STATUS
45 #define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
46 #define bfin_write_SDH_MASK0 bfin_write_RSI_MASK0
47 #define bfin_read_SDH_CFG bfin_read_RSI_CFG
48 #define bfin_write_SDH_CFG bfin_write_RSI_CFG
51 struct dma_desc_array
{
52 unsigned long start_addr
;
54 unsigned short x_count
;
67 struct dma_desc_array
*sg_cpu
;
72 unsigned int power_mode
;
75 struct mmc_request
*mrq
;
76 struct mmc_command
*cmd
;
77 struct mmc_data
*data
;
80 static struct bfin_sd_host
*get_sdh_data(struct platform_device
*pdev
)
82 return pdev
->dev
.platform_data
;
85 static void sdh_stop_clock(struct sdh_host
*host
)
87 bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() & ~CLK_E
);
91 static void sdh_enable_stat_irq(struct sdh_host
*host
, unsigned int mask
)
95 spin_lock_irqsave(&host
->lock
, flags
);
97 bfin_write_SDH_MASK0(mask
);
99 spin_unlock_irqrestore(&host
->lock
, flags
);
102 static void sdh_disable_stat_irq(struct sdh_host
*host
, unsigned int mask
)
106 spin_lock_irqsave(&host
->lock
, flags
);
107 host
->imask
&= ~mask
;
108 bfin_write_SDH_MASK0(host
->imask
);
110 spin_unlock_irqrestore(&host
->lock
, flags
);
113 static int sdh_setup_data(struct sdh_host
*host
, struct mmc_data
*data
)
116 unsigned int data_ctl
;
117 unsigned int dma_cfg
;
119 dev_dbg(mmc_dev(host
->mmc
), "%s enter flags: 0x%x\n", __func__
, data
->flags
);
124 length
= data
->blksz
* data
->blocks
;
125 bfin_write_SDH_DATA_LGTH(length
);
127 if (data
->flags
& MMC_DATA_STREAM
)
128 data_ctl
|= DTX_MODE
;
130 if (data
->flags
& MMC_DATA_READ
)
132 /* Only supports power-of-2 block size */
133 if (data
->blksz
& (data
->blksz
- 1))
135 data_ctl
|= ((ffs(data
->blksz
) - 1) << 4);
137 bfin_write_SDH_DATA_CTL(data_ctl
);
139 bfin_write_SDH_DATA_TIMER(0xFFFF);
142 if (data
->flags
& MMC_DATA_READ
) {
143 host
->dma_dir
= DMA_FROM_DEVICE
;
146 host
->dma_dir
= DMA_TO_DEVICE
;
148 sdh_enable_stat_irq(host
, (DAT_CRC_FAIL
| DAT_TIME_OUT
| DAT_END
));
149 host
->dma_len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
, host
->dma_dir
);
150 #if defined(CONFIG_BF54x)
151 dma_cfg
|= DMAFLOW_ARRAY
| NDSIZE_5
| RESTART
| WDSIZE_32
| DMAEN
;
153 struct scatterlist
*sg
;
155 for_each_sg(data
->sg
, sg
, host
->dma_len
, i
) {
156 host
->sg_cpu
[i
].start_addr
= sg_dma_address(sg
);
157 host
->sg_cpu
[i
].cfg
= dma_cfg
;
158 host
->sg_cpu
[i
].x_count
= sg_dma_len(sg
) / 4;
159 host
->sg_cpu
[i
].x_modify
= 4;
160 dev_dbg(mmc_dev(host
->mmc
), "%d: start_addr:0x%lx, "
161 "cfg:0x%x, x_count:0x%x, x_modify:0x%x\n",
162 i
, host
->sg_cpu
[i
].start_addr
,
163 host
->sg_cpu
[i
].cfg
, host
->sg_cpu
[i
].x_count
,
164 host
->sg_cpu
[i
].x_modify
);
167 flush_dcache_range((unsigned int)host
->sg_cpu
,
168 (unsigned int)host
->sg_cpu
+
169 host
->dma_len
* sizeof(struct dma_desc_array
));
170 /* Set the last descriptor to stop mode */
171 host
->sg_cpu
[host
->dma_len
- 1].cfg
&= ~(DMAFLOW
| NDSIZE
);
172 host
->sg_cpu
[host
->dma_len
- 1].cfg
|= DI_EN
;
174 set_dma_curr_desc_addr(host
->dma_ch
, (unsigned long *)host
->sg_dma
);
175 set_dma_x_count(host
->dma_ch
, 0);
176 set_dma_x_modify(host
->dma_ch
, 0);
177 set_dma_config(host
->dma_ch
, dma_cfg
);
178 #elif defined(CONFIG_BF51x)
179 /* RSI DMA doesn't work in array mode */
180 dma_cfg
|= WDSIZE_32
| DMAEN
;
181 set_dma_start_addr(host
->dma_ch
, sg_dma_address(&data
->sg
[0]));
182 set_dma_x_count(host
->dma_ch
, length
/ 4);
183 set_dma_x_modify(host
->dma_ch
, 4);
184 set_dma_config(host
->dma_ch
, dma_cfg
);
186 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E
| DTX_E
);
190 dev_dbg(mmc_dev(host
->mmc
), "%s exit\n", __func__
);
194 static void sdh_start_cmd(struct sdh_host
*host
, struct mmc_command
*cmd
)
196 unsigned int sdh_cmd
;
197 unsigned int stat_mask
;
199 dev_dbg(mmc_dev(host
->mmc
), "%s enter cmd: 0x%p\n", __func__
, cmd
);
200 WARN_ON(host
->cmd
!= NULL
);
206 sdh_cmd
|= cmd
->opcode
;
208 if (cmd
->flags
& MMC_RSP_PRESENT
) {
210 stat_mask
|= CMD_RESP_END
;
212 stat_mask
|= CMD_SENT
;
215 if (cmd
->flags
& MMC_RSP_136
)
216 sdh_cmd
|= CMD_L_RSP
;
218 stat_mask
|= CMD_CRC_FAIL
| CMD_TIME_OUT
;
220 sdh_enable_stat_irq(host
, stat_mask
);
222 bfin_write_SDH_ARGUMENT(cmd
->arg
);
223 bfin_write_SDH_COMMAND(sdh_cmd
| CMD_E
);
224 bfin_write_SDH_CLK_CTL(bfin_read_SDH_CLK_CTL() | CLK_E
);
228 static void sdh_finish_request(struct sdh_host
*host
, struct mmc_request
*mrq
)
230 dev_dbg(mmc_dev(host
->mmc
), "%s enter\n", __func__
);
234 mmc_request_done(host
->mmc
, mrq
);
237 static int sdh_cmd_done(struct sdh_host
*host
, unsigned int stat
)
239 struct mmc_command
*cmd
= host
->cmd
;
242 dev_dbg(mmc_dev(host
->mmc
), "%s enter cmd: %p\n", __func__
, cmd
);
248 if (cmd
->flags
& MMC_RSP_PRESENT
) {
249 cmd
->resp
[0] = bfin_read_SDH_RESPONSE0();
250 if (cmd
->flags
& MMC_RSP_136
) {
251 cmd
->resp
[1] = bfin_read_SDH_RESPONSE1();
252 cmd
->resp
[2] = bfin_read_SDH_RESPONSE2();
253 cmd
->resp
[3] = bfin_read_SDH_RESPONSE3();
256 if (stat
& CMD_TIME_OUT
)
257 cmd
->error
= -ETIMEDOUT
;
258 else if (stat
& CMD_CRC_FAIL
&& cmd
->flags
& MMC_RSP_CRC
)
259 cmd
->error
= -EILSEQ
;
261 sdh_disable_stat_irq(host
, (CMD_SENT
| CMD_RESP_END
| CMD_TIME_OUT
| CMD_CRC_FAIL
));
263 if (host
->data
&& !cmd
->error
) {
264 if (host
->data
->flags
& MMC_DATA_WRITE
) {
265 ret
= sdh_setup_data(host
, host
->data
);
270 sdh_enable_stat_irq(host
, DAT_END
| RX_OVERRUN
| TX_UNDERRUN
| DAT_TIME_OUT
);
272 sdh_finish_request(host
, host
->mrq
);
277 static int sdh_data_done(struct sdh_host
*host
, unsigned int stat
)
279 struct mmc_data
*data
= host
->data
;
281 dev_dbg(mmc_dev(host
->mmc
), "%s enter stat: 0x%x\n", __func__
, stat
);
285 disable_dma(host
->dma_ch
);
286 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
289 if (stat
& DAT_TIME_OUT
)
290 data
->error
= -ETIMEDOUT
;
291 else if (stat
& DAT_CRC_FAIL
)
292 data
->error
= -EILSEQ
;
293 else if (stat
& (RX_OVERRUN
| TX_UNDERRUN
))
297 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
299 data
->bytes_xfered
= 0;
301 sdh_disable_stat_irq(host
, DAT_END
| DAT_TIME_OUT
| DAT_CRC_FAIL
| RX_OVERRUN
| TX_UNDERRUN
);
302 bfin_write_SDH_STATUS_CLR(DAT_END_STAT
| DAT_TIMEOUT_STAT
| \
303 DAT_CRC_FAIL_STAT
| DAT_BLK_END_STAT
| RX_OVERRUN
| TX_UNDERRUN
);
304 bfin_write_SDH_DATA_CTL(0);
308 if (host
->mrq
->stop
) {
309 sdh_stop_clock(host
);
310 sdh_start_cmd(host
, host
->mrq
->stop
);
312 sdh_finish_request(host
, host
->mrq
);
318 static void sdh_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
320 struct sdh_host
*host
= mmc_priv(mmc
);
323 dev_dbg(mmc_dev(host
->mmc
), "%s enter, mrp:%p, cmd:%p\n", __func__
, mrq
, mrq
->cmd
);
324 WARN_ON(host
->mrq
!= NULL
);
327 host
->data
= mrq
->data
;
329 if (mrq
->data
&& mrq
->data
->flags
& MMC_DATA_READ
) {
330 ret
= sdh_setup_data(host
, mrq
->data
);
335 sdh_start_cmd(host
, mrq
->cmd
);
338 static void sdh_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
340 struct sdh_host
*host
;
345 host
= mmc_priv(mmc
);
347 spin_lock_irqsave(&host
->lock
, flags
);
349 unsigned long sys_clk
, ios_clk
;
350 unsigned char clk_div
;
351 ios_clk
= 2 * ios
->clock
;
352 sys_clk
= get_sclk();
353 clk_div
= sys_clk
/ ios_clk
;
354 if (sys_clk
% ios_clk
== 0)
356 clk_div
= min_t(unsigned char, clk_div
, 0xFF);
359 host
->clk_div
= clk_div
;
361 sdh_stop_clock(host
);
363 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
364 #ifdef CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
367 pwr_ctl
|= SD_CMD_OD
| ROD_CTL
;
370 if (ios
->bus_width
== MMC_BUS_WIDTH_4
) {
371 cfg
= bfin_read_SDH_CFG();
374 /* Enable 4 bit SDIO */
376 bfin_write_SDH_CFG(cfg
);
379 cfg
= bfin_read_SDH_CFG();
381 bfin_write_SDH_CFG(cfg
);
384 bfin_write_SDH_CLK_CTL(clk_ctl
);
386 host
->power_mode
= ios
->power_mode
;
387 if (ios
->power_mode
== MMC_POWER_ON
)
390 bfin_write_SDH_PWR_CTL(pwr_ctl
);
393 spin_unlock_irqrestore(&host
->lock
, flags
);
395 dev_dbg(mmc_dev(host
->mmc
), "SDH: clk_div = 0x%x actual clock:%ld expected clock:%d\n",
397 host
->clk_div
? get_sclk() / (2 * (host
->clk_div
+ 1)) : 0,
401 static const struct mmc_host_ops sdh_ops
= {
402 .request
= sdh_request
,
403 .set_ios
= sdh_set_ios
,
406 static irqreturn_t
sdh_dma_irq(int irq
, void *devid
)
408 struct sdh_host
*host
= devid
;
410 dev_dbg(mmc_dev(host
->mmc
), "%s enter, irq_stat: 0x%04x\n", __func__
,
411 get_dma_curr_irqstat(host
->dma_ch
));
412 clear_dma_irqstat(host
->dma_ch
);
418 static irqreturn_t
sdh_stat_irq(int irq
, void *devid
)
420 struct sdh_host
*host
= devid
;
424 dev_dbg(mmc_dev(host
->mmc
), "%s enter\n", __func__
);
425 status
= bfin_read_SDH_E_STATUS();
426 if (status
& SD_CARD_DET
) {
427 mmc_detect_change(host
->mmc
, 0);
428 bfin_write_SDH_E_STATUS(SD_CARD_DET
);
430 status
= bfin_read_SDH_STATUS();
431 if (status
& (CMD_SENT
| CMD_RESP_END
| CMD_TIME_OUT
| CMD_CRC_FAIL
)) {
432 handled
|= sdh_cmd_done(host
, status
);
433 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT
| CMD_RESP_END_STAT
| \
434 CMD_TIMEOUT_STAT
| CMD_CRC_FAIL_STAT
);
438 status
= bfin_read_SDH_STATUS();
439 if (status
& (DAT_END
| DAT_TIME_OUT
| DAT_CRC_FAIL
| RX_OVERRUN
| TX_UNDERRUN
))
440 handled
|= sdh_data_done(host
, status
);
442 dev_dbg(mmc_dev(host
->mmc
), "%s exit\n\n", __func__
);
444 return IRQ_RETVAL(handled
);
447 static int __devinit
sdh_probe(struct platform_device
*pdev
)
449 struct mmc_host
*mmc
;
450 struct sdh_host
*host
;
451 struct bfin_sd_host
*drv_data
= get_sdh_data(pdev
);
455 dev_err(&pdev
->dev
, "missing platform driver data\n");
460 mmc
= mmc_alloc_host(sizeof(*mmc
), &pdev
->dev
);
467 mmc
->max_phys_segs
= 32;
468 mmc
->max_seg_size
= 1 << 16;
469 mmc
->max_blk_size
= 1 << 11;
470 mmc
->max_blk_count
= 1 << 11;
471 mmc
->max_req_size
= PAGE_SIZE
;
472 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
473 mmc
->f_max
= get_sclk();
474 mmc
->f_min
= mmc
->f_max
>> 9;
475 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_NEEDS_POLL
;
476 host
= mmc_priv(mmc
);
479 spin_lock_init(&host
->lock
);
480 host
->irq
= drv_data
->irq_int0
;
481 host
->dma_ch
= drv_data
->dma_chan
;
483 ret
= request_dma(host
->dma_ch
, DRIVER_NAME
"DMA");
485 dev_err(&pdev
->dev
, "unable to request DMA channel\n");
489 ret
= set_dma_callback(host
->dma_ch
, sdh_dma_irq
, host
);
491 dev_err(&pdev
->dev
, "unable to request DMA irq\n");
495 host
->sg_cpu
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
, &host
->sg_dma
, GFP_KERNEL
);
496 if (host
->sg_cpu
== NULL
) {
501 platform_set_drvdata(pdev
, mmc
);
504 ret
= request_irq(host
->irq
, sdh_stat_irq
, 0, "SDH Status IRQ", host
);
506 dev_err(&pdev
->dev
, "unable to request status irq\n");
510 ret
= peripheral_request_list(drv_data
->pin_req
, DRIVER_NAME
);
512 dev_err(&pdev
->dev
, "unable to request peripheral pins\n");
515 #if defined(CONFIG_BF54x)
516 /* Secure Digital Host shares DMA with Nand controller */
517 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
520 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN
);
523 /* Disable card inserting detection pin. set MMC_CAP_NEES_POLL, and
524 * mmc stack will do the detection.
526 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT
| PUP_SDDAT3
));
532 free_irq(host
->irq
, host
);
534 mmc_remove_host(mmc
);
535 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, host
->sg_cpu
, host
->sg_dma
);
537 free_dma(host
->dma_ch
);
544 static int __devexit
sdh_remove(struct platform_device
*pdev
)
546 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
548 platform_set_drvdata(pdev
, NULL
);
551 struct sdh_host
*host
= mmc_priv(mmc
);
553 mmc_remove_host(mmc
);
555 sdh_stop_clock(host
);
556 free_irq(host
->irq
, host
);
557 free_dma(host
->dma_ch
);
558 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, host
->sg_cpu
, host
->sg_dma
);
567 static int sdh_suspend(struct platform_device
*dev
, pm_message_t state
)
569 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
570 struct bfin_sd_host
*drv_data
= get_sdh_data(dev
);
574 ret
= mmc_suspend_host(mmc
, state
);
576 bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() & ~PWR_ON
);
577 peripheral_free_list(drv_data
->pin_req
);
582 static int sdh_resume(struct platform_device
*dev
)
584 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
585 struct bfin_sd_host
*drv_data
= get_sdh_data(dev
);
588 ret
= peripheral_request_list(drv_data
->pin_req
, DRIVER_NAME
);
590 dev_err(&dev
->dev
, "unable to request peripheral pins\n");
594 bfin_write_SDH_PWR_CTL(bfin_read_SDH_PWR_CTL() | PWR_ON
);
595 #if defined(CONFIG_BF54x)
596 /* Secure Digital Host shares DMA with Nand controller */
597 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
599 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN
);
602 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | (PUP_SDDAT
| PUP_SDDAT3
));
606 ret
= mmc_resume_host(mmc
);
611 # define sdh_suspend NULL
612 # define sdh_resume NULL
615 static struct platform_driver sdh_driver
= {
617 .remove
= __devexit_p(sdh_remove
),
618 .suspend
= sdh_suspend
,
619 .resume
= sdh_resume
,
625 static int __init
sdh_init(void)
627 return platform_driver_register(&sdh_driver
);
629 module_init(sdh_init
);
631 static void __exit
sdh_exit(void)
633 platform_driver_unregister(&sdh_driver
);
635 module_exit(sdh_exit
);
637 MODULE_DESCRIPTION("Blackfin Secure Digital Host Driver");
638 MODULE_AUTHOR("Cliff Cai, Roy Huang");
639 MODULE_LICENSE("GPL");