drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/clk.h>
  13 #include <linux/mmc/host.h>
  14 #include <linux/mmc/dw_mmc.h>
  15 #include <linux/of_address.h>
  16 #include <linux/slab.h>
  17
  18 #include "dw_mmc.h"
  19 #include "dw_mmc-pltfm.h"
  20
  21 #define RK3288_CLKGEN_DIV       2
  22
  23 struct dw_mci_rockchip_priv_data {
  24         struct clk              *drv_clk;
  25         struct clk              *sample_clk;
  26         int                     default_sample_phase;
  27 };
  28
  29 static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
  30 {
  31         host->bus_hz /= RK3288_CLKGEN_DIV;
  32
  33         return 0;
  34 }
  35
  36 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  37 {
  38         struct dw_mci_rockchip_priv_data *priv = host->priv;
  39         int ret;
  40         unsigned int cclkin;
  41         u32 bus_hz;
  42
  43         if (ios->clock == 0)
  44                 return;
  45
  46         /*
  47          * cclkin: source clock of mmc controller
  48          * bus_hz: card interface clock generated by CLKGEN
  49          * bus_hz = cclkin / RK3288_CLKGEN_DIV
  50          * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
  51          *
  52          * Note: div can only be 0 or 1
  53          *       if DDR50 8bit mode(only emmc work in 8bit mode),
  54          *       div must be set 1
  55          */
  56         if (ios->bus_width == MMC_BUS_WIDTH_8 &&
  57             ios->timing == MMC_TIMING_MMC_DDR52)
  58                 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
  59         else
  60                 cclkin = ios->clock * RK3288_CLKGEN_DIV;
  61
  62         ret = clk_set_rate(host->ciu_clk, cclkin);
  63         if (ret)
  64                 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
  65
  66         bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
  67         if (bus_hz != host->bus_hz) {
  68                 host->bus_hz = bus_hz;
  69                 /* force dw_mci_setup_bus() */
  70                 host->current_speed = 0;
  71         }
  72
  73         /* Make sure we use phases which we can enumerate with */
  74         if (!IS_ERR(priv->sample_clk))
  75                 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
  76 }
  77
  78 #define NUM_PHASES                      360
  79 #define TUNING_ITERATION_TO_PHASE(i)    (DIV_ROUND_UP((i) * 360, NUM_PHASES))
  80
  81 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
  82 {
  83         struct dw_mci *host = slot->host;
  84         struct dw_mci_rockchip_priv_data *priv = host->priv;
  85         struct mmc_host *mmc = slot->mmc;
  86         int ret = 0;
  87         int i;
  88         bool v, prev_v = 0, first_v;
  89         struct range_t {
  90                 int start;
  91                 int end; /* inclusive */
  92         };
  93         struct range_t *ranges;
  94         unsigned int range_count = 0;
  95         int longest_range_len = -1;
  96         int longest_range = -1;
  97         int middle_phase;
  98
  99         if (IS_ERR(priv->sample_clk)) {
 100                 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
 101                 return -EIO;
 102         }
 103
 104         ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
 105         if (!ranges)
 106                 return -ENOMEM;
 107
 108         /* Try each phase and extract good ranges */
 109         for (i = 0; i < NUM_PHASES; ) {
 110                 clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i));
 111
 112                 v = !mmc_send_tuning(mmc, opcode, NULL);
 113
 114                 if (i == 0)
 115                         first_v = v;
 116
 117                 if ((!prev_v) && v) {
 118                         range_count++;
 119                         ranges[range_count-1].start = i;
 120                 }
 121                 if (v) {
 122                         ranges[range_count-1].end = i;
 123                         i++;
 124                 } else if (i == NUM_PHASES - 1) {
 125                         /* No extra skipping rules if we're at the end */
 126                         i++;
 127                 } else {
 128                         /*
 129                          * No need to check too close to an invalid
 130                          * one since testing bad phases is slow.  Skip
 131                          * 20 degrees.
 132                          */
 133                         i += DIV_ROUND_UP(20 * NUM_PHASES, 360);
 134
 135                         /* Always test the last one */
 136                         if (i >= NUM_PHASES)
 137                                 i = NUM_PHASES - 1;
 138                 }
 139
 140                 prev_v = v;
 141         }
 142
 143         if (range_count == 0) {
 144                 dev_warn(host->dev, "All phases bad!");
 145                 ret = -EIO;
 146                 goto free;
 147         }
 148
 149         /* wrap around case, merge the end points */
 150         if ((range_count > 1) && first_v && v) {
 151                 ranges[0].start = ranges[range_count-1].start;
 152                 range_count--;
 153         }
 154
 155         if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
 156                 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
 157                 dev_info(host->dev, "All phases work, using default phase %d.",
 158                          priv->default_sample_phase);
 159                 goto free;
 160         }
 161
 162         /* Find the longest range */
 163         for (i = 0; i < range_count; i++) {
 164                 int len = (ranges[i].end - ranges[i].start + 1);
 165
 166                 if (len < 0)
 167                         len += NUM_PHASES;
 168
 169                 if (longest_range_len < len) {
 170                         longest_range_len = len;
 171                         longest_range = i;
 172                 }
 173
 174                 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
 175                         TUNING_ITERATION_TO_PHASE(ranges[i].start),
 176                         TUNING_ITERATION_TO_PHASE(ranges[i].end),
 177                         len
 178                 );
 179         }
 180
 181         dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
 182                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
 183                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
 184                 longest_range_len
 185         );
 186
 187         middle_phase = ranges[longest_range].start + longest_range_len / 2;
 188         middle_phase %= NUM_PHASES;
 189         dev_info(host->dev, "Successfully tuned phase to %d\n",
 190                  TUNING_ITERATION_TO_PHASE(middle_phase));
 191
 192         clk_set_phase(priv->sample_clk,
 193                       TUNING_ITERATION_TO_PHASE(middle_phase));
 194
 195 free:
 196         kfree(ranges);
 197         return ret;
 198 }
 199
 200 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
 201 {
 202         struct device_node *np = host->dev->of_node;
 203         struct dw_mci_rockchip_priv_data *priv;
 204
 205         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 206         if (!priv)
 207                 return -ENOMEM;
 208
 209         if (of_property_read_u32(np, "rockchip,default-sample-phase",
 210                                         &priv->default_sample_phase))
 211                 priv->default_sample_phase = 0;
 212
 213         priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
 214         if (IS_ERR(priv->drv_clk))
 215                 dev_dbg(host->dev, "ciu_drv not available\n");
 216
 217         priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
 218         if (IS_ERR(priv->sample_clk))
 219                 dev_dbg(host->dev, "ciu_sample not available\n");
 220
 221         host->priv = priv;
 222
 223         return 0;
 224 }
 225
 226 static int dw_mci_rockchip_init(struct dw_mci *host)
 227 {
 228         /* It is slot 8 on Rockchip SoCs */
 229         host->sdio_id0 = 8;
 230
 231         /* It needs this quirk on all Rockchip SoCs */
 232         host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO;
 233
 234         return 0;
 235 }
 236
 237 static const struct dw_mci_drv_data rk2928_drv_data = {
 238         .init                   = dw_mci_rockchip_init,
 239 };
 240
 241 static const struct dw_mci_drv_data rk3288_drv_data = {
 242         .set_ios                = dw_mci_rk3288_set_ios,
 243         .execute_tuning         = dw_mci_rk3288_execute_tuning,
 244         .parse_dt               = dw_mci_rk3288_parse_dt,
 245         .setup_clock    = dw_mci_rk3288_setup_clock,
 246         .init                   = dw_mci_rockchip_init,
 247 };
 248
 249 static const struct of_device_id dw_mci_rockchip_match[] = {
 250         { .compatible = "rockchip,rk2928-dw-mshc",
 251                 .data = &rk2928_drv_data },
 252         { .compatible = "rockchip,rk3288-dw-mshc",
 253                 .data = &rk3288_drv_data },
 254         {},
 255 };
 256 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 257
 258 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 259 {
 260         const struct dw_mci_drv_data *drv_data;
 261         const struct of_device_id *match;
 262
 263         if (!pdev->dev.of_node)
 264                 return -ENODEV;
 265
 266         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 267         drv_data = match->data;
 268
 269         return dw_mci_pltfm_register(pdev, drv_data);
 270 }
 271
 272 #ifdef CONFIG_PM_SLEEP
 273 static int dw_mci_rockchip_suspend(struct device *dev)
 274 {
 275         struct dw_mci *host = dev_get_drvdata(dev);
 276
 277         return dw_mci_suspend(host);
 278 }
 279
 280 static int dw_mci_rockchip_resume(struct device *dev)
 281 {
 282         struct dw_mci *host = dev_get_drvdata(dev);
 283
 284         return dw_mci_resume(host);
 285 }
 286 #endif /* CONFIG_PM_SLEEP */
 287
 288 static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
 289                          dw_mci_rockchip_suspend,
 290                          dw_mci_rockchip_resume);
 291
 292 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 293         .probe          = dw_mci_rockchip_probe,
 294         .remove         = dw_mci_pltfm_remove,
 295         .driver         = {
 296                 .name           = "dwmmc_rockchip",
 297                 .of_match_table = dw_mci_rockchip_match,
 298                 .pm             = &dw_mci_rockchip_pmops,
 299         },
 300 };
 301
 302 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 303
 304 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 305 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
 306 MODULE_ALIAS("platform:dwmmc_rockchip");
 307 MODULE_LICENSE("GPL v2");