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[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/seq_file.h>
27 #include <linux/slab.h>
28 #include <linux/stat.h>
29 #include <linux/delay.h>
30 #include <linux/irq.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/dw_mmc.h>
34 #include <linux/bitops.h>
35
36 #include "dw_mmc.h"
37
38 /* Common flag combinations */
39 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
40 SDMMC_INT_HTO | SDMMC_INT_SBE | \
41 SDMMC_INT_EBE)
42 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
43 SDMMC_INT_RESP_ERR)
44 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
45 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
46 #define DW_MCI_SEND_STATUS 1
47 #define DW_MCI_RECV_STATUS 2
48 #define DW_MCI_DMA_THRESHOLD 16
49
50 #ifdef CONFIG_MMC_DW_IDMAC
51 struct idmac_desc {
52 u32 des0; /* Control Descriptor */
53 #define IDMAC_DES0_DIC BIT(1)
54 #define IDMAC_DES0_LD BIT(2)
55 #define IDMAC_DES0_FD BIT(3)
56 #define IDMAC_DES0_CH BIT(4)
57 #define IDMAC_DES0_ER BIT(5)
58 #define IDMAC_DES0_CES BIT(30)
59 #define IDMAC_DES0_OWN BIT(31)
60
61 u32 des1; /* Buffer sizes */
62 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
63 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
64
65 u32 des2; /* buffer 1 physical address */
66
67 u32 des3; /* buffer 2 physical address */
68 };
69 #endif /* CONFIG_MMC_DW_IDMAC */
70
71 /**
72 * struct dw_mci_slot - MMC slot state
73 * @mmc: The mmc_host representing this slot.
74 * @host: The MMC controller this slot is using.
75 * @ctype: Card type for this slot.
76 * @mrq: mmc_request currently being processed or waiting to be
77 * processed, or NULL when the slot is idle.
78 * @queue_node: List node for placing this node in the @queue list of
79 * &struct dw_mci.
80 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
81 * @flags: Random state bits associated with the slot.
82 * @id: Number of this slot.
83 * @last_detect_state: Most recently observed card detect state.
84 */
85 struct dw_mci_slot {
86 struct mmc_host *mmc;
87 struct dw_mci *host;
88
89 u32 ctype;
90
91 struct mmc_request *mrq;
92 struct list_head queue_node;
93
94 unsigned int clock;
95 unsigned long flags;
96 #define DW_MMC_CARD_PRESENT 0
97 #define DW_MMC_CARD_NEED_INIT 1
98 int id;
99 int last_detect_state;
100 };
101
102 #if defined(CONFIG_DEBUG_FS)
103 static int dw_mci_req_show(struct seq_file *s, void *v)
104 {
105 struct dw_mci_slot *slot = s->private;
106 struct mmc_request *mrq;
107 struct mmc_command *cmd;
108 struct mmc_command *stop;
109 struct mmc_data *data;
110
111 /* Make sure we get a consistent snapshot */
112 spin_lock_bh(&slot->host->lock);
113 mrq = slot->mrq;
114
115 if (mrq) {
116 cmd = mrq->cmd;
117 data = mrq->data;
118 stop = mrq->stop;
119
120 if (cmd)
121 seq_printf(s,
122 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
123 cmd->opcode, cmd->arg, cmd->flags,
124 cmd->resp[0], cmd->resp[1], cmd->resp[2],
125 cmd->resp[2], cmd->error);
126 if (data)
127 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
128 data->bytes_xfered, data->blocks,
129 data->blksz, data->flags, data->error);
130 if (stop)
131 seq_printf(s,
132 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
133 stop->opcode, stop->arg, stop->flags,
134 stop->resp[0], stop->resp[1], stop->resp[2],
135 stop->resp[2], stop->error);
136 }
137
138 spin_unlock_bh(&slot->host->lock);
139
140 return 0;
141 }
142
143 static int dw_mci_req_open(struct inode *inode, struct file *file)
144 {
145 return single_open(file, dw_mci_req_show, inode->i_private);
146 }
147
148 static const struct file_operations dw_mci_req_fops = {
149 .owner = THIS_MODULE,
150 .open = dw_mci_req_open,
151 .read = seq_read,
152 .llseek = seq_lseek,
153 .release = single_release,
154 };
155
156 static int dw_mci_regs_show(struct seq_file *s, void *v)
157 {
158 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
159 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
160 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
161 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
162 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
163 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
164
165 return 0;
166 }
167
168 static int dw_mci_regs_open(struct inode *inode, struct file *file)
169 {
170 return single_open(file, dw_mci_regs_show, inode->i_private);
171 }
172
173 static const struct file_operations dw_mci_regs_fops = {
174 .owner = THIS_MODULE,
175 .open = dw_mci_regs_open,
176 .read = seq_read,
177 .llseek = seq_lseek,
178 .release = single_release,
179 };
180
181 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
182 {
183 struct mmc_host *mmc = slot->mmc;
184 struct dw_mci *host = slot->host;
185 struct dentry *root;
186 struct dentry *node;
187
188 root = mmc->debugfs_root;
189 if (!root)
190 return;
191
192 node = debugfs_create_file("regs", S_IRUSR, root, host,
193 &dw_mci_regs_fops);
194 if (!node)
195 goto err;
196
197 node = debugfs_create_file("req", S_IRUSR, root, slot,
198 &dw_mci_req_fops);
199 if (!node)
200 goto err;
201
202 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
203 if (!node)
204 goto err;
205
206 node = debugfs_create_x32("pending_events", S_IRUSR, root,
207 (u32 *)&host->pending_events);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_x32("completed_events", S_IRUSR, root,
212 (u32 *)&host->completed_events);
213 if (!node)
214 goto err;
215
216 return;
217
218 err:
219 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
220 }
221 #endif /* defined(CONFIG_DEBUG_FS) */
222
223 static void dw_mci_set_timeout(struct dw_mci *host)
224 {
225 /* timeout (maximum) */
226 mci_writel(host, TMOUT, 0xffffffff);
227 }
228
229 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
230 {
231 struct mmc_data *data;
232 u32 cmdr;
233 cmd->error = -EINPROGRESS;
234
235 cmdr = cmd->opcode;
236
237 if (cmdr == MMC_STOP_TRANSMISSION)
238 cmdr |= SDMMC_CMD_STOP;
239 else
240 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
241
242 if (cmd->flags & MMC_RSP_PRESENT) {
243 /* We expect a response, so set this bit */
244 cmdr |= SDMMC_CMD_RESP_EXP;
245 if (cmd->flags & MMC_RSP_136)
246 cmdr |= SDMMC_CMD_RESP_LONG;
247 }
248
249 if (cmd->flags & MMC_RSP_CRC)
250 cmdr |= SDMMC_CMD_RESP_CRC;
251
252 data = cmd->data;
253 if (data) {
254 cmdr |= SDMMC_CMD_DAT_EXP;
255 if (data->flags & MMC_DATA_STREAM)
256 cmdr |= SDMMC_CMD_STRM_MODE;
257 if (data->flags & MMC_DATA_WRITE)
258 cmdr |= SDMMC_CMD_DAT_WR;
259 }
260
261 return cmdr;
262 }
263
264 static void dw_mci_start_command(struct dw_mci *host,
265 struct mmc_command *cmd, u32 cmd_flags)
266 {
267 host->cmd = cmd;
268 dev_vdbg(&host->pdev->dev,
269 "start command: ARGR=0x%08x CMDR=0x%08x\n",
270 cmd->arg, cmd_flags);
271
272 mci_writel(host, CMDARG, cmd->arg);
273 wmb();
274
275 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
276 }
277
278 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
279 {
280 dw_mci_start_command(host, data->stop, host->stop_cmdr);
281 }
282
283 /* DMA interface functions */
284 static void dw_mci_stop_dma(struct dw_mci *host)
285 {
286 if (host->use_dma) {
287 host->dma_ops->stop(host);
288 host->dma_ops->cleanup(host);
289 } else {
290 /* Data transfer was stopped by the interrupt handler */
291 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
292 }
293 }
294
295 #ifdef CONFIG_MMC_DW_IDMAC
296 static void dw_mci_dma_cleanup(struct dw_mci *host)
297 {
298 struct mmc_data *data = host->data;
299
300 if (data)
301 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
302 ((data->flags & MMC_DATA_WRITE)
303 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
304 }
305
306 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
307 {
308 u32 temp;
309
310 /* Disable and reset the IDMAC interface */
311 temp = mci_readl(host, CTRL);
312 temp &= ~SDMMC_CTRL_USE_IDMAC;
313 temp |= SDMMC_CTRL_DMA_RESET;
314 mci_writel(host, CTRL, temp);
315
316 /* Stop the IDMAC running */
317 temp = mci_readl(host, BMOD);
318 temp &= ~SDMMC_IDMAC_ENABLE;
319 mci_writel(host, BMOD, temp);
320 }
321
322 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
323 {
324 struct mmc_data *data = host->data;
325
326 dev_vdbg(&host->pdev->dev, "DMA complete\n");
327
328 host->dma_ops->cleanup(host);
329
330 /*
331 * If the card was removed, data will be NULL. No point in trying to
332 * send the stop command or waiting for NBUSY in this case.
333 */
334 if (data) {
335 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
336 tasklet_schedule(&host->tasklet);
337 }
338 }
339
340 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
341 unsigned int sg_len)
342 {
343 int i;
344 struct idmac_desc *desc = host->sg_cpu;
345
346 for (i = 0; i < sg_len; i++, desc++) {
347 unsigned int length = sg_dma_len(&data->sg[i]);
348 u32 mem_addr = sg_dma_address(&data->sg[i]);
349
350 /* Set the OWN bit and disable interrupts for this descriptor */
351 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
352
353 /* Buffer length */
354 IDMAC_SET_BUFFER1_SIZE(desc, length);
355
356 /* Physical address to DMA to/from */
357 desc->des2 = mem_addr;
358 }
359
360 /* Set first descriptor */
361 desc = host->sg_cpu;
362 desc->des0 |= IDMAC_DES0_FD;
363
364 /* Set last descriptor */
365 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
366 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
367 desc->des0 |= IDMAC_DES0_LD;
368
369 wmb();
370 }
371
372 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
373 {
374 u32 temp;
375
376 dw_mci_translate_sglist(host, host->data, sg_len);
377
378 /* Select IDMAC interface */
379 temp = mci_readl(host, CTRL);
380 temp |= SDMMC_CTRL_USE_IDMAC;
381 mci_writel(host, CTRL, temp);
382
383 wmb();
384
385 /* Enable the IDMAC */
386 temp = mci_readl(host, BMOD);
387 temp |= SDMMC_IDMAC_ENABLE;
388 mci_writel(host, BMOD, temp);
389
390 /* Start it running */
391 mci_writel(host, PLDMND, 1);
392 }
393
394 static int dw_mci_idmac_init(struct dw_mci *host)
395 {
396 struct idmac_desc *p;
397 int i;
398
399 /* Number of descriptors in the ring buffer */
400 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
401
402 /* Forward link the descriptor list */
403 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
404 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
405
406 /* Set the last descriptor as the end-of-ring descriptor */
407 p->des3 = host->sg_dma;
408 p->des0 = IDMAC_DES0_ER;
409
410 /* Mask out interrupts - get Tx & Rx complete only */
411 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
412 SDMMC_IDMAC_INT_TI);
413
414 /* Set the descriptor base address */
415 mci_writel(host, DBADDR, host->sg_dma);
416 return 0;
417 }
418
419 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
420 .init = dw_mci_idmac_init,
421 .start = dw_mci_idmac_start_dma,
422 .stop = dw_mci_idmac_stop_dma,
423 .complete = dw_mci_idmac_complete_dma,
424 .cleanup = dw_mci_dma_cleanup,
425 };
426 #endif /* CONFIG_MMC_DW_IDMAC */
427
428 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
429 {
430 struct scatterlist *sg;
431 unsigned int i, direction, sg_len;
432 u32 temp;
433
434 /* If we don't have a channel, we can't do DMA */
435 if (!host->use_dma)
436 return -ENODEV;
437
438 /*
439 * We don't do DMA on "complex" transfers, i.e. with
440 * non-word-aligned buffers or lengths. Also, we don't bother
441 * with all the DMA setup overhead for short transfers.
442 */
443 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
444 return -EINVAL;
445 if (data->blksz & 3)
446 return -EINVAL;
447
448 for_each_sg(data->sg, sg, data->sg_len, i) {
449 if (sg->offset & 3 || sg->length & 3)
450 return -EINVAL;
451 }
452
453 if (data->flags & MMC_DATA_READ)
454 direction = DMA_FROM_DEVICE;
455 else
456 direction = DMA_TO_DEVICE;
457
458 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
459 direction);
460
461 dev_vdbg(&host->pdev->dev,
462 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
463 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
464 sg_len);
465
466 /* Enable the DMA interface */
467 temp = mci_readl(host, CTRL);
468 temp |= SDMMC_CTRL_DMA_ENABLE;
469 mci_writel(host, CTRL, temp);
470
471 /* Disable RX/TX IRQs, let DMA handle it */
472 temp = mci_readl(host, INTMASK);
473 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
474 mci_writel(host, INTMASK, temp);
475
476 host->dma_ops->start(host, sg_len);
477
478 return 0;
479 }
480
481 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
482 {
483 u32 temp;
484
485 data->error = -EINPROGRESS;
486
487 WARN_ON(host->data);
488 host->sg = NULL;
489 host->data = data;
490
491 if (dw_mci_submit_data_dma(host, data)) {
492 host->sg = data->sg;
493 host->pio_offset = 0;
494 if (data->flags & MMC_DATA_READ)
495 host->dir_status = DW_MCI_RECV_STATUS;
496 else
497 host->dir_status = DW_MCI_SEND_STATUS;
498
499 temp = mci_readl(host, INTMASK);
500 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
501 mci_writel(host, INTMASK, temp);
502
503 temp = mci_readl(host, CTRL);
504 temp &= ~SDMMC_CTRL_DMA_ENABLE;
505 mci_writel(host, CTRL, temp);
506 }
507 }
508
509 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
510 {
511 struct dw_mci *host = slot->host;
512 unsigned long timeout = jiffies + msecs_to_jiffies(500);
513 unsigned int cmd_status = 0;
514
515 mci_writel(host, CMDARG, arg);
516 wmb();
517 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
518
519 while (time_before(jiffies, timeout)) {
520 cmd_status = mci_readl(host, CMD);
521 if (!(cmd_status & SDMMC_CMD_START))
522 return;
523 }
524 dev_err(&slot->mmc->class_dev,
525 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
526 cmd, arg, cmd_status);
527 }
528
529 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
530 {
531 struct dw_mci *host = slot->host;
532 u32 div;
533
534 if (slot->clock != host->current_speed) {
535 if (host->bus_hz % slot->clock)
536 /*
537 * move the + 1 after the divide to prevent
538 * over-clocking the card.
539 */
540 div = ((host->bus_hz / slot->clock) >> 1) + 1;
541 else
542 div = (host->bus_hz / slot->clock) >> 1;
543
544 dev_info(&slot->mmc->class_dev,
545 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
546 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
547 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
548
549 /* disable clock */
550 mci_writel(host, CLKENA, 0);
551 mci_writel(host, CLKSRC, 0);
552
553 /* inform CIU */
554 mci_send_cmd(slot,
555 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
556
557 /* set clock to desired speed */
558 mci_writel(host, CLKDIV, div);
559
560 /* inform CIU */
561 mci_send_cmd(slot,
562 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
563
564 /* enable clock */
565 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
566 SDMMC_CLKEN_LOW_PWR);
567
568 /* inform CIU */
569 mci_send_cmd(slot,
570 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
571
572 host->current_speed = slot->clock;
573 }
574
575 /* Set the current slot bus width */
576 mci_writel(host, CTYPE, slot->ctype);
577 }
578
579 static void dw_mci_start_request(struct dw_mci *host,
580 struct dw_mci_slot *slot)
581 {
582 struct mmc_request *mrq;
583 struct mmc_command *cmd;
584 struct mmc_data *data;
585 u32 cmdflags;
586
587 mrq = slot->mrq;
588 if (host->pdata->select_slot)
589 host->pdata->select_slot(slot->id);
590
591 /* Slot specific timing and width adjustment */
592 dw_mci_setup_bus(slot);
593
594 host->cur_slot = slot;
595 host->mrq = mrq;
596
597 host->pending_events = 0;
598 host->completed_events = 0;
599 host->data_status = 0;
600
601 data = mrq->data;
602 if (data) {
603 dw_mci_set_timeout(host);
604 mci_writel(host, BYTCNT, data->blksz*data->blocks);
605 mci_writel(host, BLKSIZ, data->blksz);
606 }
607
608 cmd = mrq->cmd;
609 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
610
611 /* this is the first command, send the initialization clock */
612 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
613 cmdflags |= SDMMC_CMD_INIT;
614
615 if (data) {
616 dw_mci_submit_data(host, data);
617 wmb();
618 }
619
620 dw_mci_start_command(host, cmd, cmdflags);
621
622 if (mrq->stop)
623 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
624 }
625
626 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
627 struct mmc_request *mrq)
628 {
629 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
630 host->state);
631
632 spin_lock_bh(&host->lock);
633 slot->mrq = mrq;
634
635 if (host->state == STATE_IDLE) {
636 host->state = STATE_SENDING_CMD;
637 dw_mci_start_request(host, slot);
638 } else {
639 list_add_tail(&slot->queue_node, &host->queue);
640 }
641
642 spin_unlock_bh(&host->lock);
643 }
644
645 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
646 {
647 struct dw_mci_slot *slot = mmc_priv(mmc);
648 struct dw_mci *host = slot->host;
649
650 WARN_ON(slot->mrq);
651
652 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
653 mrq->cmd->error = -ENOMEDIUM;
654 mmc_request_done(mmc, mrq);
655 return;
656 }
657
658 /* We don't support multiple blocks of weird lengths. */
659 dw_mci_queue_request(host, slot, mrq);
660 }
661
662 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
663 {
664 struct dw_mci_slot *slot = mmc_priv(mmc);
665 u32 regs;
666
667 /* set default 1 bit mode */
668 slot->ctype = SDMMC_CTYPE_1BIT;
669
670 switch (ios->bus_width) {
671 case MMC_BUS_WIDTH_1:
672 slot->ctype = SDMMC_CTYPE_1BIT;
673 break;
674 case MMC_BUS_WIDTH_4:
675 slot->ctype = SDMMC_CTYPE_4BIT;
676 break;
677 case MMC_BUS_WIDTH_8:
678 slot->ctype = SDMMC_CTYPE_8BIT;
679 break;
680 }
681
682 /* DDR mode set */
683 if (ios->ddr) {
684 regs = mci_readl(slot->host, UHS_REG);
685 regs |= (0x1 << slot->id) << 16;
686 mci_writel(slot->host, UHS_REG, regs);
687 }
688
689 if (ios->clock) {
690 /*
691 * Use mirror of ios->clock to prevent race with mmc
692 * core ios update when finding the minimum.
693 */
694 slot->clock = ios->clock;
695 }
696
697 switch (ios->power_mode) {
698 case MMC_POWER_UP:
699 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
700 break;
701 default:
702 break;
703 }
704 }
705
706 static int dw_mci_get_ro(struct mmc_host *mmc)
707 {
708 int read_only;
709 struct dw_mci_slot *slot = mmc_priv(mmc);
710 struct dw_mci_board *brd = slot->host->pdata;
711
712 /* Use platform get_ro function, else try on board write protect */
713 if (brd->get_ro)
714 read_only = brd->get_ro(slot->id);
715 else
716 read_only =
717 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
718
719 dev_dbg(&mmc->class_dev, "card is %s\n",
720 read_only ? "read-only" : "read-write");
721
722 return read_only;
723 }
724
725 static int dw_mci_get_cd(struct mmc_host *mmc)
726 {
727 int present;
728 struct dw_mci_slot *slot = mmc_priv(mmc);
729 struct dw_mci_board *brd = slot->host->pdata;
730
731 /* Use platform get_cd function, else try onboard card detect */
732 if (brd->get_cd)
733 present = !brd->get_cd(slot->id);
734 else
735 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
736 == 0 ? 1 : 0;
737
738 if (present)
739 dev_dbg(&mmc->class_dev, "card is present\n");
740 else
741 dev_dbg(&mmc->class_dev, "card is not present\n");
742
743 return present;
744 }
745
746 static const struct mmc_host_ops dw_mci_ops = {
747 .request = dw_mci_request,
748 .set_ios = dw_mci_set_ios,
749 .get_ro = dw_mci_get_ro,
750 .get_cd = dw_mci_get_cd,
751 };
752
753 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
754 __releases(&host->lock)
755 __acquires(&host->lock)
756 {
757 struct dw_mci_slot *slot;
758 struct mmc_host *prev_mmc = host->cur_slot->mmc;
759
760 WARN_ON(host->cmd || host->data);
761
762 host->cur_slot->mrq = NULL;
763 host->mrq = NULL;
764 if (!list_empty(&host->queue)) {
765 slot = list_entry(host->queue.next,
766 struct dw_mci_slot, queue_node);
767 list_del(&slot->queue_node);
768 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
769 mmc_hostname(slot->mmc));
770 host->state = STATE_SENDING_CMD;
771 dw_mci_start_request(host, slot);
772 } else {
773 dev_vdbg(&host->pdev->dev, "list empty\n");
774 host->state = STATE_IDLE;
775 }
776
777 spin_unlock(&host->lock);
778 mmc_request_done(prev_mmc, mrq);
779 spin_lock(&host->lock);
780 }
781
782 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
783 {
784 u32 status = host->cmd_status;
785
786 host->cmd_status = 0;
787
788 /* Read the response from the card (up to 16 bytes) */
789 if (cmd->flags & MMC_RSP_PRESENT) {
790 if (cmd->flags & MMC_RSP_136) {
791 cmd->resp[3] = mci_readl(host, RESP0);
792 cmd->resp[2] = mci_readl(host, RESP1);
793 cmd->resp[1] = mci_readl(host, RESP2);
794 cmd->resp[0] = mci_readl(host, RESP3);
795 } else {
796 cmd->resp[0] = mci_readl(host, RESP0);
797 cmd->resp[1] = 0;
798 cmd->resp[2] = 0;
799 cmd->resp[3] = 0;
800 }
801 }
802
803 if (status & SDMMC_INT_RTO)
804 cmd->error = -ETIMEDOUT;
805 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
806 cmd->error = -EILSEQ;
807 else if (status & SDMMC_INT_RESP_ERR)
808 cmd->error = -EIO;
809 else
810 cmd->error = 0;
811
812 if (cmd->error) {
813 /* newer ip versions need a delay between retries */
814 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
815 mdelay(20);
816
817 if (cmd->data) {
818 host->data = NULL;
819 dw_mci_stop_dma(host);
820 }
821 }
822 }
823
824 static void dw_mci_tasklet_func(unsigned long priv)
825 {
826 struct dw_mci *host = (struct dw_mci *)priv;
827 struct mmc_data *data;
828 struct mmc_command *cmd;
829 enum dw_mci_state state;
830 enum dw_mci_state prev_state;
831 u32 status;
832
833 spin_lock(&host->lock);
834
835 state = host->state;
836 data = host->data;
837
838 do {
839 prev_state = state;
840
841 switch (state) {
842 case STATE_IDLE:
843 break;
844
845 case STATE_SENDING_CMD:
846 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
847 &host->pending_events))
848 break;
849
850 cmd = host->cmd;
851 host->cmd = NULL;
852 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
853 dw_mci_command_complete(host, host->mrq->cmd);
854 if (!host->mrq->data || cmd->error) {
855 dw_mci_request_end(host, host->mrq);
856 goto unlock;
857 }
858
859 prev_state = state = STATE_SENDING_DATA;
860 /* fall through */
861
862 case STATE_SENDING_DATA:
863 if (test_and_clear_bit(EVENT_DATA_ERROR,
864 &host->pending_events)) {
865 dw_mci_stop_dma(host);
866 if (data->stop)
867 send_stop_cmd(host, data);
868 state = STATE_DATA_ERROR;
869 break;
870 }
871
872 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
873 &host->pending_events))
874 break;
875
876 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
877 prev_state = state = STATE_DATA_BUSY;
878 /* fall through */
879
880 case STATE_DATA_BUSY:
881 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
882 &host->pending_events))
883 break;
884
885 host->data = NULL;
886 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
887 status = host->data_status;
888
889 if (status & DW_MCI_DATA_ERROR_FLAGS) {
890 if (status & SDMMC_INT_DTO) {
891 dev_err(&host->pdev->dev,
892 "data timeout error\n");
893 data->error = -ETIMEDOUT;
894 } else if (status & SDMMC_INT_DCRC) {
895 dev_err(&host->pdev->dev,
896 "data CRC error\n");
897 data->error = -EILSEQ;
898 } else {
899 dev_err(&host->pdev->dev,
900 "data FIFO error "
901 "(status=%08x)\n",
902 status);
903 data->error = -EIO;
904 }
905 } else {
906 data->bytes_xfered = data->blocks * data->blksz;
907 data->error = 0;
908 }
909
910 if (!data->stop) {
911 dw_mci_request_end(host, host->mrq);
912 goto unlock;
913 }
914
915 prev_state = state = STATE_SENDING_STOP;
916 if (!data->error)
917 send_stop_cmd(host, data);
918 /* fall through */
919
920 case STATE_SENDING_STOP:
921 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
922 &host->pending_events))
923 break;
924
925 host->cmd = NULL;
926 dw_mci_command_complete(host, host->mrq->stop);
927 dw_mci_request_end(host, host->mrq);
928 goto unlock;
929
930 case STATE_DATA_ERROR:
931 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
932 &host->pending_events))
933 break;
934
935 state = STATE_DATA_BUSY;
936 break;
937 }
938 } while (state != prev_state);
939
940 host->state = state;
941 unlock:
942 spin_unlock(&host->lock);
943
944 }
945
946 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
947 {
948 u16 *pdata = (u16 *)buf;
949
950 WARN_ON(cnt % 2 != 0);
951
952 cnt = cnt >> 1;
953 while (cnt > 0) {
954 mci_writew(host, DATA, *pdata++);
955 cnt--;
956 }
957 }
958
959 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
960 {
961 u16 *pdata = (u16 *)buf;
962
963 WARN_ON(cnt % 2 != 0);
964
965 cnt = cnt >> 1;
966 while (cnt > 0) {
967 *pdata++ = mci_readw(host, DATA);
968 cnt--;
969 }
970 }
971
972 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
973 {
974 u32 *pdata = (u32 *)buf;
975
976 WARN_ON(cnt % 4 != 0);
977 WARN_ON((unsigned long)pdata & 0x3);
978
979 cnt = cnt >> 2;
980 while (cnt > 0) {
981 mci_writel(host, DATA, *pdata++);
982 cnt--;
983 }
984 }
985
986 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
987 {
988 u32 *pdata = (u32 *)buf;
989
990 WARN_ON(cnt % 4 != 0);
991 WARN_ON((unsigned long)pdata & 0x3);
992
993 cnt = cnt >> 2;
994 while (cnt > 0) {
995 *pdata++ = mci_readl(host, DATA);
996 cnt--;
997 }
998 }
999
1000 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1001 {
1002 u64 *pdata = (u64 *)buf;
1003
1004 WARN_ON(cnt % 8 != 0);
1005
1006 cnt = cnt >> 3;
1007 while (cnt > 0) {
1008 mci_writeq(host, DATA, *pdata++);
1009 cnt--;
1010 }
1011 }
1012
1013 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1014 {
1015 u64 *pdata = (u64 *)buf;
1016
1017 WARN_ON(cnt % 8 != 0);
1018
1019 cnt = cnt >> 3;
1020 while (cnt > 0) {
1021 *pdata++ = mci_readq(host, DATA);
1022 cnt--;
1023 }
1024 }
1025
1026 static void dw_mci_read_data_pio(struct dw_mci *host)
1027 {
1028 struct scatterlist *sg = host->sg;
1029 void *buf = sg_virt(sg);
1030 unsigned int offset = host->pio_offset;
1031 struct mmc_data *data = host->data;
1032 int shift = host->data_shift;
1033 u32 status;
1034 unsigned int nbytes = 0, len;
1035
1036 do {
1037 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
1038 if (offset + len <= sg->length) {
1039 host->pull_data(host, (void *)(buf + offset), len);
1040
1041 offset += len;
1042 nbytes += len;
1043
1044 if (offset == sg->length) {
1045 flush_dcache_page(sg_page(sg));
1046 host->sg = sg = sg_next(sg);
1047 if (!sg)
1048 goto done;
1049
1050 offset = 0;
1051 buf = sg_virt(sg);
1052 }
1053 } else {
1054 unsigned int remaining = sg->length - offset;
1055 host->pull_data(host, (void *)(buf + offset),
1056 remaining);
1057 nbytes += remaining;
1058
1059 flush_dcache_page(sg_page(sg));
1060 host->sg = sg = sg_next(sg);
1061 if (!sg)
1062 goto done;
1063
1064 offset = len - remaining;
1065 buf = sg_virt(sg);
1066 host->pull_data(host, buf, offset);
1067 nbytes += offset;
1068 }
1069
1070 status = mci_readl(host, MINTSTS);
1071 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1072 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1073 host->data_status = status;
1074 data->bytes_xfered += nbytes;
1075 smp_wmb();
1076
1077 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1078
1079 tasklet_schedule(&host->tasklet);
1080 return;
1081 }
1082 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1083 len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1084 host->pio_offset = offset;
1085 data->bytes_xfered += nbytes;
1086 return;
1087
1088 done:
1089 data->bytes_xfered += nbytes;
1090 smp_wmb();
1091 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1092 }
1093
1094 static void dw_mci_write_data_pio(struct dw_mci *host)
1095 {
1096 struct scatterlist *sg = host->sg;
1097 void *buf = sg_virt(sg);
1098 unsigned int offset = host->pio_offset;
1099 struct mmc_data *data = host->data;
1100 int shift = host->data_shift;
1101 u32 status;
1102 unsigned int nbytes = 0, len;
1103
1104 do {
1105 len = SDMMC_FIFO_SZ -
1106 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1107 if (offset + len <= sg->length) {
1108 host->push_data(host, (void *)(buf + offset), len);
1109
1110 offset += len;
1111 nbytes += len;
1112 if (offset == sg->length) {
1113 host->sg = sg = sg_next(sg);
1114 if (!sg)
1115 goto done;
1116
1117 offset = 0;
1118 buf = sg_virt(sg);
1119 }
1120 } else {
1121 unsigned int remaining = sg->length - offset;
1122
1123 host->push_data(host, (void *)(buf + offset),
1124 remaining);
1125 nbytes += remaining;
1126
1127 host->sg = sg = sg_next(sg);
1128 if (!sg)
1129 goto done;
1130
1131 offset = len - remaining;
1132 buf = sg_virt(sg);
1133 host->push_data(host, (void *)buf, offset);
1134 nbytes += offset;
1135 }
1136
1137 status = mci_readl(host, MINTSTS);
1138 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1139 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1140 host->data_status = status;
1141 data->bytes_xfered += nbytes;
1142
1143 smp_wmb();
1144
1145 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1146
1147 tasklet_schedule(&host->tasklet);
1148 return;
1149 }
1150 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1151
1152 host->pio_offset = offset;
1153 data->bytes_xfered += nbytes;
1154
1155 return;
1156
1157 done:
1158 data->bytes_xfered += nbytes;
1159 smp_wmb();
1160 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1161 }
1162
1163 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1164 {
1165 if (!host->cmd_status)
1166 host->cmd_status = status;
1167
1168 smp_wmb();
1169
1170 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1171 tasklet_schedule(&host->tasklet);
1172 }
1173
1174 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1175 {
1176 struct dw_mci *host = dev_id;
1177 u32 status, pending;
1178 unsigned int pass_count = 0;
1179
1180 do {
1181 status = mci_readl(host, RINTSTS);
1182 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1183
1184 /*
1185 * DTO fix - version 2.10a and below, and only if internal DMA
1186 * is configured.
1187 */
1188 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1189 if (!pending &&
1190 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1191 pending |= SDMMC_INT_DATA_OVER;
1192 }
1193
1194 if (!pending)
1195 break;
1196
1197 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1198 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1199 host->cmd_status = status;
1200 smp_wmb();
1201 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1202 tasklet_schedule(&host->tasklet);
1203 }
1204
1205 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1206 /* if there is an error report DATA_ERROR */
1207 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1208 host->data_status = status;
1209 smp_wmb();
1210 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1211 tasklet_schedule(&host->tasklet);
1212 }
1213
1214 if (pending & SDMMC_INT_DATA_OVER) {
1215 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1216 if (!host->data_status)
1217 host->data_status = status;
1218 smp_wmb();
1219 if (host->dir_status == DW_MCI_RECV_STATUS) {
1220 if (host->sg != NULL)
1221 dw_mci_read_data_pio(host);
1222 }
1223 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1224 tasklet_schedule(&host->tasklet);
1225 }
1226
1227 if (pending & SDMMC_INT_RXDR) {
1228 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1229 if (host->sg)
1230 dw_mci_read_data_pio(host);
1231 }
1232
1233 if (pending & SDMMC_INT_TXDR) {
1234 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1235 if (host->sg)
1236 dw_mci_write_data_pio(host);
1237 }
1238
1239 if (pending & SDMMC_INT_CMD_DONE) {
1240 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1241 dw_mci_cmd_interrupt(host, status);
1242 }
1243
1244 if (pending & SDMMC_INT_CD) {
1245 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1246 tasklet_schedule(&host->card_tasklet);
1247 }
1248
1249 } while (pass_count++ < 5);
1250
1251 #ifdef CONFIG_MMC_DW_IDMAC
1252 /* Handle DMA interrupts */
1253 pending = mci_readl(host, IDSTS);
1254 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1255 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1256 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1257 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1258 host->dma_ops->complete(host);
1259 }
1260 #endif
1261
1262 return IRQ_HANDLED;
1263 }
1264
1265 static void dw_mci_tasklet_card(unsigned long data)
1266 {
1267 struct dw_mci *host = (struct dw_mci *)data;
1268 int i;
1269
1270 for (i = 0; i < host->num_slots; i++) {
1271 struct dw_mci_slot *slot = host->slot[i];
1272 struct mmc_host *mmc = slot->mmc;
1273 struct mmc_request *mrq;
1274 int present;
1275 u32 ctrl;
1276
1277 present = dw_mci_get_cd(mmc);
1278 while (present != slot->last_detect_state) {
1279 spin_lock(&host->lock);
1280
1281 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1282 present ? "inserted" : "removed");
1283
1284 /* Card change detected */
1285 slot->last_detect_state = present;
1286
1287 /* Power up slot */
1288 if (present != 0) {
1289 if (host->pdata->setpower)
1290 host->pdata->setpower(slot->id,
1291 mmc->ocr_avail);
1292
1293 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1294 }
1295
1296 /* Clean up queue if present */
1297 mrq = slot->mrq;
1298 if (mrq) {
1299 if (mrq == host->mrq) {
1300 host->data = NULL;
1301 host->cmd = NULL;
1302
1303 switch (host->state) {
1304 case STATE_IDLE:
1305 break;
1306 case STATE_SENDING_CMD:
1307 mrq->cmd->error = -ENOMEDIUM;
1308 if (!mrq->data)
1309 break;
1310 /* fall through */
1311 case STATE_SENDING_DATA:
1312 mrq->data->error = -ENOMEDIUM;
1313 dw_mci_stop_dma(host);
1314 break;
1315 case STATE_DATA_BUSY:
1316 case STATE_DATA_ERROR:
1317 if (mrq->data->error == -EINPROGRESS)
1318 mrq->data->error = -ENOMEDIUM;
1319 if (!mrq->stop)
1320 break;
1321 /* fall through */
1322 case STATE_SENDING_STOP:
1323 mrq->stop->error = -ENOMEDIUM;
1324 break;
1325 }
1326
1327 dw_mci_request_end(host, mrq);
1328 } else {
1329 list_del(&slot->queue_node);
1330 mrq->cmd->error = -ENOMEDIUM;
1331 if (mrq->data)
1332 mrq->data->error = -ENOMEDIUM;
1333 if (mrq->stop)
1334 mrq->stop->error = -ENOMEDIUM;
1335
1336 spin_unlock(&host->lock);
1337 mmc_request_done(slot->mmc, mrq);
1338 spin_lock(&host->lock);
1339 }
1340 }
1341
1342 /* Power down slot */
1343 if (present == 0) {
1344 if (host->pdata->setpower)
1345 host->pdata->setpower(slot->id, 0);
1346 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1347
1348 /*
1349 * Clear down the FIFO - doing so generates a
1350 * block interrupt, hence setting the
1351 * scatter-gather pointer to NULL.
1352 */
1353 host->sg = NULL;
1354
1355 ctrl = mci_readl(host, CTRL);
1356 ctrl |= SDMMC_CTRL_FIFO_RESET;
1357 mci_writel(host, CTRL, ctrl);
1358
1359 #ifdef CONFIG_MMC_DW_IDMAC
1360 ctrl = mci_readl(host, BMOD);
1361 ctrl |= 0x01; /* Software reset of DMA */
1362 mci_writel(host, BMOD, ctrl);
1363 #endif
1364
1365 }
1366
1367 spin_unlock(&host->lock);
1368 present = dw_mci_get_cd(mmc);
1369 }
1370
1371 mmc_detect_change(slot->mmc,
1372 msecs_to_jiffies(host->pdata->detect_delay_ms));
1373 }
1374 }
1375
1376 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1377 {
1378 struct mmc_host *mmc;
1379 struct dw_mci_slot *slot;
1380
1381 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1382 if (!mmc)
1383 return -ENOMEM;
1384
1385 slot = mmc_priv(mmc);
1386 slot->id = id;
1387 slot->mmc = mmc;
1388 slot->host = host;
1389
1390 mmc->ops = &dw_mci_ops;
1391 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1392 mmc->f_max = host->bus_hz;
1393
1394 if (host->pdata->get_ocr)
1395 mmc->ocr_avail = host->pdata->get_ocr(id);
1396 else
1397 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1398
1399 /*
1400 * Start with slot power disabled, it will be enabled when a card
1401 * is detected.
1402 */
1403 if (host->pdata->setpower)
1404 host->pdata->setpower(id, 0);
1405
1406 mmc->caps = 0;
1407 if (host->pdata->get_bus_wd)
1408 if (host->pdata->get_bus_wd(slot->id) >= 4)
1409 mmc->caps |= MMC_CAP_4_BIT_DATA;
1410
1411 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1412 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1413
1414 #ifdef CONFIG_MMC_DW_IDMAC
1415 mmc->max_segs = host->ring_size;
1416 mmc->max_blk_size = 65536;
1417 mmc->max_blk_count = host->ring_size;
1418 mmc->max_seg_size = 0x1000;
1419 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1420 #else
1421 if (host->pdata->blk_settings) {
1422 mmc->max_segs = host->pdata->blk_settings->max_segs;
1423 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1424 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1425 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1426 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1427 } else {
1428 /* Useful defaults if platform data is unset. */
1429 mmc->max_segs = 64;
1430 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1431 mmc->max_blk_count = 512;
1432 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1433 mmc->max_seg_size = mmc->max_req_size;
1434 }
1435 #endif /* CONFIG_MMC_DW_IDMAC */
1436
1437 if (dw_mci_get_cd(mmc))
1438 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1439 else
1440 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1441
1442 host->slot[id] = slot;
1443 mmc_add_host(mmc);
1444
1445 #if defined(CONFIG_DEBUG_FS)
1446 dw_mci_init_debugfs(slot);
1447 #endif
1448
1449 /* Card initially undetected */
1450 slot->last_detect_state = 0;
1451
1452 /*
1453 * Card may have been plugged in prior to boot so we
1454 * need to run the detect tasklet
1455 */
1456 tasklet_schedule(&host->card_tasklet);
1457
1458 return 0;
1459 }
1460
1461 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1462 {
1463 /* Shutdown detect IRQ */
1464 if (slot->host->pdata->exit)
1465 slot->host->pdata->exit(id);
1466
1467 /* Debugfs stuff is cleaned up by mmc core */
1468 mmc_remove_host(slot->mmc);
1469 slot->host->slot[id] = NULL;
1470 mmc_free_host(slot->mmc);
1471 }
1472
1473 static void dw_mci_init_dma(struct dw_mci *host)
1474 {
1475 /* Alloc memory for sg translation */
1476 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1477 &host->sg_dma, GFP_KERNEL);
1478 if (!host->sg_cpu) {
1479 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1480 __func__);
1481 goto no_dma;
1482 }
1483
1484 /* Determine which DMA interface to use */
1485 #ifdef CONFIG_MMC_DW_IDMAC
1486 host->dma_ops = &dw_mci_idmac_ops;
1487 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1488 #endif
1489
1490 if (!host->dma_ops)
1491 goto no_dma;
1492
1493 if (host->dma_ops->init) {
1494 if (host->dma_ops->init(host)) {
1495 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1496 "DMA Controller.\n", __func__);
1497 goto no_dma;
1498 }
1499 } else {
1500 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1501 goto no_dma;
1502 }
1503
1504 host->use_dma = 1;
1505 return;
1506
1507 no_dma:
1508 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1509 host->use_dma = 0;
1510 return;
1511 }
1512
1513 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1514 {
1515 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1516 unsigned int ctrl;
1517
1518 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1519 SDMMC_CTRL_DMA_RESET));
1520
1521 /* wait till resets clear */
1522 do {
1523 ctrl = mci_readl(host, CTRL);
1524 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1525 SDMMC_CTRL_DMA_RESET)))
1526 return true;
1527 } while (time_before(jiffies, timeout));
1528
1529 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1530
1531 return false;
1532 }
1533
1534 static int dw_mci_probe(struct platform_device *pdev)
1535 {
1536 struct dw_mci *host;
1537 struct resource *regs;
1538 struct dw_mci_board *pdata;
1539 int irq, ret, i, width;
1540 u32 fifo_size;
1541
1542 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1543 if (!regs)
1544 return -ENXIO;
1545
1546 irq = platform_get_irq(pdev, 0);
1547 if (irq < 0)
1548 return irq;
1549
1550 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1551 if (!host)
1552 return -ENOMEM;
1553
1554 host->pdev = pdev;
1555 host->pdata = pdata = pdev->dev.platform_data;
1556 if (!pdata || !pdata->init) {
1557 dev_err(&pdev->dev,
1558 "Platform data must supply init function\n");
1559 ret = -ENODEV;
1560 goto err_freehost;
1561 }
1562
1563 if (!pdata->select_slot && pdata->num_slots > 1) {
1564 dev_err(&pdev->dev,
1565 "Platform data must supply select_slot function\n");
1566 ret = -ENODEV;
1567 goto err_freehost;
1568 }
1569
1570 if (!pdata->bus_hz) {
1571 dev_err(&pdev->dev,
1572 "Platform data must supply bus speed\n");
1573 ret = -ENODEV;
1574 goto err_freehost;
1575 }
1576
1577 host->bus_hz = pdata->bus_hz;
1578 host->quirks = pdata->quirks;
1579
1580 spin_lock_init(&host->lock);
1581 INIT_LIST_HEAD(&host->queue);
1582
1583 ret = -ENOMEM;
1584 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1585 if (!host->regs)
1586 goto err_freehost;
1587
1588 host->dma_ops = pdata->dma_ops;
1589 dw_mci_init_dma(host);
1590
1591 /*
1592 * Get the host data width - this assumes that HCON has been set with
1593 * the correct values.
1594 */
1595 i = (mci_readl(host, HCON) >> 7) & 0x7;
1596 if (!i) {
1597 host->push_data = dw_mci_push_data16;
1598 host->pull_data = dw_mci_pull_data16;
1599 width = 16;
1600 host->data_shift = 1;
1601 } else if (i == 2) {
1602 host->push_data = dw_mci_push_data64;
1603 host->pull_data = dw_mci_pull_data64;
1604 width = 64;
1605 host->data_shift = 3;
1606 } else {
1607 /* Check for a reserved value, and warn if it is */
1608 WARN((i != 1),
1609 "HCON reports a reserved host data width!\n"
1610 "Defaulting to 32-bit access.\n");
1611 host->push_data = dw_mci_push_data32;
1612 host->pull_data = dw_mci_pull_data32;
1613 width = 32;
1614 host->data_shift = 2;
1615 }
1616
1617 /* Reset all blocks */
1618 if (!mci_wait_reset(&pdev->dev, host)) {
1619 ret = -ENODEV;
1620 goto err_dmaunmap;
1621 }
1622
1623 /* Clear the interrupts for the host controller */
1624 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1625 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1626
1627 /* Put in max timeout */
1628 mci_writel(host, TMOUT, 0xFFFFFFFF);
1629
1630 /*
1631 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1632 * Tx Mark = fifo_size / 2 DMA Size = 8
1633 */
1634 fifo_size = mci_readl(host, FIFOTH);
1635 fifo_size = (fifo_size >> 16) & 0x7ff;
1636 mci_writel(host, FIFOTH, ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1637 ((fifo_size/2) << 0)));
1638
1639 /* disable clock to CIU */
1640 mci_writel(host, CLKENA, 0);
1641 mci_writel(host, CLKSRC, 0);
1642
1643 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1644 tasklet_init(&host->card_tasklet,
1645 dw_mci_tasklet_card, (unsigned long)host);
1646
1647 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1648 if (ret)
1649 goto err_dmaunmap;
1650
1651 platform_set_drvdata(pdev, host);
1652
1653 if (host->pdata->num_slots)
1654 host->num_slots = host->pdata->num_slots;
1655 else
1656 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1657
1658 /* We need at least one slot to succeed */
1659 for (i = 0; i < host->num_slots; i++) {
1660 ret = dw_mci_init_slot(host, i);
1661 if (ret) {
1662 ret = -ENODEV;
1663 goto err_init_slot;
1664 }
1665 }
1666
1667 /*
1668 * Enable interrupts for command done, data over, data empty, card det,
1669 * receive ready and error such as transmit, receive timeout, crc error
1670 */
1671 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1672 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1673 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1674 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1675 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1676
1677 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1678 "%d bit host data width\n", irq, width);
1679 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1680 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1681
1682 return 0;
1683
1684 err_init_slot:
1685 /* De-init any initialized slots */
1686 while (i > 0) {
1687 if (host->slot[i])
1688 dw_mci_cleanup_slot(host->slot[i], i);
1689 i--;
1690 }
1691 free_irq(irq, host);
1692
1693 err_dmaunmap:
1694 if (host->use_dma && host->dma_ops->exit)
1695 host->dma_ops->exit(host);
1696 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1697 host->sg_cpu, host->sg_dma);
1698 iounmap(host->regs);
1699
1700 err_freehost:
1701 kfree(host);
1702 return ret;
1703 }
1704
1705 static int __exit dw_mci_remove(struct platform_device *pdev)
1706 {
1707 struct dw_mci *host = platform_get_drvdata(pdev);
1708 int i;
1709
1710 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1711 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1712
1713 platform_set_drvdata(pdev, NULL);
1714
1715 for (i = 0; i < host->num_slots; i++) {
1716 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1717 if (host->slot[i])
1718 dw_mci_cleanup_slot(host->slot[i], i);
1719 }
1720
1721 /* disable clock to CIU */
1722 mci_writel(host, CLKENA, 0);
1723 mci_writel(host, CLKSRC, 0);
1724
1725 free_irq(platform_get_irq(pdev, 0), host);
1726 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1727
1728 if (host->use_dma && host->dma_ops->exit)
1729 host->dma_ops->exit(host);
1730
1731 iounmap(host->regs);
1732
1733 kfree(host);
1734 return 0;
1735 }
1736
1737 #ifdef CONFIG_PM
1738 /*
1739 * TODO: we should probably disable the clock to the card in the suspend path.
1740 */
1741 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1742 {
1743 int i, ret;
1744 struct dw_mci *host = platform_get_drvdata(pdev);
1745
1746 for (i = 0; i < host->num_slots; i++) {
1747 struct dw_mci_slot *slot = host->slot[i];
1748 if (!slot)
1749 continue;
1750 ret = mmc_suspend_host(slot->mmc);
1751 if (ret < 0) {
1752 while (--i >= 0) {
1753 slot = host->slot[i];
1754 if (slot)
1755 mmc_resume_host(host->slot[i]->mmc);
1756 }
1757 return ret;
1758 }
1759 }
1760
1761 return 0;
1762 }
1763
1764 static int dw_mci_resume(struct platform_device *pdev)
1765 {
1766 int i, ret;
1767 struct dw_mci *host = platform_get_drvdata(pdev);
1768
1769 for (i = 0; i < host->num_slots; i++) {
1770 struct dw_mci_slot *slot = host->slot[i];
1771 if (!slot)
1772 continue;
1773 ret = mmc_resume_host(host->slot[i]->mmc);
1774 if (ret < 0)
1775 return ret;
1776 }
1777
1778 return 0;
1779 }
1780 #else
1781 #define dw_mci_suspend NULL
1782 #define dw_mci_resume NULL
1783 #endif /* CONFIG_PM */
1784
1785 static struct platform_driver dw_mci_driver = {
1786 .remove = __exit_p(dw_mci_remove),
1787 .suspend = dw_mci_suspend,
1788 .resume = dw_mci_resume,
1789 .driver = {
1790 .name = "dw_mmc",
1791 },
1792 };
1793
1794 static int __init dw_mci_init(void)
1795 {
1796 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1797 }
1798
1799 static void __exit dw_mci_exit(void)
1800 {
1801 platform_driver_unregister(&dw_mci_driver);
1802 }
1803
1804 module_init(dw_mci_init);
1805 module_exit(dw_mci_exit);
1806
1807 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1808 MODULE_AUTHOR("NXP Semiconductor VietNam");
1809 MODULE_AUTHOR("Imagination Technologies Ltd");
1810 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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