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3f070d9f4086f2fe7ec0c2727de16a469575f3df
[deliverable/linux.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/of.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #include "dw_mmc.h"
43
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
55
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
59 #ifdef CONFIG_MMC_DW_IDMAC
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 struct idmac_desc_64addr {
66 u32 des0; /* Control Descriptor */
67
68 u32 des1; /* Reserved */
69
70 u32 des2; /*Buffer sizes */
71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
72 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
73 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
74
75 u32 des3; /* Reserved */
76
77 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
78 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
79
80 u32 des6; /* Lower 32-bits of Next Descriptor Address */
81 u32 des7; /* Upper 32-bits of Next Descriptor Address */
82 };
83
84 struct idmac_desc {
85 __le32 des0; /* Control Descriptor */
86 #define IDMAC_DES0_DIC BIT(1)
87 #define IDMAC_DES0_LD BIT(2)
88 #define IDMAC_DES0_FD BIT(3)
89 #define IDMAC_DES0_CH BIT(4)
90 #define IDMAC_DES0_ER BIT(5)
91 #define IDMAC_DES0_CES BIT(30)
92 #define IDMAC_DES0_OWN BIT(31)
93
94 __le32 des1; /* Buffer sizes */
95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
96 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
97
98 __le32 des2; /* buffer 1 physical address */
99
100 __le32 des3; /* buffer 2 physical address */
101 };
102
103 /* Each descriptor can transfer up to 4KB of data in chained mode */
104 #define DW_MCI_DESC_DATA_LENGTH 0x1000
105 #endif /* CONFIG_MMC_DW_IDMAC */
106
107 static bool dw_mci_reset(struct dw_mci *host);
108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
109 static int dw_mci_card_busy(struct mmc_host *mmc);
110
111 #if defined(CONFIG_DEBUG_FS)
112 static int dw_mci_req_show(struct seq_file *s, void *v)
113 {
114 struct dw_mci_slot *slot = s->private;
115 struct mmc_request *mrq;
116 struct mmc_command *cmd;
117 struct mmc_command *stop;
118 struct mmc_data *data;
119
120 /* Make sure we get a consistent snapshot */
121 spin_lock_bh(&slot->host->lock);
122 mrq = slot->mrq;
123
124 if (mrq) {
125 cmd = mrq->cmd;
126 data = mrq->data;
127 stop = mrq->stop;
128
129 if (cmd)
130 seq_printf(s,
131 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
132 cmd->opcode, cmd->arg, cmd->flags,
133 cmd->resp[0], cmd->resp[1], cmd->resp[2],
134 cmd->resp[2], cmd->error);
135 if (data)
136 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
137 data->bytes_xfered, data->blocks,
138 data->blksz, data->flags, data->error);
139 if (stop)
140 seq_printf(s,
141 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
142 stop->opcode, stop->arg, stop->flags,
143 stop->resp[0], stop->resp[1], stop->resp[2],
144 stop->resp[2], stop->error);
145 }
146
147 spin_unlock_bh(&slot->host->lock);
148
149 return 0;
150 }
151
152 static int dw_mci_req_open(struct inode *inode, struct file *file)
153 {
154 return single_open(file, dw_mci_req_show, inode->i_private);
155 }
156
157 static const struct file_operations dw_mci_req_fops = {
158 .owner = THIS_MODULE,
159 .open = dw_mci_req_open,
160 .read = seq_read,
161 .llseek = seq_lseek,
162 .release = single_release,
163 };
164
165 static int dw_mci_regs_show(struct seq_file *s, void *v)
166 {
167 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
168 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
169 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
170 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
171 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
172 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
173
174 return 0;
175 }
176
177 static int dw_mci_regs_open(struct inode *inode, struct file *file)
178 {
179 return single_open(file, dw_mci_regs_show, inode->i_private);
180 }
181
182 static const struct file_operations dw_mci_regs_fops = {
183 .owner = THIS_MODULE,
184 .open = dw_mci_regs_open,
185 .read = seq_read,
186 .llseek = seq_lseek,
187 .release = single_release,
188 };
189
190 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
191 {
192 struct mmc_host *mmc = slot->mmc;
193 struct dw_mci *host = slot->host;
194 struct dentry *root;
195 struct dentry *node;
196
197 root = mmc->debugfs_root;
198 if (!root)
199 return;
200
201 node = debugfs_create_file("regs", S_IRUSR, root, host,
202 &dw_mci_regs_fops);
203 if (!node)
204 goto err;
205
206 node = debugfs_create_file("req", S_IRUSR, root, slot,
207 &dw_mci_req_fops);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
212 if (!node)
213 goto err;
214
215 node = debugfs_create_x32("pending_events", S_IRUSR, root,
216 (u32 *)&host->pending_events);
217 if (!node)
218 goto err;
219
220 node = debugfs_create_x32("completed_events", S_IRUSR, root,
221 (u32 *)&host->completed_events);
222 if (!node)
223 goto err;
224
225 return;
226
227 err:
228 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
229 }
230 #endif /* defined(CONFIG_DEBUG_FS) */
231
232 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
233
234 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
235 {
236 struct mmc_data *data;
237 struct dw_mci_slot *slot = mmc_priv(mmc);
238 struct dw_mci *host = slot->host;
239 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
240 u32 cmdr;
241
242 cmd->error = -EINPROGRESS;
243 cmdr = cmd->opcode;
244
245 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
246 cmd->opcode == MMC_GO_IDLE_STATE ||
247 cmd->opcode == MMC_GO_INACTIVE_STATE ||
248 (cmd->opcode == SD_IO_RW_DIRECT &&
249 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
250 cmdr |= SDMMC_CMD_STOP;
251 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
252 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
253
254 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
255 u32 clk_en_a;
256
257 /* Special bit makes CMD11 not die */
258 cmdr |= SDMMC_CMD_VOLT_SWITCH;
259
260 /* Change state to continue to handle CMD11 weirdness */
261 WARN_ON(slot->host->state != STATE_SENDING_CMD);
262 slot->host->state = STATE_SENDING_CMD11;
263
264 /*
265 * We need to disable low power mode (automatic clock stop)
266 * while doing voltage switch so we don't confuse the card,
267 * since stopping the clock is a specific part of the UHS
268 * voltage change dance.
269 *
270 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
271 * unconditionally turned back on in dw_mci_setup_bus() if it's
272 * ever called with a non-zero clock. That shouldn't happen
273 * until the voltage change is all done.
274 */
275 clk_en_a = mci_readl(host, CLKENA);
276 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
277 mci_writel(host, CLKENA, clk_en_a);
278 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
279 SDMMC_CMD_PRV_DAT_WAIT, 0);
280 }
281
282 if (cmd->flags & MMC_RSP_PRESENT) {
283 /* We expect a response, so set this bit */
284 cmdr |= SDMMC_CMD_RESP_EXP;
285 if (cmd->flags & MMC_RSP_136)
286 cmdr |= SDMMC_CMD_RESP_LONG;
287 }
288
289 if (cmd->flags & MMC_RSP_CRC)
290 cmdr |= SDMMC_CMD_RESP_CRC;
291
292 data = cmd->data;
293 if (data) {
294 cmdr |= SDMMC_CMD_DAT_EXP;
295 if (data->flags & MMC_DATA_STREAM)
296 cmdr |= SDMMC_CMD_STRM_MODE;
297 if (data->flags & MMC_DATA_WRITE)
298 cmdr |= SDMMC_CMD_DAT_WR;
299 }
300
301 if (drv_data && drv_data->prepare_command)
302 drv_data->prepare_command(slot->host, &cmdr);
303
304 return cmdr;
305 }
306
307 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
308 {
309 struct mmc_command *stop;
310 u32 cmdr;
311
312 if (!cmd->data)
313 return 0;
314
315 stop = &host->stop_abort;
316 cmdr = cmd->opcode;
317 memset(stop, 0, sizeof(struct mmc_command));
318
319 if (cmdr == MMC_READ_SINGLE_BLOCK ||
320 cmdr == MMC_READ_MULTIPLE_BLOCK ||
321 cmdr == MMC_WRITE_BLOCK ||
322 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
323 cmdr == MMC_SEND_TUNING_BLOCK ||
324 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
325 stop->opcode = MMC_STOP_TRANSMISSION;
326 stop->arg = 0;
327 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
328 } else if (cmdr == SD_IO_RW_EXTENDED) {
329 stop->opcode = SD_IO_RW_DIRECT;
330 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
331 ((cmd->arg >> 28) & 0x7);
332 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
333 } else {
334 return 0;
335 }
336
337 cmdr = stop->opcode | SDMMC_CMD_STOP |
338 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
339
340 return cmdr;
341 }
342
343 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
344 {
345 unsigned long timeout = jiffies + msecs_to_jiffies(500);
346
347 /*
348 * Databook says that before issuing a new data transfer command
349 * we need to check to see if the card is busy. Data transfer commands
350 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
351 *
352 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
353 * expected.
354 */
355 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
356 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
357 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
358 if (time_after(jiffies, timeout)) {
359 /* Command will fail; we'll pass error then */
360 dev_err(host->dev, "Busy; trying anyway\n");
361 break;
362 }
363 udelay(10);
364 }
365 }
366 }
367
368 static void dw_mci_start_command(struct dw_mci *host,
369 struct mmc_command *cmd, u32 cmd_flags)
370 {
371 host->cmd = cmd;
372 dev_vdbg(host->dev,
373 "start command: ARGR=0x%08x CMDR=0x%08x\n",
374 cmd->arg, cmd_flags);
375
376 mci_writel(host, CMDARG, cmd->arg);
377 wmb(); /* drain writebuffer */
378 dw_mci_wait_while_busy(host, cmd_flags);
379
380 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
381 }
382
383 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
384 {
385 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
386
387 dw_mci_start_command(host, stop, host->stop_cmdr);
388 }
389
390 /* DMA interface functions */
391 static void dw_mci_stop_dma(struct dw_mci *host)
392 {
393 if (host->using_dma) {
394 host->dma_ops->stop(host);
395 host->dma_ops->cleanup(host);
396 }
397
398 /* Data transfer was stopped by the interrupt handler */
399 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
400 }
401
402 static int dw_mci_get_dma_dir(struct mmc_data *data)
403 {
404 if (data->flags & MMC_DATA_WRITE)
405 return DMA_TO_DEVICE;
406 else
407 return DMA_FROM_DEVICE;
408 }
409
410 #ifdef CONFIG_MMC_DW_IDMAC
411 static void dw_mci_dma_cleanup(struct dw_mci *host)
412 {
413 struct mmc_data *data = host->data;
414
415 if (data)
416 if (!data->host_cookie)
417 dma_unmap_sg(host->dev,
418 data->sg,
419 data->sg_len,
420 dw_mci_get_dma_dir(data));
421 }
422
423 static void dw_mci_idmac_reset(struct dw_mci *host)
424 {
425 u32 bmod = mci_readl(host, BMOD);
426 /* Software reset of DMA */
427 bmod |= SDMMC_IDMAC_SWRESET;
428 mci_writel(host, BMOD, bmod);
429 }
430
431 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
432 {
433 u32 temp;
434
435 /* Disable and reset the IDMAC interface */
436 temp = mci_readl(host, CTRL);
437 temp &= ~SDMMC_CTRL_USE_IDMAC;
438 temp |= SDMMC_CTRL_DMA_RESET;
439 mci_writel(host, CTRL, temp);
440
441 /* Stop the IDMAC running */
442 temp = mci_readl(host, BMOD);
443 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
444 temp |= SDMMC_IDMAC_SWRESET;
445 mci_writel(host, BMOD, temp);
446 }
447
448 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
449 {
450 struct mmc_data *data = host->data;
451
452 dev_vdbg(host->dev, "DMA complete\n");
453
454 host->dma_ops->cleanup(host);
455
456 /*
457 * If the card was removed, data will be NULL. No point in trying to
458 * send the stop command or waiting for NBUSY in this case.
459 */
460 if (data) {
461 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
462 tasklet_schedule(&host->tasklet);
463 }
464 }
465
466 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
467 unsigned int sg_len)
468 {
469 unsigned int desc_len;
470 int i;
471
472 if (host->dma_64bit_address == 1) {
473 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
474
475 desc_first = desc_last = desc = host->sg_cpu;
476
477 for (i = 0; i < sg_len; i++) {
478 unsigned int length = sg_dma_len(&data->sg[i]);
479
480 u64 mem_addr = sg_dma_address(&data->sg[i]);
481
482 for ( ; length ; desc++) {
483 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
484 length : DW_MCI_DESC_DATA_LENGTH;
485
486 length -= desc_len;
487
488 /*
489 * Set the OWN bit and disable interrupts
490 * for this descriptor
491 */
492 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
493 IDMAC_DES0_CH;
494
495 /* Buffer length */
496 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
497
498 /* Physical address to DMA to/from */
499 desc->des4 = mem_addr & 0xffffffff;
500 desc->des5 = mem_addr >> 32;
501
502 /* Update physical address for the next desc */
503 mem_addr += desc_len;
504
505 /* Save pointer to the last descriptor */
506 desc_last = desc;
507 }
508 }
509
510 /* Set first descriptor */
511 desc_first->des0 |= IDMAC_DES0_FD;
512
513 /* Set last descriptor */
514 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
515 desc_last->des0 |= IDMAC_DES0_LD;
516
517 } else {
518 struct idmac_desc *desc_first, *desc_last, *desc;
519
520 desc_first = desc_last = desc = host->sg_cpu;
521
522 for (i = 0; i < sg_len; i++) {
523 unsigned int length = sg_dma_len(&data->sg[i]);
524
525 u32 mem_addr = sg_dma_address(&data->sg[i]);
526
527 for ( ; length ; desc++) {
528 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
529 length : DW_MCI_DESC_DATA_LENGTH;
530
531 length -= desc_len;
532
533 /*
534 * Set the OWN bit and disable interrupts
535 * for this descriptor
536 */
537 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
538 IDMAC_DES0_DIC |
539 IDMAC_DES0_CH);
540
541 /* Buffer length */
542 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
543
544 /* Physical address to DMA to/from */
545 desc->des2 = cpu_to_le32(mem_addr);
546
547 /* Update physical address for the next desc */
548 mem_addr += desc_len;
549
550 /* Save pointer to the last descriptor */
551 desc_last = desc;
552 }
553 }
554
555 /* Set first descriptor */
556 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
557
558 /* Set last descriptor */
559 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
560 IDMAC_DES0_DIC));
561 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
562 }
563
564 wmb(); /* drain writebuffer */
565 }
566
567 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
568 {
569 u32 temp;
570
571 dw_mci_translate_sglist(host, host->data, sg_len);
572
573 /* Make sure to reset DMA in case we did PIO before this */
574 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
575 dw_mci_idmac_reset(host);
576
577 /* Select IDMAC interface */
578 temp = mci_readl(host, CTRL);
579 temp |= SDMMC_CTRL_USE_IDMAC;
580 mci_writel(host, CTRL, temp);
581
582 /* drain writebuffer */
583 wmb();
584
585 /* Enable the IDMAC */
586 temp = mci_readl(host, BMOD);
587 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
588 mci_writel(host, BMOD, temp);
589
590 /* Start it running */
591 mci_writel(host, PLDMND, 1);
592 }
593
594 static int dw_mci_idmac_init(struct dw_mci *host)
595 {
596 int i;
597
598 if (host->dma_64bit_address == 1) {
599 struct idmac_desc_64addr *p;
600 /* Number of descriptors in the ring buffer */
601 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
602
603 /* Forward link the descriptor list */
604 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
605 i++, p++) {
606 p->des6 = (host->sg_dma +
607 (sizeof(struct idmac_desc_64addr) *
608 (i + 1))) & 0xffffffff;
609
610 p->des7 = (u64)(host->sg_dma +
611 (sizeof(struct idmac_desc_64addr) *
612 (i + 1))) >> 32;
613 /* Initialize reserved and buffer size fields to "0" */
614 p->des1 = 0;
615 p->des2 = 0;
616 p->des3 = 0;
617 }
618
619 /* Set the last descriptor as the end-of-ring descriptor */
620 p->des6 = host->sg_dma & 0xffffffff;
621 p->des7 = (u64)host->sg_dma >> 32;
622 p->des0 = IDMAC_DES0_ER;
623
624 } else {
625 struct idmac_desc *p;
626 /* Number of descriptors in the ring buffer */
627 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
628
629 /* Forward link the descriptor list */
630 for (i = 0, p = host->sg_cpu;
631 i < host->ring_size - 1;
632 i++, p++) {
633 p->des3 = cpu_to_le32(host->sg_dma +
634 (sizeof(struct idmac_desc) * (i + 1)));
635 p->des1 = 0;
636 }
637
638 /* Set the last descriptor as the end-of-ring descriptor */
639 p->des3 = cpu_to_le32(host->sg_dma);
640 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
641 }
642
643 dw_mci_idmac_reset(host);
644
645 if (host->dma_64bit_address == 1) {
646 /* Mask out interrupts - get Tx & Rx complete only */
647 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
648 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
649 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
650
651 /* Set the descriptor base address */
652 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
653 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
654
655 } else {
656 /* Mask out interrupts - get Tx & Rx complete only */
657 mci_writel(host, IDSTS, IDMAC_INT_CLR);
658 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
659 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
660
661 /* Set the descriptor base address */
662 mci_writel(host, DBADDR, host->sg_dma);
663 }
664
665 return 0;
666 }
667
668 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
669 .init = dw_mci_idmac_init,
670 .start = dw_mci_idmac_start_dma,
671 .stop = dw_mci_idmac_stop_dma,
672 .complete = dw_mci_idmac_complete_dma,
673 .cleanup = dw_mci_dma_cleanup,
674 };
675 #endif /* CONFIG_MMC_DW_IDMAC */
676
677 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
678 struct mmc_data *data,
679 bool next)
680 {
681 struct scatterlist *sg;
682 unsigned int i, sg_len;
683
684 if (!next && data->host_cookie)
685 return data->host_cookie;
686
687 /*
688 * We don't do DMA on "complex" transfers, i.e. with
689 * non-word-aligned buffers or lengths. Also, we don't bother
690 * with all the DMA setup overhead for short transfers.
691 */
692 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
693 return -EINVAL;
694
695 if (data->blksz & 3)
696 return -EINVAL;
697
698 for_each_sg(data->sg, sg, data->sg_len, i) {
699 if (sg->offset & 3 || sg->length & 3)
700 return -EINVAL;
701 }
702
703 sg_len = dma_map_sg(host->dev,
704 data->sg,
705 data->sg_len,
706 dw_mci_get_dma_dir(data));
707 if (sg_len == 0)
708 return -EINVAL;
709
710 if (next)
711 data->host_cookie = sg_len;
712
713 return sg_len;
714 }
715
716 static void dw_mci_pre_req(struct mmc_host *mmc,
717 struct mmc_request *mrq,
718 bool is_first_req)
719 {
720 struct dw_mci_slot *slot = mmc_priv(mmc);
721 struct mmc_data *data = mrq->data;
722
723 if (!slot->host->use_dma || !data)
724 return;
725
726 if (data->host_cookie) {
727 data->host_cookie = 0;
728 return;
729 }
730
731 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
732 data->host_cookie = 0;
733 }
734
735 static void dw_mci_post_req(struct mmc_host *mmc,
736 struct mmc_request *mrq,
737 int err)
738 {
739 struct dw_mci_slot *slot = mmc_priv(mmc);
740 struct mmc_data *data = mrq->data;
741
742 if (!slot->host->use_dma || !data)
743 return;
744
745 if (data->host_cookie)
746 dma_unmap_sg(slot->host->dev,
747 data->sg,
748 data->sg_len,
749 dw_mci_get_dma_dir(data));
750 data->host_cookie = 0;
751 }
752
753 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
754 {
755 #ifdef CONFIG_MMC_DW_IDMAC
756 unsigned int blksz = data->blksz;
757 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
758 u32 fifo_width = 1 << host->data_shift;
759 u32 blksz_depth = blksz / fifo_width, fifoth_val;
760 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
761 int idx = ARRAY_SIZE(mszs) - 1;
762
763 tx_wmark = (host->fifo_depth) / 2;
764 tx_wmark_invers = host->fifo_depth - tx_wmark;
765
766 /*
767 * MSIZE is '1',
768 * if blksz is not a multiple of the FIFO width
769 */
770 if (blksz % fifo_width) {
771 msize = 0;
772 rx_wmark = 1;
773 goto done;
774 }
775
776 do {
777 if (!((blksz_depth % mszs[idx]) ||
778 (tx_wmark_invers % mszs[idx]))) {
779 msize = idx;
780 rx_wmark = mszs[idx] - 1;
781 break;
782 }
783 } while (--idx > 0);
784 /*
785 * If idx is '0', it won't be tried
786 * Thus, initial values are uesed
787 */
788 done:
789 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
790 mci_writel(host, FIFOTH, fifoth_val);
791 #endif
792 }
793
794 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
795 {
796 unsigned int blksz = data->blksz;
797 u32 blksz_depth, fifo_depth;
798 u16 thld_size;
799
800 WARN_ON(!(data->flags & MMC_DATA_READ));
801
802 /*
803 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
804 * in the FIFO region, so we really shouldn't access it).
805 */
806 if (host->verid < DW_MMC_240A)
807 return;
808
809 if (host->timing != MMC_TIMING_MMC_HS200 &&
810 host->timing != MMC_TIMING_MMC_HS400 &&
811 host->timing != MMC_TIMING_UHS_SDR104)
812 goto disable;
813
814 blksz_depth = blksz / (1 << host->data_shift);
815 fifo_depth = host->fifo_depth;
816
817 if (blksz_depth > fifo_depth)
818 goto disable;
819
820 /*
821 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
822 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
823 * Currently just choose blksz.
824 */
825 thld_size = blksz;
826 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
827 return;
828
829 disable:
830 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
831 }
832
833 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
834 {
835 unsigned long irqflags;
836 int sg_len;
837 u32 temp;
838
839 host->using_dma = 0;
840
841 /* If we don't have a channel, we can't do DMA */
842 if (!host->use_dma)
843 return -ENODEV;
844
845 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
846 if (sg_len < 0) {
847 host->dma_ops->stop(host);
848 return sg_len;
849 }
850
851 host->using_dma = 1;
852
853 dev_vdbg(host->dev,
854 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
855 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
856 sg_len);
857
858 /*
859 * Decide the MSIZE and RX/TX Watermark.
860 * If current block size is same with previous size,
861 * no need to update fifoth.
862 */
863 if (host->prev_blksz != data->blksz)
864 dw_mci_adjust_fifoth(host, data);
865
866 /* Enable the DMA interface */
867 temp = mci_readl(host, CTRL);
868 temp |= SDMMC_CTRL_DMA_ENABLE;
869 mci_writel(host, CTRL, temp);
870
871 /* Disable RX/TX IRQs, let DMA handle it */
872 spin_lock_irqsave(&host->irq_lock, irqflags);
873 temp = mci_readl(host, INTMASK);
874 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
875 mci_writel(host, INTMASK, temp);
876 spin_unlock_irqrestore(&host->irq_lock, irqflags);
877
878 host->dma_ops->start(host, sg_len);
879
880 return 0;
881 }
882
883 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
884 {
885 unsigned long irqflags;
886 int flags = SG_MITER_ATOMIC;
887 u32 temp;
888
889 data->error = -EINPROGRESS;
890
891 WARN_ON(host->data);
892 host->sg = NULL;
893 host->data = data;
894
895 if (data->flags & MMC_DATA_READ) {
896 host->dir_status = DW_MCI_RECV_STATUS;
897 dw_mci_ctrl_rd_thld(host, data);
898 } else {
899 host->dir_status = DW_MCI_SEND_STATUS;
900 }
901
902 if (dw_mci_submit_data_dma(host, data)) {
903 if (host->data->flags & MMC_DATA_READ)
904 flags |= SG_MITER_TO_SG;
905 else
906 flags |= SG_MITER_FROM_SG;
907
908 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
909 host->sg = data->sg;
910 host->part_buf_start = 0;
911 host->part_buf_count = 0;
912
913 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
914
915 spin_lock_irqsave(&host->irq_lock, irqflags);
916 temp = mci_readl(host, INTMASK);
917 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
918 mci_writel(host, INTMASK, temp);
919 spin_unlock_irqrestore(&host->irq_lock, irqflags);
920
921 temp = mci_readl(host, CTRL);
922 temp &= ~SDMMC_CTRL_DMA_ENABLE;
923 mci_writel(host, CTRL, temp);
924
925 /*
926 * Use the initial fifoth_val for PIO mode.
927 * If next issued data may be transfered by DMA mode,
928 * prev_blksz should be invalidated.
929 */
930 mci_writel(host, FIFOTH, host->fifoth_val);
931 host->prev_blksz = 0;
932 } else {
933 /*
934 * Keep the current block size.
935 * It will be used to decide whether to update
936 * fifoth register next time.
937 */
938 host->prev_blksz = data->blksz;
939 }
940 }
941
942 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
943 {
944 struct dw_mci *host = slot->host;
945 unsigned long timeout = jiffies + msecs_to_jiffies(500);
946 unsigned int cmd_status = 0;
947
948 mci_writel(host, CMDARG, arg);
949 wmb(); /* drain writebuffer */
950 dw_mci_wait_while_busy(host, cmd);
951 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
952
953 while (time_before(jiffies, timeout)) {
954 cmd_status = mci_readl(host, CMD);
955 if (!(cmd_status & SDMMC_CMD_START))
956 return;
957 }
958 dev_err(&slot->mmc->class_dev,
959 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
960 cmd, arg, cmd_status);
961 }
962
963 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
964 {
965 struct dw_mci *host = slot->host;
966 unsigned int clock = slot->clock;
967 u32 div;
968 u32 clk_en_a;
969 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
970
971 /* We must continue to set bit 28 in CMD until the change is complete */
972 if (host->state == STATE_WAITING_CMD11_DONE)
973 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
974
975 if (!clock) {
976 mci_writel(host, CLKENA, 0);
977 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
978 } else if (clock != host->current_speed || force_clkinit) {
979 div = host->bus_hz / clock;
980 if (host->bus_hz % clock && host->bus_hz > clock)
981 /*
982 * move the + 1 after the divide to prevent
983 * over-clocking the card.
984 */
985 div += 1;
986
987 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
988
989 if ((clock << div) != slot->__clk_old || force_clkinit)
990 dev_info(&slot->mmc->class_dev,
991 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
992 slot->id, host->bus_hz, clock,
993 div ? ((host->bus_hz / div) >> 1) :
994 host->bus_hz, div);
995
996 /* disable clock */
997 mci_writel(host, CLKENA, 0);
998 mci_writel(host, CLKSRC, 0);
999
1000 /* inform CIU */
1001 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1002
1003 /* set clock to desired speed */
1004 mci_writel(host, CLKDIV, div);
1005
1006 /* inform CIU */
1007 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1008
1009 /* enable clock; only low power if no SDIO */
1010 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1011 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1012 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1013 mci_writel(host, CLKENA, clk_en_a);
1014
1015 /* inform CIU */
1016 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1017
1018 /* keep the clock with reflecting clock dividor */
1019 slot->__clk_old = clock << div;
1020 }
1021
1022 host->current_speed = clock;
1023
1024 /* Set the current slot bus width */
1025 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1026 }
1027
1028 static void __dw_mci_start_request(struct dw_mci *host,
1029 struct dw_mci_slot *slot,
1030 struct mmc_command *cmd)
1031 {
1032 struct mmc_request *mrq;
1033 struct mmc_data *data;
1034 u32 cmdflags;
1035
1036 mrq = slot->mrq;
1037
1038 host->cur_slot = slot;
1039 host->mrq = mrq;
1040
1041 host->pending_events = 0;
1042 host->completed_events = 0;
1043 host->cmd_status = 0;
1044 host->data_status = 0;
1045 host->dir_status = 0;
1046
1047 data = cmd->data;
1048 if (data) {
1049 mci_writel(host, TMOUT, 0xFFFFFFFF);
1050 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1051 mci_writel(host, BLKSIZ, data->blksz);
1052 }
1053
1054 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1055
1056 /* this is the first command, send the initialization clock */
1057 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1058 cmdflags |= SDMMC_CMD_INIT;
1059
1060 if (data) {
1061 dw_mci_submit_data(host, data);
1062 wmb(); /* drain writebuffer */
1063 }
1064
1065 dw_mci_start_command(host, cmd, cmdflags);
1066
1067 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1068 unsigned long irqflags;
1069
1070 /*
1071 * Databook says to fail after 2ms w/ no response, but evidence
1072 * shows that sometimes the cmd11 interrupt takes over 130ms.
1073 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1074 * is just about to roll over.
1075 *
1076 * We do this whole thing under spinlock and only if the
1077 * command hasn't already completed (indicating the the irq
1078 * already ran so we don't want the timeout).
1079 */
1080 spin_lock_irqsave(&host->irq_lock, irqflags);
1081 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1082 mod_timer(&host->cmd11_timer,
1083 jiffies + msecs_to_jiffies(500) + 1);
1084 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1085 }
1086
1087 if (mrq->stop)
1088 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1089 else
1090 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1091 }
1092
1093 static void dw_mci_start_request(struct dw_mci *host,
1094 struct dw_mci_slot *slot)
1095 {
1096 struct mmc_request *mrq = slot->mrq;
1097 struct mmc_command *cmd;
1098
1099 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1100 __dw_mci_start_request(host, slot, cmd);
1101 }
1102
1103 /* must be called with host->lock held */
1104 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1105 struct mmc_request *mrq)
1106 {
1107 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1108 host->state);
1109
1110 slot->mrq = mrq;
1111
1112 if (host->state == STATE_WAITING_CMD11_DONE) {
1113 dev_warn(&slot->mmc->class_dev,
1114 "Voltage change didn't complete\n");
1115 /*
1116 * this case isn't expected to happen, so we can
1117 * either crash here or just try to continue on
1118 * in the closest possible state
1119 */
1120 host->state = STATE_IDLE;
1121 }
1122
1123 if (host->state == STATE_IDLE) {
1124 host->state = STATE_SENDING_CMD;
1125 dw_mci_start_request(host, slot);
1126 } else {
1127 list_add_tail(&slot->queue_node, &host->queue);
1128 }
1129 }
1130
1131 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1132 {
1133 struct dw_mci_slot *slot = mmc_priv(mmc);
1134 struct dw_mci *host = slot->host;
1135
1136 WARN_ON(slot->mrq);
1137
1138 /*
1139 * The check for card presence and queueing of the request must be
1140 * atomic, otherwise the card could be removed in between and the
1141 * request wouldn't fail until another card was inserted.
1142 */
1143 spin_lock_bh(&host->lock);
1144
1145 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1146 spin_unlock_bh(&host->lock);
1147 mrq->cmd->error = -ENOMEDIUM;
1148 mmc_request_done(mmc, mrq);
1149 return;
1150 }
1151
1152 dw_mci_queue_request(host, slot, mrq);
1153
1154 spin_unlock_bh(&host->lock);
1155 }
1156
1157 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1158 {
1159 struct dw_mci_slot *slot = mmc_priv(mmc);
1160 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1161 u32 regs;
1162 int ret;
1163
1164 switch (ios->bus_width) {
1165 case MMC_BUS_WIDTH_4:
1166 slot->ctype = SDMMC_CTYPE_4BIT;
1167 break;
1168 case MMC_BUS_WIDTH_8:
1169 slot->ctype = SDMMC_CTYPE_8BIT;
1170 break;
1171 default:
1172 /* set default 1 bit mode */
1173 slot->ctype = SDMMC_CTYPE_1BIT;
1174 }
1175
1176 regs = mci_readl(slot->host, UHS_REG);
1177
1178 /* DDR mode set */
1179 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1180 ios->timing == MMC_TIMING_MMC_HS400)
1181 regs |= ((0x1 << slot->id) << 16);
1182 else
1183 regs &= ~((0x1 << slot->id) << 16);
1184
1185 mci_writel(slot->host, UHS_REG, regs);
1186 slot->host->timing = ios->timing;
1187
1188 /*
1189 * Use mirror of ios->clock to prevent race with mmc
1190 * core ios update when finding the minimum.
1191 */
1192 slot->clock = ios->clock;
1193
1194 if (drv_data && drv_data->set_ios)
1195 drv_data->set_ios(slot->host, ios);
1196
1197 switch (ios->power_mode) {
1198 case MMC_POWER_UP:
1199 if (!IS_ERR(mmc->supply.vmmc)) {
1200 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1201 ios->vdd);
1202 if (ret) {
1203 dev_err(slot->host->dev,
1204 "failed to enable vmmc regulator\n");
1205 /*return, if failed turn on vmmc*/
1206 return;
1207 }
1208 }
1209 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1210 regs = mci_readl(slot->host, PWREN);
1211 regs |= (1 << slot->id);
1212 mci_writel(slot->host, PWREN, regs);
1213 break;
1214 case MMC_POWER_ON:
1215 if (!slot->host->vqmmc_enabled) {
1216 if (!IS_ERR(mmc->supply.vqmmc)) {
1217 ret = regulator_enable(mmc->supply.vqmmc);
1218 if (ret < 0)
1219 dev_err(slot->host->dev,
1220 "failed to enable vqmmc\n");
1221 else
1222 slot->host->vqmmc_enabled = true;
1223
1224 } else {
1225 /* Keep track so we don't reset again */
1226 slot->host->vqmmc_enabled = true;
1227 }
1228
1229 /* Reset our state machine after powering on */
1230 dw_mci_ctrl_reset(slot->host,
1231 SDMMC_CTRL_ALL_RESET_FLAGS);
1232 }
1233
1234 /* Adjust clock / bus width after power is up */
1235 dw_mci_setup_bus(slot, false);
1236
1237 break;
1238 case MMC_POWER_OFF:
1239 /* Turn clock off before power goes down */
1240 dw_mci_setup_bus(slot, false);
1241
1242 if (!IS_ERR(mmc->supply.vmmc))
1243 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1244
1245 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1246 regulator_disable(mmc->supply.vqmmc);
1247 slot->host->vqmmc_enabled = false;
1248
1249 regs = mci_readl(slot->host, PWREN);
1250 regs &= ~(1 << slot->id);
1251 mci_writel(slot->host, PWREN, regs);
1252 break;
1253 default:
1254 break;
1255 }
1256
1257 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1258 slot->host->state = STATE_IDLE;
1259 }
1260
1261 static int dw_mci_card_busy(struct mmc_host *mmc)
1262 {
1263 struct dw_mci_slot *slot = mmc_priv(mmc);
1264 u32 status;
1265
1266 /*
1267 * Check the busy bit which is low when DAT[3:0]
1268 * (the data lines) are 0000
1269 */
1270 status = mci_readl(slot->host, STATUS);
1271
1272 return !!(status & SDMMC_STATUS_BUSY);
1273 }
1274
1275 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1276 {
1277 struct dw_mci_slot *slot = mmc_priv(mmc);
1278 struct dw_mci *host = slot->host;
1279 const struct dw_mci_drv_data *drv_data = host->drv_data;
1280 u32 uhs;
1281 u32 v18 = SDMMC_UHS_18V << slot->id;
1282 int min_uv, max_uv;
1283 int ret;
1284
1285 if (drv_data && drv_data->switch_voltage)
1286 return drv_data->switch_voltage(mmc, ios);
1287
1288 /*
1289 * Program the voltage. Note that some instances of dw_mmc may use
1290 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1291 * does no harm but you need to set the regulator directly. Try both.
1292 */
1293 uhs = mci_readl(host, UHS_REG);
1294 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1295 min_uv = 2700000;
1296 max_uv = 3600000;
1297 uhs &= ~v18;
1298 } else {
1299 min_uv = 1700000;
1300 max_uv = 1950000;
1301 uhs |= v18;
1302 }
1303 if (!IS_ERR(mmc->supply.vqmmc)) {
1304 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1305
1306 if (ret) {
1307 dev_dbg(&mmc->class_dev,
1308 "Regulator set error %d: %d - %d\n",
1309 ret, min_uv, max_uv);
1310 return ret;
1311 }
1312 }
1313 mci_writel(host, UHS_REG, uhs);
1314
1315 return 0;
1316 }
1317
1318 static int dw_mci_get_ro(struct mmc_host *mmc)
1319 {
1320 int read_only;
1321 struct dw_mci_slot *slot = mmc_priv(mmc);
1322 int gpio_ro = mmc_gpio_get_ro(mmc);
1323
1324 /* Use platform get_ro function, else try on board write protect */
1325 if (!IS_ERR_VALUE(gpio_ro))
1326 read_only = gpio_ro;
1327 else
1328 read_only =
1329 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1330
1331 dev_dbg(&mmc->class_dev, "card is %s\n",
1332 read_only ? "read-only" : "read-write");
1333
1334 return read_only;
1335 }
1336
1337 static int dw_mci_get_cd(struct mmc_host *mmc)
1338 {
1339 int present;
1340 struct dw_mci_slot *slot = mmc_priv(mmc);
1341 struct dw_mci_board *brd = slot->host->pdata;
1342 struct dw_mci *host = slot->host;
1343 int gpio_cd = mmc_gpio_get_cd(mmc);
1344
1345 /* Use platform get_cd function, else try onboard card detect */
1346 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1347 (mmc->caps & MMC_CAP_NONREMOVABLE))
1348 present = 1;
1349 else if (!IS_ERR_VALUE(gpio_cd))
1350 present = gpio_cd;
1351 else
1352 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1353 == 0 ? 1 : 0;
1354
1355 spin_lock_bh(&host->lock);
1356 if (present) {
1357 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1358 dev_dbg(&mmc->class_dev, "card is present\n");
1359 } else {
1360 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1361 dev_dbg(&mmc->class_dev, "card is not present\n");
1362 }
1363 spin_unlock_bh(&host->lock);
1364
1365 return present;
1366 }
1367
1368 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1369 {
1370 struct dw_mci_slot *slot = mmc_priv(mmc);
1371 struct dw_mci *host = slot->host;
1372
1373 /*
1374 * Low power mode will stop the card clock when idle. According to the
1375 * description of the CLKENA register we should disable low power mode
1376 * for SDIO cards if we need SDIO interrupts to work.
1377 */
1378 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1379 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1380 u32 clk_en_a_old;
1381 u32 clk_en_a;
1382
1383 clk_en_a_old = mci_readl(host, CLKENA);
1384
1385 if (card->type == MMC_TYPE_SDIO ||
1386 card->type == MMC_TYPE_SD_COMBO) {
1387 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1388 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1389 } else {
1390 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1391 clk_en_a = clk_en_a_old | clken_low_pwr;
1392 }
1393
1394 if (clk_en_a != clk_en_a_old) {
1395 mci_writel(host, CLKENA, clk_en_a);
1396 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1397 SDMMC_CMD_PRV_DAT_WAIT, 0);
1398 }
1399 }
1400 }
1401
1402 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1403 {
1404 struct dw_mci_slot *slot = mmc_priv(mmc);
1405 struct dw_mci *host = slot->host;
1406 unsigned long irqflags;
1407 u32 int_mask;
1408
1409 spin_lock_irqsave(&host->irq_lock, irqflags);
1410
1411 /* Enable/disable Slot Specific SDIO interrupt */
1412 int_mask = mci_readl(host, INTMASK);
1413 if (enb)
1414 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1415 else
1416 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1417 mci_writel(host, INTMASK, int_mask);
1418
1419 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1420 }
1421
1422 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1423 {
1424 struct dw_mci_slot *slot = mmc_priv(mmc);
1425 struct dw_mci *host = slot->host;
1426 const struct dw_mci_drv_data *drv_data = host->drv_data;
1427 int err = -EINVAL;
1428
1429 if (drv_data && drv_data->execute_tuning)
1430 err = drv_data->execute_tuning(slot);
1431 return err;
1432 }
1433
1434 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1435 struct mmc_ios *ios)
1436 {
1437 struct dw_mci_slot *slot = mmc_priv(mmc);
1438 struct dw_mci *host = slot->host;
1439 const struct dw_mci_drv_data *drv_data = host->drv_data;
1440
1441 if (drv_data && drv_data->prepare_hs400_tuning)
1442 return drv_data->prepare_hs400_tuning(host, ios);
1443
1444 return 0;
1445 }
1446
1447 static const struct mmc_host_ops dw_mci_ops = {
1448 .request = dw_mci_request,
1449 .pre_req = dw_mci_pre_req,
1450 .post_req = dw_mci_post_req,
1451 .set_ios = dw_mci_set_ios,
1452 .get_ro = dw_mci_get_ro,
1453 .get_cd = dw_mci_get_cd,
1454 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1455 .execute_tuning = dw_mci_execute_tuning,
1456 .card_busy = dw_mci_card_busy,
1457 .start_signal_voltage_switch = dw_mci_switch_voltage,
1458 .init_card = dw_mci_init_card,
1459 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1460 };
1461
1462 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1463 __releases(&host->lock)
1464 __acquires(&host->lock)
1465 {
1466 struct dw_mci_slot *slot;
1467 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1468
1469 WARN_ON(host->cmd || host->data);
1470
1471 host->cur_slot->mrq = NULL;
1472 host->mrq = NULL;
1473 if (!list_empty(&host->queue)) {
1474 slot = list_entry(host->queue.next,
1475 struct dw_mci_slot, queue_node);
1476 list_del(&slot->queue_node);
1477 dev_vdbg(host->dev, "list not empty: %s is next\n",
1478 mmc_hostname(slot->mmc));
1479 host->state = STATE_SENDING_CMD;
1480 dw_mci_start_request(host, slot);
1481 } else {
1482 dev_vdbg(host->dev, "list empty\n");
1483
1484 if (host->state == STATE_SENDING_CMD11)
1485 host->state = STATE_WAITING_CMD11_DONE;
1486 else
1487 host->state = STATE_IDLE;
1488 }
1489
1490 spin_unlock(&host->lock);
1491 mmc_request_done(prev_mmc, mrq);
1492 spin_lock(&host->lock);
1493 }
1494
1495 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1496 {
1497 u32 status = host->cmd_status;
1498
1499 host->cmd_status = 0;
1500
1501 /* Read the response from the card (up to 16 bytes) */
1502 if (cmd->flags & MMC_RSP_PRESENT) {
1503 if (cmd->flags & MMC_RSP_136) {
1504 cmd->resp[3] = mci_readl(host, RESP0);
1505 cmd->resp[2] = mci_readl(host, RESP1);
1506 cmd->resp[1] = mci_readl(host, RESP2);
1507 cmd->resp[0] = mci_readl(host, RESP3);
1508 } else {
1509 cmd->resp[0] = mci_readl(host, RESP0);
1510 cmd->resp[1] = 0;
1511 cmd->resp[2] = 0;
1512 cmd->resp[3] = 0;
1513 }
1514 }
1515
1516 if (status & SDMMC_INT_RTO)
1517 cmd->error = -ETIMEDOUT;
1518 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1519 cmd->error = -EILSEQ;
1520 else if (status & SDMMC_INT_RESP_ERR)
1521 cmd->error = -EIO;
1522 else
1523 cmd->error = 0;
1524
1525 if (cmd->error) {
1526 /* newer ip versions need a delay between retries */
1527 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1528 mdelay(20);
1529 }
1530
1531 return cmd->error;
1532 }
1533
1534 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1535 {
1536 u32 status = host->data_status;
1537
1538 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1539 if (status & SDMMC_INT_DRTO) {
1540 data->error = -ETIMEDOUT;
1541 } else if (status & SDMMC_INT_DCRC) {
1542 data->error = -EILSEQ;
1543 } else if (status & SDMMC_INT_EBE) {
1544 if (host->dir_status ==
1545 DW_MCI_SEND_STATUS) {
1546 /*
1547 * No data CRC status was returned.
1548 * The number of bytes transferred
1549 * will be exaggerated in PIO mode.
1550 */
1551 data->bytes_xfered = 0;
1552 data->error = -ETIMEDOUT;
1553 } else if (host->dir_status ==
1554 DW_MCI_RECV_STATUS) {
1555 data->error = -EIO;
1556 }
1557 } else {
1558 /* SDMMC_INT_SBE is included */
1559 data->error = -EIO;
1560 }
1561
1562 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1563
1564 /*
1565 * After an error, there may be data lingering
1566 * in the FIFO
1567 */
1568 dw_mci_reset(host);
1569 } else {
1570 data->bytes_xfered = data->blocks * data->blksz;
1571 data->error = 0;
1572 }
1573
1574 return data->error;
1575 }
1576
1577 static void dw_mci_tasklet_func(unsigned long priv)
1578 {
1579 struct dw_mci *host = (struct dw_mci *)priv;
1580 struct mmc_data *data;
1581 struct mmc_command *cmd;
1582 struct mmc_request *mrq;
1583 enum dw_mci_state state;
1584 enum dw_mci_state prev_state;
1585 unsigned int err;
1586
1587 spin_lock(&host->lock);
1588
1589 state = host->state;
1590 data = host->data;
1591 mrq = host->mrq;
1592
1593 do {
1594 prev_state = state;
1595
1596 switch (state) {
1597 case STATE_IDLE:
1598 case STATE_WAITING_CMD11_DONE:
1599 break;
1600
1601 case STATE_SENDING_CMD11:
1602 case STATE_SENDING_CMD:
1603 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1604 &host->pending_events))
1605 break;
1606
1607 cmd = host->cmd;
1608 host->cmd = NULL;
1609 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1610 err = dw_mci_command_complete(host, cmd);
1611 if (cmd == mrq->sbc && !err) {
1612 prev_state = state = STATE_SENDING_CMD;
1613 __dw_mci_start_request(host, host->cur_slot,
1614 mrq->cmd);
1615 goto unlock;
1616 }
1617
1618 if (cmd->data && err) {
1619 dw_mci_stop_dma(host);
1620 send_stop_abort(host, data);
1621 state = STATE_SENDING_STOP;
1622 break;
1623 }
1624
1625 if (!cmd->data || err) {
1626 dw_mci_request_end(host, mrq);
1627 goto unlock;
1628 }
1629
1630 prev_state = state = STATE_SENDING_DATA;
1631 /* fall through */
1632
1633 case STATE_SENDING_DATA:
1634 /*
1635 * We could get a data error and never a transfer
1636 * complete so we'd better check for it here.
1637 *
1638 * Note that we don't really care if we also got a
1639 * transfer complete; stopping the DMA and sending an
1640 * abort won't hurt.
1641 */
1642 if (test_and_clear_bit(EVENT_DATA_ERROR,
1643 &host->pending_events)) {
1644 dw_mci_stop_dma(host);
1645 if (data->stop ||
1646 !(host->data_status & (SDMMC_INT_DRTO |
1647 SDMMC_INT_EBE)))
1648 send_stop_abort(host, data);
1649 state = STATE_DATA_ERROR;
1650 break;
1651 }
1652
1653 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1654 &host->pending_events))
1655 break;
1656
1657 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1658
1659 /*
1660 * Handle an EVENT_DATA_ERROR that might have shown up
1661 * before the transfer completed. This might not have
1662 * been caught by the check above because the interrupt
1663 * could have gone off between the previous check and
1664 * the check for transfer complete.
1665 *
1666 * Technically this ought not be needed assuming we
1667 * get a DATA_COMPLETE eventually (we'll notice the
1668 * error and end the request), but it shouldn't hurt.
1669 *
1670 * This has the advantage of sending the stop command.
1671 */
1672 if (test_and_clear_bit(EVENT_DATA_ERROR,
1673 &host->pending_events)) {
1674 dw_mci_stop_dma(host);
1675 if (data->stop ||
1676 !(host->data_status & (SDMMC_INT_DRTO |
1677 SDMMC_INT_EBE)))
1678 send_stop_abort(host, data);
1679 state = STATE_DATA_ERROR;
1680 break;
1681 }
1682 prev_state = state = STATE_DATA_BUSY;
1683
1684 /* fall through */
1685
1686 case STATE_DATA_BUSY:
1687 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1688 &host->pending_events))
1689 break;
1690
1691 host->data = NULL;
1692 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1693 err = dw_mci_data_complete(host, data);
1694
1695 if (!err) {
1696 if (!data->stop || mrq->sbc) {
1697 if (mrq->sbc && data->stop)
1698 data->stop->error = 0;
1699 dw_mci_request_end(host, mrq);
1700 goto unlock;
1701 }
1702
1703 /* stop command for open-ended transfer*/
1704 if (data->stop)
1705 send_stop_abort(host, data);
1706 } else {
1707 /*
1708 * If we don't have a command complete now we'll
1709 * never get one since we just reset everything;
1710 * better end the request.
1711 *
1712 * If we do have a command complete we'll fall
1713 * through to the SENDING_STOP command and
1714 * everything will be peachy keen.
1715 */
1716 if (!test_bit(EVENT_CMD_COMPLETE,
1717 &host->pending_events)) {
1718 host->cmd = NULL;
1719 dw_mci_request_end(host, mrq);
1720 goto unlock;
1721 }
1722 }
1723
1724 /*
1725 * If err has non-zero,
1726 * stop-abort command has been already issued.
1727 */
1728 prev_state = state = STATE_SENDING_STOP;
1729
1730 /* fall through */
1731
1732 case STATE_SENDING_STOP:
1733 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1734 &host->pending_events))
1735 break;
1736
1737 /* CMD error in data command */
1738 if (mrq->cmd->error && mrq->data)
1739 dw_mci_reset(host);
1740
1741 host->cmd = NULL;
1742 host->data = NULL;
1743
1744 if (mrq->stop)
1745 dw_mci_command_complete(host, mrq->stop);
1746 else
1747 host->cmd_status = 0;
1748
1749 dw_mci_request_end(host, mrq);
1750 goto unlock;
1751
1752 case STATE_DATA_ERROR:
1753 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1754 &host->pending_events))
1755 break;
1756
1757 state = STATE_DATA_BUSY;
1758 break;
1759 }
1760 } while (state != prev_state);
1761
1762 host->state = state;
1763 unlock:
1764 spin_unlock(&host->lock);
1765
1766 }
1767
1768 /* push final bytes to part_buf, only use during push */
1769 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1770 {
1771 memcpy((void *)&host->part_buf, buf, cnt);
1772 host->part_buf_count = cnt;
1773 }
1774
1775 /* append bytes to part_buf, only use during push */
1776 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1777 {
1778 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1779 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1780 host->part_buf_count += cnt;
1781 return cnt;
1782 }
1783
1784 /* pull first bytes from part_buf, only use during pull */
1785 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1786 {
1787 cnt = min_t(int, cnt, host->part_buf_count);
1788 if (cnt) {
1789 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1790 cnt);
1791 host->part_buf_count -= cnt;
1792 host->part_buf_start += cnt;
1793 }
1794 return cnt;
1795 }
1796
1797 /* pull final bytes from the part_buf, assuming it's just been filled */
1798 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1799 {
1800 memcpy(buf, &host->part_buf, cnt);
1801 host->part_buf_start = cnt;
1802 host->part_buf_count = (1 << host->data_shift) - cnt;
1803 }
1804
1805 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1806 {
1807 struct mmc_data *data = host->data;
1808 int init_cnt = cnt;
1809
1810 /* try and push anything in the part_buf */
1811 if (unlikely(host->part_buf_count)) {
1812 int len = dw_mci_push_part_bytes(host, buf, cnt);
1813
1814 buf += len;
1815 cnt -= len;
1816 if (host->part_buf_count == 2) {
1817 mci_fifo_writew(host->fifo_reg, host->part_buf16);
1818 host->part_buf_count = 0;
1819 }
1820 }
1821 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1822 if (unlikely((unsigned long)buf & 0x1)) {
1823 while (cnt >= 2) {
1824 u16 aligned_buf[64];
1825 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1826 int items = len >> 1;
1827 int i;
1828 /* memcpy from input buffer into aligned buffer */
1829 memcpy(aligned_buf, buf, len);
1830 buf += len;
1831 cnt -= len;
1832 /* push data from aligned buffer into fifo */
1833 for (i = 0; i < items; ++i)
1834 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
1835 }
1836 } else
1837 #endif
1838 {
1839 u16 *pdata = buf;
1840
1841 for (; cnt >= 2; cnt -= 2)
1842 mci_fifo_writew(host->fifo_reg, *pdata++);
1843 buf = pdata;
1844 }
1845 /* put anything remaining in the part_buf */
1846 if (cnt) {
1847 dw_mci_set_part_bytes(host, buf, cnt);
1848 /* Push data if we have reached the expected data length */
1849 if ((data->bytes_xfered + init_cnt) ==
1850 (data->blksz * data->blocks))
1851 mci_fifo_writew(host->fifo_reg, host->part_buf16);
1852 }
1853 }
1854
1855 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1856 {
1857 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1858 if (unlikely((unsigned long)buf & 0x1)) {
1859 while (cnt >= 2) {
1860 /* pull data from fifo into aligned buffer */
1861 u16 aligned_buf[64];
1862 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1863 int items = len >> 1;
1864 int i;
1865
1866 for (i = 0; i < items; ++i)
1867 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
1868 /* memcpy from aligned buffer into output buffer */
1869 memcpy(buf, aligned_buf, len);
1870 buf += len;
1871 cnt -= len;
1872 }
1873 } else
1874 #endif
1875 {
1876 u16 *pdata = buf;
1877
1878 for (; cnt >= 2; cnt -= 2)
1879 *pdata++ = mci_fifo_readw(host->fifo_reg);
1880 buf = pdata;
1881 }
1882 if (cnt) {
1883 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
1884 dw_mci_pull_final_bytes(host, buf, cnt);
1885 }
1886 }
1887
1888 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1889 {
1890 struct mmc_data *data = host->data;
1891 int init_cnt = cnt;
1892
1893 /* try and push anything in the part_buf */
1894 if (unlikely(host->part_buf_count)) {
1895 int len = dw_mci_push_part_bytes(host, buf, cnt);
1896
1897 buf += len;
1898 cnt -= len;
1899 if (host->part_buf_count == 4) {
1900 mci_fifo_writel(host->fifo_reg, host->part_buf32);
1901 host->part_buf_count = 0;
1902 }
1903 }
1904 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1905 if (unlikely((unsigned long)buf & 0x3)) {
1906 while (cnt >= 4) {
1907 u32 aligned_buf[32];
1908 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1909 int items = len >> 2;
1910 int i;
1911 /* memcpy from input buffer into aligned buffer */
1912 memcpy(aligned_buf, buf, len);
1913 buf += len;
1914 cnt -= len;
1915 /* push data from aligned buffer into fifo */
1916 for (i = 0; i < items; ++i)
1917 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
1918 }
1919 } else
1920 #endif
1921 {
1922 u32 *pdata = buf;
1923
1924 for (; cnt >= 4; cnt -= 4)
1925 mci_fifo_writel(host->fifo_reg, *pdata++);
1926 buf = pdata;
1927 }
1928 /* put anything remaining in the part_buf */
1929 if (cnt) {
1930 dw_mci_set_part_bytes(host, buf, cnt);
1931 /* Push data if we have reached the expected data length */
1932 if ((data->bytes_xfered + init_cnt) ==
1933 (data->blksz * data->blocks))
1934 mci_fifo_writel(host->fifo_reg, host->part_buf32);
1935 }
1936 }
1937
1938 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1939 {
1940 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1941 if (unlikely((unsigned long)buf & 0x3)) {
1942 while (cnt >= 4) {
1943 /* pull data from fifo into aligned buffer */
1944 u32 aligned_buf[32];
1945 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1946 int items = len >> 2;
1947 int i;
1948
1949 for (i = 0; i < items; ++i)
1950 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
1951 /* memcpy from aligned buffer into output buffer */
1952 memcpy(buf, aligned_buf, len);
1953 buf += len;
1954 cnt -= len;
1955 }
1956 } else
1957 #endif
1958 {
1959 u32 *pdata = buf;
1960
1961 for (; cnt >= 4; cnt -= 4)
1962 *pdata++ = mci_fifo_readl(host->fifo_reg);
1963 buf = pdata;
1964 }
1965 if (cnt) {
1966 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
1967 dw_mci_pull_final_bytes(host, buf, cnt);
1968 }
1969 }
1970
1971 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1972 {
1973 struct mmc_data *data = host->data;
1974 int init_cnt = cnt;
1975
1976 /* try and push anything in the part_buf */
1977 if (unlikely(host->part_buf_count)) {
1978 int len = dw_mci_push_part_bytes(host, buf, cnt);
1979
1980 buf += len;
1981 cnt -= len;
1982
1983 if (host->part_buf_count == 8) {
1984 mci_fifo_writeq(host->fifo_reg, host->part_buf);
1985 host->part_buf_count = 0;
1986 }
1987 }
1988 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1989 if (unlikely((unsigned long)buf & 0x7)) {
1990 while (cnt >= 8) {
1991 u64 aligned_buf[16];
1992 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1993 int items = len >> 3;
1994 int i;
1995 /* memcpy from input buffer into aligned buffer */
1996 memcpy(aligned_buf, buf, len);
1997 buf += len;
1998 cnt -= len;
1999 /* push data from aligned buffer into fifo */
2000 for (i = 0; i < items; ++i)
2001 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2002 }
2003 } else
2004 #endif
2005 {
2006 u64 *pdata = buf;
2007
2008 for (; cnt >= 8; cnt -= 8)
2009 mci_fifo_writeq(host->fifo_reg, *pdata++);
2010 buf = pdata;
2011 }
2012 /* put anything remaining in the part_buf */
2013 if (cnt) {
2014 dw_mci_set_part_bytes(host, buf, cnt);
2015 /* Push data if we have reached the expected data length */
2016 if ((data->bytes_xfered + init_cnt) ==
2017 (data->blksz * data->blocks))
2018 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2019 }
2020 }
2021
2022 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2023 {
2024 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2025 if (unlikely((unsigned long)buf & 0x7)) {
2026 while (cnt >= 8) {
2027 /* pull data from fifo into aligned buffer */
2028 u64 aligned_buf[16];
2029 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2030 int items = len >> 3;
2031 int i;
2032
2033 for (i = 0; i < items; ++i)
2034 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2035
2036 /* memcpy from aligned buffer into output buffer */
2037 memcpy(buf, aligned_buf, len);
2038 buf += len;
2039 cnt -= len;
2040 }
2041 } else
2042 #endif
2043 {
2044 u64 *pdata = buf;
2045
2046 for (; cnt >= 8; cnt -= 8)
2047 *pdata++ = mci_fifo_readq(host->fifo_reg);
2048 buf = pdata;
2049 }
2050 if (cnt) {
2051 host->part_buf = mci_fifo_readq(host->fifo_reg);
2052 dw_mci_pull_final_bytes(host, buf, cnt);
2053 }
2054 }
2055
2056 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2057 {
2058 int len;
2059
2060 /* get remaining partial bytes */
2061 len = dw_mci_pull_part_bytes(host, buf, cnt);
2062 if (unlikely(len == cnt))
2063 return;
2064 buf += len;
2065 cnt -= len;
2066
2067 /* get the rest of the data */
2068 host->pull_data(host, buf, cnt);
2069 }
2070
2071 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2072 {
2073 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2074 void *buf;
2075 unsigned int offset;
2076 struct mmc_data *data = host->data;
2077 int shift = host->data_shift;
2078 u32 status;
2079 unsigned int len;
2080 unsigned int remain, fcnt;
2081
2082 do {
2083 if (!sg_miter_next(sg_miter))
2084 goto done;
2085
2086 host->sg = sg_miter->piter.sg;
2087 buf = sg_miter->addr;
2088 remain = sg_miter->length;
2089 offset = 0;
2090
2091 do {
2092 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2093 << shift) + host->part_buf_count;
2094 len = min(remain, fcnt);
2095 if (!len)
2096 break;
2097 dw_mci_pull_data(host, (void *)(buf + offset), len);
2098 data->bytes_xfered += len;
2099 offset += len;
2100 remain -= len;
2101 } while (remain);
2102
2103 sg_miter->consumed = offset;
2104 status = mci_readl(host, MINTSTS);
2105 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2106 /* if the RXDR is ready read again */
2107 } while ((status & SDMMC_INT_RXDR) ||
2108 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2109
2110 if (!remain) {
2111 if (!sg_miter_next(sg_miter))
2112 goto done;
2113 sg_miter->consumed = 0;
2114 }
2115 sg_miter_stop(sg_miter);
2116 return;
2117
2118 done:
2119 sg_miter_stop(sg_miter);
2120 host->sg = NULL;
2121 smp_wmb(); /* drain writebuffer */
2122 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2123 }
2124
2125 static void dw_mci_write_data_pio(struct dw_mci *host)
2126 {
2127 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2128 void *buf;
2129 unsigned int offset;
2130 struct mmc_data *data = host->data;
2131 int shift = host->data_shift;
2132 u32 status;
2133 unsigned int len;
2134 unsigned int fifo_depth = host->fifo_depth;
2135 unsigned int remain, fcnt;
2136
2137 do {
2138 if (!sg_miter_next(sg_miter))
2139 goto done;
2140
2141 host->sg = sg_miter->piter.sg;
2142 buf = sg_miter->addr;
2143 remain = sg_miter->length;
2144 offset = 0;
2145
2146 do {
2147 fcnt = ((fifo_depth -
2148 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2149 << shift) - host->part_buf_count;
2150 len = min(remain, fcnt);
2151 if (!len)
2152 break;
2153 host->push_data(host, (void *)(buf + offset), len);
2154 data->bytes_xfered += len;
2155 offset += len;
2156 remain -= len;
2157 } while (remain);
2158
2159 sg_miter->consumed = offset;
2160 status = mci_readl(host, MINTSTS);
2161 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2162 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2163
2164 if (!remain) {
2165 if (!sg_miter_next(sg_miter))
2166 goto done;
2167 sg_miter->consumed = 0;
2168 }
2169 sg_miter_stop(sg_miter);
2170 return;
2171
2172 done:
2173 sg_miter_stop(sg_miter);
2174 host->sg = NULL;
2175 smp_wmb(); /* drain writebuffer */
2176 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2177 }
2178
2179 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2180 {
2181 if (!host->cmd_status)
2182 host->cmd_status = status;
2183
2184 smp_wmb(); /* drain writebuffer */
2185
2186 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2187 tasklet_schedule(&host->tasklet);
2188 }
2189
2190 static void dw_mci_handle_cd(struct dw_mci *host)
2191 {
2192 int i;
2193
2194 for (i = 0; i < host->num_slots; i++) {
2195 struct dw_mci_slot *slot = host->slot[i];
2196
2197 if (!slot)
2198 continue;
2199
2200 if (slot->mmc->ops->card_event)
2201 slot->mmc->ops->card_event(slot->mmc);
2202 mmc_detect_change(slot->mmc,
2203 msecs_to_jiffies(host->pdata->detect_delay_ms));
2204 }
2205 }
2206
2207 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2208 {
2209 struct dw_mci *host = dev_id;
2210 u32 pending;
2211 int i;
2212
2213 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2214
2215 /*
2216 * DTO fix - version 2.10a and below, and only if internal DMA
2217 * is configured.
2218 */
2219 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2220 if (!pending &&
2221 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2222 pending |= SDMMC_INT_DATA_OVER;
2223 }
2224
2225 if (pending) {
2226 /* Check volt switch first, since it can look like an error */
2227 if ((host->state == STATE_SENDING_CMD11) &&
2228 (pending & SDMMC_INT_VOLT_SWITCH)) {
2229 unsigned long irqflags;
2230
2231 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2232 pending &= ~SDMMC_INT_VOLT_SWITCH;
2233
2234 /*
2235 * Hold the lock; we know cmd11_timer can't be kicked
2236 * off after the lock is released, so safe to delete.
2237 */
2238 spin_lock_irqsave(&host->irq_lock, irqflags);
2239 dw_mci_cmd_interrupt(host, pending);
2240 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2241
2242 del_timer(&host->cmd11_timer);
2243 }
2244
2245 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2246 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2247 host->cmd_status = pending;
2248 smp_wmb(); /* drain writebuffer */
2249 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2250 }
2251
2252 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2253 /* if there is an error report DATA_ERROR */
2254 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2255 host->data_status = pending;
2256 smp_wmb(); /* drain writebuffer */
2257 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2258 tasklet_schedule(&host->tasklet);
2259 }
2260
2261 if (pending & SDMMC_INT_DATA_OVER) {
2262 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2263 if (!host->data_status)
2264 host->data_status = pending;
2265 smp_wmb(); /* drain writebuffer */
2266 if (host->dir_status == DW_MCI_RECV_STATUS) {
2267 if (host->sg != NULL)
2268 dw_mci_read_data_pio(host, true);
2269 }
2270 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2271 tasklet_schedule(&host->tasklet);
2272 }
2273
2274 if (pending & SDMMC_INT_RXDR) {
2275 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2276 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2277 dw_mci_read_data_pio(host, false);
2278 }
2279
2280 if (pending & SDMMC_INT_TXDR) {
2281 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2282 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2283 dw_mci_write_data_pio(host);
2284 }
2285
2286 if (pending & SDMMC_INT_CMD_DONE) {
2287 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2288 dw_mci_cmd_interrupt(host, pending);
2289 }
2290
2291 if (pending & SDMMC_INT_CD) {
2292 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2293 dw_mci_handle_cd(host);
2294 }
2295
2296 /* Handle SDIO Interrupts */
2297 for (i = 0; i < host->num_slots; i++) {
2298 struct dw_mci_slot *slot = host->slot[i];
2299
2300 if (!slot)
2301 continue;
2302
2303 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2304 mci_writel(host, RINTSTS,
2305 SDMMC_INT_SDIO(slot->sdio_id));
2306 mmc_signal_sdio_irq(slot->mmc);
2307 }
2308 }
2309
2310 }
2311
2312 #ifdef CONFIG_MMC_DW_IDMAC
2313 /* Handle DMA interrupts */
2314 if (host->dma_64bit_address == 1) {
2315 pending = mci_readl(host, IDSTS64);
2316 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2317 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2318 SDMMC_IDMAC_INT_RI);
2319 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2320 host->dma_ops->complete(host);
2321 }
2322 } else {
2323 pending = mci_readl(host, IDSTS);
2324 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2325 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2326 SDMMC_IDMAC_INT_RI);
2327 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2328 host->dma_ops->complete(host);
2329 }
2330 }
2331 #endif
2332
2333 return IRQ_HANDLED;
2334 }
2335
2336 #ifdef CONFIG_OF
2337 /* given a slot, find out the device node representing that slot */
2338 static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
2339 {
2340 struct device *dev = slot->mmc->parent;
2341 struct device_node *np;
2342 const __be32 *addr;
2343 int len;
2344
2345 if (!dev || !dev->of_node)
2346 return NULL;
2347
2348 for_each_child_of_node(dev->of_node, np) {
2349 addr = of_get_property(np, "reg", &len);
2350 if (!addr || (len < sizeof(int)))
2351 continue;
2352 if (be32_to_cpup(addr) == slot->id)
2353 return np;
2354 }
2355 return NULL;
2356 }
2357
2358 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2359 {
2360 struct device_node *np = dw_mci_of_find_slot_node(slot);
2361
2362 if (!np)
2363 return;
2364
2365 if (of_property_read_bool(np, "disable-wp")) {
2366 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2367 dev_warn(slot->mmc->parent,
2368 "Slot quirk 'disable-wp' is deprecated\n");
2369 }
2370 }
2371 #else /* CONFIG_OF */
2372 static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
2373 {
2374 }
2375 #endif /* CONFIG_OF */
2376
2377 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2378 {
2379 struct mmc_host *mmc;
2380 struct dw_mci_slot *slot;
2381 const struct dw_mci_drv_data *drv_data = host->drv_data;
2382 int ctrl_id, ret;
2383 u32 freq[2];
2384
2385 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2386 if (!mmc)
2387 return -ENOMEM;
2388
2389 slot = mmc_priv(mmc);
2390 slot->id = id;
2391 slot->sdio_id = host->sdio_id0 + id;
2392 slot->mmc = mmc;
2393 slot->host = host;
2394 host->slot[id] = slot;
2395
2396 mmc->ops = &dw_mci_ops;
2397 if (of_property_read_u32_array(host->dev->of_node,
2398 "clock-freq-min-max", freq, 2)) {
2399 mmc->f_min = DW_MCI_FREQ_MIN;
2400 mmc->f_max = DW_MCI_FREQ_MAX;
2401 } else {
2402 mmc->f_min = freq[0];
2403 mmc->f_max = freq[1];
2404 }
2405
2406 /*if there are external regulators, get them*/
2407 ret = mmc_regulator_get_supply(mmc);
2408 if (ret == -EPROBE_DEFER)
2409 goto err_host_allocated;
2410
2411 if (!mmc->ocr_avail)
2412 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2413
2414 if (host->pdata->caps)
2415 mmc->caps = host->pdata->caps;
2416
2417 if (host->pdata->pm_caps)
2418 mmc->pm_caps = host->pdata->pm_caps;
2419
2420 if (host->dev->of_node) {
2421 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2422 if (ctrl_id < 0)
2423 ctrl_id = 0;
2424 } else {
2425 ctrl_id = to_platform_device(host->dev)->id;
2426 }
2427 if (drv_data && drv_data->caps)
2428 mmc->caps |= drv_data->caps[ctrl_id];
2429
2430 if (host->pdata->caps2)
2431 mmc->caps2 = host->pdata->caps2;
2432
2433 dw_mci_slot_of_parse(slot);
2434
2435 ret = mmc_of_parse(mmc);
2436 if (ret)
2437 goto err_host_allocated;
2438
2439 if (host->pdata->blk_settings) {
2440 mmc->max_segs = host->pdata->blk_settings->max_segs;
2441 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2442 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2443 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2444 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2445 } else {
2446 /* Useful defaults if platform data is unset. */
2447 #ifdef CONFIG_MMC_DW_IDMAC
2448 mmc->max_segs = host->ring_size;
2449 mmc->max_blk_size = 65536;
2450 mmc->max_seg_size = DW_MCI_DESC_DATA_LENGTH;
2451 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2452 mmc->max_blk_count = mmc->max_req_size / 512;
2453 #else
2454 mmc->max_segs = 64;
2455 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2456 mmc->max_blk_count = 512;
2457 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2458 mmc->max_seg_size = mmc->max_req_size;
2459 #endif /* CONFIG_MMC_DW_IDMAC */
2460 }
2461
2462 if (dw_mci_get_cd(mmc))
2463 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2464 else
2465 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2466
2467 ret = mmc_add_host(mmc);
2468 if (ret)
2469 goto err_host_allocated;
2470
2471 #if defined(CONFIG_DEBUG_FS)
2472 dw_mci_init_debugfs(slot);
2473 #endif
2474
2475 return 0;
2476
2477 err_host_allocated:
2478 mmc_free_host(mmc);
2479 return ret;
2480 }
2481
2482 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2483 {
2484 /* Debugfs stuff is cleaned up by mmc core */
2485 mmc_remove_host(slot->mmc);
2486 slot->host->slot[id] = NULL;
2487 mmc_free_host(slot->mmc);
2488 }
2489
2490 static void dw_mci_init_dma(struct dw_mci *host)
2491 {
2492 int addr_config;
2493 /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
2494 addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2495
2496 if (addr_config == 1) {
2497 /* host supports IDMAC in 64-bit address mode */
2498 host->dma_64bit_address = 1;
2499 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2500 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2501 dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2502 } else {
2503 /* host supports IDMAC in 32-bit address mode */
2504 host->dma_64bit_address = 0;
2505 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2506 }
2507
2508 /* Alloc memory for sg translation */
2509 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2510 &host->sg_dma, GFP_KERNEL);
2511 if (!host->sg_cpu) {
2512 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2513 __func__);
2514 goto no_dma;
2515 }
2516
2517 /* Determine which DMA interface to use */
2518 #ifdef CONFIG_MMC_DW_IDMAC
2519 host->dma_ops = &dw_mci_idmac_ops;
2520 dev_info(host->dev, "Using internal DMA controller.\n");
2521 #endif
2522
2523 if (!host->dma_ops)
2524 goto no_dma;
2525
2526 if (host->dma_ops->init && host->dma_ops->start &&
2527 host->dma_ops->stop && host->dma_ops->cleanup) {
2528 if (host->dma_ops->init(host)) {
2529 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2530 __func__);
2531 goto no_dma;
2532 }
2533 } else {
2534 dev_err(host->dev, "DMA initialization not found.\n");
2535 goto no_dma;
2536 }
2537
2538 host->use_dma = 1;
2539 return;
2540
2541 no_dma:
2542 dev_info(host->dev, "Using PIO mode.\n");
2543 host->use_dma = 0;
2544 }
2545
2546 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2547 {
2548 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2549 u32 ctrl;
2550
2551 ctrl = mci_readl(host, CTRL);
2552 ctrl |= reset;
2553 mci_writel(host, CTRL, ctrl);
2554
2555 /* wait till resets clear */
2556 do {
2557 ctrl = mci_readl(host, CTRL);
2558 if (!(ctrl & reset))
2559 return true;
2560 } while (time_before(jiffies, timeout));
2561
2562 dev_err(host->dev,
2563 "Timeout resetting block (ctrl reset %#x)\n",
2564 ctrl & reset);
2565
2566 return false;
2567 }
2568
2569 static bool dw_mci_reset(struct dw_mci *host)
2570 {
2571 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2572 bool ret = false;
2573
2574 /*
2575 * Reseting generates a block interrupt, hence setting
2576 * the scatter-gather pointer to NULL.
2577 */
2578 if (host->sg) {
2579 sg_miter_stop(&host->sg_miter);
2580 host->sg = NULL;
2581 }
2582
2583 if (host->use_dma)
2584 flags |= SDMMC_CTRL_DMA_RESET;
2585
2586 if (dw_mci_ctrl_reset(host, flags)) {
2587 /*
2588 * In all cases we clear the RAWINTS register to clear any
2589 * interrupts.
2590 */
2591 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2592
2593 /* if using dma we wait for dma_req to clear */
2594 if (host->use_dma) {
2595 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2596 u32 status;
2597
2598 do {
2599 status = mci_readl(host, STATUS);
2600 if (!(status & SDMMC_STATUS_DMA_REQ))
2601 break;
2602 cpu_relax();
2603 } while (time_before(jiffies, timeout));
2604
2605 if (status & SDMMC_STATUS_DMA_REQ) {
2606 dev_err(host->dev,
2607 "%s: Timeout waiting for dma_req to clear during reset\n",
2608 __func__);
2609 goto ciu_out;
2610 }
2611
2612 /* when using DMA next we reset the fifo again */
2613 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2614 goto ciu_out;
2615 }
2616 } else {
2617 /* if the controller reset bit did clear, then set clock regs */
2618 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2619 dev_err(host->dev,
2620 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2621 __func__);
2622 goto ciu_out;
2623 }
2624 }
2625
2626 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2627 /* It is also recommended that we reset and reprogram idmac */
2628 dw_mci_idmac_reset(host);
2629 #endif
2630
2631 ret = true;
2632
2633 ciu_out:
2634 /* After a CTRL reset we need to have CIU set clock registers */
2635 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2636
2637 return ret;
2638 }
2639
2640 static void dw_mci_cmd11_timer(unsigned long arg)
2641 {
2642 struct dw_mci *host = (struct dw_mci *)arg;
2643
2644 if (host->state != STATE_SENDING_CMD11) {
2645 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2646 return;
2647 }
2648
2649 host->cmd_status = SDMMC_INT_RTO;
2650 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2651 tasklet_schedule(&host->tasklet);
2652 }
2653
2654 #ifdef CONFIG_OF
2655 static struct dw_mci_of_quirks {
2656 char *quirk;
2657 int id;
2658 } of_quirks[] = {
2659 {
2660 .quirk = "broken-cd",
2661 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2662 },
2663 };
2664
2665 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2666 {
2667 struct dw_mci_board *pdata;
2668 struct device *dev = host->dev;
2669 struct device_node *np = dev->of_node;
2670 const struct dw_mci_drv_data *drv_data = host->drv_data;
2671 int idx, ret;
2672 u32 clock_frequency;
2673
2674 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2675 if (!pdata)
2676 return ERR_PTR(-ENOMEM);
2677
2678 /* find out number of slots supported */
2679 if (of_property_read_u32(dev->of_node, "num-slots",
2680 &pdata->num_slots)) {
2681 dev_info(dev,
2682 "num-slots property not found, assuming 1 slot is available\n");
2683 pdata->num_slots = 1;
2684 }
2685
2686 /* get quirks */
2687 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2688 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2689 pdata->quirks |= of_quirks[idx].id;
2690
2691 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2692 dev_info(dev,
2693 "fifo-depth property not found, using value of FIFOTH register as default\n");
2694
2695 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2696
2697 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2698 pdata->bus_hz = clock_frequency;
2699
2700 if (drv_data && drv_data->parse_dt) {
2701 ret = drv_data->parse_dt(host);
2702 if (ret)
2703 return ERR_PTR(ret);
2704 }
2705
2706 if (of_find_property(np, "supports-highspeed", NULL))
2707 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2708
2709 return pdata;
2710 }
2711
2712 #else /* CONFIG_OF */
2713 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2714 {
2715 return ERR_PTR(-EINVAL);
2716 }
2717 #endif /* CONFIG_OF */
2718
2719 static void dw_mci_enable_cd(struct dw_mci *host)
2720 {
2721 struct dw_mci_board *brd = host->pdata;
2722 unsigned long irqflags;
2723 u32 temp;
2724 int i;
2725
2726 /* No need for CD if broken card detection */
2727 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2728 return;
2729
2730 /* No need for CD if all slots have a non-error GPIO */
2731 for (i = 0; i < host->num_slots; i++) {
2732 struct dw_mci_slot *slot = host->slot[i];
2733
2734 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2735 break;
2736 }
2737 if (i == host->num_slots)
2738 return;
2739
2740 spin_lock_irqsave(&host->irq_lock, irqflags);
2741 temp = mci_readl(host, INTMASK);
2742 temp |= SDMMC_INT_CD;
2743 mci_writel(host, INTMASK, temp);
2744 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2745 }
2746
2747 int dw_mci_probe(struct dw_mci *host)
2748 {
2749 const struct dw_mci_drv_data *drv_data = host->drv_data;
2750 int width, i, ret = 0;
2751 u32 fifo_size;
2752 int init_slots = 0;
2753
2754 if (!host->pdata) {
2755 host->pdata = dw_mci_parse_dt(host);
2756 if (IS_ERR(host->pdata)) {
2757 dev_err(host->dev, "platform data not available\n");
2758 return -EINVAL;
2759 }
2760 }
2761
2762 if (host->pdata->num_slots > 1) {
2763 dev_err(host->dev,
2764 "Platform data must supply num_slots.\n");
2765 return -ENODEV;
2766 }
2767
2768 host->biu_clk = devm_clk_get(host->dev, "biu");
2769 if (IS_ERR(host->biu_clk)) {
2770 dev_dbg(host->dev, "biu clock not available\n");
2771 } else {
2772 ret = clk_prepare_enable(host->biu_clk);
2773 if (ret) {
2774 dev_err(host->dev, "failed to enable biu clock\n");
2775 return ret;
2776 }
2777 }
2778
2779 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2780 if (IS_ERR(host->ciu_clk)) {
2781 dev_dbg(host->dev, "ciu clock not available\n");
2782 host->bus_hz = host->pdata->bus_hz;
2783 } else {
2784 ret = clk_prepare_enable(host->ciu_clk);
2785 if (ret) {
2786 dev_err(host->dev, "failed to enable ciu clock\n");
2787 goto err_clk_biu;
2788 }
2789
2790 if (host->pdata->bus_hz) {
2791 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2792 if (ret)
2793 dev_warn(host->dev,
2794 "Unable to set bus rate to %uHz\n",
2795 host->pdata->bus_hz);
2796 }
2797 host->bus_hz = clk_get_rate(host->ciu_clk);
2798 }
2799
2800 if (!host->bus_hz) {
2801 dev_err(host->dev,
2802 "Platform data must supply bus speed\n");
2803 ret = -ENODEV;
2804 goto err_clk_ciu;
2805 }
2806
2807 if (drv_data && drv_data->init) {
2808 ret = drv_data->init(host);
2809 if (ret) {
2810 dev_err(host->dev,
2811 "implementation specific init failed\n");
2812 goto err_clk_ciu;
2813 }
2814 }
2815
2816 if (drv_data && drv_data->setup_clock) {
2817 ret = drv_data->setup_clock(host);
2818 if (ret) {
2819 dev_err(host->dev,
2820 "implementation specific clock setup failed\n");
2821 goto err_clk_ciu;
2822 }
2823 }
2824
2825 setup_timer(&host->cmd11_timer,
2826 dw_mci_cmd11_timer, (unsigned long)host);
2827
2828 host->quirks = host->pdata->quirks;
2829
2830 spin_lock_init(&host->lock);
2831 spin_lock_init(&host->irq_lock);
2832 INIT_LIST_HEAD(&host->queue);
2833
2834 /*
2835 * Get the host data width - this assumes that HCON has been set with
2836 * the correct values.
2837 */
2838 i = (mci_readl(host, HCON) >> 7) & 0x7;
2839 if (!i) {
2840 host->push_data = dw_mci_push_data16;
2841 host->pull_data = dw_mci_pull_data16;
2842 width = 16;
2843 host->data_shift = 1;
2844 } else if (i == 2) {
2845 host->push_data = dw_mci_push_data64;
2846 host->pull_data = dw_mci_pull_data64;
2847 width = 64;
2848 host->data_shift = 3;
2849 } else {
2850 /* Check for a reserved value, and warn if it is */
2851 WARN((i != 1),
2852 "HCON reports a reserved host data width!\n"
2853 "Defaulting to 32-bit access.\n");
2854 host->push_data = dw_mci_push_data32;
2855 host->pull_data = dw_mci_pull_data32;
2856 width = 32;
2857 host->data_shift = 2;
2858 }
2859
2860 /* Reset all blocks */
2861 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2862 return -ENODEV;
2863
2864 host->dma_ops = host->pdata->dma_ops;
2865 dw_mci_init_dma(host);
2866
2867 /* Clear the interrupts for the host controller */
2868 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2869 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2870
2871 /* Put in max timeout */
2872 mci_writel(host, TMOUT, 0xFFFFFFFF);
2873
2874 /*
2875 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2876 * Tx Mark = fifo_size / 2 DMA Size = 8
2877 */
2878 if (!host->pdata->fifo_depth) {
2879 /*
2880 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2881 * have been overwritten by the bootloader, just like we're
2882 * about to do, so if you know the value for your hardware, you
2883 * should put it in the platform data.
2884 */
2885 fifo_size = mci_readl(host, FIFOTH);
2886 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2887 } else {
2888 fifo_size = host->pdata->fifo_depth;
2889 }
2890 host->fifo_depth = fifo_size;
2891 host->fifoth_val =
2892 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2893 mci_writel(host, FIFOTH, host->fifoth_val);
2894
2895 /* disable clock to CIU */
2896 mci_writel(host, CLKENA, 0);
2897 mci_writel(host, CLKSRC, 0);
2898
2899 /*
2900 * In 2.40a spec, Data offset is changed.
2901 * Need to check the version-id and set data-offset for DATA register.
2902 */
2903 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2904 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2905
2906 if (host->verid < DW_MMC_240A)
2907 host->fifo_reg = host->regs + DATA_OFFSET;
2908 else
2909 host->fifo_reg = host->regs + DATA_240A_OFFSET;
2910
2911 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2912 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2913 host->irq_flags, "dw-mci", host);
2914 if (ret)
2915 goto err_dmaunmap;
2916
2917 if (host->pdata->num_slots)
2918 host->num_slots = host->pdata->num_slots;
2919 else
2920 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2921
2922 /*
2923 * Enable interrupts for command done, data over, data empty,
2924 * receive ready and error such as transmit, receive timeout, crc error
2925 */
2926 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2927 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2928 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2929 DW_MCI_ERROR_FLAGS);
2930 /* Enable mci interrupt */
2931 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2932
2933 dev_info(host->dev,
2934 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2935 host->irq, width, fifo_size);
2936
2937 /* We need at least one slot to succeed */
2938 for (i = 0; i < host->num_slots; i++) {
2939 ret = dw_mci_init_slot(host, i);
2940 if (ret)
2941 dev_dbg(host->dev, "slot %d init failed\n", i);
2942 else
2943 init_slots++;
2944 }
2945
2946 if (init_slots) {
2947 dev_info(host->dev, "%d slots initialized\n", init_slots);
2948 } else {
2949 dev_dbg(host->dev,
2950 "attempted to initialize %d slots, but failed on all\n",
2951 host->num_slots);
2952 goto err_dmaunmap;
2953 }
2954
2955 /* Now that slots are all setup, we can enable card detect */
2956 dw_mci_enable_cd(host);
2957
2958 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2959 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2960
2961 return 0;
2962
2963 err_dmaunmap:
2964 if (host->use_dma && host->dma_ops->exit)
2965 host->dma_ops->exit(host);
2966
2967 err_clk_ciu:
2968 if (!IS_ERR(host->ciu_clk))
2969 clk_disable_unprepare(host->ciu_clk);
2970
2971 err_clk_biu:
2972 if (!IS_ERR(host->biu_clk))
2973 clk_disable_unprepare(host->biu_clk);
2974
2975 return ret;
2976 }
2977 EXPORT_SYMBOL(dw_mci_probe);
2978
2979 void dw_mci_remove(struct dw_mci *host)
2980 {
2981 int i;
2982
2983 for (i = 0; i < host->num_slots; i++) {
2984 dev_dbg(host->dev, "remove slot %d\n", i);
2985 if (host->slot[i])
2986 dw_mci_cleanup_slot(host->slot[i], i);
2987 }
2988
2989 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2990 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2991
2992 /* disable clock to CIU */
2993 mci_writel(host, CLKENA, 0);
2994 mci_writel(host, CLKSRC, 0);
2995
2996 if (host->use_dma && host->dma_ops->exit)
2997 host->dma_ops->exit(host);
2998
2999 if (!IS_ERR(host->ciu_clk))
3000 clk_disable_unprepare(host->ciu_clk);
3001
3002 if (!IS_ERR(host->biu_clk))
3003 clk_disable_unprepare(host->biu_clk);
3004 }
3005 EXPORT_SYMBOL(dw_mci_remove);
3006
3007
3008
3009 #ifdef CONFIG_PM_SLEEP
3010 /*
3011 * TODO: we should probably disable the clock to the card in the suspend path.
3012 */
3013 int dw_mci_suspend(struct dw_mci *host)
3014 {
3015 return 0;
3016 }
3017 EXPORT_SYMBOL(dw_mci_suspend);
3018
3019 int dw_mci_resume(struct dw_mci *host)
3020 {
3021 int i, ret;
3022
3023 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3024 ret = -ENODEV;
3025 return ret;
3026 }
3027
3028 if (host->use_dma && host->dma_ops->init)
3029 host->dma_ops->init(host);
3030
3031 /*
3032 * Restore the initial value at FIFOTH register
3033 * And Invalidate the prev_blksz with zero
3034 */
3035 mci_writel(host, FIFOTH, host->fifoth_val);
3036 host->prev_blksz = 0;
3037
3038 /* Put in max timeout */
3039 mci_writel(host, TMOUT, 0xFFFFFFFF);
3040
3041 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3042 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3043 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3044 DW_MCI_ERROR_FLAGS);
3045 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3046
3047 for (i = 0; i < host->num_slots; i++) {
3048 struct dw_mci_slot *slot = host->slot[i];
3049
3050 if (!slot)
3051 continue;
3052 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3053 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3054 dw_mci_setup_bus(slot, true);
3055 }
3056 }
3057
3058 /* Now that slots are all setup, we can enable card detect */
3059 dw_mci_enable_cd(host);
3060
3061 return 0;
3062 }
3063 EXPORT_SYMBOL(dw_mci_resume);
3064 #endif /* CONFIG_PM_SLEEP */
3065
3066 static int __init dw_mci_init(void)
3067 {
3068 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3069 return 0;
3070 }
3071
3072 static void __exit dw_mci_exit(void)
3073 {
3074 }
3075
3076 module_init(dw_mci_init);
3077 module_exit(dw_mci_exit);
3078
3079 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3080 MODULE_AUTHOR("NXP Semiconductor VietNam");
3081 MODULE_AUTHOR("Imagination Technologies Ltd");
3082 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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