2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sd.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/dw_mmc.h>
36 #include <linux/bitops.h>
37 #include <linux/regulator/consumer.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
59 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
64 struct idmac_desc_64addr
{
65 u32 des0
; /* Control Descriptor */
67 u32 des1
; /* Reserved */
69 u32 des2
; /*Buffer sizes */
70 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
74 u32 des3
; /* Reserved */
76 u32 des4
; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5
; /* Upper 32-bits of Buffer Address Pointer 1*/
79 u32 des6
; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7
; /* Upper 32-bits of Next Descriptor Address */
84 __le32 des0
; /* Control Descriptor */
85 #define IDMAC_DES0_DIC BIT(1)
86 #define IDMAC_DES0_LD BIT(2)
87 #define IDMAC_DES0_FD BIT(3)
88 #define IDMAC_DES0_CH BIT(4)
89 #define IDMAC_DES0_ER BIT(5)
90 #define IDMAC_DES0_CES BIT(30)
91 #define IDMAC_DES0_OWN BIT(31)
93 __le32 des1
; /* Buffer sizes */
94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
97 __le32 des2
; /* buffer 1 physical address */
99 __le32 des3
; /* buffer 2 physical address */
102 /* Each descriptor can transfer up to 4KB of data in chained mode */
103 #define DW_MCI_DESC_DATA_LENGTH 0x1000
105 static bool dw_mci_reset(struct dw_mci
*host
);
106 static bool dw_mci_ctrl_reset(struct dw_mci
*host
, u32 reset
);
107 static int dw_mci_card_busy(struct mmc_host
*mmc
);
109 #if defined(CONFIG_DEBUG_FS)
110 static int dw_mci_req_show(struct seq_file
*s
, void *v
)
112 struct dw_mci_slot
*slot
= s
->private;
113 struct mmc_request
*mrq
;
114 struct mmc_command
*cmd
;
115 struct mmc_command
*stop
;
116 struct mmc_data
*data
;
118 /* Make sure we get a consistent snapshot */
119 spin_lock_bh(&slot
->host
->lock
);
129 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
130 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
131 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
132 cmd
->resp
[2], cmd
->error
);
134 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
135 data
->bytes_xfered
, data
->blocks
,
136 data
->blksz
, data
->flags
, data
->error
);
139 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
140 stop
->opcode
, stop
->arg
, stop
->flags
,
141 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
142 stop
->resp
[2], stop
->error
);
145 spin_unlock_bh(&slot
->host
->lock
);
150 static int dw_mci_req_open(struct inode
*inode
, struct file
*file
)
152 return single_open(file
, dw_mci_req_show
, inode
->i_private
);
155 static const struct file_operations dw_mci_req_fops
= {
156 .owner
= THIS_MODULE
,
157 .open
= dw_mci_req_open
,
160 .release
= single_release
,
163 static int dw_mci_regs_show(struct seq_file
*s
, void *v
)
165 seq_printf(s
, "STATUS:\t0x%08x\n", SDMMC_STATUS
);
166 seq_printf(s
, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS
);
167 seq_printf(s
, "CMD:\t0x%08x\n", SDMMC_CMD
);
168 seq_printf(s
, "CTRL:\t0x%08x\n", SDMMC_CTRL
);
169 seq_printf(s
, "INTMASK:\t0x%08x\n", SDMMC_INTMASK
);
170 seq_printf(s
, "CLKENA:\t0x%08x\n", SDMMC_CLKENA
);
175 static int dw_mci_regs_open(struct inode
*inode
, struct file
*file
)
177 return single_open(file
, dw_mci_regs_show
, inode
->i_private
);
180 static const struct file_operations dw_mci_regs_fops
= {
181 .owner
= THIS_MODULE
,
182 .open
= dw_mci_regs_open
,
185 .release
= single_release
,
188 static void dw_mci_init_debugfs(struct dw_mci_slot
*slot
)
190 struct mmc_host
*mmc
= slot
->mmc
;
191 struct dw_mci
*host
= slot
->host
;
195 root
= mmc
->debugfs_root
;
199 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
204 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
,
209 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
213 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
214 (u32
*)&host
->pending_events
);
218 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
219 (u32
*)&host
->completed_events
);
226 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
228 #endif /* defined(CONFIG_DEBUG_FS) */
230 static void mci_send_cmd(struct dw_mci_slot
*slot
, u32 cmd
, u32 arg
);
232 static u32
dw_mci_prepare_command(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
234 struct mmc_data
*data
;
235 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
236 struct dw_mci
*host
= slot
->host
;
237 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
240 cmd
->error
= -EINPROGRESS
;
243 if (cmd
->opcode
== MMC_STOP_TRANSMISSION
||
244 cmd
->opcode
== MMC_GO_IDLE_STATE
||
245 cmd
->opcode
== MMC_GO_INACTIVE_STATE
||
246 (cmd
->opcode
== SD_IO_RW_DIRECT
&&
247 ((cmd
->arg
>> 9) & 0x1FFFF) == SDIO_CCCR_ABORT
))
248 cmdr
|= SDMMC_CMD_STOP
;
249 else if (cmd
->opcode
!= MMC_SEND_STATUS
&& cmd
->data
)
250 cmdr
|= SDMMC_CMD_PRV_DAT_WAIT
;
252 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
255 /* Special bit makes CMD11 not die */
256 cmdr
|= SDMMC_CMD_VOLT_SWITCH
;
258 /* Change state to continue to handle CMD11 weirdness */
259 WARN_ON(slot
->host
->state
!= STATE_SENDING_CMD
);
260 slot
->host
->state
= STATE_SENDING_CMD11
;
263 * We need to disable low power mode (automatic clock stop)
264 * while doing voltage switch so we don't confuse the card,
265 * since stopping the clock is a specific part of the UHS
266 * voltage change dance.
268 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
269 * unconditionally turned back on in dw_mci_setup_bus() if it's
270 * ever called with a non-zero clock. That shouldn't happen
271 * until the voltage change is all done.
273 clk_en_a
= mci_readl(host
, CLKENA
);
274 clk_en_a
&= ~(SDMMC_CLKEN_LOW_PWR
<< slot
->id
);
275 mci_writel(host
, CLKENA
, clk_en_a
);
276 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
277 SDMMC_CMD_PRV_DAT_WAIT
, 0);
280 if (cmd
->flags
& MMC_RSP_PRESENT
) {
281 /* We expect a response, so set this bit */
282 cmdr
|= SDMMC_CMD_RESP_EXP
;
283 if (cmd
->flags
& MMC_RSP_136
)
284 cmdr
|= SDMMC_CMD_RESP_LONG
;
287 if (cmd
->flags
& MMC_RSP_CRC
)
288 cmdr
|= SDMMC_CMD_RESP_CRC
;
292 cmdr
|= SDMMC_CMD_DAT_EXP
;
293 if (data
->flags
& MMC_DATA_STREAM
)
294 cmdr
|= SDMMC_CMD_STRM_MODE
;
295 if (data
->flags
& MMC_DATA_WRITE
)
296 cmdr
|= SDMMC_CMD_DAT_WR
;
299 if (drv_data
&& drv_data
->prepare_command
)
300 drv_data
->prepare_command(slot
->host
, &cmdr
);
305 static u32
dw_mci_prep_stop_abort(struct dw_mci
*host
, struct mmc_command
*cmd
)
307 struct mmc_command
*stop
;
313 stop
= &host
->stop_abort
;
315 memset(stop
, 0, sizeof(struct mmc_command
));
317 if (cmdr
== MMC_READ_SINGLE_BLOCK
||
318 cmdr
== MMC_READ_MULTIPLE_BLOCK
||
319 cmdr
== MMC_WRITE_BLOCK
||
320 cmdr
== MMC_WRITE_MULTIPLE_BLOCK
||
321 cmdr
== MMC_SEND_TUNING_BLOCK
||
322 cmdr
== MMC_SEND_TUNING_BLOCK_HS200
) {
323 stop
->opcode
= MMC_STOP_TRANSMISSION
;
325 stop
->flags
= MMC_RSP_R1B
| MMC_CMD_AC
;
326 } else if (cmdr
== SD_IO_RW_EXTENDED
) {
327 stop
->opcode
= SD_IO_RW_DIRECT
;
328 stop
->arg
|= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT
<< 9) |
329 ((cmd
->arg
>> 28) & 0x7);
330 stop
->flags
= MMC_RSP_SPI_R5
| MMC_RSP_R5
| MMC_CMD_AC
;
335 cmdr
= stop
->opcode
| SDMMC_CMD_STOP
|
336 SDMMC_CMD_RESP_CRC
| SDMMC_CMD_RESP_EXP
;
341 static void dw_mci_wait_while_busy(struct dw_mci
*host
, u32 cmd_flags
)
343 unsigned long timeout
= jiffies
+ msecs_to_jiffies(500);
346 * Databook says that before issuing a new data transfer command
347 * we need to check to see if the card is busy. Data transfer commands
348 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
350 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
353 if ((cmd_flags
& SDMMC_CMD_PRV_DAT_WAIT
) &&
354 !(cmd_flags
& SDMMC_CMD_VOLT_SWITCH
)) {
355 while (mci_readl(host
, STATUS
) & SDMMC_STATUS_BUSY
) {
356 if (time_after(jiffies
, timeout
)) {
357 /* Command will fail; we'll pass error then */
358 dev_err(host
->dev
, "Busy; trying anyway\n");
366 static void dw_mci_start_command(struct dw_mci
*host
,
367 struct mmc_command
*cmd
, u32 cmd_flags
)
371 "start command: ARGR=0x%08x CMDR=0x%08x\n",
372 cmd
->arg
, cmd_flags
);
374 mci_writel(host
, CMDARG
, cmd
->arg
);
375 wmb(); /* drain writebuffer */
376 dw_mci_wait_while_busy(host
, cmd_flags
);
378 mci_writel(host
, CMD
, cmd_flags
| SDMMC_CMD_START
);
381 static inline void send_stop_abort(struct dw_mci
*host
, struct mmc_data
*data
)
383 struct mmc_command
*stop
= data
->stop
? data
->stop
: &host
->stop_abort
;
385 dw_mci_start_command(host
, stop
, host
->stop_cmdr
);
388 /* DMA interface functions */
389 static void dw_mci_stop_dma(struct dw_mci
*host
)
391 if (host
->using_dma
) {
392 host
->dma_ops
->stop(host
);
393 host
->dma_ops
->cleanup(host
);
396 /* Data transfer was stopped by the interrupt handler */
397 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
400 static int dw_mci_get_dma_dir(struct mmc_data
*data
)
402 if (data
->flags
& MMC_DATA_WRITE
)
403 return DMA_TO_DEVICE
;
405 return DMA_FROM_DEVICE
;
408 static void dw_mci_dma_cleanup(struct dw_mci
*host
)
410 struct mmc_data
*data
= host
->data
;
413 if (!data
->host_cookie
)
414 dma_unmap_sg(host
->dev
,
417 dw_mci_get_dma_dir(data
));
420 static void dw_mci_idmac_reset(struct dw_mci
*host
)
422 u32 bmod
= mci_readl(host
, BMOD
);
423 /* Software reset of DMA */
424 bmod
|= SDMMC_IDMAC_SWRESET
;
425 mci_writel(host
, BMOD
, bmod
);
428 static void dw_mci_idmac_stop_dma(struct dw_mci
*host
)
432 /* Disable and reset the IDMAC interface */
433 temp
= mci_readl(host
, CTRL
);
434 temp
&= ~SDMMC_CTRL_USE_IDMAC
;
435 temp
|= SDMMC_CTRL_DMA_RESET
;
436 mci_writel(host
, CTRL
, temp
);
438 /* Stop the IDMAC running */
439 temp
= mci_readl(host
, BMOD
);
440 temp
&= ~(SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
);
441 temp
|= SDMMC_IDMAC_SWRESET
;
442 mci_writel(host
, BMOD
, temp
);
445 static void dw_mci_dmac_complete_dma(void *arg
)
447 struct dw_mci
*host
= arg
;
448 struct mmc_data
*data
= host
->data
;
450 dev_vdbg(host
->dev
, "DMA complete\n");
452 if ((host
->use_dma
== TRANS_MODE_EDMAC
) &&
453 data
&& (data
->flags
& MMC_DATA_READ
))
454 /* Invalidate cache after read */
455 dma_sync_sg_for_cpu(mmc_dev(host
->cur_slot
->mmc
),
460 host
->dma_ops
->cleanup(host
);
463 * If the card was removed, data will be NULL. No point in trying to
464 * send the stop command or waiting for NBUSY in this case.
467 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
468 tasklet_schedule(&host
->tasklet
);
472 static void dw_mci_translate_sglist(struct dw_mci
*host
, struct mmc_data
*data
,
475 unsigned int desc_len
;
478 if (host
->dma_64bit_address
== 1) {
479 struct idmac_desc_64addr
*desc_first
, *desc_last
, *desc
;
481 desc_first
= desc_last
= desc
= host
->sg_cpu
;
483 for (i
= 0; i
< sg_len
; i
++) {
484 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
486 u64 mem_addr
= sg_dma_address(&data
->sg
[i
]);
488 for ( ; length
; desc
++) {
489 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
490 length
: DW_MCI_DESC_DATA_LENGTH
;
495 * Set the OWN bit and disable interrupts
496 * for this descriptor
498 desc
->des0
= IDMAC_DES0_OWN
| IDMAC_DES0_DIC
|
502 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc
, desc_len
);
504 /* Physical address to DMA to/from */
505 desc
->des4
= mem_addr
& 0xffffffff;
506 desc
->des5
= mem_addr
>> 32;
508 /* Update physical address for the next desc */
509 mem_addr
+= desc_len
;
511 /* Save pointer to the last descriptor */
516 /* Set first descriptor */
517 desc_first
->des0
|= IDMAC_DES0_FD
;
519 /* Set last descriptor */
520 desc_last
->des0
&= ~(IDMAC_DES0_CH
| IDMAC_DES0_DIC
);
521 desc_last
->des0
|= IDMAC_DES0_LD
;
524 struct idmac_desc
*desc_first
, *desc_last
, *desc
;
526 desc_first
= desc_last
= desc
= host
->sg_cpu
;
528 for (i
= 0; i
< sg_len
; i
++) {
529 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
531 u32 mem_addr
= sg_dma_address(&data
->sg
[i
]);
533 for ( ; length
; desc
++) {
534 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
535 length
: DW_MCI_DESC_DATA_LENGTH
;
540 * Set the OWN bit and disable interrupts
541 * for this descriptor
543 desc
->des0
= cpu_to_le32(IDMAC_DES0_OWN
|
548 IDMAC_SET_BUFFER1_SIZE(desc
, desc_len
);
550 /* Physical address to DMA to/from */
551 desc
->des2
= cpu_to_le32(mem_addr
);
553 /* Update physical address for the next desc */
554 mem_addr
+= desc_len
;
556 /* Save pointer to the last descriptor */
561 /* Set first descriptor */
562 desc_first
->des0
|= cpu_to_le32(IDMAC_DES0_FD
);
564 /* Set last descriptor */
565 desc_last
->des0
&= cpu_to_le32(~(IDMAC_DES0_CH
|
567 desc_last
->des0
|= cpu_to_le32(IDMAC_DES0_LD
);
570 wmb(); /* drain writebuffer */
573 static int dw_mci_idmac_start_dma(struct dw_mci
*host
, unsigned int sg_len
)
577 dw_mci_translate_sglist(host
, host
->data
, sg_len
);
579 /* Make sure to reset DMA in case we did PIO before this */
580 dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
);
581 dw_mci_idmac_reset(host
);
583 /* Select IDMAC interface */
584 temp
= mci_readl(host
, CTRL
);
585 temp
|= SDMMC_CTRL_USE_IDMAC
;
586 mci_writel(host
, CTRL
, temp
);
588 /* drain writebuffer */
591 /* Enable the IDMAC */
592 temp
= mci_readl(host
, BMOD
);
593 temp
|= SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
;
594 mci_writel(host
, BMOD
, temp
);
596 /* Start it running */
597 mci_writel(host
, PLDMND
, 1);
602 static int dw_mci_idmac_init(struct dw_mci
*host
)
606 if (host
->dma_64bit_address
== 1) {
607 struct idmac_desc_64addr
*p
;
608 /* Number of descriptors in the ring buffer */
609 host
->ring_size
= PAGE_SIZE
/ sizeof(struct idmac_desc_64addr
);
611 /* Forward link the descriptor list */
612 for (i
= 0, p
= host
->sg_cpu
; i
< host
->ring_size
- 1;
614 p
->des6
= (host
->sg_dma
+
615 (sizeof(struct idmac_desc_64addr
) *
616 (i
+ 1))) & 0xffffffff;
618 p
->des7
= (u64
)(host
->sg_dma
+
619 (sizeof(struct idmac_desc_64addr
) *
621 /* Initialize reserved and buffer size fields to "0" */
627 /* Set the last descriptor as the end-of-ring descriptor */
628 p
->des6
= host
->sg_dma
& 0xffffffff;
629 p
->des7
= (u64
)host
->sg_dma
>> 32;
630 p
->des0
= IDMAC_DES0_ER
;
633 struct idmac_desc
*p
;
634 /* Number of descriptors in the ring buffer */
635 host
->ring_size
= PAGE_SIZE
/ sizeof(struct idmac_desc
);
637 /* Forward link the descriptor list */
638 for (i
= 0, p
= host
->sg_cpu
;
639 i
< host
->ring_size
- 1;
641 p
->des3
= cpu_to_le32(host
->sg_dma
+
642 (sizeof(struct idmac_desc
) * (i
+ 1)));
646 /* Set the last descriptor as the end-of-ring descriptor */
647 p
->des3
= cpu_to_le32(host
->sg_dma
);
648 p
->des0
= cpu_to_le32(IDMAC_DES0_ER
);
651 dw_mci_idmac_reset(host
);
653 if (host
->dma_64bit_address
== 1) {
654 /* Mask out interrupts - get Tx & Rx complete only */
655 mci_writel(host
, IDSTS64
, IDMAC_INT_CLR
);
656 mci_writel(host
, IDINTEN64
, SDMMC_IDMAC_INT_NI
|
657 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
659 /* Set the descriptor base address */
660 mci_writel(host
, DBADDRL
, host
->sg_dma
& 0xffffffff);
661 mci_writel(host
, DBADDRU
, (u64
)host
->sg_dma
>> 32);
664 /* Mask out interrupts - get Tx & Rx complete only */
665 mci_writel(host
, IDSTS
, IDMAC_INT_CLR
);
666 mci_writel(host
, IDINTEN
, SDMMC_IDMAC_INT_NI
|
667 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
669 /* Set the descriptor base address */
670 mci_writel(host
, DBADDR
, host
->sg_dma
);
676 static const struct dw_mci_dma_ops dw_mci_idmac_ops
= {
677 .init
= dw_mci_idmac_init
,
678 .start
= dw_mci_idmac_start_dma
,
679 .stop
= dw_mci_idmac_stop_dma
,
680 .complete
= dw_mci_dmac_complete_dma
,
681 .cleanup
= dw_mci_dma_cleanup
,
684 static void dw_mci_edmac_stop_dma(struct dw_mci
*host
)
686 dmaengine_terminate_all(host
->dms
->ch
);
689 static int dw_mci_edmac_start_dma(struct dw_mci
*host
,
692 struct dma_slave_config cfg
;
693 struct dma_async_tx_descriptor
*desc
= NULL
;
694 struct scatterlist
*sgl
= host
->data
->sg
;
695 const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
696 u32 sg_elems
= host
->data
->sg_len
;
698 u32 fifo_offset
= host
->fifo_reg
- host
->regs
;
701 /* Set external dma config: burst size, burst width */
702 cfg
.dst_addr
= host
->phy_regs
+ fifo_offset
;
703 cfg
.src_addr
= cfg
.dst_addr
;
704 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
705 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
707 /* Match burst msize with external dma config */
708 fifoth_val
= mci_readl(host
, FIFOTH
);
709 cfg
.dst_maxburst
= mszs
[(fifoth_val
>> 28) & 0x7];
710 cfg
.src_maxburst
= cfg
.dst_maxburst
;
712 if (host
->data
->flags
& MMC_DATA_WRITE
)
713 cfg
.direction
= DMA_MEM_TO_DEV
;
715 cfg
.direction
= DMA_DEV_TO_MEM
;
717 ret
= dmaengine_slave_config(host
->dms
->ch
, &cfg
);
719 dev_err(host
->dev
, "Failed to config edmac.\n");
723 desc
= dmaengine_prep_slave_sg(host
->dms
->ch
, sgl
,
724 sg_len
, cfg
.direction
,
725 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
727 dev_err(host
->dev
, "Can't prepare slave sg.\n");
731 /* Set dw_mci_dmac_complete_dma as callback */
732 desc
->callback
= dw_mci_dmac_complete_dma
;
733 desc
->callback_param
= (void *)host
;
734 dmaengine_submit(desc
);
736 /* Flush cache before write */
737 if (host
->data
->flags
& MMC_DATA_WRITE
)
738 dma_sync_sg_for_device(mmc_dev(host
->cur_slot
->mmc
), sgl
,
739 sg_elems
, DMA_TO_DEVICE
);
741 dma_async_issue_pending(host
->dms
->ch
);
746 static int dw_mci_edmac_init(struct dw_mci
*host
)
748 /* Request external dma channel */
749 host
->dms
= kzalloc(sizeof(struct dw_mci_dma_slave
), GFP_KERNEL
);
753 host
->dms
->ch
= dma_request_slave_channel(host
->dev
, "rx-tx");
754 if (!host
->dms
->ch
) {
755 dev_err(host
->dev
, "Failed to get external DMA channel.\n");
764 static void dw_mci_edmac_exit(struct dw_mci
*host
)
768 dma_release_channel(host
->dms
->ch
);
769 host
->dms
->ch
= NULL
;
776 static const struct dw_mci_dma_ops dw_mci_edmac_ops
= {
777 .init
= dw_mci_edmac_init
,
778 .exit
= dw_mci_edmac_exit
,
779 .start
= dw_mci_edmac_start_dma
,
780 .stop
= dw_mci_edmac_stop_dma
,
781 .complete
= dw_mci_dmac_complete_dma
,
782 .cleanup
= dw_mci_dma_cleanup
,
785 static int dw_mci_pre_dma_transfer(struct dw_mci
*host
,
786 struct mmc_data
*data
,
789 struct scatterlist
*sg
;
790 unsigned int i
, sg_len
;
792 if (!next
&& data
->host_cookie
)
793 return data
->host_cookie
;
796 * We don't do DMA on "complex" transfers, i.e. with
797 * non-word-aligned buffers or lengths. Also, we don't bother
798 * with all the DMA setup overhead for short transfers.
800 if (data
->blocks
* data
->blksz
< DW_MCI_DMA_THRESHOLD
)
806 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
807 if (sg
->offset
& 3 || sg
->length
& 3)
811 sg_len
= dma_map_sg(host
->dev
,
814 dw_mci_get_dma_dir(data
));
819 data
->host_cookie
= sg_len
;
824 static void dw_mci_pre_req(struct mmc_host
*mmc
,
825 struct mmc_request
*mrq
,
828 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
829 struct mmc_data
*data
= mrq
->data
;
831 if (!slot
->host
->use_dma
|| !data
)
834 if (data
->host_cookie
) {
835 data
->host_cookie
= 0;
839 if (dw_mci_pre_dma_transfer(slot
->host
, mrq
->data
, 1) < 0)
840 data
->host_cookie
= 0;
843 static void dw_mci_post_req(struct mmc_host
*mmc
,
844 struct mmc_request
*mrq
,
847 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
848 struct mmc_data
*data
= mrq
->data
;
850 if (!slot
->host
->use_dma
|| !data
)
853 if (data
->host_cookie
)
854 dma_unmap_sg(slot
->host
->dev
,
857 dw_mci_get_dma_dir(data
));
858 data
->host_cookie
= 0;
861 static void dw_mci_adjust_fifoth(struct dw_mci
*host
, struct mmc_data
*data
)
863 unsigned int blksz
= data
->blksz
;
864 const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
865 u32 fifo_width
= 1 << host
->data_shift
;
866 u32 blksz_depth
= blksz
/ fifo_width
, fifoth_val
;
867 u32 msize
= 0, rx_wmark
= 1, tx_wmark
, tx_wmark_invers
;
868 int idx
= ARRAY_SIZE(mszs
) - 1;
870 /* pio should ship this scenario */
874 tx_wmark
= (host
->fifo_depth
) / 2;
875 tx_wmark_invers
= host
->fifo_depth
- tx_wmark
;
879 * if blksz is not a multiple of the FIFO width
881 if (blksz
% fifo_width
) {
888 if (!((blksz_depth
% mszs
[idx
]) ||
889 (tx_wmark_invers
% mszs
[idx
]))) {
891 rx_wmark
= mszs
[idx
] - 1;
896 * If idx is '0', it won't be tried
897 * Thus, initial values are uesed
900 fifoth_val
= SDMMC_SET_FIFOTH(msize
, rx_wmark
, tx_wmark
);
901 mci_writel(host
, FIFOTH
, fifoth_val
);
904 static void dw_mci_ctrl_rd_thld(struct dw_mci
*host
, struct mmc_data
*data
)
906 unsigned int blksz
= data
->blksz
;
907 u32 blksz_depth
, fifo_depth
;
910 WARN_ON(!(data
->flags
& MMC_DATA_READ
));
913 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
914 * in the FIFO region, so we really shouldn't access it).
916 if (host
->verid
< DW_MMC_240A
)
919 if (host
->timing
!= MMC_TIMING_MMC_HS200
&&
920 host
->timing
!= MMC_TIMING_MMC_HS400
&&
921 host
->timing
!= MMC_TIMING_UHS_SDR104
)
924 blksz_depth
= blksz
/ (1 << host
->data_shift
);
925 fifo_depth
= host
->fifo_depth
;
927 if (blksz_depth
> fifo_depth
)
931 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
932 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
933 * Currently just choose blksz.
936 mci_writel(host
, CDTHRCTL
, SDMMC_SET_RD_THLD(thld_size
, 1));
940 mci_writel(host
, CDTHRCTL
, SDMMC_SET_RD_THLD(0, 0));
943 static int dw_mci_submit_data_dma(struct dw_mci
*host
, struct mmc_data
*data
)
945 unsigned long irqflags
;
951 /* If we don't have a channel, we can't do DMA */
955 sg_len
= dw_mci_pre_dma_transfer(host
, data
, 0);
957 host
->dma_ops
->stop(host
);
963 if (host
->use_dma
== TRANS_MODE_IDMAC
)
965 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
966 (unsigned long)host
->sg_cpu
,
967 (unsigned long)host
->sg_dma
,
971 * Decide the MSIZE and RX/TX Watermark.
972 * If current block size is same with previous size,
973 * no need to update fifoth.
975 if (host
->prev_blksz
!= data
->blksz
)
976 dw_mci_adjust_fifoth(host
, data
);
978 /* Enable the DMA interface */
979 temp
= mci_readl(host
, CTRL
);
980 temp
|= SDMMC_CTRL_DMA_ENABLE
;
981 mci_writel(host
, CTRL
, temp
);
983 /* Disable RX/TX IRQs, let DMA handle it */
984 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
985 temp
= mci_readl(host
, INTMASK
);
986 temp
&= ~(SDMMC_INT_RXDR
| SDMMC_INT_TXDR
);
987 mci_writel(host
, INTMASK
, temp
);
988 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
990 if (host
->dma_ops
->start(host
, sg_len
)) {
991 /* We can't do DMA */
992 dev_err(host
->dev
, "%s: failed to start DMA.\n", __func__
);
999 static void dw_mci_submit_data(struct dw_mci
*host
, struct mmc_data
*data
)
1001 unsigned long irqflags
;
1002 int flags
= SG_MITER_ATOMIC
;
1005 data
->error
= -EINPROGRESS
;
1007 WARN_ON(host
->data
);
1011 if (data
->flags
& MMC_DATA_READ
) {
1012 host
->dir_status
= DW_MCI_RECV_STATUS
;
1013 dw_mci_ctrl_rd_thld(host
, data
);
1015 host
->dir_status
= DW_MCI_SEND_STATUS
;
1018 if (dw_mci_submit_data_dma(host
, data
)) {
1019 if (host
->data
->flags
& MMC_DATA_READ
)
1020 flags
|= SG_MITER_TO_SG
;
1022 flags
|= SG_MITER_FROM_SG
;
1024 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
1025 host
->sg
= data
->sg
;
1026 host
->part_buf_start
= 0;
1027 host
->part_buf_count
= 0;
1029 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
| SDMMC_INT_RXDR
);
1031 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1032 temp
= mci_readl(host
, INTMASK
);
1033 temp
|= SDMMC_INT_TXDR
| SDMMC_INT_RXDR
;
1034 mci_writel(host
, INTMASK
, temp
);
1035 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1037 temp
= mci_readl(host
, CTRL
);
1038 temp
&= ~SDMMC_CTRL_DMA_ENABLE
;
1039 mci_writel(host
, CTRL
, temp
);
1042 * Use the initial fifoth_val for PIO mode.
1043 * If next issued data may be transfered by DMA mode,
1044 * prev_blksz should be invalidated.
1046 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
1047 host
->prev_blksz
= 0;
1050 * Keep the current block size.
1051 * It will be used to decide whether to update
1052 * fifoth register next time.
1054 host
->prev_blksz
= data
->blksz
;
1058 static void mci_send_cmd(struct dw_mci_slot
*slot
, u32 cmd
, u32 arg
)
1060 struct dw_mci
*host
= slot
->host
;
1061 unsigned long timeout
= jiffies
+ msecs_to_jiffies(500);
1062 unsigned int cmd_status
= 0;
1064 mci_writel(host
, CMDARG
, arg
);
1065 wmb(); /* drain writebuffer */
1066 dw_mci_wait_while_busy(host
, cmd
);
1067 mci_writel(host
, CMD
, SDMMC_CMD_START
| cmd
);
1069 while (time_before(jiffies
, timeout
)) {
1070 cmd_status
= mci_readl(host
, CMD
);
1071 if (!(cmd_status
& SDMMC_CMD_START
))
1074 dev_err(&slot
->mmc
->class_dev
,
1075 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1076 cmd
, arg
, cmd_status
);
1079 static void dw_mci_setup_bus(struct dw_mci_slot
*slot
, bool force_clkinit
)
1081 struct dw_mci
*host
= slot
->host
;
1082 unsigned int clock
= slot
->clock
;
1085 u32 sdmmc_cmd_bits
= SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
;
1087 /* We must continue to set bit 28 in CMD until the change is complete */
1088 if (host
->state
== STATE_WAITING_CMD11_DONE
)
1089 sdmmc_cmd_bits
|= SDMMC_CMD_VOLT_SWITCH
;
1092 mci_writel(host
, CLKENA
, 0);
1093 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1094 } else if (clock
!= host
->current_speed
|| force_clkinit
) {
1095 div
= host
->bus_hz
/ clock
;
1096 if (host
->bus_hz
% clock
&& host
->bus_hz
> clock
)
1098 * move the + 1 after the divide to prevent
1099 * over-clocking the card.
1103 div
= (host
->bus_hz
!= clock
) ? DIV_ROUND_UP(div
, 2) : 0;
1105 if ((clock
<< div
) != slot
->__clk_old
|| force_clkinit
)
1106 dev_info(&slot
->mmc
->class_dev
,
1107 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1108 slot
->id
, host
->bus_hz
, clock
,
1109 div
? ((host
->bus_hz
/ div
) >> 1) :
1113 mci_writel(host
, CLKENA
, 0);
1114 mci_writel(host
, CLKSRC
, 0);
1117 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1119 /* set clock to desired speed */
1120 mci_writel(host
, CLKDIV
, div
);
1123 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1125 /* enable clock; only low power if no SDIO */
1126 clk_en_a
= SDMMC_CLKEN_ENABLE
<< slot
->id
;
1127 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
))
1128 clk_en_a
|= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1129 mci_writel(host
, CLKENA
, clk_en_a
);
1132 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1134 /* keep the clock with reflecting clock dividor */
1135 slot
->__clk_old
= clock
<< div
;
1138 host
->current_speed
= clock
;
1140 /* Set the current slot bus width */
1141 mci_writel(host
, CTYPE
, (slot
->ctype
<< slot
->id
));
1144 static void __dw_mci_start_request(struct dw_mci
*host
,
1145 struct dw_mci_slot
*slot
,
1146 struct mmc_command
*cmd
)
1148 struct mmc_request
*mrq
;
1149 struct mmc_data
*data
;
1154 host
->cur_slot
= slot
;
1157 host
->pending_events
= 0;
1158 host
->completed_events
= 0;
1159 host
->cmd_status
= 0;
1160 host
->data_status
= 0;
1161 host
->dir_status
= 0;
1165 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
1166 mci_writel(host
, BYTCNT
, data
->blksz
*data
->blocks
);
1167 mci_writel(host
, BLKSIZ
, data
->blksz
);
1170 cmdflags
= dw_mci_prepare_command(slot
->mmc
, cmd
);
1172 /* this is the first command, send the initialization clock */
1173 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
))
1174 cmdflags
|= SDMMC_CMD_INIT
;
1177 dw_mci_submit_data(host
, data
);
1178 wmb(); /* drain writebuffer */
1181 dw_mci_start_command(host
, cmd
, cmdflags
);
1183 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
1184 unsigned long irqflags
;
1187 * Databook says to fail after 2ms w/ no response, but evidence
1188 * shows that sometimes the cmd11 interrupt takes over 130ms.
1189 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1190 * is just about to roll over.
1192 * We do this whole thing under spinlock and only if the
1193 * command hasn't already completed (indicating the the irq
1194 * already ran so we don't want the timeout).
1196 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1197 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
1198 mod_timer(&host
->cmd11_timer
,
1199 jiffies
+ msecs_to_jiffies(500) + 1);
1200 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1204 host
->stop_cmdr
= dw_mci_prepare_command(slot
->mmc
, mrq
->stop
);
1206 host
->stop_cmdr
= dw_mci_prep_stop_abort(host
, cmd
);
1209 static void dw_mci_start_request(struct dw_mci
*host
,
1210 struct dw_mci_slot
*slot
)
1212 struct mmc_request
*mrq
= slot
->mrq
;
1213 struct mmc_command
*cmd
;
1215 cmd
= mrq
->sbc
? mrq
->sbc
: mrq
->cmd
;
1216 __dw_mci_start_request(host
, slot
, cmd
);
1219 /* must be called with host->lock held */
1220 static void dw_mci_queue_request(struct dw_mci
*host
, struct dw_mci_slot
*slot
,
1221 struct mmc_request
*mrq
)
1223 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
1228 if (host
->state
== STATE_WAITING_CMD11_DONE
) {
1229 dev_warn(&slot
->mmc
->class_dev
,
1230 "Voltage change didn't complete\n");
1232 * this case isn't expected to happen, so we can
1233 * either crash here or just try to continue on
1234 * in the closest possible state
1236 host
->state
= STATE_IDLE
;
1239 if (host
->state
== STATE_IDLE
) {
1240 host
->state
= STATE_SENDING_CMD
;
1241 dw_mci_start_request(host
, slot
);
1243 list_add_tail(&slot
->queue_node
, &host
->queue
);
1247 static void dw_mci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1249 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1250 struct dw_mci
*host
= slot
->host
;
1255 * The check for card presence and queueing of the request must be
1256 * atomic, otherwise the card could be removed in between and the
1257 * request wouldn't fail until another card was inserted.
1259 spin_lock_bh(&host
->lock
);
1261 if (!test_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
)) {
1262 spin_unlock_bh(&host
->lock
);
1263 mrq
->cmd
->error
= -ENOMEDIUM
;
1264 mmc_request_done(mmc
, mrq
);
1268 dw_mci_queue_request(host
, slot
, mrq
);
1270 spin_unlock_bh(&host
->lock
);
1273 static void dw_mci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1275 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1276 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
1280 switch (ios
->bus_width
) {
1281 case MMC_BUS_WIDTH_4
:
1282 slot
->ctype
= SDMMC_CTYPE_4BIT
;
1284 case MMC_BUS_WIDTH_8
:
1285 slot
->ctype
= SDMMC_CTYPE_8BIT
;
1288 /* set default 1 bit mode */
1289 slot
->ctype
= SDMMC_CTYPE_1BIT
;
1292 regs
= mci_readl(slot
->host
, UHS_REG
);
1295 if (ios
->timing
== MMC_TIMING_MMC_DDR52
||
1296 ios
->timing
== MMC_TIMING_UHS_DDR50
||
1297 ios
->timing
== MMC_TIMING_MMC_HS400
)
1298 regs
|= ((0x1 << slot
->id
) << 16);
1300 regs
&= ~((0x1 << slot
->id
) << 16);
1302 mci_writel(slot
->host
, UHS_REG
, regs
);
1303 slot
->host
->timing
= ios
->timing
;
1306 * Use mirror of ios->clock to prevent race with mmc
1307 * core ios update when finding the minimum.
1309 slot
->clock
= ios
->clock
;
1311 if (drv_data
&& drv_data
->set_ios
)
1312 drv_data
->set_ios(slot
->host
, ios
);
1314 switch (ios
->power_mode
) {
1316 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1317 ret
= mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
,
1320 dev_err(slot
->host
->dev
,
1321 "failed to enable vmmc regulator\n");
1322 /*return, if failed turn on vmmc*/
1326 set_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
);
1327 regs
= mci_readl(slot
->host
, PWREN
);
1328 regs
|= (1 << slot
->id
);
1329 mci_writel(slot
->host
, PWREN
, regs
);
1332 if (!slot
->host
->vqmmc_enabled
) {
1333 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1334 ret
= regulator_enable(mmc
->supply
.vqmmc
);
1336 dev_err(slot
->host
->dev
,
1337 "failed to enable vqmmc\n");
1339 slot
->host
->vqmmc_enabled
= true;
1342 /* Keep track so we don't reset again */
1343 slot
->host
->vqmmc_enabled
= true;
1346 /* Reset our state machine after powering on */
1347 dw_mci_ctrl_reset(slot
->host
,
1348 SDMMC_CTRL_ALL_RESET_FLAGS
);
1351 /* Adjust clock / bus width after power is up */
1352 dw_mci_setup_bus(slot
, false);
1356 /* Turn clock off before power goes down */
1357 dw_mci_setup_bus(slot
, false);
1359 if (!IS_ERR(mmc
->supply
.vmmc
))
1360 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1362 if (!IS_ERR(mmc
->supply
.vqmmc
) && slot
->host
->vqmmc_enabled
)
1363 regulator_disable(mmc
->supply
.vqmmc
);
1364 slot
->host
->vqmmc_enabled
= false;
1366 regs
= mci_readl(slot
->host
, PWREN
);
1367 regs
&= ~(1 << slot
->id
);
1368 mci_writel(slot
->host
, PWREN
, regs
);
1374 if (slot
->host
->state
== STATE_WAITING_CMD11_DONE
&& ios
->clock
!= 0)
1375 slot
->host
->state
= STATE_IDLE
;
1378 static int dw_mci_card_busy(struct mmc_host
*mmc
)
1380 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1384 * Check the busy bit which is low when DAT[3:0]
1385 * (the data lines) are 0000
1387 status
= mci_readl(slot
->host
, STATUS
);
1389 return !!(status
& SDMMC_STATUS_BUSY
);
1392 static int dw_mci_switch_voltage(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1394 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1395 struct dw_mci
*host
= slot
->host
;
1396 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1398 u32 v18
= SDMMC_UHS_18V
<< slot
->id
;
1401 if (drv_data
&& drv_data
->switch_voltage
)
1402 return drv_data
->switch_voltage(mmc
, ios
);
1405 * Program the voltage. Note that some instances of dw_mmc may use
1406 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1407 * does no harm but you need to set the regulator directly. Try both.
1409 uhs
= mci_readl(host
, UHS_REG
);
1410 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
1415 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1416 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1419 dev_dbg(&mmc
->class_dev
,
1420 "Regulator set error %d - %s V\n",
1421 ret
, uhs
& v18
? "1.8" : "3.3");
1425 mci_writel(host
, UHS_REG
, uhs
);
1430 static int dw_mci_get_ro(struct mmc_host
*mmc
)
1433 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1434 int gpio_ro
= mmc_gpio_get_ro(mmc
);
1436 /* Use platform get_ro function, else try on board write protect */
1437 if (!IS_ERR_VALUE(gpio_ro
))
1438 read_only
= gpio_ro
;
1441 mci_readl(slot
->host
, WRTPRT
) & (1 << slot
->id
) ? 1 : 0;
1443 dev_dbg(&mmc
->class_dev
, "card is %s\n",
1444 read_only
? "read-only" : "read-write");
1449 static int dw_mci_get_cd(struct mmc_host
*mmc
)
1452 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1453 struct dw_mci_board
*brd
= slot
->host
->pdata
;
1454 struct dw_mci
*host
= slot
->host
;
1455 int gpio_cd
= mmc_gpio_get_cd(mmc
);
1457 /* Use platform get_cd function, else try onboard card detect */
1458 if ((brd
->quirks
& DW_MCI_QUIRK_BROKEN_CARD_DETECTION
) ||
1459 (mmc
->caps
& MMC_CAP_NONREMOVABLE
))
1461 else if (!IS_ERR_VALUE(gpio_cd
))
1464 present
= (mci_readl(slot
->host
, CDETECT
) & (1 << slot
->id
))
1467 spin_lock_bh(&host
->lock
);
1469 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1470 dev_dbg(&mmc
->class_dev
, "card is present\n");
1472 clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
1473 dev_dbg(&mmc
->class_dev
, "card is not present\n");
1475 spin_unlock_bh(&host
->lock
);
1480 static void dw_mci_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1482 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1483 struct dw_mci
*host
= slot
->host
;
1486 * Low power mode will stop the card clock when idle. According to the
1487 * description of the CLKENA register we should disable low power mode
1488 * for SDIO cards if we need SDIO interrupts to work.
1490 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
) {
1491 const u32 clken_low_pwr
= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1495 clk_en_a_old
= mci_readl(host
, CLKENA
);
1497 if (card
->type
== MMC_TYPE_SDIO
||
1498 card
->type
== MMC_TYPE_SD_COMBO
) {
1499 set_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1500 clk_en_a
= clk_en_a_old
& ~clken_low_pwr
;
1502 clear_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1503 clk_en_a
= clk_en_a_old
| clken_low_pwr
;
1506 if (clk_en_a
!= clk_en_a_old
) {
1507 mci_writel(host
, CLKENA
, clk_en_a
);
1508 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
1509 SDMMC_CMD_PRV_DAT_WAIT
, 0);
1514 static void dw_mci_enable_sdio_irq(struct mmc_host
*mmc
, int enb
)
1516 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1517 struct dw_mci
*host
= slot
->host
;
1518 unsigned long irqflags
;
1521 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1523 /* Enable/disable Slot Specific SDIO interrupt */
1524 int_mask
= mci_readl(host
, INTMASK
);
1526 int_mask
|= SDMMC_INT_SDIO(slot
->sdio_id
);
1528 int_mask
&= ~SDMMC_INT_SDIO(slot
->sdio_id
);
1529 mci_writel(host
, INTMASK
, int_mask
);
1531 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1534 static int dw_mci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1536 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1537 struct dw_mci
*host
= slot
->host
;
1538 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1541 if (drv_data
&& drv_data
->execute_tuning
)
1542 err
= drv_data
->execute_tuning(slot
, opcode
);
1546 static int dw_mci_prepare_hs400_tuning(struct mmc_host
*mmc
,
1547 struct mmc_ios
*ios
)
1549 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1550 struct dw_mci
*host
= slot
->host
;
1551 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1553 if (drv_data
&& drv_data
->prepare_hs400_tuning
)
1554 return drv_data
->prepare_hs400_tuning(host
, ios
);
1559 static const struct mmc_host_ops dw_mci_ops
= {
1560 .request
= dw_mci_request
,
1561 .pre_req
= dw_mci_pre_req
,
1562 .post_req
= dw_mci_post_req
,
1563 .set_ios
= dw_mci_set_ios
,
1564 .get_ro
= dw_mci_get_ro
,
1565 .get_cd
= dw_mci_get_cd
,
1566 .enable_sdio_irq
= dw_mci_enable_sdio_irq
,
1567 .execute_tuning
= dw_mci_execute_tuning
,
1568 .card_busy
= dw_mci_card_busy
,
1569 .start_signal_voltage_switch
= dw_mci_switch_voltage
,
1570 .init_card
= dw_mci_init_card
,
1571 .prepare_hs400_tuning
= dw_mci_prepare_hs400_tuning
,
1574 static void dw_mci_request_end(struct dw_mci
*host
, struct mmc_request
*mrq
)
1575 __releases(&host
->lock
)
1576 __acquires(&host
->lock
)
1578 struct dw_mci_slot
*slot
;
1579 struct mmc_host
*prev_mmc
= host
->cur_slot
->mmc
;
1581 WARN_ON(host
->cmd
|| host
->data
);
1583 host
->cur_slot
->mrq
= NULL
;
1585 if (!list_empty(&host
->queue
)) {
1586 slot
= list_entry(host
->queue
.next
,
1587 struct dw_mci_slot
, queue_node
);
1588 list_del(&slot
->queue_node
);
1589 dev_vdbg(host
->dev
, "list not empty: %s is next\n",
1590 mmc_hostname(slot
->mmc
));
1591 host
->state
= STATE_SENDING_CMD
;
1592 dw_mci_start_request(host
, slot
);
1594 dev_vdbg(host
->dev
, "list empty\n");
1596 if (host
->state
== STATE_SENDING_CMD11
)
1597 host
->state
= STATE_WAITING_CMD11_DONE
;
1599 host
->state
= STATE_IDLE
;
1602 spin_unlock(&host
->lock
);
1603 mmc_request_done(prev_mmc
, mrq
);
1604 spin_lock(&host
->lock
);
1607 static int dw_mci_command_complete(struct dw_mci
*host
, struct mmc_command
*cmd
)
1609 u32 status
= host
->cmd_status
;
1611 host
->cmd_status
= 0;
1613 /* Read the response from the card (up to 16 bytes) */
1614 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1615 if (cmd
->flags
& MMC_RSP_136
) {
1616 cmd
->resp
[3] = mci_readl(host
, RESP0
);
1617 cmd
->resp
[2] = mci_readl(host
, RESP1
);
1618 cmd
->resp
[1] = mci_readl(host
, RESP2
);
1619 cmd
->resp
[0] = mci_readl(host
, RESP3
);
1621 cmd
->resp
[0] = mci_readl(host
, RESP0
);
1628 if (status
& SDMMC_INT_RTO
)
1629 cmd
->error
= -ETIMEDOUT
;
1630 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& SDMMC_INT_RCRC
))
1631 cmd
->error
= -EILSEQ
;
1632 else if (status
& SDMMC_INT_RESP_ERR
)
1640 static int dw_mci_data_complete(struct dw_mci
*host
, struct mmc_data
*data
)
1642 u32 status
= host
->data_status
;
1644 if (status
& DW_MCI_DATA_ERROR_FLAGS
) {
1645 if (status
& SDMMC_INT_DRTO
) {
1646 data
->error
= -ETIMEDOUT
;
1647 } else if (status
& SDMMC_INT_DCRC
) {
1648 data
->error
= -EILSEQ
;
1649 } else if (status
& SDMMC_INT_EBE
) {
1650 if (host
->dir_status
==
1651 DW_MCI_SEND_STATUS
) {
1653 * No data CRC status was returned.
1654 * The number of bytes transferred
1655 * will be exaggerated in PIO mode.
1657 data
->bytes_xfered
= 0;
1658 data
->error
= -ETIMEDOUT
;
1659 } else if (host
->dir_status
==
1660 DW_MCI_RECV_STATUS
) {
1664 /* SDMMC_INT_SBE is included */
1668 dev_dbg(host
->dev
, "data error, status 0x%08x\n", status
);
1671 * After an error, there may be data lingering
1676 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1683 static void dw_mci_set_drto(struct dw_mci
*host
)
1685 unsigned int drto_clks
;
1686 unsigned int drto_ms
;
1688 drto_clks
= mci_readl(host
, TMOUT
) >> 8;
1689 drto_ms
= DIV_ROUND_UP(drto_clks
, host
->bus_hz
/ 1000);
1691 /* add a bit spare time */
1694 mod_timer(&host
->dto_timer
, jiffies
+ msecs_to_jiffies(drto_ms
));
1697 static void dw_mci_tasklet_func(unsigned long priv
)
1699 struct dw_mci
*host
= (struct dw_mci
*)priv
;
1700 struct mmc_data
*data
;
1701 struct mmc_command
*cmd
;
1702 struct mmc_request
*mrq
;
1703 enum dw_mci_state state
;
1704 enum dw_mci_state prev_state
;
1707 spin_lock(&host
->lock
);
1709 state
= host
->state
;
1718 case STATE_WAITING_CMD11_DONE
:
1721 case STATE_SENDING_CMD11
:
1722 case STATE_SENDING_CMD
:
1723 if (!test_and_clear_bit(EVENT_CMD_COMPLETE
,
1724 &host
->pending_events
))
1729 set_bit(EVENT_CMD_COMPLETE
, &host
->completed_events
);
1730 err
= dw_mci_command_complete(host
, cmd
);
1731 if (cmd
== mrq
->sbc
&& !err
) {
1732 prev_state
= state
= STATE_SENDING_CMD
;
1733 __dw_mci_start_request(host
, host
->cur_slot
,
1738 if (cmd
->data
&& err
) {
1739 dw_mci_stop_dma(host
);
1740 send_stop_abort(host
, data
);
1741 state
= STATE_SENDING_STOP
;
1745 if (!cmd
->data
|| err
) {
1746 dw_mci_request_end(host
, mrq
);
1750 prev_state
= state
= STATE_SENDING_DATA
;
1753 case STATE_SENDING_DATA
:
1755 * We could get a data error and never a transfer
1756 * complete so we'd better check for it here.
1758 * Note that we don't really care if we also got a
1759 * transfer complete; stopping the DMA and sending an
1762 if (test_and_clear_bit(EVENT_DATA_ERROR
,
1763 &host
->pending_events
)) {
1764 dw_mci_stop_dma(host
);
1766 !(host
->data_status
& (SDMMC_INT_DRTO
|
1768 send_stop_abort(host
, data
);
1769 state
= STATE_DATA_ERROR
;
1773 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
1774 &host
->pending_events
)) {
1776 * If all data-related interrupts don't come
1777 * within the given time in reading data state.
1779 if ((host
->quirks
& DW_MCI_QUIRK_BROKEN_DTO
) &&
1780 (host
->dir_status
== DW_MCI_RECV_STATUS
))
1781 dw_mci_set_drto(host
);
1785 set_bit(EVENT_XFER_COMPLETE
, &host
->completed_events
);
1788 * Handle an EVENT_DATA_ERROR that might have shown up
1789 * before the transfer completed. This might not have
1790 * been caught by the check above because the interrupt
1791 * could have gone off between the previous check and
1792 * the check for transfer complete.
1794 * Technically this ought not be needed assuming we
1795 * get a DATA_COMPLETE eventually (we'll notice the
1796 * error and end the request), but it shouldn't hurt.
1798 * This has the advantage of sending the stop command.
1800 if (test_and_clear_bit(EVENT_DATA_ERROR
,
1801 &host
->pending_events
)) {
1802 dw_mci_stop_dma(host
);
1804 !(host
->data_status
& (SDMMC_INT_DRTO
|
1806 send_stop_abort(host
, data
);
1807 state
= STATE_DATA_ERROR
;
1810 prev_state
= state
= STATE_DATA_BUSY
;
1814 case STATE_DATA_BUSY
:
1815 if (!test_and_clear_bit(EVENT_DATA_COMPLETE
,
1816 &host
->pending_events
)) {
1818 * If data error interrupt comes but data over
1819 * interrupt doesn't come within the given time.
1820 * in reading data state.
1822 if ((host
->quirks
& DW_MCI_QUIRK_BROKEN_DTO
) &&
1823 (host
->dir_status
== DW_MCI_RECV_STATUS
))
1824 dw_mci_set_drto(host
);
1829 set_bit(EVENT_DATA_COMPLETE
, &host
->completed_events
);
1830 err
= dw_mci_data_complete(host
, data
);
1833 if (!data
->stop
|| mrq
->sbc
) {
1834 if (mrq
->sbc
&& data
->stop
)
1835 data
->stop
->error
= 0;
1836 dw_mci_request_end(host
, mrq
);
1840 /* stop command for open-ended transfer*/
1842 send_stop_abort(host
, data
);
1845 * If we don't have a command complete now we'll
1846 * never get one since we just reset everything;
1847 * better end the request.
1849 * If we do have a command complete we'll fall
1850 * through to the SENDING_STOP command and
1851 * everything will be peachy keen.
1853 if (!test_bit(EVENT_CMD_COMPLETE
,
1854 &host
->pending_events
)) {
1856 dw_mci_request_end(host
, mrq
);
1862 * If err has non-zero,
1863 * stop-abort command has been already issued.
1865 prev_state
= state
= STATE_SENDING_STOP
;
1869 case STATE_SENDING_STOP
:
1870 if (!test_and_clear_bit(EVENT_CMD_COMPLETE
,
1871 &host
->pending_events
))
1874 /* CMD error in data command */
1875 if (mrq
->cmd
->error
&& mrq
->data
)
1882 dw_mci_command_complete(host
, mrq
->stop
);
1884 host
->cmd_status
= 0;
1886 dw_mci_request_end(host
, mrq
);
1889 case STATE_DATA_ERROR
:
1890 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
1891 &host
->pending_events
))
1894 state
= STATE_DATA_BUSY
;
1897 } while (state
!= prev_state
);
1899 host
->state
= state
;
1901 spin_unlock(&host
->lock
);
1905 /* push final bytes to part_buf, only use during push */
1906 static void dw_mci_set_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1908 memcpy((void *)&host
->part_buf
, buf
, cnt
);
1909 host
->part_buf_count
= cnt
;
1912 /* append bytes to part_buf, only use during push */
1913 static int dw_mci_push_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1915 cnt
= min(cnt
, (1 << host
->data_shift
) - host
->part_buf_count
);
1916 memcpy((void *)&host
->part_buf
+ host
->part_buf_count
, buf
, cnt
);
1917 host
->part_buf_count
+= cnt
;
1921 /* pull first bytes from part_buf, only use during pull */
1922 static int dw_mci_pull_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1924 cnt
= min_t(int, cnt
, host
->part_buf_count
);
1926 memcpy(buf
, (void *)&host
->part_buf
+ host
->part_buf_start
,
1928 host
->part_buf_count
-= cnt
;
1929 host
->part_buf_start
+= cnt
;
1934 /* pull final bytes from the part_buf, assuming it's just been filled */
1935 static void dw_mci_pull_final_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
1937 memcpy(buf
, &host
->part_buf
, cnt
);
1938 host
->part_buf_start
= cnt
;
1939 host
->part_buf_count
= (1 << host
->data_shift
) - cnt
;
1942 static void dw_mci_push_data16(struct dw_mci
*host
, void *buf
, int cnt
)
1944 struct mmc_data
*data
= host
->data
;
1947 /* try and push anything in the part_buf */
1948 if (unlikely(host
->part_buf_count
)) {
1949 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
1953 if (host
->part_buf_count
== 2) {
1954 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
1955 host
->part_buf_count
= 0;
1958 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1959 if (unlikely((unsigned long)buf
& 0x1)) {
1961 u16 aligned_buf
[64];
1962 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
1963 int items
= len
>> 1;
1965 /* memcpy from input buffer into aligned buffer */
1966 memcpy(aligned_buf
, buf
, len
);
1969 /* push data from aligned buffer into fifo */
1970 for (i
= 0; i
< items
; ++i
)
1971 mci_fifo_writew(host
->fifo_reg
, aligned_buf
[i
]);
1978 for (; cnt
>= 2; cnt
-= 2)
1979 mci_fifo_writew(host
->fifo_reg
, *pdata
++);
1982 /* put anything remaining in the part_buf */
1984 dw_mci_set_part_bytes(host
, buf
, cnt
);
1985 /* Push data if we have reached the expected data length */
1986 if ((data
->bytes_xfered
+ init_cnt
) ==
1987 (data
->blksz
* data
->blocks
))
1988 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
1992 static void dw_mci_pull_data16(struct dw_mci
*host
, void *buf
, int cnt
)
1994 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1995 if (unlikely((unsigned long)buf
& 0x1)) {
1997 /* pull data from fifo into aligned buffer */
1998 u16 aligned_buf
[64];
1999 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2000 int items
= len
>> 1;
2003 for (i
= 0; i
< items
; ++i
)
2004 aligned_buf
[i
] = mci_fifo_readw(host
->fifo_reg
);
2005 /* memcpy from aligned buffer into output buffer */
2006 memcpy(buf
, aligned_buf
, len
);
2015 for (; cnt
>= 2; cnt
-= 2)
2016 *pdata
++ = mci_fifo_readw(host
->fifo_reg
);
2020 host
->part_buf16
= mci_fifo_readw(host
->fifo_reg
);
2021 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2025 static void dw_mci_push_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2027 struct mmc_data
*data
= host
->data
;
2030 /* try and push anything in the part_buf */
2031 if (unlikely(host
->part_buf_count
)) {
2032 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2036 if (host
->part_buf_count
== 4) {
2037 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2038 host
->part_buf_count
= 0;
2041 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2042 if (unlikely((unsigned long)buf
& 0x3)) {
2044 u32 aligned_buf
[32];
2045 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2046 int items
= len
>> 2;
2048 /* memcpy from input buffer into aligned buffer */
2049 memcpy(aligned_buf
, buf
, len
);
2052 /* push data from aligned buffer into fifo */
2053 for (i
= 0; i
< items
; ++i
)
2054 mci_fifo_writel(host
->fifo_reg
, aligned_buf
[i
]);
2061 for (; cnt
>= 4; cnt
-= 4)
2062 mci_fifo_writel(host
->fifo_reg
, *pdata
++);
2065 /* put anything remaining in the part_buf */
2067 dw_mci_set_part_bytes(host
, buf
, cnt
);
2068 /* Push data if we have reached the expected data length */
2069 if ((data
->bytes_xfered
+ init_cnt
) ==
2070 (data
->blksz
* data
->blocks
))
2071 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2075 static void dw_mci_pull_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2077 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2078 if (unlikely((unsigned long)buf
& 0x3)) {
2080 /* pull data from fifo into aligned buffer */
2081 u32 aligned_buf
[32];
2082 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2083 int items
= len
>> 2;
2086 for (i
= 0; i
< items
; ++i
)
2087 aligned_buf
[i
] = mci_fifo_readl(host
->fifo_reg
);
2088 /* memcpy from aligned buffer into output buffer */
2089 memcpy(buf
, aligned_buf
, len
);
2098 for (; cnt
>= 4; cnt
-= 4)
2099 *pdata
++ = mci_fifo_readl(host
->fifo_reg
);
2103 host
->part_buf32
= mci_fifo_readl(host
->fifo_reg
);
2104 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2108 static void dw_mci_push_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2110 struct mmc_data
*data
= host
->data
;
2113 /* try and push anything in the part_buf */
2114 if (unlikely(host
->part_buf_count
)) {
2115 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2120 if (host
->part_buf_count
== 8) {
2121 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2122 host
->part_buf_count
= 0;
2125 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2126 if (unlikely((unsigned long)buf
& 0x7)) {
2128 u64 aligned_buf
[16];
2129 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2130 int items
= len
>> 3;
2132 /* memcpy from input buffer into aligned buffer */
2133 memcpy(aligned_buf
, buf
, len
);
2136 /* push data from aligned buffer into fifo */
2137 for (i
= 0; i
< items
; ++i
)
2138 mci_fifo_writeq(host
->fifo_reg
, aligned_buf
[i
]);
2145 for (; cnt
>= 8; cnt
-= 8)
2146 mci_fifo_writeq(host
->fifo_reg
, *pdata
++);
2149 /* put anything remaining in the part_buf */
2151 dw_mci_set_part_bytes(host
, buf
, cnt
);
2152 /* Push data if we have reached the expected data length */
2153 if ((data
->bytes_xfered
+ init_cnt
) ==
2154 (data
->blksz
* data
->blocks
))
2155 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2159 static void dw_mci_pull_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2161 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2162 if (unlikely((unsigned long)buf
& 0x7)) {
2164 /* pull data from fifo into aligned buffer */
2165 u64 aligned_buf
[16];
2166 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2167 int items
= len
>> 3;
2170 for (i
= 0; i
< items
; ++i
)
2171 aligned_buf
[i
] = mci_fifo_readq(host
->fifo_reg
);
2173 /* memcpy from aligned buffer into output buffer */
2174 memcpy(buf
, aligned_buf
, len
);
2183 for (; cnt
>= 8; cnt
-= 8)
2184 *pdata
++ = mci_fifo_readq(host
->fifo_reg
);
2188 host
->part_buf
= mci_fifo_readq(host
->fifo_reg
);
2189 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2193 static void dw_mci_pull_data(struct dw_mci
*host
, void *buf
, int cnt
)
2197 /* get remaining partial bytes */
2198 len
= dw_mci_pull_part_bytes(host
, buf
, cnt
);
2199 if (unlikely(len
== cnt
))
2204 /* get the rest of the data */
2205 host
->pull_data(host
, buf
, cnt
);
2208 static void dw_mci_read_data_pio(struct dw_mci
*host
, bool dto
)
2210 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2212 unsigned int offset
;
2213 struct mmc_data
*data
= host
->data
;
2214 int shift
= host
->data_shift
;
2217 unsigned int remain
, fcnt
;
2220 if (!sg_miter_next(sg_miter
))
2223 host
->sg
= sg_miter
->piter
.sg
;
2224 buf
= sg_miter
->addr
;
2225 remain
= sg_miter
->length
;
2229 fcnt
= (SDMMC_GET_FCNT(mci_readl(host
, STATUS
))
2230 << shift
) + host
->part_buf_count
;
2231 len
= min(remain
, fcnt
);
2234 dw_mci_pull_data(host
, (void *)(buf
+ offset
), len
);
2235 data
->bytes_xfered
+= len
;
2240 sg_miter
->consumed
= offset
;
2241 status
= mci_readl(host
, MINTSTS
);
2242 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2243 /* if the RXDR is ready read again */
2244 } while ((status
& SDMMC_INT_RXDR
) ||
2245 (dto
&& SDMMC_GET_FCNT(mci_readl(host
, STATUS
))));
2248 if (!sg_miter_next(sg_miter
))
2250 sg_miter
->consumed
= 0;
2252 sg_miter_stop(sg_miter
);
2256 sg_miter_stop(sg_miter
);
2258 smp_wmb(); /* drain writebuffer */
2259 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2262 static void dw_mci_write_data_pio(struct dw_mci
*host
)
2264 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2266 unsigned int offset
;
2267 struct mmc_data
*data
= host
->data
;
2268 int shift
= host
->data_shift
;
2271 unsigned int fifo_depth
= host
->fifo_depth
;
2272 unsigned int remain
, fcnt
;
2275 if (!sg_miter_next(sg_miter
))
2278 host
->sg
= sg_miter
->piter
.sg
;
2279 buf
= sg_miter
->addr
;
2280 remain
= sg_miter
->length
;
2284 fcnt
= ((fifo_depth
-
2285 SDMMC_GET_FCNT(mci_readl(host
, STATUS
)))
2286 << shift
) - host
->part_buf_count
;
2287 len
= min(remain
, fcnt
);
2290 host
->push_data(host
, (void *)(buf
+ offset
), len
);
2291 data
->bytes_xfered
+= len
;
2296 sg_miter
->consumed
= offset
;
2297 status
= mci_readl(host
, MINTSTS
);
2298 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2299 } while (status
& SDMMC_INT_TXDR
); /* if TXDR write again */
2302 if (!sg_miter_next(sg_miter
))
2304 sg_miter
->consumed
= 0;
2306 sg_miter_stop(sg_miter
);
2310 sg_miter_stop(sg_miter
);
2312 smp_wmb(); /* drain writebuffer */
2313 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2316 static void dw_mci_cmd_interrupt(struct dw_mci
*host
, u32 status
)
2318 if (!host
->cmd_status
)
2319 host
->cmd_status
= status
;
2321 smp_wmb(); /* drain writebuffer */
2323 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2324 tasklet_schedule(&host
->tasklet
);
2327 static void dw_mci_handle_cd(struct dw_mci
*host
)
2331 for (i
= 0; i
< host
->num_slots
; i
++) {
2332 struct dw_mci_slot
*slot
= host
->slot
[i
];
2337 if (slot
->mmc
->ops
->card_event
)
2338 slot
->mmc
->ops
->card_event(slot
->mmc
);
2339 mmc_detect_change(slot
->mmc
,
2340 msecs_to_jiffies(host
->pdata
->detect_delay_ms
));
2344 static irqreturn_t
dw_mci_interrupt(int irq
, void *dev_id
)
2346 struct dw_mci
*host
= dev_id
;
2350 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
2353 /* Check volt switch first, since it can look like an error */
2354 if ((host
->state
== STATE_SENDING_CMD11
) &&
2355 (pending
& SDMMC_INT_VOLT_SWITCH
)) {
2356 unsigned long irqflags
;
2358 mci_writel(host
, RINTSTS
, SDMMC_INT_VOLT_SWITCH
);
2359 pending
&= ~SDMMC_INT_VOLT_SWITCH
;
2362 * Hold the lock; we know cmd11_timer can't be kicked
2363 * off after the lock is released, so safe to delete.
2365 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2366 dw_mci_cmd_interrupt(host
, pending
);
2367 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2369 del_timer(&host
->cmd11_timer
);
2372 if (pending
& DW_MCI_CMD_ERROR_FLAGS
) {
2373 mci_writel(host
, RINTSTS
, DW_MCI_CMD_ERROR_FLAGS
);
2374 host
->cmd_status
= pending
;
2375 smp_wmb(); /* drain writebuffer */
2376 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2379 if (pending
& DW_MCI_DATA_ERROR_FLAGS
) {
2380 /* if there is an error report DATA_ERROR */
2381 mci_writel(host
, RINTSTS
, DW_MCI_DATA_ERROR_FLAGS
);
2382 host
->data_status
= pending
;
2383 smp_wmb(); /* drain writebuffer */
2384 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
2385 tasklet_schedule(&host
->tasklet
);
2388 if (pending
& SDMMC_INT_DATA_OVER
) {
2389 if (host
->quirks
& DW_MCI_QUIRK_BROKEN_DTO
)
2390 del_timer(&host
->dto_timer
);
2392 mci_writel(host
, RINTSTS
, SDMMC_INT_DATA_OVER
);
2393 if (!host
->data_status
)
2394 host
->data_status
= pending
;
2395 smp_wmb(); /* drain writebuffer */
2396 if (host
->dir_status
== DW_MCI_RECV_STATUS
) {
2397 if (host
->sg
!= NULL
)
2398 dw_mci_read_data_pio(host
, true);
2400 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2401 tasklet_schedule(&host
->tasklet
);
2404 if (pending
& SDMMC_INT_RXDR
) {
2405 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2406 if (host
->dir_status
== DW_MCI_RECV_STATUS
&& host
->sg
)
2407 dw_mci_read_data_pio(host
, false);
2410 if (pending
& SDMMC_INT_TXDR
) {
2411 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2412 if (host
->dir_status
== DW_MCI_SEND_STATUS
&& host
->sg
)
2413 dw_mci_write_data_pio(host
);
2416 if (pending
& SDMMC_INT_CMD_DONE
) {
2417 mci_writel(host
, RINTSTS
, SDMMC_INT_CMD_DONE
);
2418 dw_mci_cmd_interrupt(host
, pending
);
2421 if (pending
& SDMMC_INT_CD
) {
2422 mci_writel(host
, RINTSTS
, SDMMC_INT_CD
);
2423 dw_mci_handle_cd(host
);
2426 /* Handle SDIO Interrupts */
2427 for (i
= 0; i
< host
->num_slots
; i
++) {
2428 struct dw_mci_slot
*slot
= host
->slot
[i
];
2433 if (pending
& SDMMC_INT_SDIO(slot
->sdio_id
)) {
2434 mci_writel(host
, RINTSTS
,
2435 SDMMC_INT_SDIO(slot
->sdio_id
));
2436 mmc_signal_sdio_irq(slot
->mmc
);
2442 if (host
->use_dma
!= TRANS_MODE_IDMAC
)
2445 /* Handle IDMA interrupts */
2446 if (host
->dma_64bit_address
== 1) {
2447 pending
= mci_readl(host
, IDSTS64
);
2448 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2449 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_TI
|
2450 SDMMC_IDMAC_INT_RI
);
2451 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_NI
);
2452 host
->dma_ops
->complete((void *)host
);
2455 pending
= mci_readl(host
, IDSTS
);
2456 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2457 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_TI
|
2458 SDMMC_IDMAC_INT_RI
);
2459 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_NI
);
2460 host
->dma_ops
->complete((void *)host
);
2468 /* given a slot, find out the device node representing that slot */
2469 static struct device_node
*dw_mci_of_find_slot_node(struct dw_mci_slot
*slot
)
2471 struct device
*dev
= slot
->mmc
->parent
;
2472 struct device_node
*np
;
2476 if (!dev
|| !dev
->of_node
)
2479 for_each_child_of_node(dev
->of_node
, np
) {
2480 addr
= of_get_property(np
, "reg", &len
);
2481 if (!addr
|| (len
< sizeof(int)))
2483 if (be32_to_cpup(addr
) == slot
->id
)
2489 static void dw_mci_slot_of_parse(struct dw_mci_slot
*slot
)
2491 struct device_node
*np
= dw_mci_of_find_slot_node(slot
);
2496 if (of_property_read_bool(np
, "disable-wp")) {
2497 slot
->mmc
->caps2
|= MMC_CAP2_NO_WRITE_PROTECT
;
2498 dev_warn(slot
->mmc
->parent
,
2499 "Slot quirk 'disable-wp' is deprecated\n");
2502 #else /* CONFIG_OF */
2503 static void dw_mci_slot_of_parse(struct dw_mci_slot
*slot
)
2506 #endif /* CONFIG_OF */
2508 static int dw_mci_init_slot(struct dw_mci
*host
, unsigned int id
)
2510 struct mmc_host
*mmc
;
2511 struct dw_mci_slot
*slot
;
2512 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2516 mmc
= mmc_alloc_host(sizeof(struct dw_mci_slot
), host
->dev
);
2520 slot
= mmc_priv(mmc
);
2522 slot
->sdio_id
= host
->sdio_id0
+ id
;
2525 host
->slot
[id
] = slot
;
2527 mmc
->ops
= &dw_mci_ops
;
2528 if (of_property_read_u32_array(host
->dev
->of_node
,
2529 "clock-freq-min-max", freq
, 2)) {
2530 mmc
->f_min
= DW_MCI_FREQ_MIN
;
2531 mmc
->f_max
= DW_MCI_FREQ_MAX
;
2533 mmc
->f_min
= freq
[0];
2534 mmc
->f_max
= freq
[1];
2537 /*if there are external regulators, get them*/
2538 ret
= mmc_regulator_get_supply(mmc
);
2539 if (ret
== -EPROBE_DEFER
)
2540 goto err_host_allocated
;
2542 if (!mmc
->ocr_avail
)
2543 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
2545 if (host
->pdata
->caps
)
2546 mmc
->caps
= host
->pdata
->caps
;
2548 if (host
->pdata
->pm_caps
)
2549 mmc
->pm_caps
= host
->pdata
->pm_caps
;
2551 if (host
->dev
->of_node
) {
2552 ctrl_id
= of_alias_get_id(host
->dev
->of_node
, "mshc");
2556 ctrl_id
= to_platform_device(host
->dev
)->id
;
2558 if (drv_data
&& drv_data
->caps
)
2559 mmc
->caps
|= drv_data
->caps
[ctrl_id
];
2561 if (host
->pdata
->caps2
)
2562 mmc
->caps2
= host
->pdata
->caps2
;
2564 dw_mci_slot_of_parse(slot
);
2566 ret
= mmc_of_parse(mmc
);
2568 goto err_host_allocated
;
2570 /* Useful defaults if platform data is unset. */
2571 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2572 mmc
->max_segs
= host
->ring_size
;
2573 mmc
->max_blk_size
= 65536;
2574 mmc
->max_seg_size
= 0x1000;
2575 mmc
->max_req_size
= mmc
->max_seg_size
* host
->ring_size
;
2576 mmc
->max_blk_count
= mmc
->max_req_size
/ 512;
2577 } else if (host
->use_dma
== TRANS_MODE_EDMAC
) {
2579 mmc
->max_blk_size
= 65536;
2580 mmc
->max_blk_count
= 65535;
2582 mmc
->max_blk_size
* mmc
->max_blk_count
;
2583 mmc
->max_seg_size
= mmc
->max_req_size
;
2585 /* TRANS_MODE_PIO */
2587 mmc
->max_blk_size
= 65536; /* BLKSIZ is 16 bits */
2588 mmc
->max_blk_count
= 512;
2589 mmc
->max_req_size
= mmc
->max_blk_size
*
2591 mmc
->max_seg_size
= mmc
->max_req_size
;
2594 if (dw_mci_get_cd(mmc
))
2595 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
2597 clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
2599 ret
= mmc_add_host(mmc
);
2601 goto err_host_allocated
;
2603 #if defined(CONFIG_DEBUG_FS)
2604 dw_mci_init_debugfs(slot
);
2614 static void dw_mci_cleanup_slot(struct dw_mci_slot
*slot
, unsigned int id
)
2616 /* Debugfs stuff is cleaned up by mmc core */
2617 mmc_remove_host(slot
->mmc
);
2618 slot
->host
->slot
[id
] = NULL
;
2619 mmc_free_host(slot
->mmc
);
2622 static void dw_mci_init_dma(struct dw_mci
*host
)
2625 struct device
*dev
= host
->dev
;
2626 struct device_node
*np
= dev
->of_node
;
2629 * Check tansfer mode from HCON[17:16]
2630 * Clear the ambiguous description of dw_mmc databook:
2631 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2632 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2633 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2634 * 2b'11: Non DW DMA Interface -> pio only
2635 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2636 * simpler request/acknowledge handshake mechanism and both of them
2637 * are regarded as external dma master for dw_mmc.
2639 host
->use_dma
= SDMMC_GET_TRANS_MODE(mci_readl(host
, HCON
));
2640 if (host
->use_dma
== DMA_INTERFACE_IDMA
) {
2641 host
->use_dma
= TRANS_MODE_IDMAC
;
2642 } else if (host
->use_dma
== DMA_INTERFACE_DWDMA
||
2643 host
->use_dma
== DMA_INTERFACE_GDMA
) {
2644 host
->use_dma
= TRANS_MODE_EDMAC
;
2649 /* Determine which DMA interface to use */
2650 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2652 * Check ADDR_CONFIG bit in HCON to find
2653 * IDMAC address bus width
2655 addr_config
= SDMMC_GET_ADDR_CONFIG(mci_readl(host
, HCON
));
2657 if (addr_config
== 1) {
2658 /* host supports IDMAC in 64-bit address mode */
2659 host
->dma_64bit_address
= 1;
2661 "IDMAC supports 64-bit address mode.\n");
2662 if (!dma_set_mask(host
->dev
, DMA_BIT_MASK(64)))
2663 dma_set_coherent_mask(host
->dev
,
2666 /* host supports IDMAC in 32-bit address mode */
2667 host
->dma_64bit_address
= 0;
2669 "IDMAC supports 32-bit address mode.\n");
2672 /* Alloc memory for sg translation */
2673 host
->sg_cpu
= dmam_alloc_coherent(host
->dev
, PAGE_SIZE
,
2674 &host
->sg_dma
, GFP_KERNEL
);
2675 if (!host
->sg_cpu
) {
2677 "%s: could not alloc DMA memory\n",
2682 host
->dma_ops
= &dw_mci_idmac_ops
;
2683 dev_info(host
->dev
, "Using internal DMA controller.\n");
2685 /* TRANS_MODE_EDMAC: check dma bindings again */
2686 if ((of_property_count_strings(np
, "dma-names") < 0) ||
2687 (!of_find_property(np
, "dmas", NULL
))) {
2690 host
->dma_ops
= &dw_mci_edmac_ops
;
2691 dev_info(host
->dev
, "Using external DMA controller.\n");
2694 if (host
->dma_ops
->init
&& host
->dma_ops
->start
&&
2695 host
->dma_ops
->stop
&& host
->dma_ops
->cleanup
) {
2696 if (host
->dma_ops
->init(host
)) {
2697 dev_err(host
->dev
, "%s: Unable to initialize DMA Controller.\n",
2702 dev_err(host
->dev
, "DMA initialization not found.\n");
2709 dev_info(host
->dev
, "Using PIO mode.\n");
2710 host
->use_dma
= TRANS_MODE_PIO
;
2713 static bool dw_mci_ctrl_reset(struct dw_mci
*host
, u32 reset
)
2715 unsigned long timeout
= jiffies
+ msecs_to_jiffies(500);
2718 ctrl
= mci_readl(host
, CTRL
);
2720 mci_writel(host
, CTRL
, ctrl
);
2722 /* wait till resets clear */
2724 ctrl
= mci_readl(host
, CTRL
);
2725 if (!(ctrl
& reset
))
2727 } while (time_before(jiffies
, timeout
));
2730 "Timeout resetting block (ctrl reset %#x)\n",
2736 static bool dw_mci_reset(struct dw_mci
*host
)
2738 u32 flags
= SDMMC_CTRL_RESET
| SDMMC_CTRL_FIFO_RESET
;
2742 * Reseting generates a block interrupt, hence setting
2743 * the scatter-gather pointer to NULL.
2746 sg_miter_stop(&host
->sg_miter
);
2751 flags
|= SDMMC_CTRL_DMA_RESET
;
2753 if (dw_mci_ctrl_reset(host
, flags
)) {
2755 * In all cases we clear the RAWINTS register to clear any
2758 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
2760 /* if using dma we wait for dma_req to clear */
2761 if (host
->use_dma
) {
2762 unsigned long timeout
= jiffies
+ msecs_to_jiffies(500);
2766 status
= mci_readl(host
, STATUS
);
2767 if (!(status
& SDMMC_STATUS_DMA_REQ
))
2770 } while (time_before(jiffies
, timeout
));
2772 if (status
& SDMMC_STATUS_DMA_REQ
) {
2774 "%s: Timeout waiting for dma_req to clear during reset\n",
2779 /* when using DMA next we reset the fifo again */
2780 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_FIFO_RESET
))
2784 /* if the controller reset bit did clear, then set clock regs */
2785 if (!(mci_readl(host
, CTRL
) & SDMMC_CTRL_RESET
)) {
2787 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2793 if (host
->use_dma
== TRANS_MODE_IDMAC
)
2794 /* It is also recommended that we reset and reprogram idmac */
2795 dw_mci_idmac_reset(host
);
2800 /* After a CTRL reset we need to have CIU set clock registers */
2801 mci_send_cmd(host
->cur_slot
, SDMMC_CMD_UPD_CLK
, 0);
2806 static void dw_mci_cmd11_timer(unsigned long arg
)
2808 struct dw_mci
*host
= (struct dw_mci
*)arg
;
2810 if (host
->state
!= STATE_SENDING_CMD11
) {
2811 dev_warn(host
->dev
, "Unexpected CMD11 timeout\n");
2815 host
->cmd_status
= SDMMC_INT_RTO
;
2816 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2817 tasklet_schedule(&host
->tasklet
);
2820 static void dw_mci_dto_timer(unsigned long arg
)
2822 struct dw_mci
*host
= (struct dw_mci
*)arg
;
2824 switch (host
->state
) {
2825 case STATE_SENDING_DATA
:
2826 case STATE_DATA_BUSY
:
2828 * If DTO interrupt does NOT come in sending data state,
2829 * we should notify the driver to terminate current transfer
2830 * and report a data timeout to the core.
2832 host
->data_status
= SDMMC_INT_DRTO
;
2833 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
2834 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2835 tasklet_schedule(&host
->tasklet
);
2843 static struct dw_mci_of_quirks
{
2848 .quirk
= "broken-cd",
2849 .id
= DW_MCI_QUIRK_BROKEN_CARD_DETECTION
,
2853 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
2855 struct dw_mci_board
*pdata
;
2856 struct device
*dev
= host
->dev
;
2857 struct device_node
*np
= dev
->of_node
;
2858 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2860 u32 clock_frequency
;
2862 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
2864 return ERR_PTR(-ENOMEM
);
2866 /* find out number of slots supported */
2867 if (of_property_read_u32(dev
->of_node
, "num-slots",
2868 &pdata
->num_slots
)) {
2870 "num-slots property not found, assuming 1 slot is available\n");
2871 pdata
->num_slots
= 1;
2875 for (idx
= 0; idx
< ARRAY_SIZE(of_quirks
); idx
++)
2876 if (of_get_property(np
, of_quirks
[idx
].quirk
, NULL
))
2877 pdata
->quirks
|= of_quirks
[idx
].id
;
2879 if (of_property_read_u32(np
, "fifo-depth", &pdata
->fifo_depth
))
2881 "fifo-depth property not found, using value of FIFOTH register as default\n");
2883 of_property_read_u32(np
, "card-detect-delay", &pdata
->detect_delay_ms
);
2885 if (!of_property_read_u32(np
, "clock-frequency", &clock_frequency
))
2886 pdata
->bus_hz
= clock_frequency
;
2888 if (drv_data
&& drv_data
->parse_dt
) {
2889 ret
= drv_data
->parse_dt(host
);
2891 return ERR_PTR(ret
);
2894 if (of_find_property(np
, "supports-highspeed", NULL
)) {
2895 dev_info(dev
, "supports-highspeed property is deprecated.\n");
2896 pdata
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
2902 #else /* CONFIG_OF */
2903 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
2905 return ERR_PTR(-EINVAL
);
2907 #endif /* CONFIG_OF */
2909 static void dw_mci_enable_cd(struct dw_mci
*host
)
2911 struct dw_mci_board
*brd
= host
->pdata
;
2912 unsigned long irqflags
;
2916 /* No need for CD if broken card detection */
2917 if (brd
->quirks
& DW_MCI_QUIRK_BROKEN_CARD_DETECTION
)
2920 /* No need for CD if all slots have a non-error GPIO */
2921 for (i
= 0; i
< host
->num_slots
; i
++) {
2922 struct dw_mci_slot
*slot
= host
->slot
[i
];
2924 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot
->mmc
)))
2927 if (i
== host
->num_slots
)
2930 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2931 temp
= mci_readl(host
, INTMASK
);
2932 temp
|= SDMMC_INT_CD
;
2933 mci_writel(host
, INTMASK
, temp
);
2934 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2937 int dw_mci_probe(struct dw_mci
*host
)
2939 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2940 int width
, i
, ret
= 0;
2945 host
->pdata
= dw_mci_parse_dt(host
);
2946 if (IS_ERR(host
->pdata
)) {
2947 dev_err(host
->dev
, "platform data not available\n");
2952 if (host
->pdata
->num_slots
< 1) {
2954 "Platform data must supply num_slots.\n");
2958 host
->biu_clk
= devm_clk_get(host
->dev
, "biu");
2959 if (IS_ERR(host
->biu_clk
)) {
2960 dev_dbg(host
->dev
, "biu clock not available\n");
2962 ret
= clk_prepare_enable(host
->biu_clk
);
2964 dev_err(host
->dev
, "failed to enable biu clock\n");
2969 host
->ciu_clk
= devm_clk_get(host
->dev
, "ciu");
2970 if (IS_ERR(host
->ciu_clk
)) {
2971 dev_dbg(host
->dev
, "ciu clock not available\n");
2972 host
->bus_hz
= host
->pdata
->bus_hz
;
2974 ret
= clk_prepare_enable(host
->ciu_clk
);
2976 dev_err(host
->dev
, "failed to enable ciu clock\n");
2980 if (host
->pdata
->bus_hz
) {
2981 ret
= clk_set_rate(host
->ciu_clk
, host
->pdata
->bus_hz
);
2984 "Unable to set bus rate to %uHz\n",
2985 host
->pdata
->bus_hz
);
2987 host
->bus_hz
= clk_get_rate(host
->ciu_clk
);
2990 if (!host
->bus_hz
) {
2992 "Platform data must supply bus speed\n");
2997 if (drv_data
&& drv_data
->init
) {
2998 ret
= drv_data
->init(host
);
3001 "implementation specific init failed\n");
3006 if (drv_data
&& drv_data
->setup_clock
) {
3007 ret
= drv_data
->setup_clock(host
);
3010 "implementation specific clock setup failed\n");
3015 setup_timer(&host
->cmd11_timer
,
3016 dw_mci_cmd11_timer
, (unsigned long)host
);
3018 host
->quirks
= host
->pdata
->quirks
;
3020 if (host
->quirks
& DW_MCI_QUIRK_BROKEN_DTO
)
3021 setup_timer(&host
->dto_timer
,
3022 dw_mci_dto_timer
, (unsigned long)host
);
3024 spin_lock_init(&host
->lock
);
3025 spin_lock_init(&host
->irq_lock
);
3026 INIT_LIST_HEAD(&host
->queue
);
3029 * Get the host data width - this assumes that HCON has been set with
3030 * the correct values.
3032 i
= SDMMC_GET_HDATA_WIDTH(mci_readl(host
, HCON
));
3034 host
->push_data
= dw_mci_push_data16
;
3035 host
->pull_data
= dw_mci_pull_data16
;
3037 host
->data_shift
= 1;
3038 } else if (i
== 2) {
3039 host
->push_data
= dw_mci_push_data64
;
3040 host
->pull_data
= dw_mci_pull_data64
;
3042 host
->data_shift
= 3;
3044 /* Check for a reserved value, and warn if it is */
3046 "HCON reports a reserved host data width!\n"
3047 "Defaulting to 32-bit access.\n");
3048 host
->push_data
= dw_mci_push_data32
;
3049 host
->pull_data
= dw_mci_pull_data32
;
3051 host
->data_shift
= 2;
3054 /* Reset all blocks */
3055 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
))
3058 host
->dma_ops
= host
->pdata
->dma_ops
;
3059 dw_mci_init_dma(host
);
3061 /* Clear the interrupts for the host controller */
3062 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3063 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3065 /* Put in max timeout */
3066 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3069 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3070 * Tx Mark = fifo_size / 2 DMA Size = 8
3072 if (!host
->pdata
->fifo_depth
) {
3074 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3075 * have been overwritten by the bootloader, just like we're
3076 * about to do, so if you know the value for your hardware, you
3077 * should put it in the platform data.
3079 fifo_size
= mci_readl(host
, FIFOTH
);
3080 fifo_size
= 1 + ((fifo_size
>> 16) & 0xfff);
3082 fifo_size
= host
->pdata
->fifo_depth
;
3084 host
->fifo_depth
= fifo_size
;
3086 SDMMC_SET_FIFOTH(0x2, fifo_size
/ 2 - 1, fifo_size
/ 2);
3087 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3089 /* disable clock to CIU */
3090 mci_writel(host
, CLKENA
, 0);
3091 mci_writel(host
, CLKSRC
, 0);
3094 * In 2.40a spec, Data offset is changed.
3095 * Need to check the version-id and set data-offset for DATA register.
3097 host
->verid
= SDMMC_GET_VERID(mci_readl(host
, VERID
));
3098 dev_info(host
->dev
, "Version ID is %04x\n", host
->verid
);
3100 if (host
->verid
< DW_MMC_240A
)
3101 host
->fifo_reg
= host
->regs
+ DATA_OFFSET
;
3103 host
->fifo_reg
= host
->regs
+ DATA_240A_OFFSET
;
3105 tasklet_init(&host
->tasklet
, dw_mci_tasklet_func
, (unsigned long)host
);
3106 ret
= devm_request_irq(host
->dev
, host
->irq
, dw_mci_interrupt
,
3107 host
->irq_flags
, "dw-mci", host
);
3111 if (host
->pdata
->num_slots
)
3112 host
->num_slots
= host
->pdata
->num_slots
;
3114 host
->num_slots
= SDMMC_GET_SLOT_NUM(mci_readl(host
, HCON
));
3117 * Enable interrupts for command done, data over, data empty,
3118 * receive ready and error such as transmit, receive timeout, crc error
3120 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3121 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3122 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3123 DW_MCI_ERROR_FLAGS
);
3124 /* Enable mci interrupt */
3125 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3128 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3129 host
->irq
, width
, fifo_size
);
3131 /* We need at least one slot to succeed */
3132 for (i
= 0; i
< host
->num_slots
; i
++) {
3133 ret
= dw_mci_init_slot(host
, i
);
3135 dev_dbg(host
->dev
, "slot %d init failed\n", i
);
3141 dev_info(host
->dev
, "%d slots initialized\n", init_slots
);
3144 "attempted to initialize %d slots, but failed on all\n",
3149 /* Now that slots are all setup, we can enable card detect */
3150 dw_mci_enable_cd(host
);
3155 if (host
->use_dma
&& host
->dma_ops
->exit
)
3156 host
->dma_ops
->exit(host
);
3159 if (!IS_ERR(host
->ciu_clk
))
3160 clk_disable_unprepare(host
->ciu_clk
);
3163 if (!IS_ERR(host
->biu_clk
))
3164 clk_disable_unprepare(host
->biu_clk
);
3168 EXPORT_SYMBOL(dw_mci_probe
);
3170 void dw_mci_remove(struct dw_mci
*host
)
3174 for (i
= 0; i
< host
->num_slots
; i
++) {
3175 dev_dbg(host
->dev
, "remove slot %d\n", i
);
3177 dw_mci_cleanup_slot(host
->slot
[i
], i
);
3180 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3181 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3183 /* disable clock to CIU */
3184 mci_writel(host
, CLKENA
, 0);
3185 mci_writel(host
, CLKSRC
, 0);
3187 if (host
->use_dma
&& host
->dma_ops
->exit
)
3188 host
->dma_ops
->exit(host
);
3190 if (!IS_ERR(host
->ciu_clk
))
3191 clk_disable_unprepare(host
->ciu_clk
);
3193 if (!IS_ERR(host
->biu_clk
))
3194 clk_disable_unprepare(host
->biu_clk
);
3196 EXPORT_SYMBOL(dw_mci_remove
);
3200 #ifdef CONFIG_PM_SLEEP
3202 * TODO: we should probably disable the clock to the card in the suspend path.
3204 int dw_mci_suspend(struct dw_mci
*host
)
3206 if (host
->use_dma
&& host
->dma_ops
->exit
)
3207 host
->dma_ops
->exit(host
);
3211 EXPORT_SYMBOL(dw_mci_suspend
);
3213 int dw_mci_resume(struct dw_mci
*host
)
3217 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3222 if (host
->use_dma
&& host
->dma_ops
->init
)
3223 host
->dma_ops
->init(host
);
3226 * Restore the initial value at FIFOTH register
3227 * And Invalidate the prev_blksz with zero
3229 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3230 host
->prev_blksz
= 0;
3232 /* Put in max timeout */
3233 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3235 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3236 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3237 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3238 DW_MCI_ERROR_FLAGS
);
3239 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3241 for (i
= 0; i
< host
->num_slots
; i
++) {
3242 struct dw_mci_slot
*slot
= host
->slot
[i
];
3246 if (slot
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) {
3247 dw_mci_set_ios(slot
->mmc
, &slot
->mmc
->ios
);
3248 dw_mci_setup_bus(slot
, true);
3252 /* Now that slots are all setup, we can enable card detect */
3253 dw_mci_enable_cd(host
);
3257 EXPORT_SYMBOL(dw_mci_resume
);
3258 #endif /* CONFIG_PM_SLEEP */
3260 static int __init
dw_mci_init(void)
3262 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3266 static void __exit
dw_mci_exit(void)
3270 module_init(dw_mci_init
);
3271 module_exit(dw_mci_exit
);
3273 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3274 MODULE_AUTHOR("NXP Semiconductor VietNam");
3275 MODULE_AUTHOR("Imagination Technologies Ltd");
3276 MODULE_LICENSE("GPL v2");