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imxmmc: fix platform resources
[deliverable/linux.git] / drivers / mmc / host / imxmmc.c
1 /*
2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
3 *
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6 *
7 * derived from pxamci.c by Russell King
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14 * Changed to conform redesigned i.MX scatter gather DMA interface
15 *
16 * 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17 * Updated for 2.6.14 kernel
18 *
19 * 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20 * Found and corrected problems in the write path
21 *
22 * 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23 * The event handling rewritten right way in softirq.
24 * Added many ugly hacks and delays to overcome SDHC
25 * deficiencies
26 *
27 */
28
29 #include <linux/module.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/blkdev.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/card.h>
38 #include <linux/delay.h>
39 #include <linux/clk.h>
40
41 #include <asm/dma.h>
42 #include <asm/io.h>
43 #include <asm/irq.h>
44 #include <asm/sizes.h>
45 #include <asm/arch/mmc.h>
46 #include <asm/arch/imx-dma.h>
47
48 #include "imxmmc.h"
49
50 #define DRIVER_NAME "imx-mmc"
51
52 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
53 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
54 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
55
56 struct imxmci_host {
57 struct mmc_host *mmc;
58 spinlock_t lock;
59 struct resource *res;
60 int irq;
61 imx_dmach_t dma;
62 unsigned int clkrt;
63 unsigned int cmdat;
64 volatile unsigned int imask;
65 unsigned int power_mode;
66 unsigned int present;
67 struct imxmmc_platform_data *pdata;
68
69 struct mmc_request *req;
70 struct mmc_command *cmd;
71 struct mmc_data *data;
72
73 struct timer_list timer;
74 struct tasklet_struct tasklet;
75 unsigned int status_reg;
76 unsigned long pending_events;
77 /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
78 u16 *data_ptr;
79 unsigned int data_cnt;
80 atomic_t stuck_timeout;
81
82 unsigned int dma_nents;
83 unsigned int dma_size;
84 unsigned int dma_dir;
85 int dma_allocated;
86
87 unsigned char actual_bus_width;
88
89 int prev_cmd_code;
90
91 struct clk *clk;
92 };
93
94 #define IMXMCI_PEND_IRQ_b 0
95 #define IMXMCI_PEND_DMA_END_b 1
96 #define IMXMCI_PEND_DMA_ERR_b 2
97 #define IMXMCI_PEND_WAIT_RESP_b 3
98 #define IMXMCI_PEND_DMA_DATA_b 4
99 #define IMXMCI_PEND_CPU_DATA_b 5
100 #define IMXMCI_PEND_CARD_XCHG_b 6
101 #define IMXMCI_PEND_SET_INIT_b 7
102 #define IMXMCI_PEND_STARTED_b 8
103
104 #define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
105 #define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
106 #define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
107 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
108 #define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
109 #define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
110 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
111 #define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
112 #define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
113
114 static void imxmci_stop_clock(struct imxmci_host *host)
115 {
116 int i = 0;
117 MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
118 while(i < 0x1000) {
119 if(!(i & 0x7f))
120 MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
121
122 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
123 /* Check twice before cut */
124 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
125 return;
126 }
127
128 i++;
129 }
130 dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
131 }
132
133 static int imxmci_start_clock(struct imxmci_host *host)
134 {
135 unsigned int trials = 0;
136 unsigned int delay_limit = 128;
137 unsigned long flags;
138
139 MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
140
141 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
142
143 /*
144 * Command start of the clock, this usually succeeds in less
145 * then 6 delay loops, but during card detection (low clockrate)
146 * it takes up to 5000 delay loops and sometimes fails for the first time
147 */
148 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
149
150 do {
151 unsigned int delay = delay_limit;
152
153 while(delay--){
154 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
155 /* Check twice before cut */
156 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
157 return 0;
158
159 if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
160 return 0;
161 }
162
163 local_irq_save(flags);
164 /*
165 * Ensure, that request is not doubled under all possible circumstances.
166 * It is possible, that cock running state is missed, because some other
167 * IRQ or schedule delays this function execution and the clocks has
168 * been already stopped by other means (response processing, SDHC HW)
169 */
170 if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
171 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
172 local_irq_restore(flags);
173
174 } while(++trials<256);
175
176 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
177
178 return -1;
179 }
180
181 static void imxmci_softreset(void)
182 {
183 /* reset sequence */
184 MMC_STR_STP_CLK = 0x8;
185 MMC_STR_STP_CLK = 0xD;
186 MMC_STR_STP_CLK = 0x5;
187 MMC_STR_STP_CLK = 0x5;
188 MMC_STR_STP_CLK = 0x5;
189 MMC_STR_STP_CLK = 0x5;
190 MMC_STR_STP_CLK = 0x5;
191 MMC_STR_STP_CLK = 0x5;
192 MMC_STR_STP_CLK = 0x5;
193 MMC_STR_STP_CLK = 0x5;
194
195 MMC_RES_TO = 0xff;
196 MMC_BLK_LEN = 512;
197 MMC_NOB = 1;
198 }
199
200 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
201 unsigned int *pstat, unsigned int stat_mask,
202 int timeout, const char *where)
203 {
204 int loops=0;
205 while(!(*pstat & stat_mask)) {
206 loops+=2;
207 if(loops >= timeout) {
208 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
209 where, *pstat, stat_mask);
210 return -1;
211 }
212 udelay(2);
213 *pstat |= MMC_STATUS;
214 }
215 if(!loops)
216 return 0;
217
218 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
219 if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
220 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
221 loops, where, *pstat, stat_mask);
222 return loops;
223 }
224
225 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
226 {
227 unsigned int nob = data->blocks;
228 unsigned int blksz = data->blksz;
229 unsigned int datasz = nob * blksz;
230 int i;
231
232 if (data->flags & MMC_DATA_STREAM)
233 nob = 0xffff;
234
235 host->data = data;
236 data->bytes_xfered = 0;
237
238 MMC_NOB = nob;
239 MMC_BLK_LEN = blksz;
240
241 /*
242 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
243 * We are in big troubles for non-512 byte transfers according to note in the paragraph
244 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
245 * The situation is even more complex in reality. The SDHC in not able to handle wll
246 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
247 * This is required for SCR read at least.
248 */
249 if (datasz < 512) {
250 host->dma_size = datasz;
251 if (data->flags & MMC_DATA_READ) {
252 host->dma_dir = DMA_FROM_DEVICE;
253
254 /* Hack to enable read SCR */
255 MMC_NOB = 1;
256 MMC_BLK_LEN = 512;
257 } else {
258 host->dma_dir = DMA_TO_DEVICE;
259 }
260
261 /* Convert back to virtual address */
262 host->data_ptr = (u16*)sg_virt(data->sg);
263 host->data_cnt = 0;
264
265 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
266 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
267
268 return;
269 }
270
271 if (data->flags & MMC_DATA_READ) {
272 host->dma_dir = DMA_FROM_DEVICE;
273 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
274 data->sg_len, host->dma_dir);
275
276 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
277 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
278
279 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
280 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
281 } else {
282 host->dma_dir = DMA_TO_DEVICE;
283
284 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
285 data->sg_len, host->dma_dir);
286
287 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
288 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
289
290 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
291 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
292 }
293
294 #if 1 /* This code is there only for consistency checking and can be disabled in future */
295 host->dma_size = 0;
296 for(i=0; i<host->dma_nents; i++)
297 host->dma_size+=data->sg[i].length;
298
299 if (datasz > host->dma_size) {
300 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
301 datasz, host->dma_size);
302 }
303 #endif
304
305 host->dma_size = datasz;
306
307 wmb();
308
309 if(host->actual_bus_width == MMC_BUS_WIDTH_4)
310 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
311 else
312 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
313
314 RSSR(host->dma) = DMA_REQ_SDHC;
315
316 set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
317 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
318
319 /* start DMA engine for read, write is delayed after initial response */
320 if (host->dma_dir == DMA_FROM_DEVICE) {
321 imx_dma_enable(host->dma);
322 }
323 }
324
325 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
326 {
327 unsigned long flags;
328 u32 imask;
329
330 WARN_ON(host->cmd != NULL);
331 host->cmd = cmd;
332
333 /* Ensure, that clock are stopped else command programming and start fails */
334 imxmci_stop_clock(host);
335
336 if (cmd->flags & MMC_RSP_BUSY)
337 cmdat |= CMD_DAT_CONT_BUSY;
338
339 switch (mmc_resp_type(cmd)) {
340 case MMC_RSP_R1: /* short CRC, OPCODE */
341 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
342 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
343 break;
344 case MMC_RSP_R2: /* long 136 bit + CRC */
345 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
346 break;
347 case MMC_RSP_R3: /* short */
348 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
349 break;
350 default:
351 break;
352 }
353
354 if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
355 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
356
357 if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
358 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
359
360 MMC_CMD = cmd->opcode;
361 MMC_ARGH = cmd->arg >> 16;
362 MMC_ARGL = cmd->arg & 0xffff;
363 MMC_CMD_DAT_CONT = cmdat;
364
365 atomic_set(&host->stuck_timeout, 0);
366 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
367
368
369 imask = IMXMCI_INT_MASK_DEFAULT;
370 imask &= ~INT_MASK_END_CMD_RES;
371 if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
372 /*imask &= ~INT_MASK_BUF_READY;*/
373 imask &= ~INT_MASK_DATA_TRAN;
374 if ( cmdat & CMD_DAT_CONT_WRITE )
375 imask &= ~INT_MASK_WRITE_OP_DONE;
376 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
377 imask &= ~INT_MASK_BUF_READY;
378 }
379
380 spin_lock_irqsave(&host->lock, flags);
381 host->imask = imask;
382 MMC_INT_MASK = host->imask;
383 spin_unlock_irqrestore(&host->lock, flags);
384
385 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
386 cmd->opcode, cmd->opcode, imask);
387
388 imxmci_start_clock(host);
389 }
390
391 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
392 {
393 unsigned long flags;
394
395 spin_lock_irqsave(&host->lock, flags);
396
397 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
398 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
399
400 host->imask = IMXMCI_INT_MASK_DEFAULT;
401 MMC_INT_MASK = host->imask;
402
403 spin_unlock_irqrestore(&host->lock, flags);
404
405 if(req && req->cmd)
406 host->prev_cmd_code = req->cmd->opcode;
407
408 host->req = NULL;
409 host->cmd = NULL;
410 host->data = NULL;
411 mmc_request_done(host->mmc, req);
412 }
413
414 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
415 {
416 struct mmc_data *data = host->data;
417 int data_error;
418
419 if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
420 imx_dma_disable(host->dma);
421 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
422 host->dma_dir);
423 }
424
425 if ( stat & STATUS_ERR_MASK ) {
426 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
427 if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
428 data->error = -EILSEQ;
429 else if(stat & STATUS_TIME_OUT_READ)
430 data->error = -ETIMEDOUT;
431 else
432 data->error = -EIO;
433 } else {
434 data->bytes_xfered = host->dma_size;
435 }
436
437 data_error = data->error;
438
439 host->data = NULL;
440
441 return data_error;
442 }
443
444 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
445 {
446 struct mmc_command *cmd = host->cmd;
447 int i;
448 u32 a,b,c;
449 struct mmc_data *data = host->data;
450
451 if (!cmd)
452 return 0;
453
454 host->cmd = NULL;
455
456 if (stat & STATUS_TIME_OUT_RESP) {
457 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
458 cmd->error = -ETIMEDOUT;
459 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
460 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
461 cmd->error = -EILSEQ;
462 }
463
464 if(cmd->flags & MMC_RSP_PRESENT) {
465 if(cmd->flags & MMC_RSP_136) {
466 for (i = 0; i < 4; i++) {
467 u32 a = MMC_RES_FIFO & 0xffff;
468 u32 b = MMC_RES_FIFO & 0xffff;
469 cmd->resp[i] = a<<16 | b;
470 }
471 } else {
472 a = MMC_RES_FIFO & 0xffff;
473 b = MMC_RES_FIFO & 0xffff;
474 c = MMC_RES_FIFO & 0xffff;
475 cmd->resp[0] = a<<24 | b<<8 | c>>8;
476 }
477 }
478
479 dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
480 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
481
482 if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
483 if (host->req->data->flags & MMC_DATA_WRITE) {
484
485 /* Wait for FIFO to be empty before starting DMA write */
486
487 stat = MMC_STATUS;
488 if(imxmci_busy_wait_for_status(host, &stat,
489 STATUS_APPL_BUFF_FE,
490 40, "imxmci_cmd_done DMA WR") < 0) {
491 cmd->error = -EIO;
492 imxmci_finish_data(host, stat);
493 if(host->req)
494 imxmci_finish_request(host, host->req);
495 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
496 stat);
497 return 0;
498 }
499
500 if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
501 imx_dma_enable(host->dma);
502 }
503 }
504 } else {
505 struct mmc_request *req;
506 imxmci_stop_clock(host);
507 req = host->req;
508
509 if(data)
510 imxmci_finish_data(host, stat);
511
512 if( req ) {
513 imxmci_finish_request(host, req);
514 } else {
515 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
516 }
517 }
518
519 return 1;
520 }
521
522 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
523 {
524 struct mmc_data *data = host->data;
525 int data_error;
526
527 if (!data)
528 return 0;
529
530 data_error = imxmci_finish_data(host, stat);
531
532 if (host->req->stop) {
533 imxmci_stop_clock(host);
534 imxmci_start_cmd(host, host->req->stop, 0);
535 } else {
536 struct mmc_request *req;
537 req = host->req;
538 if( req ) {
539 imxmci_finish_request(host, req);
540 } else {
541 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
542 }
543 }
544
545 return 1;
546 }
547
548 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
549 {
550 int i;
551 int burst_len;
552 int trans_done = 0;
553 unsigned int stat = *pstat;
554
555 if(host->actual_bus_width != MMC_BUS_WIDTH_4)
556 burst_len = 16;
557 else
558 burst_len = 64;
559
560 /* This is unfortunately required */
561 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
562 stat);
563
564 udelay(20); /* required for clocks < 8MHz*/
565
566 if(host->dma_dir == DMA_FROM_DEVICE) {
567 imxmci_busy_wait_for_status(host, &stat,
568 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
569 STATUS_TIME_OUT_READ,
570 50, "imxmci_cpu_driven_data read");
571
572 while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
573 !(stat & STATUS_TIME_OUT_READ) &&
574 (host->data_cnt < 512)) {
575
576 udelay(20); /* required for clocks < 8MHz*/
577
578 for(i = burst_len; i>=2 ; i-=2) {
579 u16 data;
580 data = MMC_BUFFER_ACCESS;
581 udelay(10); /* required for clocks < 8MHz*/
582 if(host->data_cnt+2 <= host->dma_size) {
583 *(host->data_ptr++) = data;
584 } else {
585 if(host->data_cnt < host->dma_size)
586 *(u8*)(host->data_ptr) = data;
587 }
588 host->data_cnt += 2;
589 }
590
591 stat = MMC_STATUS;
592
593 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
594 host->data_cnt, burst_len, stat);
595 }
596
597 if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
598 trans_done = 1;
599
600 if(host->dma_size & 0x1ff)
601 stat &= ~STATUS_CRC_READ_ERR;
602
603 if(stat & STATUS_TIME_OUT_READ) {
604 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
605 stat);
606 trans_done = -1;
607 }
608
609 } else {
610 imxmci_busy_wait_for_status(host, &stat,
611 STATUS_APPL_BUFF_FE,
612 20, "imxmci_cpu_driven_data write");
613
614 while((stat & STATUS_APPL_BUFF_FE) &&
615 (host->data_cnt < host->dma_size)) {
616 if(burst_len >= host->dma_size - host->data_cnt) {
617 burst_len = host->dma_size - host->data_cnt;
618 host->data_cnt = host->dma_size;
619 trans_done = 1;
620 } else {
621 host->data_cnt += burst_len;
622 }
623
624 for(i = burst_len; i>0 ; i-=2)
625 MMC_BUFFER_ACCESS = *(host->data_ptr++);
626
627 stat = MMC_STATUS;
628
629 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
630 burst_len, stat);
631 }
632 }
633
634 *pstat = stat;
635
636 return trans_done;
637 }
638
639 static void imxmci_dma_irq(int dma, void *devid)
640 {
641 struct imxmci_host *host = devid;
642 uint32_t stat = MMC_STATUS;
643
644 atomic_set(&host->stuck_timeout, 0);
645 host->status_reg = stat;
646 set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
647 tasklet_schedule(&host->tasklet);
648 }
649
650 static irqreturn_t imxmci_irq(int irq, void *devid)
651 {
652 struct imxmci_host *host = devid;
653 uint32_t stat = MMC_STATUS;
654 int handled = 1;
655
656 MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
657
658 atomic_set(&host->stuck_timeout, 0);
659 host->status_reg = stat;
660 set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
661 set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
662 tasklet_schedule(&host->tasklet);
663
664 return IRQ_RETVAL(handled);;
665 }
666
667 static void imxmci_tasklet_fnc(unsigned long data)
668 {
669 struct imxmci_host *host = (struct imxmci_host *)data;
670 u32 stat;
671 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
672 int timeout = 0;
673
674 if(atomic_read(&host->stuck_timeout) > 4) {
675 char *what;
676 timeout = 1;
677 stat = MMC_STATUS;
678 host->status_reg = stat;
679 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
680 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
681 what = "RESP+DMA";
682 else
683 what = "RESP";
684 else
685 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
686 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
687 what = "DATA";
688 else
689 what = "DMA";
690 else
691 what = "???";
692
693 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
694 what, stat, MMC_INT_MASK);
695 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
696 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
697 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
698 host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
699 }
700
701 if(!host->present || timeout)
702 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
703 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
704
705 if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
706 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
707
708 stat = MMC_STATUS;
709 /*
710 * This is not required in theory, but there is chance to miss some flag
711 * which clears automatically by mask write, FreeScale original code keeps
712 * stat from IRQ time so do I
713 */
714 stat |= host->status_reg;
715
716 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
717 stat &= ~STATUS_CRC_READ_ERR;
718
719 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
720 imxmci_busy_wait_for_status(host, &stat,
721 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
722 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
723 }
724
725 if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
726 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
727 imxmci_cmd_done(host, stat);
728 if(host->data && (stat & STATUS_ERR_MASK))
729 imxmci_data_done(host, stat);
730 }
731
732 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
733 stat |= MMC_STATUS;
734 if(imxmci_cpu_driven_data(host, &stat)){
735 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
736 imxmci_cmd_done(host, stat);
737 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
738 &host->pending_events);
739 imxmci_data_done(host, stat);
740 }
741 }
742 }
743
744 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
745 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
746
747 stat = MMC_STATUS;
748 /* Same as above */
749 stat |= host->status_reg;
750
751 if(host->dma_dir == DMA_TO_DEVICE) {
752 data_dir_mask = STATUS_WRITE_OP_DONE;
753 } else {
754 data_dir_mask = STATUS_DATA_TRANS_DONE;
755 }
756
757 if(stat & data_dir_mask) {
758 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
759 imxmci_data_done(host, stat);
760 }
761 }
762
763 if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
764
765 if(host->cmd)
766 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
767
768 if(host->data)
769 imxmci_data_done(host, STATUS_TIME_OUT_READ |
770 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
771
772 if(host->req)
773 imxmci_finish_request(host, host->req);
774
775 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
776
777 }
778 }
779
780 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
781 {
782 struct imxmci_host *host = mmc_priv(mmc);
783 unsigned int cmdat;
784
785 WARN_ON(host->req != NULL);
786
787 host->req = req;
788
789 cmdat = 0;
790
791 if (req->data) {
792 imxmci_setup_data(host, req->data);
793
794 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
795
796 if (req->data->flags & MMC_DATA_WRITE)
797 cmdat |= CMD_DAT_CONT_WRITE;
798
799 if (req->data->flags & MMC_DATA_STREAM) {
800 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
801 }
802 }
803
804 imxmci_start_cmd(host, req->cmd, cmdat);
805 }
806
807 #define CLK_RATE 19200000
808
809 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
810 {
811 struct imxmci_host *host = mmc_priv(mmc);
812 int prescaler;
813
814 if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
815 host->actual_bus_width = MMC_BUS_WIDTH_4;
816 imx_gpio_mode(PB11_PF_SD_DAT3);
817 }else{
818 host->actual_bus_width = MMC_BUS_WIDTH_1;
819 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
820 }
821
822 if ( host->power_mode != ios->power_mode ) {
823 switch (ios->power_mode) {
824 case MMC_POWER_OFF:
825 break;
826 case MMC_POWER_UP:
827 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
828 break;
829 case MMC_POWER_ON:
830 break;
831 }
832 host->power_mode = ios->power_mode;
833 }
834
835 if ( ios->clock ) {
836 unsigned int clk;
837
838 /* The prescaler is 5 for PERCLK2 equal to 96MHz
839 * then 96MHz / 5 = 19.2 MHz
840 */
841 clk = clk_get_rate(host->clk);
842 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
843 switch(prescaler) {
844 case 0:
845 case 1: prescaler = 0;
846 break;
847 case 2: prescaler = 1;
848 break;
849 case 3: prescaler = 2;
850 break;
851 case 4: prescaler = 4;
852 break;
853 default:
854 case 5: prescaler = 5;
855 break;
856 }
857
858 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
859 clk, prescaler);
860
861 for(clk=0; clk<8; clk++) {
862 int x;
863 x = CLK_RATE / (1<<clk);
864 if( x <= ios->clock)
865 break;
866 }
867
868 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
869
870 imxmci_stop_clock(host);
871 MMC_CLK_RATE = (prescaler<<3) | clk;
872 /*
873 * Under my understanding, clock should not be started there, because it would
874 * initiate SDHC sequencer and send last or random command into card
875 */
876 /*imxmci_start_clock(host);*/
877
878 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
879 } else {
880 imxmci_stop_clock(host);
881 }
882 }
883
884 static int imxmci_get_ro(struct mmc_host *mmc)
885 {
886 struct imxmci_host *host = mmc_priv(mmc);
887
888 if (host->pdata && host->pdata->get_ro)
889 return !!host->pdata->get_ro(mmc_dev(mmc));
890 /*
891 * Board doesn't support read only detection; let the mmc core
892 * decide what to do.
893 */
894 return -ENOSYS;
895 }
896
897
898 static const struct mmc_host_ops imxmci_ops = {
899 .request = imxmci_request,
900 .set_ios = imxmci_set_ios,
901 .get_ro = imxmci_get_ro,
902 };
903
904 static void imxmci_check_status(unsigned long data)
905 {
906 struct imxmci_host *host = (struct imxmci_host *)data;
907
908 if( host->pdata->card_present(mmc_dev(host->mmc)) != host->present ) {
909 host->present ^= 1;
910 dev_info(mmc_dev(host->mmc), "card %s\n",
911 host->present ? "inserted" : "removed");
912
913 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
914 tasklet_schedule(&host->tasklet);
915 }
916
917 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
918 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
919 atomic_inc(&host->stuck_timeout);
920 if(atomic_read(&host->stuck_timeout) > 4)
921 tasklet_schedule(&host->tasklet);
922 } else {
923 atomic_set(&host->stuck_timeout, 0);
924
925 }
926
927 mod_timer(&host->timer, jiffies + (HZ>>1));
928 }
929
930 static int imxmci_probe(struct platform_device *pdev)
931 {
932 struct mmc_host *mmc;
933 struct imxmci_host *host = NULL;
934 struct resource *r;
935 int ret = 0, irq;
936
937 printk(KERN_INFO "i.MX mmc driver\n");
938
939 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
940 irq = platform_get_irq(pdev, 0);
941 if (!r || irq < 0)
942 return -ENXIO;
943
944 if (!request_mem_region(r->start, 0x100, pdev->name))
945 return -EBUSY;
946
947 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
948 if (!mmc) {
949 ret = -ENOMEM;
950 goto out;
951 }
952
953 mmc->ops = &imxmci_ops;
954 mmc->f_min = 150000;
955 mmc->f_max = CLK_RATE/2;
956 mmc->ocr_avail = MMC_VDD_32_33;
957 mmc->caps = MMC_CAP_4_BIT_DATA;
958
959 /* MMC core transfer sizes tunable parameters */
960 mmc->max_hw_segs = 64;
961 mmc->max_phys_segs = 64;
962 mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */
963 mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */
964 mmc->max_blk_size = 2048;
965 mmc->max_blk_count = 65535;
966
967 host = mmc_priv(mmc);
968 host->mmc = mmc;
969 host->dma_allocated = 0;
970 host->pdata = pdev->dev.platform_data;
971
972 spin_lock_init(&host->lock);
973 host->res = r;
974 host->irq = irq;
975
976 host->clk = clk_get(&pdev->dev, "perclk2");
977 if (IS_ERR(host->clk)) {
978 ret = PTR_ERR(host->clk);
979 goto out;
980 }
981 clk_enable(host->clk);
982
983 imx_gpio_mode(PB8_PF_SD_DAT0);
984 imx_gpio_mode(PB9_PF_SD_DAT1);
985 imx_gpio_mode(PB10_PF_SD_DAT2);
986 /* Configured as GPIO with pull-up to ensure right MCC card mode */
987 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
988 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
989 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
990 imx_gpio_mode(PB12_PF_SD_CLK);
991 imx_gpio_mode(PB13_PF_SD_CMD);
992
993 imxmci_softreset();
994
995 if ( MMC_REV_NO != 0x390 ) {
996 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
997 MMC_REV_NO);
998 goto out;
999 }
1000
1001 MMC_READ_TO = 0x2db4; /* recommended in data sheet */
1002
1003 host->imask = IMXMCI_INT_MASK_DEFAULT;
1004 MMC_INT_MASK = host->imask;
1005
1006 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1007 if(host->dma < 0) {
1008 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
1009 ret = -EBUSY;
1010 goto out;
1011 }
1012 host->dma_allocated=1;
1013 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1014
1015 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1016 host->status_reg=0;
1017 host->pending_events=0;
1018
1019 ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1020 if (ret)
1021 goto out;
1022
1023 host->present = host->pdata->card_present(mmc_dev(mmc));
1024 init_timer(&host->timer);
1025 host->timer.data = (unsigned long)host;
1026 host->timer.function = imxmci_check_status;
1027 add_timer(&host->timer);
1028 mod_timer(&host->timer, jiffies + (HZ>>1));
1029
1030 platform_set_drvdata(pdev, mmc);
1031
1032 mmc_add_host(mmc);
1033
1034 return 0;
1035
1036 out:
1037 if (host) {
1038 if(host->dma_allocated){
1039 imx_dma_free(host->dma);
1040 host->dma_allocated=0;
1041 }
1042 if (host->clk) {
1043 clk_disable(host->clk);
1044 clk_put(host->clk);
1045 }
1046 }
1047 if (mmc)
1048 mmc_free_host(mmc);
1049 release_mem_region(r->start, 0x100);
1050 return ret;
1051 }
1052
1053 static int imxmci_remove(struct platform_device *pdev)
1054 {
1055 struct mmc_host *mmc = platform_get_drvdata(pdev);
1056
1057 platform_set_drvdata(pdev, NULL);
1058
1059 if (mmc) {
1060 struct imxmci_host *host = mmc_priv(mmc);
1061
1062 tasklet_disable(&host->tasklet);
1063
1064 del_timer_sync(&host->timer);
1065 mmc_remove_host(mmc);
1066
1067 free_irq(host->irq, host);
1068 if(host->dma_allocated){
1069 imx_dma_free(host->dma);
1070 host->dma_allocated=0;
1071 }
1072
1073 tasklet_kill(&host->tasklet);
1074
1075 clk_disable(host->clk);
1076 clk_put(host->clk);
1077
1078 release_mem_region(host->res->start, 0x100);
1079
1080 mmc_free_host(mmc);
1081 }
1082 return 0;
1083 }
1084
1085 #ifdef CONFIG_PM
1086 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1087 {
1088 struct mmc_host *mmc = platform_get_drvdata(dev);
1089 int ret = 0;
1090
1091 if (mmc)
1092 ret = mmc_suspend_host(mmc, state);
1093
1094 return ret;
1095 }
1096
1097 static int imxmci_resume(struct platform_device *dev)
1098 {
1099 struct mmc_host *mmc = platform_get_drvdata(dev);
1100 struct imxmci_host *host;
1101 int ret = 0;
1102
1103 if (mmc) {
1104 host = mmc_priv(mmc);
1105 if(host)
1106 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1107 ret = mmc_resume_host(mmc);
1108 }
1109
1110 return ret;
1111 }
1112 #else
1113 #define imxmci_suspend NULL
1114 #define imxmci_resume NULL
1115 #endif /* CONFIG_PM */
1116
1117 static struct platform_driver imxmci_driver = {
1118 .probe = imxmci_probe,
1119 .remove = imxmci_remove,
1120 .suspend = imxmci_suspend,
1121 .resume = imxmci_resume,
1122 .driver = {
1123 .name = DRIVER_NAME,
1124 .owner = THIS_MODULE,
1125 }
1126 };
1127
1128 static int __init imxmci_init(void)
1129 {
1130 return platform_driver_register(&imxmci_driver);
1131 }
1132
1133 static void __exit imxmci_exit(void)
1134 {
1135 platform_driver_unregister(&imxmci_driver);
1136 }
1137
1138 module_init(imxmci_init);
1139 module_exit(imxmci_exit);
1140
1141 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1142 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1143 MODULE_LICENSE("GPL");
1144 MODULE_ALIAS("platform:imx-mmc");
Linux kernel - Deliverables
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