2 * mmc_spi.c - Access SD/MMC cards through SPI master controllers
4 * (C) Copyright 2005, Intec Automation,
5 * Mike Lavender (mike@steroidmicros)
6 * (C) Copyright 2006-2007, David Brownell
7 * (C) Copyright 2007, Axis Communications,
8 * Hans-Peter Nilsson (hp@axis.com)
9 * (C) Copyright 2007, ATRON electronic GmbH,
10 * Jan Nikitenko <jan.nikitenko@gmail.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/hrtimer.h>
28 #include <linux/delay.h>
29 #include <linux/bio.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/crc7.h>
32 #include <linux/crc-itu-t.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
37 #include <linux/spi/spi.h>
38 #include <linux/spi/mmc_spi.h>
40 #include <asm/unaligned.h>
45 * - For now, we won't try to interoperate with a real mmc/sd/sdio
46 * controller, although some of them do have hardware support for
47 * SPI protocol. The main reason for such configs would be mmc-ish
48 * cards like DataFlash, which don't support that "native" protocol.
50 * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
51 * switch between driver stacks, and in any case if "native" mode
52 * is available, it will be faster and hence preferable.
54 * - MMC depends on a different chipselect management policy than the
55 * SPI interface currently supports for shared bus segments: it needs
56 * to issue multiple spi_message requests with the chipselect active,
57 * using the results of one message to decide the next one to issue.
59 * Pending updates to the programming interface, this driver expects
60 * that it not share the bus with other drivers (precluding conflicts).
62 * - We tell the controller to keep the chipselect active from the
63 * beginning of an mmc_host_ops.request until the end. So beware
64 * of SPI controller drivers that mis-handle the cs_change flag!
66 * However, many cards seem OK with chipselect flapping up/down
67 * during that time ... at least on unshared bus segments.
72 * Local protocol constants, internal to data block protocols.
75 /* Response tokens used to ack each block written: */
76 #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
77 #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
78 #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
79 #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
81 /* Read and write blocks start with these tokens and end with crc;
82 * on error, read tokens act like a subset of R2_SPI_* values.
84 #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
85 #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
86 #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
88 #define MMC_SPI_BLOCKSIZE 512
91 /* These fixed timeouts come from the latest SD specs, which say to ignore
92 * the CSD values. The R1B value is for card erase (e.g. the "I forgot the
93 * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
94 * reads which takes nowhere near that long. Older cards may be able to use
95 * shorter timeouts ... but why bother?
97 #define readblock_timeout ktime_set(0, 100 * 1000 * 1000)
98 #define writeblock_timeout ktime_set(0, 250 * 1000 * 1000)
99 #define r1b_timeout ktime_set(3, 0)
102 /****************************************************************************/
105 * Local Data Structures
108 /* "scratch" is per-{command,block} data exchanged with the card */
115 struct mmc_spi_host
{
116 struct mmc_host
*mmc
;
117 struct spi_device
*spi
;
119 unsigned char power_mode
;
122 struct mmc_spi_platform_data
*pdata
;
124 /* for bulk data transfers */
125 struct spi_transfer token
, t
, crc
, early_status
;
126 struct spi_message m
;
128 /* for status readback */
129 struct spi_transfer status
;
130 struct spi_message readback
;
132 /* underlying DMA-aware controller, or null */
133 struct device
*dma_dev
;
135 /* buffer used for commands and for message "overhead" */
136 struct scratch
*data
;
139 /* Specs say to write ones most of the time, even when the card
140 * has no need to read its input data; and many cards won't care.
141 * This is our source of those ones.
148 /****************************************************************************/
151 * MMC-over-SPI protocol glue, used by the MMC stack interface
154 static inline int mmc_cs_off(struct mmc_spi_host
*host
)
156 /* chipselect will always be inactive after setup() */
157 return spi_setup(host
->spi
);
161 mmc_spi_readbytes(struct mmc_spi_host
*host
, unsigned len
)
165 if (len
> sizeof(*host
->data
)) {
170 host
->status
.len
= len
;
173 dma_sync_single_for_device(host
->dma_dev
,
174 host
->data_dma
, sizeof(*host
->data
),
177 status
= spi_sync(host
->spi
, &host
->readback
);
179 status
= host
->readback
.status
;
182 dma_sync_single_for_cpu(host
->dma_dev
,
183 host
->data_dma
, sizeof(*host
->data
),
190 mmc_spi_skip(struct mmc_spi_host
*host
, ktime_t timeout
, unsigned n
, u8 byte
)
192 u8
*cp
= host
->data
->status
;
194 timeout
= ktime_add(timeout
, ktime_get());
200 status
= mmc_spi_readbytes(host
, n
);
204 for (i
= 0; i
< n
; i
++) {
209 /* REVISIT investigate msleep() to avoid busy-wait I/O
210 * in at least some cases.
212 if (ktime_to_ns(ktime_sub(ktime_get(), timeout
)) > 0)
219 mmc_spi_wait_unbusy(struct mmc_spi_host
*host
, ktime_t timeout
)
221 return mmc_spi_skip(host
, timeout
, sizeof(host
->data
->status
), 0);
224 static int mmc_spi_readtoken(struct mmc_spi_host
*host
)
226 return mmc_spi_skip(host
, readblock_timeout
, 1, 0xff);
231 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
232 * hosts return! The low byte holds R1_SPI bits. The next byte may hold
233 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
235 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
236 * newer cards R7 (IF_COND).
239 static char *maptype(struct mmc_command
*cmd
)
241 switch (mmc_spi_resp_type(cmd
)) {
242 case MMC_RSP_SPI_R1
: return "R1";
243 case MMC_RSP_SPI_R1B
: return "R1B";
244 case MMC_RSP_SPI_R2
: return "R2/R5";
245 case MMC_RSP_SPI_R3
: return "R3/R4/R7";
250 /* return zero, else negative errno after setting cmd->error */
251 static int mmc_spi_response_get(struct mmc_spi_host
*host
,
252 struct mmc_command
*cmd
, int cs_on
)
254 u8
*cp
= host
->data
->status
;
255 u8
*end
= cp
+ host
->t
.len
;
259 snprintf(tag
, sizeof(tag
), " ... CMD%d response SPI_%s",
260 cmd
->opcode
, maptype(cmd
));
262 /* Except for data block reads, the whole response will already
263 * be stored in the scratch buffer. It's somewhere after the
264 * command and the first byte we read after it. We ignore that
265 * first byte. After STOP_TRANSMISSION command it may include
266 * two data bits, but otherwise it's all ones.
269 while (cp
< end
&& *cp
== 0xff)
272 /* Data block reads (R1 response types) may need more data... */
276 cp
= host
->data
->status
;
278 /* Card sends N(CR) (== 1..8) bytes of all-ones then one
279 * status byte ... and we already scanned 2 bytes.
281 * REVISIT block read paths use nasty byte-at-a-time I/O
282 * so it can always DMA directly into the target buffer.
283 * It'd probably be better to memcpy() the first chunk and
284 * avoid extra i/o calls...
286 for (i
= 2; i
< 9; i
++) {
287 value
= mmc_spi_readbytes(host
, 1);
299 dev_dbg(&host
->spi
->dev
, "%s: INVALID RESPONSE, %02x\n",
305 cmd
->resp
[0] = *cp
++;
308 /* Status byte: the entire seven-bit R1 response. */
309 if (cmd
->resp
[0] != 0) {
310 if ((R1_SPI_PARAMETER
| R1_SPI_ADDRESS
311 | R1_SPI_ILLEGAL_COMMAND
)
314 else if (R1_SPI_COM_CRC
& cmd
->resp
[0])
316 else if ((R1_SPI_ERASE_SEQ
| R1_SPI_ERASE_RESET
)
319 /* else R1_SPI_IDLE, "it's resetting" */
322 switch (mmc_spi_resp_type(cmd
)) {
324 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
325 * and less-common stuff like various erase operations.
327 case MMC_RSP_SPI_R1B
:
328 /* maybe we read all the busy tokens already */
329 while (cp
< end
&& *cp
== 0)
332 mmc_spi_wait_unbusy(host
, r1b_timeout
);
335 /* SPI R2 == R1 + second status byte; SEND_STATUS
336 * SPI R5 == R1 + data byte; IO_RW_DIRECT
339 cmd
->resp
[0] |= *cp
<< 8;
342 /* SPI R3, R4, or R7 == R1 + 4 bytes */
344 cmd
->resp
[1] = be32_to_cpu(get_unaligned((u32
*)cp
));
347 /* SPI R1 == just one status byte */
352 dev_dbg(&host
->spi
->dev
, "bad response type %04x\n",
353 mmc_spi_resp_type(cmd
));
360 dev_dbg(&host
->spi
->dev
, "%s: resp %04x %08x\n",
361 tag
, cmd
->resp
[0], cmd
->resp
[1]);
363 /* disable chipselect on errors and some success cases */
364 if (value
>= 0 && cs_on
)
373 /* Issue command and read its response.
374 * Returns zero on success, negative for error.
376 * On error, caller must cope with mmc core retry mechanism. That
377 * means immediate low-level resubmit, which affects the bus lock...
380 mmc_spi_command_send(struct mmc_spi_host
*host
,
381 struct mmc_request
*mrq
,
382 struct mmc_command
*cmd
, int cs_on
)
384 struct scratch
*data
= host
->data
;
385 u8
*cp
= data
->status
;
388 struct spi_transfer
*t
;
390 /* We can handle most commands (except block reads) in one full
391 * duplex I/O operation before either starting the next transfer
392 * (data block or command) or else deselecting the card.
394 * First, write 7 bytes:
395 * - an all-ones byte to ensure the card is ready
396 * - opcode byte (plus start and transmission bits)
397 * - four bytes of big-endian argument
398 * - crc7 (plus end bit) ... always computed, it's cheap
400 * We init the whole buffer to all-ones, which is what we need
401 * to write while we're reading (later) response data.
403 memset(cp
++, 0xff, sizeof(data
->status
));
405 *cp
++ = 0x40 | cmd
->opcode
;
406 *cp
++ = (u8
)(arg
>> 24);
407 *cp
++ = (u8
)(arg
>> 16);
408 *cp
++ = (u8
)(arg
>> 8);
410 *cp
++ = (crc7(0, &data
->status
[1], 5) << 1) | 0x01;
412 /* Then, read up to 13 bytes (while writing all-ones):
413 * - N(CR) (== 1..8) bytes of all-ones
414 * - status byte (for all response types)
415 * - the rest of the response, either:
416 * + nothing, for R1 or R1B responses
417 * + second status byte, for R2 responses
418 * + four data bytes, for R3 and R7 responses
420 * Finally, read some more bytes ... in the nice cases we know in
421 * advance how many, and reading 1 more is always OK:
422 * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
423 * - N(RC) (== 1..N) bytes of all-ones, before next command
424 * - N(WR) (== 1..N) bytes of all-ones, before data write
426 * So in those cases one full duplex I/O of at most 21 bytes will
427 * handle the whole command, leaving the card ready to receive a
428 * data block or new command. We do that whenever we can, shaving
429 * CPU and IRQ costs (especially when using DMA or FIFOs).
431 * There are two other cases, where it's not generally practical
432 * to rely on a single I/O:
434 * - R1B responses need at least N(EC) bytes of all-zeroes.
436 * In this case we can *try* to fit it into one I/O, then
437 * maybe read more data later.
439 * - Data block reads are more troublesome, since a variable
440 * number of padding bytes precede the token and data.
441 * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
442 * + N(AC) (== 1..many) bytes of all-ones
444 * In this case we currently only have minimal speedups here:
445 * when N(CR) == 1 we can avoid I/O in response_get().
447 if (cs_on
&& (mrq
->data
->flags
& MMC_DATA_READ
)) {
448 cp
+= 2; /* min(N(CR)) + status */
451 cp
+= 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */
452 if (cmd
->flags
& MMC_RSP_SPI_S2
) /* R2/R5 */
454 else if (cmd
->flags
& MMC_RSP_SPI_B4
) /* R3/R4/R7 */
456 else if (cmd
->flags
& MMC_RSP_BUSY
) /* R1B */
457 cp
= data
->status
+ sizeof(data
->status
);
458 /* else: R1 (most commands) */
461 dev_dbg(&host
->spi
->dev
, " mmc_spi: CMD%d, resp %s\n",
462 cmd
->opcode
, maptype(cmd
));
464 /* send command, leaving chipselect active */
465 spi_message_init(&host
->m
);
468 memset(t
, 0, sizeof(*t
));
469 t
->tx_buf
= t
->rx_buf
= data
->status
;
470 t
->tx_dma
= t
->rx_dma
= host
->data_dma
;
471 t
->len
= cp
- data
->status
;
473 spi_message_add_tail(t
, &host
->m
);
476 host
->m
.is_dma_mapped
= 1;
477 dma_sync_single_for_device(host
->dma_dev
,
478 host
->data_dma
, sizeof(*host
->data
),
481 status
= spi_sync(host
->spi
, &host
->m
);
483 status
= host
->m
.status
;
486 dma_sync_single_for_cpu(host
->dma_dev
,
487 host
->data_dma
, sizeof(*host
->data
),
490 dev_dbg(&host
->spi
->dev
, " ... write returned %d\n", status
);
495 /* after no-data commands and STOP_TRANSMISSION, chipselect off */
496 return mmc_spi_response_get(host
, cmd
, cs_on
);
499 /* Build data message with up to four separate transfers. For TX, we
500 * start by writing the data token. And in most cases, we finish with
503 * We always provide TX data for data and CRC. The MMC/SD protocol
504 * requires us to write ones; but Linux defaults to writing zeroes;
505 * so we explicitly initialize it to all ones on RX paths.
507 * We also handle DMA mapping, so the underlying SPI controller does
508 * not need to (re)do it for each message.
511 mmc_spi_setup_data_message(
512 struct mmc_spi_host
*host
,
514 enum dma_data_direction direction
)
516 struct spi_transfer
*t
;
517 struct scratch
*scratch
= host
->data
;
518 dma_addr_t dma
= host
->data_dma
;
520 spi_message_init(&host
->m
);
522 host
->m
.is_dma_mapped
= 1;
524 /* for reads, readblock() skips 0xff bytes before finding
525 * the token; for writes, this transfer issues that token.
527 if (direction
== DMA_TO_DEVICE
) {
529 memset(t
, 0, sizeof(*t
));
532 scratch
->data_token
= SPI_TOKEN_MULTI_WRITE
;
534 scratch
->data_token
= SPI_TOKEN_SINGLE
;
535 t
->tx_buf
= &scratch
->data_token
;
537 t
->tx_dma
= dma
+ offsetof(struct scratch
, data_token
);
538 spi_message_add_tail(t
, &host
->m
);
541 /* Body of transfer is buffer, then CRC ...
542 * either TX-only, or RX with TX-ones.
545 memset(t
, 0, sizeof(*t
));
546 t
->tx_buf
= host
->ones
;
547 t
->tx_dma
= host
->ones_dma
;
548 /* length and actual buffer info are written later */
549 spi_message_add_tail(t
, &host
->m
);
552 memset(t
, 0, sizeof(*t
));
554 if (direction
== DMA_TO_DEVICE
) {
555 /* the actual CRC may get written later */
556 t
->tx_buf
= &scratch
->crc_val
;
558 t
->tx_dma
= dma
+ offsetof(struct scratch
, crc_val
);
560 t
->tx_buf
= host
->ones
;
561 t
->tx_dma
= host
->ones_dma
;
562 t
->rx_buf
= &scratch
->crc_val
;
564 t
->rx_dma
= dma
+ offsetof(struct scratch
, crc_val
);
566 spi_message_add_tail(t
, &host
->m
);
569 * A single block read is followed by N(EC) [0+] all-ones bytes
570 * before deselect ... don't bother.
572 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
573 * the next block is read, or a STOP_TRANSMISSION is issued. We'll
574 * collect that single byte, so readblock() doesn't need to.
576 * For a write, the one-byte data response follows immediately, then
577 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
578 * Then single block reads may deselect, and multiblock ones issue
579 * the next token (next data block, or STOP_TRAN). We can try to
580 * minimize I/O ops by using a single read to collect end-of-busy.
582 if (multiple
|| direction
== DMA_TO_DEVICE
) {
583 t
= &host
->early_status
;
584 memset(t
, 0, sizeof(*t
));
585 t
->len
= (direction
== DMA_TO_DEVICE
)
586 ? sizeof(scratch
->status
)
588 t
->tx_buf
= host
->ones
;
589 t
->tx_dma
= host
->ones_dma
;
590 t
->rx_buf
= scratch
->status
;
592 t
->rx_dma
= dma
+ offsetof(struct scratch
, status
);
594 spi_message_add_tail(t
, &host
->m
);
600 * - caller handled preceding N(WR) [1+] all-ones bytes
605 * - an all-ones byte ... card writes a data-response byte
606 * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
608 * Return negative errno, else success.
611 mmc_spi_writeblock(struct mmc_spi_host
*host
, struct spi_transfer
*t
)
613 struct spi_device
*spi
= host
->spi
;
615 struct scratch
*scratch
= host
->data
;
617 if (host
->mmc
->use_spi_crc
)
618 scratch
->crc_val
= cpu_to_be16(
619 crc_itu_t(0, t
->tx_buf
, t
->len
));
621 dma_sync_single_for_device(host
->dma_dev
,
622 host
->data_dma
, sizeof(*scratch
),
625 status
= spi_sync(spi
, &host
->m
);
627 status
= host
->m
.status
;
630 dev_dbg(&spi
->dev
, "write error (%d)\n", status
);
635 dma_sync_single_for_cpu(host
->dma_dev
,
636 host
->data_dma
, sizeof(*scratch
),
640 * Get the transmission data-response reply. It must follow
641 * immediately after the data block we transferred. This reply
642 * doesn't necessarily tell whether the write operation succeeded;
643 * it just says if the transmission was ok and whether *earlier*
644 * writes succeeded; see the standard.
646 switch (SPI_MMC_RESPONSE_CODE(scratch
->status
[0])) {
647 case SPI_RESPONSE_ACCEPTED
:
650 case SPI_RESPONSE_CRC_ERR
:
651 /* host shall then issue MMC_STOP_TRANSMISSION */
654 case SPI_RESPONSE_WRITE_ERR
:
655 /* host shall then issue MMC_STOP_TRANSMISSION,
656 * and should MMC_SEND_STATUS to sort it out
665 dev_dbg(&spi
->dev
, "write error %02x (%d)\n",
666 scratch
->status
[0], status
);
674 /* Return when not busy. If we didn't collect that status yet,
675 * we'll need some more I/O.
677 for (i
= 1; i
< sizeof(scratch
->status
); i
++) {
678 if (scratch
->status
[i
] != 0)
681 return mmc_spi_wait_unbusy(host
, writeblock_timeout
);
686 * - skip leading all-ones bytes ... either
687 * + N(AC) [1..f(clock,CSD)] usually, else
688 * + N(CX) [0..8] when reading CSD or CID
690 * + token ... if error token, no data or crc
694 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
695 * before dropping chipselect.
697 * For multiblock reads, caller either reads the next block or issues a
698 * STOP_TRANSMISSION command.
701 mmc_spi_readblock(struct mmc_spi_host
*host
, struct spi_transfer
*t
)
703 struct spi_device
*spi
= host
->spi
;
705 struct scratch
*scratch
= host
->data
;
707 /* At least one SD card sends an all-zeroes byte when N(CX)
708 * applies, before the all-ones bytes ... just cope with that.
710 status
= mmc_spi_readbytes(host
, 1);
713 status
= scratch
->status
[0];
714 if (status
== 0xff || status
== 0)
715 status
= mmc_spi_readtoken(host
);
717 if (status
== SPI_TOKEN_SINGLE
) {
719 dma_sync_single_for_device(host
->dma_dev
,
720 host
->data_dma
, sizeof(*scratch
),
722 dma_sync_single_for_device(host
->dma_dev
,
727 status
= spi_sync(spi
, &host
->m
);
729 status
= host
->m
.status
;
732 dma_sync_single_for_cpu(host
->dma_dev
,
733 host
->data_dma
, sizeof(*scratch
),
735 dma_sync_single_for_cpu(host
->dma_dev
,
741 dev_dbg(&spi
->dev
, "read error %02x (%d)\n", status
, status
);
743 /* we've read extra garbage, timed out, etc */
747 /* low four bits are an R2 subset, fifth seems to be
748 * vendor specific ... map them all to generic error..
753 if (host
->mmc
->use_spi_crc
) {
754 u16 crc
= crc_itu_t(0, t
->rx_buf
, t
->len
);
756 be16_to_cpus(&scratch
->crc_val
);
757 if (scratch
->crc_val
!= crc
) {
758 dev_dbg(&spi
->dev
, "read - crc error: crc_val=0x%04x, "
759 "computed=0x%04x len=%d\n",
760 scratch
->crc_val
, crc
, t
->len
);
773 * An MMC/SD data stage includes one or more blocks, optional CRCs,
774 * and inline handshaking. That handhaking makes it unlike most
775 * other SPI protocol stacks.
778 mmc_spi_data_do(struct mmc_spi_host
*host
, struct mmc_command
*cmd
,
779 struct mmc_data
*data
, u32 blk_size
)
781 struct spi_device
*spi
= host
->spi
;
782 struct device
*dma_dev
= host
->dma_dev
;
783 struct spi_transfer
*t
;
784 enum dma_data_direction direction
;
785 struct scatterlist
*sg
;
787 int multiple
= (data
->blocks
> 1);
789 if (data
->flags
& MMC_DATA_READ
)
790 direction
= DMA_FROM_DEVICE
;
792 direction
= DMA_TO_DEVICE
;
793 mmc_spi_setup_data_message(host
, multiple
, direction
);
796 /* Handle scatterlist segments one at a time, with synch for
797 * each 512-byte block
799 for (sg
= data
->sg
, n_sg
= data
->sg_len
; n_sg
; n_sg
--, sg
++) {
801 dma_addr_t dma_addr
= 0;
803 unsigned length
= sg
->length
;
804 enum dma_data_direction dir
= direction
;
806 /* set up dma mapping for controller drivers that might
807 * use DMA ... though they may fall back to PIO
810 /* never invalidate whole *shared* pages ... */
811 if ((sg
->offset
!= 0 || length
!= PAGE_SIZE
)
812 && dir
== DMA_FROM_DEVICE
)
813 dir
= DMA_BIDIRECTIONAL
;
815 dma_addr
= dma_map_page(dma_dev
, sg
->page
, 0,
817 if (direction
== DMA_TO_DEVICE
)
818 t
->tx_dma
= dma_addr
+ sg
->offset
;
820 t
->rx_dma
= dma_addr
+ sg
->offset
;
823 /* allow pio too; we don't allow highmem */
824 kmap_addr
= kmap(sg
->page
);
825 if (direction
== DMA_TO_DEVICE
)
826 t
->tx_buf
= kmap_addr
+ sg
->offset
;
828 t
->rx_buf
= kmap_addr
+ sg
->offset
;
830 /* transfer each block, and update request status */
832 t
->len
= min(length
, blk_size
);
834 dev_dbg(&host
->spi
->dev
,
835 " mmc_spi: %s block, %d bytes\n",
836 (direction
== DMA_TO_DEVICE
)
841 if (direction
== DMA_TO_DEVICE
)
842 status
= mmc_spi_writeblock(host
, t
);
844 status
= mmc_spi_readblock(host
, t
);
848 data
->bytes_xfered
+= t
->len
;
855 /* discard mappings */
856 if (direction
== DMA_FROM_DEVICE
)
857 flush_kernel_dcache_page(sg
->page
);
860 dma_unmap_page(dma_dev
, dma_addr
, PAGE_SIZE
, dir
);
863 data
->error
= status
;
864 dev_dbg(&spi
->dev
, "%s status %d\n",
865 (direction
== DMA_TO_DEVICE
)
872 /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
873 * can be issued before multiblock writes. Unlike its more widely
874 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
875 * that can affect the STOP_TRAN logic. Complete (and current)
876 * MMC specs should sort that out before Linux starts using CMD23.
878 if (direction
== DMA_TO_DEVICE
&& multiple
) {
879 struct scratch
*scratch
= host
->data
;
881 const unsigned statlen
= sizeof(scratch
->status
);
883 dev_dbg(&spi
->dev
, " mmc_spi: STOP_TRAN\n");
885 /* Tweak the per-block message we set up earlier by morphing
886 * it to hold single buffer with the token followed by some
887 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
888 * "not busy any longer" status, and leave chip selected.
890 INIT_LIST_HEAD(&host
->m
.transfers
);
891 list_add(&host
->early_status
.transfer_list
,
894 memset(scratch
->status
, 0xff, statlen
);
895 scratch
->status
[0] = SPI_TOKEN_STOP_TRAN
;
897 host
->early_status
.tx_buf
= host
->early_status
.rx_buf
;
898 host
->early_status
.tx_dma
= host
->early_status
.rx_dma
;
899 host
->early_status
.len
= statlen
;
902 dma_sync_single_for_device(host
->dma_dev
,
903 host
->data_dma
, sizeof(*scratch
),
906 tmp
= spi_sync(spi
, &host
->m
);
908 tmp
= host
->m
.status
;
911 dma_sync_single_for_cpu(host
->dma_dev
,
912 host
->data_dma
, sizeof(*scratch
),
921 /* Ideally we collected "not busy" status with one I/O,
922 * avoiding wasteful byte-at-a-time scanning... but more
923 * I/O is often needed.
925 for (tmp
= 2; tmp
< statlen
; tmp
++) {
926 if (scratch
->status
[tmp
] != 0)
929 tmp
= mmc_spi_wait_unbusy(host
, writeblock_timeout
);
930 if (tmp
< 0 && !data
->error
)
935 /****************************************************************************/
938 * MMC driver implementation -- the interface to the MMC stack
941 static void mmc_spi_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
943 struct mmc_spi_host
*host
= mmc_priv(mmc
);
944 int status
= -EINVAL
;
947 /* MMC core and layered drivers *MUST* issue SPI-aware commands */
949 struct mmc_command
*cmd
;
953 if (!mmc_spi_resp_type(cmd
)) {
954 dev_dbg(&host
->spi
->dev
, "bogus command\n");
955 cmd
->error
= -EINVAL
;
960 if (cmd
&& !mmc_spi_resp_type(cmd
)) {
961 dev_dbg(&host
->spi
->dev
, "bogus STOP command\n");
962 cmd
->error
= -EINVAL
;
968 mmc_request_done(host
->mmc
, mrq
);
974 /* issue command; then optionally data and stop */
975 status
= mmc_spi_command_send(host
, mrq
, mrq
->cmd
, mrq
->data
!= NULL
);
976 if (status
== 0 && mrq
->data
) {
977 mmc_spi_data_do(host
, mrq
->cmd
, mrq
->data
, mrq
->data
->blksz
);
979 status
= mmc_spi_command_send(host
, mrq
, mrq
->stop
, 0);
984 mmc_request_done(host
->mmc
, mrq
);
987 /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
989 * NOTE that here we can't know that the card has just been powered up;
990 * not all MMC/SD sockets support power switching.
992 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
993 * this doesn't seem to do the right thing at all...
995 static void mmc_spi_initsequence(struct mmc_spi_host
*host
)
997 /* Try to be very sure any previous command has completed;
998 * wait till not-busy, skip debris from any old commands.
1000 mmc_spi_wait_unbusy(host
, r1b_timeout
);
1001 mmc_spi_readbytes(host
, 10);
1004 * Do a burst with chipselect active-high. We need to do this to
1005 * meet the requirement of 74 clock cycles with both chipselect
1006 * and CMD (MOSI) high before CMD0 ... after the card has been
1007 * powered up to Vdd(min), and so is ready to take commands.
1009 * Some cards are particularly needy of this (e.g. Viking "SD256")
1010 * while most others don't seem to care.
1012 * Note that this is one of the places MMC/SD plays games with the
1013 * SPI protocol. Another is that when chipselect is released while
1014 * the card returns BUSY status, the clock must issue several cycles
1015 * with chipselect high before the card will stop driving its output.
1017 host
->spi
->mode
|= SPI_CS_HIGH
;
1018 if (spi_setup(host
->spi
) != 0) {
1019 /* Just warn; most cards work without it. */
1020 dev_warn(&host
->spi
->dev
,
1021 "can't change chip-select polarity\n");
1022 host
->spi
->mode
&= ~SPI_CS_HIGH
;
1024 mmc_spi_readbytes(host
, 18);
1026 host
->spi
->mode
&= ~SPI_CS_HIGH
;
1027 if (spi_setup(host
->spi
) != 0) {
1028 /* Wot, we can't get the same setup we had before? */
1029 dev_err(&host
->spi
->dev
,
1030 "can't restore chip-select polarity\n");
1035 static char *mmc_powerstring(u8 power_mode
)
1037 switch (power_mode
) {
1038 case MMC_POWER_OFF
: return "off";
1039 case MMC_POWER_UP
: return "up";
1040 case MMC_POWER_ON
: return "on";
1045 static void mmc_spi_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1047 struct mmc_spi_host
*host
= mmc_priv(mmc
);
1049 if (host
->power_mode
!= ios
->power_mode
) {
1052 canpower
= host
->pdata
&& host
->pdata
->setpower
;
1054 dev_dbg(&host
->spi
->dev
, "mmc_spi: power %s (%d)%s\n",
1055 mmc_powerstring(ios
->power_mode
),
1057 canpower
? ", can switch" : "");
1059 /* switch power on/off if possible, accounting for
1060 * max 250msec powerup time if needed.
1063 switch (ios
->power_mode
) {
1066 host
->pdata
->setpower(&host
->spi
->dev
,
1068 if (ios
->power_mode
== MMC_POWER_UP
)
1069 msleep(host
->powerup_msecs
);
1073 /* See 6.4.1 in the simplified SD card physical spec 2.0 */
1074 if (ios
->power_mode
== MMC_POWER_ON
)
1075 mmc_spi_initsequence(host
);
1077 /* If powering down, ground all card inputs to avoid power
1078 * delivery from data lines! On a shared SPI bus, this
1079 * will probably be temporary; 6.4.2 of the simplified SD
1080 * spec says this must last at least 1msec.
1082 * - Clock low means CPOL 0, e.g. mode 0
1083 * - MOSI low comes from writing zero
1084 * - Chipselect is usually active low...
1086 if (canpower
&& ios
->power_mode
== MMC_POWER_OFF
) {
1089 host
->spi
->mode
&= ~(SPI_CPOL
|SPI_CPHA
);
1090 mres
= spi_setup(host
->spi
);
1092 dev_dbg(&host
->spi
->dev
,
1093 "switch to SPI mode 0 failed\n");
1095 if (spi_w8r8(host
->spi
, 0x00) < 0)
1096 dev_dbg(&host
->spi
->dev
,
1097 "put spi signals to low failed\n");
1100 * Now clock should be low due to spi mode 0;
1101 * MOSI should be low because of written 0x00;
1102 * chipselect should be low (it is active low)
1103 * power supply is off, so now MMC is off too!
1105 * FIXME no, chipselect can be high since the
1106 * device is inactive and SPI_CS_HIGH is clear...
1110 host
->spi
->mode
|= (SPI_CPOL
|SPI_CPHA
);
1111 mres
= spi_setup(host
->spi
);
1113 dev_dbg(&host
->spi
->dev
,
1114 "switch back to SPI mode 3"
1119 host
->power_mode
= ios
->power_mode
;
1122 if (host
->spi
->max_speed_hz
!= ios
->clock
&& ios
->clock
!= 0) {
1125 host
->spi
->max_speed_hz
= ios
->clock
;
1126 status
= spi_setup(host
->spi
);
1127 dev_dbg(&host
->spi
->dev
,
1128 "mmc_spi: clock to %d Hz, %d\n",
1129 host
->spi
->max_speed_hz
, status
);
1133 static int mmc_spi_get_ro(struct mmc_host
*mmc
)
1135 struct mmc_spi_host
*host
= mmc_priv(mmc
);
1137 if (host
->pdata
&& host
->pdata
->get_ro
)
1138 return host
->pdata
->get_ro(mmc
->parent
);
1139 /* board doesn't support read only detection; assume writeable */
1144 static const struct mmc_host_ops mmc_spi_ops
= {
1145 .request
= mmc_spi_request
,
1146 .set_ios
= mmc_spi_set_ios
,
1147 .get_ro
= mmc_spi_get_ro
,
1151 /****************************************************************************/
1154 * SPI driver implementation
1158 mmc_spi_detect_irq(int irq
, void *mmc
)
1160 struct mmc_spi_host
*host
= mmc_priv(mmc
);
1161 u16 delay_msec
= max(host
->pdata
->detect_delay
, (u16
)100);
1163 mmc_detect_change(mmc
, msecs_to_jiffies(delay_msec
));
1167 static int mmc_spi_probe(struct spi_device
*spi
)
1170 struct mmc_host
*mmc
;
1171 struct mmc_spi_host
*host
;
1174 /* MMC and SD specs only seem to care that sampling is on the
1175 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
1176 * should be legit. We'll use mode 0 since it seems to be a
1177 * bit less troublesome on some hardware ... unclear why.
1179 spi
->mode
= SPI_MODE_0
;
1180 spi
->bits_per_word
= 8;
1182 status
= spi_setup(spi
);
1184 dev_dbg(&spi
->dev
, "needs SPI mode %02x, %d KHz; %d\n",
1185 spi
->mode
, spi
->max_speed_hz
/ 1000,
1190 /* We can use the bus safely iff nobody else will interfere with
1191 * us. That is, either we have the experimental exclusive access
1192 * primitives ... or else there's nobody to share it with.
1194 if (spi
->master
->num_chipselect
> 1) {
1195 struct device
*parent
= spi
->dev
.parent
;
1197 /* If there are multiple devices on this bus, we
1200 spin_lock(&parent
->klist_children
.k_lock
);
1201 if (parent
->klist_children
.k_list
.next
1202 != parent
->klist_children
.k_list
.prev
)
1206 spin_unlock(&parent
->klist_children
.k_lock
);
1208 dev_err(&spi
->dev
, "can't share SPI bus\n");
1212 /* REVISIT we can't guarantee another device won't
1213 * be added later. It's uncommon though ... for now,
1214 * work as if this is safe.
1216 dev_warn(&spi
->dev
, "ASSUMING unshared SPI bus!\n");
1219 /* We need a supply of ones to transmit. This is the only time
1220 * the CPU touches these, so cache coherency isn't a concern.
1222 * NOTE if many systems use more than one MMC-over-SPI connector
1223 * it'd save some memory to share this. That's evidently rare.
1226 ones
= kmalloc(MMC_SPI_BLOCKSIZE
, GFP_KERNEL
);
1229 memset(ones
, 0xff, MMC_SPI_BLOCKSIZE
);
1231 mmc
= mmc_alloc_host(sizeof(*host
), &spi
->dev
);
1235 mmc
->ops
= &mmc_spi_ops
;
1236 mmc
->max_blk_size
= MMC_SPI_BLOCKSIZE
;
1238 /* As long as we keep track of the number of successfully
1239 * transmitted blocks, we're good for multiwrite.
1241 mmc
->caps
= MMC_CAP_SPI
| MMC_CAP_MULTIWRITE
;
1243 /* SPI doesn't need the lowspeed device identification thing for
1244 * MMC or SD cards, since it never comes up in open drain mode.
1245 * That's good; some SPI masters can't handle very low speeds!
1247 * However, low speed SDIO cards need not handle over 400 KHz;
1248 * that's the only reason not to use a few MHz for f_min (until
1249 * the upper layer reads the target frequency from the CSD).
1251 mmc
->f_min
= 400000;
1252 mmc
->f_max
= spi
->max_speed_hz
;
1254 host
= mmc_priv(mmc
);
1260 /* Platform data is used to hook up things like card sensing
1261 * and power switching gpios.
1263 host
->pdata
= spi
->dev
.platform_data
;
1265 mmc
->ocr_avail
= host
->pdata
->ocr_mask
;
1266 if (!mmc
->ocr_avail
) {
1267 dev_warn(&spi
->dev
, "ASSUMING 3.2-3.4 V slot power\n");
1268 mmc
->ocr_avail
= MMC_VDD_32_33
|MMC_VDD_33_34
;
1270 if (host
->pdata
&& host
->pdata
->setpower
) {
1271 host
->powerup_msecs
= host
->pdata
->powerup_msecs
;
1272 if (!host
->powerup_msecs
|| host
->powerup_msecs
> 250)
1273 host
->powerup_msecs
= 250;
1276 dev_set_drvdata(&spi
->dev
, mmc
);
1278 /* preallocate dma buffers */
1279 host
->data
= kmalloc(sizeof(*host
->data
), GFP_KERNEL
);
1283 if (spi
->master
->cdev
.dev
->dma_mask
) {
1284 struct device
*dev
= spi
->master
->cdev
.dev
;
1286 host
->dma_dev
= dev
;
1287 host
->ones_dma
= dma_map_single(dev
, ones
,
1288 MMC_SPI_BLOCKSIZE
, DMA_TO_DEVICE
);
1289 host
->data_dma
= dma_map_single(dev
, host
->data
,
1290 sizeof(*host
->data
), DMA_BIDIRECTIONAL
);
1292 /* REVISIT in theory those map operations can fail... */
1294 dma_sync_single_for_cpu(host
->dma_dev
,
1295 host
->data_dma
, sizeof(*host
->data
),
1299 /* setup message for status/busy readback */
1300 spi_message_init(&host
->readback
);
1301 host
->readback
.is_dma_mapped
= (host
->dma_dev
!= NULL
);
1303 spi_message_add_tail(&host
->status
, &host
->readback
);
1304 host
->status
.tx_buf
= host
->ones
;
1305 host
->status
.tx_dma
= host
->ones_dma
;
1306 host
->status
.rx_buf
= &host
->data
->status
;
1307 host
->status
.rx_dma
= host
->data_dma
+ offsetof(struct scratch
, status
);
1308 host
->status
.cs_change
= 1;
1310 /* register card detect irq */
1311 if (host
->pdata
&& host
->pdata
->init
) {
1312 status
= host
->pdata
->init(&spi
->dev
, mmc_spi_detect_irq
, mmc
);
1314 goto fail_glue_init
;
1317 status
= mmc_add_host(mmc
);
1321 dev_info(&spi
->dev
, "SD/MMC host %s%s%s%s\n",
1322 mmc
->class_dev
.bus_id
,
1323 host
->dma_dev
? "" : ", no DMA",
1324 (host
->pdata
&& host
->pdata
->get_ro
)
1326 (host
->pdata
&& host
->pdata
->setpower
)
1327 ? "" : ", no poweroff");
1331 mmc_remove_host (mmc
);
1334 dma_unmap_single(host
->dma_dev
, host
->data_dma
,
1335 sizeof(*host
->data
), DMA_BIDIRECTIONAL
);
1340 dev_set_drvdata(&spi
->dev
, NULL
);
1348 static int __devexit
mmc_spi_remove(struct spi_device
*spi
)
1350 struct mmc_host
*mmc
= dev_get_drvdata(&spi
->dev
);
1351 struct mmc_spi_host
*host
;
1354 host
= mmc_priv(mmc
);
1356 /* prevent new mmc_detect_change() calls */
1357 if (host
->pdata
&& host
->pdata
->exit
)
1358 host
->pdata
->exit(&spi
->dev
, mmc
);
1360 mmc_remove_host(mmc
);
1362 if (host
->dma_dev
) {
1363 dma_unmap_single(host
->dma_dev
, host
->ones_dma
,
1364 MMC_SPI_BLOCKSIZE
, DMA_TO_DEVICE
);
1365 dma_unmap_single(host
->dma_dev
, host
->data_dma
,
1366 sizeof(*host
->data
), DMA_BIDIRECTIONAL
);
1372 spi
->max_speed_hz
= mmc
->f_max
;
1374 dev_set_drvdata(&spi
->dev
, NULL
);
1380 static struct spi_driver mmc_spi_driver
= {
1383 .bus
= &spi_bus_type
,
1384 .owner
= THIS_MODULE
,
1386 .probe
= mmc_spi_probe
,
1387 .remove
= __devexit_p(mmc_spi_remove
),
1391 static int __init
mmc_spi_init(void)
1393 return spi_register_driver(&mmc_spi_driver
);
1395 module_init(mmc_spi_init
);
1398 static void __exit
mmc_spi_exit(void)
1400 spi_unregister_driver(&mmc_spi_driver
);
1402 module_exit(mmc_spi_exit
);
1405 MODULE_AUTHOR("Mike Lavender, David Brownell, "
1406 "Hans-Peter Nilsson, Jan Nikitenko");
1407 MODULE_DESCRIPTION("SPI SD/MMC host driver");
1408 MODULE_LICENSE("GPL");