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ARM: 7551/1: mmc: mmci: Fix incorrect handling of HW flow control for SDIO
[deliverable/linux.git] / drivers / mmc / host / mmci.c
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/highmem.h>
22 #include <linux/log2.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/card.h>
25 #include <linux/amba/bus.h>
26 #include <linux/clk.h>
27 #include <linux/scatterlist.h>
28 #include <linux/gpio.h>
29 #include <linux/of_gpio.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/amba/mmci.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/types.h>
36
37 #include <asm/div64.h>
38 #include <asm/io.h>
39 #include <asm/sizes.h>
40
41 #include "mmci.h"
42
43 #define DRIVER_NAME "mmci-pl18x"
44
45 static unsigned int fmax = 515633;
46
47 /**
48 * struct variant_data - MMCI variant-specific quirks
49 * @clkreg: default value for MCICLOCK register
50 * @clkreg_enable: enable value for MMCICLOCK register
51 * @datalength_bits: number of bits in the MMCIDATALENGTH register
52 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
53 * is asserted (likewise for RX)
54 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
55 * is asserted (likewise for RX)
56 * @sdio: variant supports SDIO
57 * @st_clkdiv: true if using a ST-specific clock divider algorithm
58 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
59 * @pwrreg_powerup: power up value for MMCIPOWER register
60 * @signal_direction: input/out direction of bus signals can be indicated
61 */
62 struct variant_data {
63 unsigned int clkreg;
64 unsigned int clkreg_enable;
65 unsigned int datalength_bits;
66 unsigned int fifosize;
67 unsigned int fifohalfsize;
68 bool sdio;
69 bool st_clkdiv;
70 bool blksz_datactrl16;
71 u32 pwrreg_powerup;
72 bool signal_direction;
73 };
74
75 static struct variant_data variant_arm = {
76 .fifosize = 16 * 4,
77 .fifohalfsize = 8 * 4,
78 .datalength_bits = 16,
79 .pwrreg_powerup = MCI_PWR_UP,
80 };
81
82 static struct variant_data variant_arm_extended_fifo = {
83 .fifosize = 128 * 4,
84 .fifohalfsize = 64 * 4,
85 .datalength_bits = 16,
86 .pwrreg_powerup = MCI_PWR_UP,
87 };
88
89 static struct variant_data variant_u300 = {
90 .fifosize = 16 * 4,
91 .fifohalfsize = 8 * 4,
92 .clkreg_enable = MCI_ST_U300_HWFCEN,
93 .datalength_bits = 16,
94 .sdio = true,
95 .pwrreg_powerup = MCI_PWR_ON,
96 .signal_direction = true,
97 };
98
99 static struct variant_data variant_nomadik = {
100 .fifosize = 16 * 4,
101 .fifohalfsize = 8 * 4,
102 .clkreg = MCI_CLK_ENABLE,
103 .datalength_bits = 24,
104 .sdio = true,
105 .st_clkdiv = true,
106 .pwrreg_powerup = MCI_PWR_ON,
107 .signal_direction = true,
108 };
109
110 static struct variant_data variant_ux500 = {
111 .fifosize = 30 * 4,
112 .fifohalfsize = 8 * 4,
113 .clkreg = MCI_CLK_ENABLE,
114 .clkreg_enable = MCI_ST_UX500_HWFCEN,
115 .datalength_bits = 24,
116 .sdio = true,
117 .st_clkdiv = true,
118 .pwrreg_powerup = MCI_PWR_ON,
119 .signal_direction = true,
120 };
121
122 static struct variant_data variant_ux500v2 = {
123 .fifosize = 30 * 4,
124 .fifohalfsize = 8 * 4,
125 .clkreg = MCI_CLK_ENABLE,
126 .clkreg_enable = MCI_ST_UX500_HWFCEN,
127 .datalength_bits = 24,
128 .sdio = true,
129 .st_clkdiv = true,
130 .blksz_datactrl16 = true,
131 .pwrreg_powerup = MCI_PWR_ON,
132 .signal_direction = true,
133 };
134
135 /*
136 * This must be called with host->lock held
137 */
138 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
139 {
140 if (host->clk_reg != clk) {
141 host->clk_reg = clk;
142 writel(clk, host->base + MMCICLOCK);
143 }
144 }
145
146 /*
147 * This must be called with host->lock held
148 */
149 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
150 {
151 if (host->pwr_reg != pwr) {
152 host->pwr_reg = pwr;
153 writel(pwr, host->base + MMCIPOWER);
154 }
155 }
156
157 /*
158 * This must be called with host->lock held
159 */
160 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
161 {
162 struct variant_data *variant = host->variant;
163 u32 clk = variant->clkreg;
164
165 if (desired) {
166 if (desired >= host->mclk) {
167 clk = MCI_CLK_BYPASS;
168 if (variant->st_clkdiv)
169 clk |= MCI_ST_UX500_NEG_EDGE;
170 host->cclk = host->mclk;
171 } else if (variant->st_clkdiv) {
172 /*
173 * DB8500 TRM says f = mclk / (clkdiv + 2)
174 * => clkdiv = (mclk / f) - 2
175 * Round the divider up so we don't exceed the max
176 * frequency
177 */
178 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
179 if (clk >= 256)
180 clk = 255;
181 host->cclk = host->mclk / (clk + 2);
182 } else {
183 /*
184 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
185 * => clkdiv = mclk / (2 * f) - 1
186 */
187 clk = host->mclk / (2 * desired) - 1;
188 if (clk >= 256)
189 clk = 255;
190 host->cclk = host->mclk / (2 * (clk + 1));
191 }
192
193 clk |= variant->clkreg_enable;
194 clk |= MCI_CLK_ENABLE;
195 /* This hasn't proven to be worthwhile */
196 /* clk |= MCI_CLK_PWRSAVE; */
197 }
198
199 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
200 clk |= MCI_4BIT_BUS;
201 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
202 clk |= MCI_ST_8BIT_BUS;
203
204 mmci_write_clkreg(host, clk);
205 }
206
207 static void
208 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
209 {
210 writel(0, host->base + MMCICOMMAND);
211
212 BUG_ON(host->data);
213
214 host->mrq = NULL;
215 host->cmd = NULL;
216
217 mmc_request_done(host->mmc, mrq);
218
219 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
220 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
221 }
222
223 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
224 {
225 void __iomem *base = host->base;
226
227 if (host->singleirq) {
228 unsigned int mask0 = readl(base + MMCIMASK0);
229
230 mask0 &= ~MCI_IRQ1MASK;
231 mask0 |= mask;
232
233 writel(mask0, base + MMCIMASK0);
234 }
235
236 writel(mask, base + MMCIMASK1);
237 }
238
239 static void mmci_stop_data(struct mmci_host *host)
240 {
241 writel(0, host->base + MMCIDATACTRL);
242 mmci_set_mask1(host, 0);
243 host->data = NULL;
244 }
245
246 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
247 {
248 unsigned int flags = SG_MITER_ATOMIC;
249
250 if (data->flags & MMC_DATA_READ)
251 flags |= SG_MITER_TO_SG;
252 else
253 flags |= SG_MITER_FROM_SG;
254
255 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
256 }
257
258 /*
259 * All the DMA operation mode stuff goes inside this ifdef.
260 * This assumes that you have a generic DMA device interface,
261 * no custom DMA interfaces are supported.
262 */
263 #ifdef CONFIG_DMA_ENGINE
264 static void __devinit mmci_dma_setup(struct mmci_host *host)
265 {
266 struct mmci_platform_data *plat = host->plat;
267 const char *rxname, *txname;
268 dma_cap_mask_t mask;
269
270 if (!plat || !plat->dma_filter) {
271 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
272 return;
273 }
274
275 /* initialize pre request cookie */
276 host->next_data.cookie = 1;
277
278 /* Try to acquire a generic DMA engine slave channel */
279 dma_cap_zero(mask);
280 dma_cap_set(DMA_SLAVE, mask);
281
282 /*
283 * If only an RX channel is specified, the driver will
284 * attempt to use it bidirectionally, however if it is
285 * is specified but cannot be located, DMA will be disabled.
286 */
287 if (plat->dma_rx_param) {
288 host->dma_rx_channel = dma_request_channel(mask,
289 plat->dma_filter,
290 plat->dma_rx_param);
291 /* E.g if no DMA hardware is present */
292 if (!host->dma_rx_channel)
293 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
294 }
295
296 if (plat->dma_tx_param) {
297 host->dma_tx_channel = dma_request_channel(mask,
298 plat->dma_filter,
299 plat->dma_tx_param);
300 if (!host->dma_tx_channel)
301 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
302 } else {
303 host->dma_tx_channel = host->dma_rx_channel;
304 }
305
306 if (host->dma_rx_channel)
307 rxname = dma_chan_name(host->dma_rx_channel);
308 else
309 rxname = "none";
310
311 if (host->dma_tx_channel)
312 txname = dma_chan_name(host->dma_tx_channel);
313 else
314 txname = "none";
315
316 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
317 rxname, txname);
318
319 /*
320 * Limit the maximum segment size in any SG entry according to
321 * the parameters of the DMA engine device.
322 */
323 if (host->dma_tx_channel) {
324 struct device *dev = host->dma_tx_channel->device->dev;
325 unsigned int max_seg_size = dma_get_max_seg_size(dev);
326
327 if (max_seg_size < host->mmc->max_seg_size)
328 host->mmc->max_seg_size = max_seg_size;
329 }
330 if (host->dma_rx_channel) {
331 struct device *dev = host->dma_rx_channel->device->dev;
332 unsigned int max_seg_size = dma_get_max_seg_size(dev);
333
334 if (max_seg_size < host->mmc->max_seg_size)
335 host->mmc->max_seg_size = max_seg_size;
336 }
337 }
338
339 /*
340 * This is used in __devinit or __devexit so inline it
341 * so it can be discarded.
342 */
343 static inline void mmci_dma_release(struct mmci_host *host)
344 {
345 struct mmci_platform_data *plat = host->plat;
346
347 if (host->dma_rx_channel)
348 dma_release_channel(host->dma_rx_channel);
349 if (host->dma_tx_channel && plat->dma_tx_param)
350 dma_release_channel(host->dma_tx_channel);
351 host->dma_rx_channel = host->dma_tx_channel = NULL;
352 }
353
354 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
355 {
356 struct dma_chan *chan = host->dma_current;
357 enum dma_data_direction dir;
358 u32 status;
359 int i;
360
361 /* Wait up to 1ms for the DMA to complete */
362 for (i = 0; ; i++) {
363 status = readl(host->base + MMCISTATUS);
364 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
365 break;
366 udelay(10);
367 }
368
369 /*
370 * Check to see whether we still have some data left in the FIFO -
371 * this catches DMA controllers which are unable to monitor the
372 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
373 * contiguous buffers. On TX, we'll get a FIFO underrun error.
374 */
375 if (status & MCI_RXDATAAVLBLMASK) {
376 dmaengine_terminate_all(chan);
377 if (!data->error)
378 data->error = -EIO;
379 }
380
381 if (data->flags & MMC_DATA_WRITE) {
382 dir = DMA_TO_DEVICE;
383 } else {
384 dir = DMA_FROM_DEVICE;
385 }
386
387 if (!data->host_cookie)
388 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
389
390 /*
391 * Use of DMA with scatter-gather is impossible.
392 * Give up with DMA and switch back to PIO mode.
393 */
394 if (status & MCI_RXDATAAVLBLMASK) {
395 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
396 mmci_dma_release(host);
397 }
398 }
399
400 static void mmci_dma_data_error(struct mmci_host *host)
401 {
402 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
403 dmaengine_terminate_all(host->dma_current);
404 }
405
406 static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
407 struct mmci_host_next *next)
408 {
409 struct variant_data *variant = host->variant;
410 struct dma_slave_config conf = {
411 .src_addr = host->phybase + MMCIFIFO,
412 .dst_addr = host->phybase + MMCIFIFO,
413 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
414 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
415 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
416 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
417 .device_fc = false,
418 };
419 struct dma_chan *chan;
420 struct dma_device *device;
421 struct dma_async_tx_descriptor *desc;
422 enum dma_data_direction buffer_dirn;
423 int nr_sg;
424
425 /* Check if next job is already prepared */
426 if (data->host_cookie && !next &&
427 host->dma_current && host->dma_desc_current)
428 return 0;
429
430 if (!next) {
431 host->dma_current = NULL;
432 host->dma_desc_current = NULL;
433 }
434
435 if (data->flags & MMC_DATA_READ) {
436 conf.direction = DMA_DEV_TO_MEM;
437 buffer_dirn = DMA_FROM_DEVICE;
438 chan = host->dma_rx_channel;
439 } else {
440 conf.direction = DMA_MEM_TO_DEV;
441 buffer_dirn = DMA_TO_DEVICE;
442 chan = host->dma_tx_channel;
443 }
444
445 /* If there's no DMA channel, fall back to PIO */
446 if (!chan)
447 return -EINVAL;
448
449 /* If less than or equal to the fifo size, don't bother with DMA */
450 if (data->blksz * data->blocks <= variant->fifosize)
451 return -EINVAL;
452
453 device = chan->device;
454 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
455 if (nr_sg == 0)
456 return -EINVAL;
457
458 dmaengine_slave_config(chan, &conf);
459 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
460 conf.direction, DMA_CTRL_ACK);
461 if (!desc)
462 goto unmap_exit;
463
464 if (next) {
465 next->dma_chan = chan;
466 next->dma_desc = desc;
467 } else {
468 host->dma_current = chan;
469 host->dma_desc_current = desc;
470 }
471
472 return 0;
473
474 unmap_exit:
475 if (!next)
476 dmaengine_terminate_all(chan);
477 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
478 return -ENOMEM;
479 }
480
481 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
482 {
483 int ret;
484 struct mmc_data *data = host->data;
485
486 ret = mmci_dma_prep_data(host, host->data, NULL);
487 if (ret)
488 return ret;
489
490 /* Okay, go for it. */
491 dev_vdbg(mmc_dev(host->mmc),
492 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
493 data->sg_len, data->blksz, data->blocks, data->flags);
494 dmaengine_submit(host->dma_desc_current);
495 dma_async_issue_pending(host->dma_current);
496
497 datactrl |= MCI_DPSM_DMAENABLE;
498
499 /* Trigger the DMA transfer */
500 writel(datactrl, host->base + MMCIDATACTRL);
501
502 /*
503 * Let the MMCI say when the data is ended and it's time
504 * to fire next DMA request. When that happens, MMCI will
505 * call mmci_data_end()
506 */
507 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
508 host->base + MMCIMASK0);
509 return 0;
510 }
511
512 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
513 {
514 struct mmci_host_next *next = &host->next_data;
515
516 if (data->host_cookie && data->host_cookie != next->cookie) {
517 pr_warning("[%s] invalid cookie: data->host_cookie %d"
518 " host->next_data.cookie %d\n",
519 __func__, data->host_cookie, host->next_data.cookie);
520 data->host_cookie = 0;
521 }
522
523 if (!data->host_cookie)
524 return;
525
526 host->dma_desc_current = next->dma_desc;
527 host->dma_current = next->dma_chan;
528
529 next->dma_desc = NULL;
530 next->dma_chan = NULL;
531 }
532
533 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
534 bool is_first_req)
535 {
536 struct mmci_host *host = mmc_priv(mmc);
537 struct mmc_data *data = mrq->data;
538 struct mmci_host_next *nd = &host->next_data;
539
540 if (!data)
541 return;
542
543 if (data->host_cookie) {
544 data->host_cookie = 0;
545 return;
546 }
547
548 /* if config for dma */
549 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
550 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
551 if (mmci_dma_prep_data(host, data, nd))
552 data->host_cookie = 0;
553 else
554 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
555 }
556 }
557
558 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
559 int err)
560 {
561 struct mmci_host *host = mmc_priv(mmc);
562 struct mmc_data *data = mrq->data;
563 struct dma_chan *chan;
564 enum dma_data_direction dir;
565
566 if (!data)
567 return;
568
569 if (data->flags & MMC_DATA_READ) {
570 dir = DMA_FROM_DEVICE;
571 chan = host->dma_rx_channel;
572 } else {
573 dir = DMA_TO_DEVICE;
574 chan = host->dma_tx_channel;
575 }
576
577
578 /* if config for dma */
579 if (chan) {
580 if (err)
581 dmaengine_terminate_all(chan);
582 if (data->host_cookie)
583 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
584 data->sg_len, dir);
585 mrq->data->host_cookie = 0;
586 }
587 }
588
589 #else
590 /* Blank functions if the DMA engine is not available */
591 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
592 {
593 }
594 static inline void mmci_dma_setup(struct mmci_host *host)
595 {
596 }
597
598 static inline void mmci_dma_release(struct mmci_host *host)
599 {
600 }
601
602 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
603 {
604 }
605
606 static inline void mmci_dma_data_error(struct mmci_host *host)
607 {
608 }
609
610 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
611 {
612 return -ENOSYS;
613 }
614
615 #define mmci_pre_request NULL
616 #define mmci_post_request NULL
617
618 #endif
619
620 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
621 {
622 struct variant_data *variant = host->variant;
623 unsigned int datactrl, timeout, irqmask;
624 unsigned long long clks;
625 void __iomem *base;
626 int blksz_bits;
627
628 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
629 data->blksz, data->blocks, data->flags);
630
631 host->data = data;
632 host->size = data->blksz * data->blocks;
633 data->bytes_xfered = 0;
634
635 clks = (unsigned long long)data->timeout_ns * host->cclk;
636 do_div(clks, 1000000000UL);
637
638 timeout = data->timeout_clks + (unsigned int)clks;
639
640 base = host->base;
641 writel(timeout, base + MMCIDATATIMER);
642 writel(host->size, base + MMCIDATALENGTH);
643
644 blksz_bits = ffs(data->blksz) - 1;
645 BUG_ON(1 << blksz_bits != data->blksz);
646
647 if (variant->blksz_datactrl16)
648 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
649 else
650 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
651
652 if (data->flags & MMC_DATA_READ)
653 datactrl |= MCI_DPSM_DIRECTION;
654
655 /* The ST Micro variants has a special bit to enable SDIO */
656 if (variant->sdio && host->mmc->card)
657 if (mmc_card_sdio(host->mmc->card)) {
658 /*
659 * The ST Micro variants has a special bit
660 * to enable SDIO.
661 */
662 u32 clk;
663
664 datactrl |= MCI_ST_DPSM_SDIOEN;
665
666 /*
667 * The ST Micro variant for SDIO transfer sizes
668 * less then 8 bytes should have clock H/W flow
669 * control disabled.
670 */
671 if ((host->size < 8) &&
672 (data->flags & MMC_DATA_WRITE))
673 clk = host->clk_reg & ~variant->clkreg_enable;
674 else
675 clk = host->clk_reg | variant->clkreg_enable;
676
677 mmci_write_clkreg(host, clk);
678 }
679
680 /*
681 * Attempt to use DMA operation mode, if this
682 * should fail, fall back to PIO mode
683 */
684 if (!mmci_dma_start_data(host, datactrl))
685 return;
686
687 /* IRQ mode, map the SG list for CPU reading/writing */
688 mmci_init_sg(host, data);
689
690 if (data->flags & MMC_DATA_READ) {
691 irqmask = MCI_RXFIFOHALFFULLMASK;
692
693 /*
694 * If we have less than the fifo 'half-full' threshold to
695 * transfer, trigger a PIO interrupt as soon as any data
696 * is available.
697 */
698 if (host->size < variant->fifohalfsize)
699 irqmask |= MCI_RXDATAAVLBLMASK;
700 } else {
701 /*
702 * We don't actually need to include "FIFO empty" here
703 * since its implicit in "FIFO half empty".
704 */
705 irqmask = MCI_TXFIFOHALFEMPTYMASK;
706 }
707
708 writel(datactrl, base + MMCIDATACTRL);
709 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
710 mmci_set_mask1(host, irqmask);
711 }
712
713 static void
714 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
715 {
716 void __iomem *base = host->base;
717
718 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
719 cmd->opcode, cmd->arg, cmd->flags);
720
721 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
722 writel(0, base + MMCICOMMAND);
723 udelay(1);
724 }
725
726 c |= cmd->opcode | MCI_CPSM_ENABLE;
727 if (cmd->flags & MMC_RSP_PRESENT) {
728 if (cmd->flags & MMC_RSP_136)
729 c |= MCI_CPSM_LONGRSP;
730 c |= MCI_CPSM_RESPONSE;
731 }
732 if (/*interrupt*/0)
733 c |= MCI_CPSM_INTERRUPT;
734
735 host->cmd = cmd;
736
737 writel(cmd->arg, base + MMCIARGUMENT);
738 writel(c, base + MMCICOMMAND);
739 }
740
741 static void
742 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
743 unsigned int status)
744 {
745 /* First check for errors */
746 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
747 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
748 u32 remain, success;
749
750 /* Terminate the DMA transfer */
751 if (dma_inprogress(host))
752 mmci_dma_data_error(host);
753
754 /*
755 * Calculate how far we are into the transfer. Note that
756 * the data counter gives the number of bytes transferred
757 * on the MMC bus, not on the host side. On reads, this
758 * can be as much as a FIFO-worth of data ahead. This
759 * matters for FIFO overruns only.
760 */
761 remain = readl(host->base + MMCIDATACNT);
762 success = data->blksz * data->blocks - remain;
763
764 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
765 status, success);
766 if (status & MCI_DATACRCFAIL) {
767 /* Last block was not successful */
768 success -= 1;
769 data->error = -EILSEQ;
770 } else if (status & MCI_DATATIMEOUT) {
771 data->error = -ETIMEDOUT;
772 } else if (status & MCI_STARTBITERR) {
773 data->error = -ECOMM;
774 } else if (status & MCI_TXUNDERRUN) {
775 data->error = -EIO;
776 } else if (status & MCI_RXOVERRUN) {
777 if (success > host->variant->fifosize)
778 success -= host->variant->fifosize;
779 else
780 success = 0;
781 data->error = -EIO;
782 }
783 data->bytes_xfered = round_down(success, data->blksz);
784 }
785
786 if (status & MCI_DATABLOCKEND)
787 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
788
789 if (status & MCI_DATAEND || data->error) {
790 if (dma_inprogress(host))
791 mmci_dma_unmap(host, data);
792 mmci_stop_data(host);
793
794 if (!data->error)
795 /* The error clause is handled above, success! */
796 data->bytes_xfered = data->blksz * data->blocks;
797
798 if (!data->stop) {
799 mmci_request_end(host, data->mrq);
800 } else {
801 mmci_start_command(host, data->stop, 0);
802 }
803 }
804 }
805
806 static void
807 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
808 unsigned int status)
809 {
810 void __iomem *base = host->base;
811
812 host->cmd = NULL;
813
814 if (status & MCI_CMDTIMEOUT) {
815 cmd->error = -ETIMEDOUT;
816 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
817 cmd->error = -EILSEQ;
818 } else {
819 cmd->resp[0] = readl(base + MMCIRESPONSE0);
820 cmd->resp[1] = readl(base + MMCIRESPONSE1);
821 cmd->resp[2] = readl(base + MMCIRESPONSE2);
822 cmd->resp[3] = readl(base + MMCIRESPONSE3);
823 }
824
825 if (!cmd->data || cmd->error) {
826 if (host->data) {
827 /* Terminate the DMA transfer */
828 if (dma_inprogress(host))
829 mmci_dma_data_error(host);
830 mmci_stop_data(host);
831 }
832 mmci_request_end(host, cmd->mrq);
833 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
834 mmci_start_data(host, cmd->data);
835 }
836 }
837
838 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
839 {
840 void __iomem *base = host->base;
841 char *ptr = buffer;
842 u32 status;
843 int host_remain = host->size;
844
845 do {
846 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
847
848 if (count > remain)
849 count = remain;
850
851 if (count <= 0)
852 break;
853
854 /*
855 * SDIO especially may want to send something that is
856 * not divisible by 4 (as opposed to card sectors
857 * etc). Therefore make sure to always read the last bytes
858 * while only doing full 32-bit reads towards the FIFO.
859 */
860 if (unlikely(count & 0x3)) {
861 if (count < 4) {
862 unsigned char buf[4];
863 readsl(base + MMCIFIFO, buf, 1);
864 memcpy(ptr, buf, count);
865 } else {
866 readsl(base + MMCIFIFO, ptr, count >> 2);
867 count &= ~0x3;
868 }
869 } else {
870 readsl(base + MMCIFIFO, ptr, count >> 2);
871 }
872
873 ptr += count;
874 remain -= count;
875 host_remain -= count;
876
877 if (remain == 0)
878 break;
879
880 status = readl(base + MMCISTATUS);
881 } while (status & MCI_RXDATAAVLBL);
882
883 return ptr - buffer;
884 }
885
886 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
887 {
888 struct variant_data *variant = host->variant;
889 void __iomem *base = host->base;
890 char *ptr = buffer;
891
892 do {
893 unsigned int count, maxcnt;
894
895 maxcnt = status & MCI_TXFIFOEMPTY ?
896 variant->fifosize : variant->fifohalfsize;
897 count = min(remain, maxcnt);
898
899 /*
900 * SDIO especially may want to send something that is
901 * not divisible by 4 (as opposed to card sectors
902 * etc), and the FIFO only accept full 32-bit writes.
903 * So compensate by adding +3 on the count, a single
904 * byte become a 32bit write, 7 bytes will be two
905 * 32bit writes etc.
906 */
907 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
908
909 ptr += count;
910 remain -= count;
911
912 if (remain == 0)
913 break;
914
915 status = readl(base + MMCISTATUS);
916 } while (status & MCI_TXFIFOHALFEMPTY);
917
918 return ptr - buffer;
919 }
920
921 /*
922 * PIO data transfer IRQ handler.
923 */
924 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
925 {
926 struct mmci_host *host = dev_id;
927 struct sg_mapping_iter *sg_miter = &host->sg_miter;
928 struct variant_data *variant = host->variant;
929 void __iomem *base = host->base;
930 unsigned long flags;
931 u32 status;
932
933 status = readl(base + MMCISTATUS);
934
935 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
936
937 local_irq_save(flags);
938
939 do {
940 unsigned int remain, len;
941 char *buffer;
942
943 /*
944 * For write, we only need to test the half-empty flag
945 * here - if the FIFO is completely empty, then by
946 * definition it is more than half empty.
947 *
948 * For read, check for data available.
949 */
950 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
951 break;
952
953 if (!sg_miter_next(sg_miter))
954 break;
955
956 buffer = sg_miter->addr;
957 remain = sg_miter->length;
958
959 len = 0;
960 if (status & MCI_RXACTIVE)
961 len = mmci_pio_read(host, buffer, remain);
962 if (status & MCI_TXACTIVE)
963 len = mmci_pio_write(host, buffer, remain, status);
964
965 sg_miter->consumed = len;
966
967 host->size -= len;
968 remain -= len;
969
970 if (remain)
971 break;
972
973 status = readl(base + MMCISTATUS);
974 } while (1);
975
976 sg_miter_stop(sg_miter);
977
978 local_irq_restore(flags);
979
980 /*
981 * If we have less than the fifo 'half-full' threshold to transfer,
982 * trigger a PIO interrupt as soon as any data is available.
983 */
984 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
985 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
986
987 /*
988 * If we run out of data, disable the data IRQs; this
989 * prevents a race where the FIFO becomes empty before
990 * the chip itself has disabled the data path, and
991 * stops us racing with our data end IRQ.
992 */
993 if (host->size == 0) {
994 mmci_set_mask1(host, 0);
995 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
996 }
997
998 return IRQ_HANDLED;
999 }
1000
1001 /*
1002 * Handle completion of command and data transfers.
1003 */
1004 static irqreturn_t mmci_irq(int irq, void *dev_id)
1005 {
1006 struct mmci_host *host = dev_id;
1007 u32 status;
1008 int ret = 0;
1009
1010 spin_lock(&host->lock);
1011
1012 do {
1013 struct mmc_command *cmd;
1014 struct mmc_data *data;
1015
1016 status = readl(host->base + MMCISTATUS);
1017
1018 if (host->singleirq) {
1019 if (status & readl(host->base + MMCIMASK1))
1020 mmci_pio_irq(irq, dev_id);
1021
1022 status &= ~MCI_IRQ1MASK;
1023 }
1024
1025 status &= readl(host->base + MMCIMASK0);
1026 writel(status, host->base + MMCICLEAR);
1027
1028 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1029
1030 data = host->data;
1031 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1032 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1033 MCI_DATABLOCKEND) && data)
1034 mmci_data_irq(host, data, status);
1035
1036 cmd = host->cmd;
1037 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1038 mmci_cmd_irq(host, cmd, status);
1039
1040 ret = 1;
1041 } while (status);
1042
1043 spin_unlock(&host->lock);
1044
1045 return IRQ_RETVAL(ret);
1046 }
1047
1048 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1049 {
1050 struct mmci_host *host = mmc_priv(mmc);
1051 unsigned long flags;
1052
1053 WARN_ON(host->mrq != NULL);
1054
1055 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
1056 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
1057 mrq->data->blksz);
1058 mrq->cmd->error = -EINVAL;
1059 mmc_request_done(mmc, mrq);
1060 return;
1061 }
1062
1063 pm_runtime_get_sync(mmc_dev(mmc));
1064
1065 spin_lock_irqsave(&host->lock, flags);
1066
1067 host->mrq = mrq;
1068
1069 if (mrq->data)
1070 mmci_get_next_data(host, mrq->data);
1071
1072 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1073 mmci_start_data(host, mrq->data);
1074
1075 mmci_start_command(host, mrq->cmd, 0);
1076
1077 spin_unlock_irqrestore(&host->lock, flags);
1078 }
1079
1080 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1081 {
1082 struct mmci_host *host = mmc_priv(mmc);
1083 struct variant_data *variant = host->variant;
1084 u32 pwr = 0;
1085 unsigned long flags;
1086 int ret;
1087
1088 pm_runtime_get_sync(mmc_dev(mmc));
1089
1090 if (host->plat->ios_handler &&
1091 host->plat->ios_handler(mmc_dev(mmc), ios))
1092 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1093
1094 switch (ios->power_mode) {
1095 case MMC_POWER_OFF:
1096 if (host->vcc)
1097 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
1098 break;
1099 case MMC_POWER_UP:
1100 if (host->vcc) {
1101 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
1102 if (ret) {
1103 dev_err(mmc_dev(mmc), "unable to set OCR\n");
1104 /*
1105 * The .set_ios() function in the mmc_host_ops
1106 * struct return void, and failing to set the
1107 * power should be rare so we print an error
1108 * and return here.
1109 */
1110 goto out;
1111 }
1112 }
1113 /*
1114 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1115 * and instead uses MCI_PWR_ON so apply whatever value is
1116 * configured in the variant data.
1117 */
1118 pwr |= variant->pwrreg_powerup;
1119
1120 break;
1121 case MMC_POWER_ON:
1122 pwr |= MCI_PWR_ON;
1123 break;
1124 }
1125
1126 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1127 /*
1128 * The ST Micro variant has some additional bits
1129 * indicating signal direction for the signals in
1130 * the SD/MMC bus and feedback-clock usage.
1131 */
1132 pwr |= host->plat->sigdir;
1133
1134 if (ios->bus_width == MMC_BUS_WIDTH_4)
1135 pwr &= ~MCI_ST_DATA74DIREN;
1136 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1137 pwr &= (~MCI_ST_DATA74DIREN &
1138 ~MCI_ST_DATA31DIREN &
1139 ~MCI_ST_DATA2DIREN);
1140 }
1141
1142 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1143 if (host->hw_designer != AMBA_VENDOR_ST)
1144 pwr |= MCI_ROD;
1145 else {
1146 /*
1147 * The ST Micro variant use the ROD bit for something
1148 * else and only has OD (Open Drain).
1149 */
1150 pwr |= MCI_OD;
1151 }
1152 }
1153
1154 spin_lock_irqsave(&host->lock, flags);
1155
1156 mmci_set_clkreg(host, ios->clock);
1157 mmci_write_pwrreg(host, pwr);
1158
1159 spin_unlock_irqrestore(&host->lock, flags);
1160
1161 out:
1162 pm_runtime_mark_last_busy(mmc_dev(mmc));
1163 pm_runtime_put_autosuspend(mmc_dev(mmc));
1164 }
1165
1166 static int mmci_get_ro(struct mmc_host *mmc)
1167 {
1168 struct mmci_host *host = mmc_priv(mmc);
1169
1170 if (host->gpio_wp == -ENOSYS)
1171 return -ENOSYS;
1172
1173 return gpio_get_value_cansleep(host->gpio_wp);
1174 }
1175
1176 static int mmci_get_cd(struct mmc_host *mmc)
1177 {
1178 struct mmci_host *host = mmc_priv(mmc);
1179 struct mmci_platform_data *plat = host->plat;
1180 unsigned int status;
1181
1182 if (host->gpio_cd == -ENOSYS) {
1183 if (!plat->status)
1184 return 1; /* Assume always present */
1185
1186 status = plat->status(mmc_dev(host->mmc));
1187 } else
1188 status = !!gpio_get_value_cansleep(host->gpio_cd)
1189 ^ plat->cd_invert;
1190
1191 /*
1192 * Use positive logic throughout - status is zero for no card,
1193 * non-zero for card inserted.
1194 */
1195 return status;
1196 }
1197
1198 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1199 {
1200 struct mmci_host *host = dev_id;
1201
1202 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1203
1204 return IRQ_HANDLED;
1205 }
1206
1207 static const struct mmc_host_ops mmci_ops = {
1208 .request = mmci_request,
1209 .pre_req = mmci_pre_request,
1210 .post_req = mmci_post_request,
1211 .set_ios = mmci_set_ios,
1212 .get_ro = mmci_get_ro,
1213 .get_cd = mmci_get_cd,
1214 };
1215
1216 #ifdef CONFIG_OF
1217 static void mmci_dt_populate_generic_pdata(struct device_node *np,
1218 struct mmci_platform_data *pdata)
1219 {
1220 int bus_width = 0;
1221
1222 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1223 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
1224
1225 if (of_get_property(np, "cd-inverted", NULL))
1226 pdata->cd_invert = true;
1227 else
1228 pdata->cd_invert = false;
1229
1230 of_property_read_u32(np, "max-frequency", &pdata->f_max);
1231 if (!pdata->f_max)
1232 pr_warn("%s has no 'max-frequency' property\n", np->full_name);
1233
1234 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1235 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
1236 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1237 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;
1238
1239 of_property_read_u32(np, "bus-width", &bus_width);
1240 switch (bus_width) {
1241 case 0 :
1242 /* No bus-width supplied. */
1243 break;
1244 case 4 :
1245 pdata->capabilities |= MMC_CAP_4_BIT_DATA;
1246 break;
1247 case 8 :
1248 pdata->capabilities |= MMC_CAP_8_BIT_DATA;
1249 break;
1250 default :
1251 pr_warn("%s: Unsupported bus width\n", np->full_name);
1252 }
1253 }
1254 #else
1255 static void mmci_dt_populate_generic_pdata(struct device_node *np,
1256 struct mmci_platform_data *pdata)
1257 {
1258 return;
1259 }
1260 #endif
1261
1262 static int __devinit mmci_probe(struct amba_device *dev,
1263 const struct amba_id *id)
1264 {
1265 struct mmci_platform_data *plat = dev->dev.platform_data;
1266 struct device_node *np = dev->dev.of_node;
1267 struct variant_data *variant = id->data;
1268 struct mmci_host *host;
1269 struct mmc_host *mmc;
1270 int ret;
1271
1272 /* Must have platform data or Device Tree. */
1273 if (!plat && !np) {
1274 dev_err(&dev->dev, "No plat data or DT found\n");
1275 return -EINVAL;
1276 }
1277
1278 if (!plat) {
1279 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1280 if (!plat)
1281 return -ENOMEM;
1282 }
1283
1284 if (np)
1285 mmci_dt_populate_generic_pdata(np, plat);
1286
1287 ret = amba_request_regions(dev, DRIVER_NAME);
1288 if (ret)
1289 goto out;
1290
1291 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1292 if (!mmc) {
1293 ret = -ENOMEM;
1294 goto rel_regions;
1295 }
1296
1297 host = mmc_priv(mmc);
1298 host->mmc = mmc;
1299
1300 host->gpio_wp = -ENOSYS;
1301 host->gpio_cd = -ENOSYS;
1302 host->gpio_cd_irq = -1;
1303
1304 host->hw_designer = amba_manf(dev);
1305 host->hw_revision = amba_rev(dev);
1306 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1307 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1308
1309 host->clk = clk_get(&dev->dev, NULL);
1310 if (IS_ERR(host->clk)) {
1311 ret = PTR_ERR(host->clk);
1312 host->clk = NULL;
1313 goto host_free;
1314 }
1315
1316 ret = clk_prepare_enable(host->clk);
1317 if (ret)
1318 goto clk_free;
1319
1320 host->plat = plat;
1321 host->variant = variant;
1322 host->mclk = clk_get_rate(host->clk);
1323 /*
1324 * According to the spec, mclk is max 100 MHz,
1325 * so we try to adjust the clock down to this,
1326 * (if possible).
1327 */
1328 if (host->mclk > 100000000) {
1329 ret = clk_set_rate(host->clk, 100000000);
1330 if (ret < 0)
1331 goto clk_disable;
1332 host->mclk = clk_get_rate(host->clk);
1333 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1334 host->mclk);
1335 }
1336 host->phybase = dev->res.start;
1337 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1338 if (!host->base) {
1339 ret = -ENOMEM;
1340 goto clk_disable;
1341 }
1342
1343 mmc->ops = &mmci_ops;
1344 /*
1345 * The ARM and ST versions of the block have slightly different
1346 * clock divider equations which means that the minimum divider
1347 * differs too.
1348 */
1349 if (variant->st_clkdiv)
1350 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1351 else
1352 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1353 /*
1354 * If the platform data supplies a maximum operating
1355 * frequency, this takes precedence. Else, we fall back
1356 * to using the module parameter, which has a (low)
1357 * default value in case it is not specified. Either
1358 * value must not exceed the clock rate into the block,
1359 * of course.
1360 */
1361 if (plat->f_max)
1362 mmc->f_max = min(host->mclk, plat->f_max);
1363 else
1364 mmc->f_max = min(host->mclk, fmax);
1365 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1366
1367 #ifdef CONFIG_REGULATOR
1368 /* If we're using the regulator framework, try to fetch a regulator */
1369 host->vcc = regulator_get(&dev->dev, "vmmc");
1370 if (IS_ERR(host->vcc))
1371 host->vcc = NULL;
1372 else {
1373 int mask = mmc_regulator_get_ocrmask(host->vcc);
1374
1375 if (mask < 0)
1376 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1377 mask);
1378 else {
1379 host->mmc->ocr_avail = (u32) mask;
1380 if (plat->ocr_mask)
1381 dev_warn(&dev->dev,
1382 "Provided ocr_mask/setpower will not be used "
1383 "(using regulator instead)\n");
1384 }
1385 }
1386 #endif
1387 /* Fall back to platform data if no regulator is found */
1388 if (host->vcc == NULL)
1389 mmc->ocr_avail = plat->ocr_mask;
1390 mmc->caps = plat->capabilities;
1391 mmc->caps2 = plat->capabilities2;
1392
1393 /*
1394 * We can do SGIO
1395 */
1396 mmc->max_segs = NR_SG;
1397
1398 /*
1399 * Since only a certain number of bits are valid in the data length
1400 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1401 * single request.
1402 */
1403 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1404
1405 /*
1406 * Set the maximum segment size. Since we aren't doing DMA
1407 * (yet) we are only limited by the data length register.
1408 */
1409 mmc->max_seg_size = mmc->max_req_size;
1410
1411 /*
1412 * Block size can be up to 2048 bytes, but must be a power of two.
1413 */
1414 mmc->max_blk_size = 1 << 11;
1415
1416 /*
1417 * Limit the number of blocks transferred so that we don't overflow
1418 * the maximum request size.
1419 */
1420 mmc->max_blk_count = mmc->max_req_size >> 11;
1421
1422 spin_lock_init(&host->lock);
1423
1424 writel(0, host->base + MMCIMASK0);
1425 writel(0, host->base + MMCIMASK1);
1426 writel(0xfff, host->base + MMCICLEAR);
1427
1428 if (plat->gpio_cd == -EPROBE_DEFER) {
1429 ret = -EPROBE_DEFER;
1430 goto err_gpio_cd;
1431 }
1432 if (gpio_is_valid(plat->gpio_cd)) {
1433 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1434 if (ret == 0)
1435 ret = gpio_direction_input(plat->gpio_cd);
1436 if (ret == 0)
1437 host->gpio_cd = plat->gpio_cd;
1438 else if (ret != -ENOSYS)
1439 goto err_gpio_cd;
1440
1441 /*
1442 * A gpio pin that will detect cards when inserted and removed
1443 * will most likely want to trigger on the edges if it is
1444 * 0 when ejected and 1 when inserted (or mutatis mutandis
1445 * for the inverted case) so we request triggers on both
1446 * edges.
1447 */
1448 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1449 mmci_cd_irq,
1450 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1451 DRIVER_NAME " (cd)", host);
1452 if (ret >= 0)
1453 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1454 }
1455 if (plat->gpio_wp == -EPROBE_DEFER) {
1456 ret = -EPROBE_DEFER;
1457 goto err_gpio_wp;
1458 }
1459 if (gpio_is_valid(plat->gpio_wp)) {
1460 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1461 if (ret == 0)
1462 ret = gpio_direction_input(plat->gpio_wp);
1463 if (ret == 0)
1464 host->gpio_wp = plat->gpio_wp;
1465 else if (ret != -ENOSYS)
1466 goto err_gpio_wp;
1467 }
1468
1469 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1470 && host->gpio_cd_irq < 0)
1471 mmc->caps |= MMC_CAP_NEEDS_POLL;
1472
1473 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1474 if (ret)
1475 goto unmap;
1476
1477 if (!dev->irq[1])
1478 host->singleirq = true;
1479 else {
1480 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1481 DRIVER_NAME " (pio)", host);
1482 if (ret)
1483 goto irq0_free;
1484 }
1485
1486 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1487
1488 amba_set_drvdata(dev, mmc);
1489
1490 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1491 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1492 amba_rev(dev), (unsigned long long)dev->res.start,
1493 dev->irq[0], dev->irq[1]);
1494
1495 mmci_dma_setup(host);
1496
1497 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1498 pm_runtime_use_autosuspend(&dev->dev);
1499 pm_runtime_put(&dev->dev);
1500
1501 mmc_add_host(mmc);
1502
1503 return 0;
1504
1505 irq0_free:
1506 free_irq(dev->irq[0], host);
1507 unmap:
1508 if (host->gpio_wp != -ENOSYS)
1509 gpio_free(host->gpio_wp);
1510 err_gpio_wp:
1511 if (host->gpio_cd_irq >= 0)
1512 free_irq(host->gpio_cd_irq, host);
1513 if (host->gpio_cd != -ENOSYS)
1514 gpio_free(host->gpio_cd);
1515 err_gpio_cd:
1516 iounmap(host->base);
1517 clk_disable:
1518 clk_disable_unprepare(host->clk);
1519 clk_free:
1520 clk_put(host->clk);
1521 host_free:
1522 mmc_free_host(mmc);
1523 rel_regions:
1524 amba_release_regions(dev);
1525 out:
1526 return ret;
1527 }
1528
1529 static int __devexit mmci_remove(struct amba_device *dev)
1530 {
1531 struct mmc_host *mmc = amba_get_drvdata(dev);
1532
1533 amba_set_drvdata(dev, NULL);
1534
1535 if (mmc) {
1536 struct mmci_host *host = mmc_priv(mmc);
1537
1538 /*
1539 * Undo pm_runtime_put() in probe. We use the _sync
1540 * version here so that we can access the primecell.
1541 */
1542 pm_runtime_get_sync(&dev->dev);
1543
1544 mmc_remove_host(mmc);
1545
1546 writel(0, host->base + MMCIMASK0);
1547 writel(0, host->base + MMCIMASK1);
1548
1549 writel(0, host->base + MMCICOMMAND);
1550 writel(0, host->base + MMCIDATACTRL);
1551
1552 mmci_dma_release(host);
1553 free_irq(dev->irq[0], host);
1554 if (!host->singleirq)
1555 free_irq(dev->irq[1], host);
1556
1557 if (host->gpio_wp != -ENOSYS)
1558 gpio_free(host->gpio_wp);
1559 if (host->gpio_cd_irq >= 0)
1560 free_irq(host->gpio_cd_irq, host);
1561 if (host->gpio_cd != -ENOSYS)
1562 gpio_free(host->gpio_cd);
1563
1564 iounmap(host->base);
1565 clk_disable_unprepare(host->clk);
1566 clk_put(host->clk);
1567
1568 if (host->vcc)
1569 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1570 regulator_put(host->vcc);
1571
1572 mmc_free_host(mmc);
1573
1574 amba_release_regions(dev);
1575 }
1576
1577 return 0;
1578 }
1579
1580 #ifdef CONFIG_SUSPEND
1581 static int mmci_suspend(struct device *dev)
1582 {
1583 struct amba_device *adev = to_amba_device(dev);
1584 struct mmc_host *mmc = amba_get_drvdata(adev);
1585 int ret = 0;
1586
1587 if (mmc) {
1588 struct mmci_host *host = mmc_priv(mmc);
1589
1590 ret = mmc_suspend_host(mmc);
1591 if (ret == 0) {
1592 pm_runtime_get_sync(dev);
1593 writel(0, host->base + MMCIMASK0);
1594 }
1595 }
1596
1597 return ret;
1598 }
1599
1600 static int mmci_resume(struct device *dev)
1601 {
1602 struct amba_device *adev = to_amba_device(dev);
1603 struct mmc_host *mmc = amba_get_drvdata(adev);
1604 int ret = 0;
1605
1606 if (mmc) {
1607 struct mmci_host *host = mmc_priv(mmc);
1608
1609 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1610 pm_runtime_put(dev);
1611
1612 ret = mmc_resume_host(mmc);
1613 }
1614
1615 return ret;
1616 }
1617 #endif
1618
1619 static const struct dev_pm_ops mmci_dev_pm_ops = {
1620 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
1621 };
1622
1623 static struct amba_id mmci_ids[] = {
1624 {
1625 .id = 0x00041180,
1626 .mask = 0xff0fffff,
1627 .data = &variant_arm,
1628 },
1629 {
1630 .id = 0x01041180,
1631 .mask = 0xff0fffff,
1632 .data = &variant_arm_extended_fifo,
1633 },
1634 {
1635 .id = 0x00041181,
1636 .mask = 0x000fffff,
1637 .data = &variant_arm,
1638 },
1639 /* ST Micro variants */
1640 {
1641 .id = 0x00180180,
1642 .mask = 0x00ffffff,
1643 .data = &variant_u300,
1644 },
1645 {
1646 .id = 0x10180180,
1647 .mask = 0xf0ffffff,
1648 .data = &variant_nomadik,
1649 },
1650 {
1651 .id = 0x00280180,
1652 .mask = 0x00ffffff,
1653 .data = &variant_u300,
1654 },
1655 {
1656 .id = 0x00480180,
1657 .mask = 0xf0ffffff,
1658 .data = &variant_ux500,
1659 },
1660 {
1661 .id = 0x10480180,
1662 .mask = 0xf0ffffff,
1663 .data = &variant_ux500v2,
1664 },
1665 { 0, 0 },
1666 };
1667
1668 MODULE_DEVICE_TABLE(amba, mmci_ids);
1669
1670 static struct amba_driver mmci_driver = {
1671 .drv = {
1672 .name = DRIVER_NAME,
1673 .pm = &mmci_dev_pm_ops,
1674 },
1675 .probe = mmci_probe,
1676 .remove = __devexit_p(mmci_remove),
1677 .id_table = mmci_ids,
1678 };
1679
1680 module_amba_driver(mmci_driver);
1681
1682 module_param(fmax, uint, 0444);
1683
1684 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1685 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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