projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: mmci: Remove redundant check of status for DATA irq
[deliverable/linux.git] / drivers / mmc / host / mmci.c
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
40
41 #include <asm/div64.h>
42 #include <asm/io.h>
43 #include <asm/sizes.h>
44
45 #include "mmci.h"
46
47 #define DRIVER_NAME "mmci-pl18x"
48
49 static unsigned int fmax = 515633;
50
51 /**
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
54 * @clkreg_enable: enable value for MMCICLOCK register
55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
57 * @datalength_bits: number of bits in the MMCIDATALENGTH register
58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
59 * is asserted (likewise for RX)
60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
61 * is asserted (likewise for RX)
62 * @data_cmd_enable: enable value for data commands.
63 * @sdio: variant supports SDIO
64 * @st_clkdiv: true if using a ST-specific clock divider algorithm
65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
68 * register
69 * @pwrreg_powerup: power up value for MMCIPOWER register
70 * @f_max: maximum clk frequency supported by the controller.
71 * @signal_direction: input/out direction of bus signals can be indicated
72 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
73 * @busy_detect: true if busy detection on dat0 is supported
74 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
75 * @explicit_mclk_control: enable explicit mclk control in driver.
76 * @qcom_fifo: enables qcom specific fifo pio read logic.
77 */
78 struct variant_data {
79 unsigned int clkreg;
80 unsigned int clkreg_enable;
81 unsigned int clkreg_8bit_bus_enable;
82 unsigned int clkreg_neg_edge_enable;
83 unsigned int datalength_bits;
84 unsigned int fifosize;
85 unsigned int fifohalfsize;
86 unsigned int data_cmd_enable;
87 unsigned int datactrl_mask_ddrmode;
88 bool sdio;
89 bool st_clkdiv;
90 bool blksz_datactrl16;
91 bool blksz_datactrl4;
92 u32 pwrreg_powerup;
93 u32 f_max;
94 bool signal_direction;
95 bool pwrreg_clkgate;
96 bool busy_detect;
97 bool pwrreg_nopower;
98 bool explicit_mclk_control;
99 bool qcom_fifo;
100 };
101
102 static struct variant_data variant_arm = {
103 .fifosize = 16 * 4,
104 .fifohalfsize = 8 * 4,
105 .datalength_bits = 16,
106 .pwrreg_powerup = MCI_PWR_UP,
107 .f_max = 100000000,
108 };
109
110 static struct variant_data variant_arm_extended_fifo = {
111 .fifosize = 128 * 4,
112 .fifohalfsize = 64 * 4,
113 .datalength_bits = 16,
114 .pwrreg_powerup = MCI_PWR_UP,
115 .f_max = 100000000,
116 };
117
118 static struct variant_data variant_arm_extended_fifo_hwfc = {
119 .fifosize = 128 * 4,
120 .fifohalfsize = 64 * 4,
121 .clkreg_enable = MCI_ARM_HWFCEN,
122 .datalength_bits = 16,
123 .pwrreg_powerup = MCI_PWR_UP,
124 .f_max = 100000000,
125 };
126
127 static struct variant_data variant_u300 = {
128 .fifosize = 16 * 4,
129 .fifohalfsize = 8 * 4,
130 .clkreg_enable = MCI_ST_U300_HWFCEN,
131 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
132 .datalength_bits = 16,
133 .sdio = true,
134 .pwrreg_powerup = MCI_PWR_ON,
135 .f_max = 100000000,
136 .signal_direction = true,
137 .pwrreg_clkgate = true,
138 .pwrreg_nopower = true,
139 };
140
141 static struct variant_data variant_nomadik = {
142 .fifosize = 16 * 4,
143 .fifohalfsize = 8 * 4,
144 .clkreg = MCI_CLK_ENABLE,
145 .datalength_bits = 24,
146 .sdio = true,
147 .st_clkdiv = true,
148 .pwrreg_powerup = MCI_PWR_ON,
149 .f_max = 100000000,
150 .signal_direction = true,
151 .pwrreg_clkgate = true,
152 .pwrreg_nopower = true,
153 };
154
155 static struct variant_data variant_ux500 = {
156 .fifosize = 30 * 4,
157 .fifohalfsize = 8 * 4,
158 .clkreg = MCI_CLK_ENABLE,
159 .clkreg_enable = MCI_ST_UX500_HWFCEN,
160 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
161 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
162 .datalength_bits = 24,
163 .sdio = true,
164 .st_clkdiv = true,
165 .pwrreg_powerup = MCI_PWR_ON,
166 .f_max = 100000000,
167 .signal_direction = true,
168 .pwrreg_clkgate = true,
169 .busy_detect = true,
170 .pwrreg_nopower = true,
171 };
172
173 static struct variant_data variant_ux500v2 = {
174 .fifosize = 30 * 4,
175 .fifohalfsize = 8 * 4,
176 .clkreg = MCI_CLK_ENABLE,
177 .clkreg_enable = MCI_ST_UX500_HWFCEN,
178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
180 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
181 .datalength_bits = 24,
182 .sdio = true,
183 .st_clkdiv = true,
184 .blksz_datactrl16 = true,
185 .pwrreg_powerup = MCI_PWR_ON,
186 .f_max = 100000000,
187 .signal_direction = true,
188 .pwrreg_clkgate = true,
189 .busy_detect = true,
190 .pwrreg_nopower = true,
191 };
192
193 static struct variant_data variant_qcom = {
194 .fifosize = 16 * 4,
195 .fifohalfsize = 8 * 4,
196 .clkreg = MCI_CLK_ENABLE,
197 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
198 MCI_QCOM_CLK_SELECT_IN_FBCLK,
199 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
200 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
201 .data_cmd_enable = MCI_QCOM_CSPM_DATCMD,
202 .blksz_datactrl4 = true,
203 .datalength_bits = 24,
204 .pwrreg_powerup = MCI_PWR_UP,
205 .f_max = 208000000,
206 .explicit_mclk_control = true,
207 .qcom_fifo = true,
208 };
209
210 static int mmci_card_busy(struct mmc_host *mmc)
211 {
212 struct mmci_host *host = mmc_priv(mmc);
213 unsigned long flags;
214 int busy = 0;
215
216 pm_runtime_get_sync(mmc_dev(mmc));
217
218 spin_lock_irqsave(&host->lock, flags);
219 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
220 busy = 1;
221 spin_unlock_irqrestore(&host->lock, flags);
222
223 pm_runtime_mark_last_busy(mmc_dev(mmc));
224 pm_runtime_put_autosuspend(mmc_dev(mmc));
225
226 return busy;
227 }
228
229 /*
230 * Validate mmc prerequisites
231 */
232 static int mmci_validate_data(struct mmci_host *host,
233 struct mmc_data *data)
234 {
235 if (!data)
236 return 0;
237
238 if (!is_power_of_2(data->blksz)) {
239 dev_err(mmc_dev(host->mmc),
240 "unsupported block size (%d bytes)\n", data->blksz);
241 return -EINVAL;
242 }
243
244 return 0;
245 }
246
247 static void mmci_reg_delay(struct mmci_host *host)
248 {
249 /*
250 * According to the spec, at least three feedback clock cycles
251 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
252 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
253 * Worst delay time during card init is at 100 kHz => 30 us.
254 * Worst delay time when up and running is at 25 MHz => 120 ns.
255 */
256 if (host->cclk < 25000000)
257 udelay(30);
258 else
259 ndelay(120);
260 }
261
262 /*
263 * This must be called with host->lock held
264 */
265 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
266 {
267 if (host->clk_reg != clk) {
268 host->clk_reg = clk;
269 writel(clk, host->base + MMCICLOCK);
270 }
271 }
272
273 /*
274 * This must be called with host->lock held
275 */
276 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
277 {
278 if (host->pwr_reg != pwr) {
279 host->pwr_reg = pwr;
280 writel(pwr, host->base + MMCIPOWER);
281 }
282 }
283
284 /*
285 * This must be called with host->lock held
286 */
287 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
288 {
289 /* Keep ST Micro busy mode if enabled */
290 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
291
292 if (host->datactrl_reg != datactrl) {
293 host->datactrl_reg = datactrl;
294 writel(datactrl, host->base + MMCIDATACTRL);
295 }
296 }
297
298 /*
299 * This must be called with host->lock held
300 */
301 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
302 {
303 struct variant_data *variant = host->variant;
304 u32 clk = variant->clkreg;
305
306 /* Make sure cclk reflects the current calculated clock */
307 host->cclk = 0;
308
309 if (desired) {
310 if (variant->explicit_mclk_control) {
311 host->cclk = host->mclk;
312 } else if (desired >= host->mclk) {
313 clk = MCI_CLK_BYPASS;
314 if (variant->st_clkdiv)
315 clk |= MCI_ST_UX500_NEG_EDGE;
316 host->cclk = host->mclk;
317 } else if (variant->st_clkdiv) {
318 /*
319 * DB8500 TRM says f = mclk / (clkdiv + 2)
320 * => clkdiv = (mclk / f) - 2
321 * Round the divider up so we don't exceed the max
322 * frequency
323 */
324 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
325 if (clk >= 256)
326 clk = 255;
327 host->cclk = host->mclk / (clk + 2);
328 } else {
329 /*
330 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
331 * => clkdiv = mclk / (2 * f) - 1
332 */
333 clk = host->mclk / (2 * desired) - 1;
334 if (clk >= 256)
335 clk = 255;
336 host->cclk = host->mclk / (2 * (clk + 1));
337 }
338
339 clk |= variant->clkreg_enable;
340 clk |= MCI_CLK_ENABLE;
341 /* This hasn't proven to be worthwhile */
342 /* clk |= MCI_CLK_PWRSAVE; */
343 }
344
345 /* Set actual clock for debug */
346 host->mmc->actual_clock = host->cclk;
347
348 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
349 clk |= MCI_4BIT_BUS;
350 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
351 clk |= variant->clkreg_8bit_bus_enable;
352
353 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
354 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
355 clk |= variant->clkreg_neg_edge_enable;
356
357 mmci_write_clkreg(host, clk);
358 }
359
360 static void
361 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
362 {
363 writel(0, host->base + MMCICOMMAND);
364
365 BUG_ON(host->data);
366
367 host->mrq = NULL;
368 host->cmd = NULL;
369
370 mmc_request_done(host->mmc, mrq);
371
372 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
373 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
374 }
375
376 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
377 {
378 void __iomem *base = host->base;
379
380 if (host->singleirq) {
381 unsigned int mask0 = readl(base + MMCIMASK0);
382
383 mask0 &= ~MCI_IRQ1MASK;
384 mask0 |= mask;
385
386 writel(mask0, base + MMCIMASK0);
387 }
388
389 writel(mask, base + MMCIMASK1);
390 }
391
392 static void mmci_stop_data(struct mmci_host *host)
393 {
394 mmci_write_datactrlreg(host, 0);
395 mmci_set_mask1(host, 0);
396 host->data = NULL;
397 }
398
399 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
400 {
401 unsigned int flags = SG_MITER_ATOMIC;
402
403 if (data->flags & MMC_DATA_READ)
404 flags |= SG_MITER_TO_SG;
405 else
406 flags |= SG_MITER_FROM_SG;
407
408 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
409 }
410
411 /*
412 * All the DMA operation mode stuff goes inside this ifdef.
413 * This assumes that you have a generic DMA device interface,
414 * no custom DMA interfaces are supported.
415 */
416 #ifdef CONFIG_DMA_ENGINE
417 static void mmci_dma_setup(struct mmci_host *host)
418 {
419 const char *rxname, *txname;
420 dma_cap_mask_t mask;
421
422 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
423 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
424
425 /* initialize pre request cookie */
426 host->next_data.cookie = 1;
427
428 /* Try to acquire a generic DMA engine slave channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
432 /*
433 * If only an RX channel is specified, the driver will
434 * attempt to use it bidirectionally, however if it is
435 * is specified but cannot be located, DMA will be disabled.
436 */
437 if (host->dma_rx_channel && !host->dma_tx_channel)
438 host->dma_tx_channel = host->dma_rx_channel;
439
440 if (host->dma_rx_channel)
441 rxname = dma_chan_name(host->dma_rx_channel);
442 else
443 rxname = "none";
444
445 if (host->dma_tx_channel)
446 txname = dma_chan_name(host->dma_tx_channel);
447 else
448 txname = "none";
449
450 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
451 rxname, txname);
452
453 /*
454 * Limit the maximum segment size in any SG entry according to
455 * the parameters of the DMA engine device.
456 */
457 if (host->dma_tx_channel) {
458 struct device *dev = host->dma_tx_channel->device->dev;
459 unsigned int max_seg_size = dma_get_max_seg_size(dev);
460
461 if (max_seg_size < host->mmc->max_seg_size)
462 host->mmc->max_seg_size = max_seg_size;
463 }
464 if (host->dma_rx_channel) {
465 struct device *dev = host->dma_rx_channel->device->dev;
466 unsigned int max_seg_size = dma_get_max_seg_size(dev);
467
468 if (max_seg_size < host->mmc->max_seg_size)
469 host->mmc->max_seg_size = max_seg_size;
470 }
471 }
472
473 /*
474 * This is used in or so inline it
475 * so it can be discarded.
476 */
477 static inline void mmci_dma_release(struct mmci_host *host)
478 {
479 if (host->dma_rx_channel)
480 dma_release_channel(host->dma_rx_channel);
481 if (host->dma_tx_channel)
482 dma_release_channel(host->dma_tx_channel);
483 host->dma_rx_channel = host->dma_tx_channel = NULL;
484 }
485
486 static void mmci_dma_data_error(struct mmci_host *host)
487 {
488 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
489 dmaengine_terminate_all(host->dma_current);
490 host->dma_current = NULL;
491 host->dma_desc_current = NULL;
492 host->data->host_cookie = 0;
493 }
494
495 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
496 {
497 struct dma_chan *chan;
498 enum dma_data_direction dir;
499
500 if (data->flags & MMC_DATA_READ) {
501 dir = DMA_FROM_DEVICE;
502 chan = host->dma_rx_channel;
503 } else {
504 dir = DMA_TO_DEVICE;
505 chan = host->dma_tx_channel;
506 }
507
508 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
509 }
510
511 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
512 {
513 u32 status;
514 int i;
515
516 /* Wait up to 1ms for the DMA to complete */
517 for (i = 0; ; i++) {
518 status = readl(host->base + MMCISTATUS);
519 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
520 break;
521 udelay(10);
522 }
523
524 /*
525 * Check to see whether we still have some data left in the FIFO -
526 * this catches DMA controllers which are unable to monitor the
527 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
528 * contiguous buffers. On TX, we'll get a FIFO underrun error.
529 */
530 if (status & MCI_RXDATAAVLBLMASK) {
531 mmci_dma_data_error(host);
532 if (!data->error)
533 data->error = -EIO;
534 }
535
536 if (!data->host_cookie)
537 mmci_dma_unmap(host, data);
538
539 /*
540 * Use of DMA with scatter-gather is impossible.
541 * Give up with DMA and switch back to PIO mode.
542 */
543 if (status & MCI_RXDATAAVLBLMASK) {
544 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
545 mmci_dma_release(host);
546 }
547
548 host->dma_current = NULL;
549 host->dma_desc_current = NULL;
550 }
551
552 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
553 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
554 struct dma_chan **dma_chan,
555 struct dma_async_tx_descriptor **dma_desc)
556 {
557 struct variant_data *variant = host->variant;
558 struct dma_slave_config conf = {
559 .src_addr = host->phybase + MMCIFIFO,
560 .dst_addr = host->phybase + MMCIFIFO,
561 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
562 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
563 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
564 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
565 .device_fc = false,
566 };
567 struct dma_chan *chan;
568 struct dma_device *device;
569 struct dma_async_tx_descriptor *desc;
570 enum dma_data_direction buffer_dirn;
571 int nr_sg;
572
573 if (data->flags & MMC_DATA_READ) {
574 conf.direction = DMA_DEV_TO_MEM;
575 buffer_dirn = DMA_FROM_DEVICE;
576 chan = host->dma_rx_channel;
577 } else {
578 conf.direction = DMA_MEM_TO_DEV;
579 buffer_dirn = DMA_TO_DEVICE;
580 chan = host->dma_tx_channel;
581 }
582
583 /* If there's no DMA channel, fall back to PIO */
584 if (!chan)
585 return -EINVAL;
586
587 /* If less than or equal to the fifo size, don't bother with DMA */
588 if (data->blksz * data->blocks <= variant->fifosize)
589 return -EINVAL;
590
591 device = chan->device;
592 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
593 if (nr_sg == 0)
594 return -EINVAL;
595
596 dmaengine_slave_config(chan, &conf);
597 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
598 conf.direction, DMA_CTRL_ACK);
599 if (!desc)
600 goto unmap_exit;
601
602 *dma_chan = chan;
603 *dma_desc = desc;
604
605 return 0;
606
607 unmap_exit:
608 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
609 return -ENOMEM;
610 }
611
612 static inline int mmci_dma_prep_data(struct mmci_host *host,
613 struct mmc_data *data)
614 {
615 /* Check if next job is already prepared. */
616 if (host->dma_current && host->dma_desc_current)
617 return 0;
618
619 /* No job were prepared thus do it now. */
620 return __mmci_dma_prep_data(host, data, &host->dma_current,
621 &host->dma_desc_current);
622 }
623
624 static inline int mmci_dma_prep_next(struct mmci_host *host,
625 struct mmc_data *data)
626 {
627 struct mmci_host_next *nd = &host->next_data;
628 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
629 }
630
631 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
632 {
633 int ret;
634 struct mmc_data *data = host->data;
635
636 ret = mmci_dma_prep_data(host, host->data);
637 if (ret)
638 return ret;
639
640 /* Okay, go for it. */
641 dev_vdbg(mmc_dev(host->mmc),
642 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
643 data->sg_len, data->blksz, data->blocks, data->flags);
644 dmaengine_submit(host->dma_desc_current);
645 dma_async_issue_pending(host->dma_current);
646
647 datactrl |= MCI_DPSM_DMAENABLE;
648
649 /* Trigger the DMA transfer */
650 mmci_write_datactrlreg(host, datactrl);
651
652 /*
653 * Let the MMCI say when the data is ended and it's time
654 * to fire next DMA request. When that happens, MMCI will
655 * call mmci_data_end()
656 */
657 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
658 host->base + MMCIMASK0);
659 return 0;
660 }
661
662 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
663 {
664 struct mmci_host_next *next = &host->next_data;
665
666 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
667 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
668
669 host->dma_desc_current = next->dma_desc;
670 host->dma_current = next->dma_chan;
671 next->dma_desc = NULL;
672 next->dma_chan = NULL;
673 }
674
675 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
676 bool is_first_req)
677 {
678 struct mmci_host *host = mmc_priv(mmc);
679 struct mmc_data *data = mrq->data;
680 struct mmci_host_next *nd = &host->next_data;
681
682 if (!data)
683 return;
684
685 BUG_ON(data->host_cookie);
686
687 if (mmci_validate_data(host, data))
688 return;
689
690 if (!mmci_dma_prep_next(host, data))
691 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
692 }
693
694 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
695 int err)
696 {
697 struct mmci_host *host = mmc_priv(mmc);
698 struct mmc_data *data = mrq->data;
699
700 if (!data || !data->host_cookie)
701 return;
702
703 mmci_dma_unmap(host, data);
704
705 if (err) {
706 struct mmci_host_next *next = &host->next_data;
707 struct dma_chan *chan;
708 if (data->flags & MMC_DATA_READ)
709 chan = host->dma_rx_channel;
710 else
711 chan = host->dma_tx_channel;
712 dmaengine_terminate_all(chan);
713
714 next->dma_desc = NULL;
715 next->dma_chan = NULL;
716 }
717 }
718
719 #else
720 /* Blank functions if the DMA engine is not available */
721 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
722 {
723 }
724 static inline void mmci_dma_setup(struct mmci_host *host)
725 {
726 }
727
728 static inline void mmci_dma_release(struct mmci_host *host)
729 {
730 }
731
732 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
733 {
734 }
735
736 static inline void mmci_dma_finalize(struct mmci_host *host,
737 struct mmc_data *data)
738 {
739 }
740
741 static inline void mmci_dma_data_error(struct mmci_host *host)
742 {
743 }
744
745 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
746 {
747 return -ENOSYS;
748 }
749
750 #define mmci_pre_request NULL
751 #define mmci_post_request NULL
752
753 #endif
754
755 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
756 {
757 struct variant_data *variant = host->variant;
758 unsigned int datactrl, timeout, irqmask;
759 unsigned long long clks;
760 void __iomem *base;
761 int blksz_bits;
762
763 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
764 data->blksz, data->blocks, data->flags);
765
766 host->data = data;
767 host->size = data->blksz * data->blocks;
768 data->bytes_xfered = 0;
769
770 clks = (unsigned long long)data->timeout_ns * host->cclk;
771 do_div(clks, NSEC_PER_SEC);
772
773 timeout = data->timeout_clks + (unsigned int)clks;
774
775 base = host->base;
776 writel(timeout, base + MMCIDATATIMER);
777 writel(host->size, base + MMCIDATALENGTH);
778
779 blksz_bits = ffs(data->blksz) - 1;
780 BUG_ON(1 << blksz_bits != data->blksz);
781
782 if (variant->blksz_datactrl16)
783 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
784 else if (variant->blksz_datactrl4)
785 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
786 else
787 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
788
789 if (data->flags & MMC_DATA_READ)
790 datactrl |= MCI_DPSM_DIRECTION;
791
792 /* The ST Micro variants has a special bit to enable SDIO */
793 if (variant->sdio && host->mmc->card)
794 if (mmc_card_sdio(host->mmc->card)) {
795 /*
796 * The ST Micro variants has a special bit
797 * to enable SDIO.
798 */
799 u32 clk;
800
801 datactrl |= MCI_ST_DPSM_SDIOEN;
802
803 /*
804 * The ST Micro variant for SDIO small write transfers
805 * needs to have clock H/W flow control disabled,
806 * otherwise the transfer will not start. The threshold
807 * depends on the rate of MCLK.
808 */
809 if (data->flags & MMC_DATA_WRITE &&
810 (host->size < 8 ||
811 (host->size <= 8 && host->mclk > 50000000)))
812 clk = host->clk_reg & ~variant->clkreg_enable;
813 else
814 clk = host->clk_reg | variant->clkreg_enable;
815
816 mmci_write_clkreg(host, clk);
817 }
818
819 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
820 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
821 datactrl |= variant->datactrl_mask_ddrmode;
822
823 /*
824 * Attempt to use DMA operation mode, if this
825 * should fail, fall back to PIO mode
826 */
827 if (!mmci_dma_start_data(host, datactrl))
828 return;
829
830 /* IRQ mode, map the SG list for CPU reading/writing */
831 mmci_init_sg(host, data);
832
833 if (data->flags & MMC_DATA_READ) {
834 irqmask = MCI_RXFIFOHALFFULLMASK;
835
836 /*
837 * If we have less than the fifo 'half-full' threshold to
838 * transfer, trigger a PIO interrupt as soon as any data
839 * is available.
840 */
841 if (host->size < variant->fifohalfsize)
842 irqmask |= MCI_RXDATAAVLBLMASK;
843 } else {
844 /*
845 * We don't actually need to include "FIFO empty" here
846 * since its implicit in "FIFO half empty".
847 */
848 irqmask = MCI_TXFIFOHALFEMPTYMASK;
849 }
850
851 mmci_write_datactrlreg(host, datactrl);
852 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
853 mmci_set_mask1(host, irqmask);
854 }
855
856 static void
857 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
858 {
859 void __iomem *base = host->base;
860
861 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
862 cmd->opcode, cmd->arg, cmd->flags);
863
864 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
865 writel(0, base + MMCICOMMAND);
866 mmci_reg_delay(host);
867 }
868
869 c |= cmd->opcode | MCI_CPSM_ENABLE;
870 if (cmd->flags & MMC_RSP_PRESENT) {
871 if (cmd->flags & MMC_RSP_136)
872 c |= MCI_CPSM_LONGRSP;
873 c |= MCI_CPSM_RESPONSE;
874 }
875 if (/*interrupt*/0)
876 c |= MCI_CPSM_INTERRUPT;
877
878 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
879 c |= host->variant->data_cmd_enable;
880
881 host->cmd = cmd;
882
883 writel(cmd->arg, base + MMCIARGUMENT);
884 writel(c, base + MMCICOMMAND);
885 }
886
887 static void
888 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
889 unsigned int status)
890 {
891 /* Make sure we have data to handle */
892 if (!data)
893 return;
894
895 /* First check for errors */
896 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
897 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
898 u32 remain, success;
899
900 /* Terminate the DMA transfer */
901 if (dma_inprogress(host)) {
902 mmci_dma_data_error(host);
903 mmci_dma_unmap(host, data);
904 }
905
906 /*
907 * Calculate how far we are into the transfer. Note that
908 * the data counter gives the number of bytes transferred
909 * on the MMC bus, not on the host side. On reads, this
910 * can be as much as a FIFO-worth of data ahead. This
911 * matters for FIFO overruns only.
912 */
913 remain = readl(host->base + MMCIDATACNT);
914 success = data->blksz * data->blocks - remain;
915
916 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
917 status, success);
918 if (status & MCI_DATACRCFAIL) {
919 /* Last block was not successful */
920 success -= 1;
921 data->error = -EILSEQ;
922 } else if (status & MCI_DATATIMEOUT) {
923 data->error = -ETIMEDOUT;
924 } else if (status & MCI_STARTBITERR) {
925 data->error = -ECOMM;
926 } else if (status & MCI_TXUNDERRUN) {
927 data->error = -EIO;
928 } else if (status & MCI_RXOVERRUN) {
929 if (success > host->variant->fifosize)
930 success -= host->variant->fifosize;
931 else
932 success = 0;
933 data->error = -EIO;
934 }
935 data->bytes_xfered = round_down(success, data->blksz);
936 }
937
938 if (status & MCI_DATABLOCKEND)
939 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
940
941 if (status & MCI_DATAEND || data->error) {
942 if (dma_inprogress(host))
943 mmci_dma_finalize(host, data);
944 mmci_stop_data(host);
945
946 if (!data->error)
947 /* The error clause is handled above, success! */
948 data->bytes_xfered = data->blksz * data->blocks;
949
950 if (!data->stop || host->mrq->sbc) {
951 mmci_request_end(host, data->mrq);
952 } else {
953 mmci_start_command(host, data->stop, 0);
954 }
955 }
956 }
957
958 static void
959 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
960 unsigned int status)
961 {
962 void __iomem *base = host->base;
963 bool sbc = (cmd == host->mrq->sbc);
964 bool busy_resp = host->variant->busy_detect &&
965 (cmd->flags & MMC_RSP_BUSY);
966
967 /* Check if we need to wait for busy completion. */
968 if (host->busy_status && (status & MCI_ST_CARDBUSY))
969 return;
970
971 /* Enable busy completion if needed and supported. */
972 if (!host->busy_status && busy_resp &&
973 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
974 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
975 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
976 base + MMCIMASK0);
977 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
978 return;
979 }
980
981 /* At busy completion, mask the IRQ and complete the request. */
982 if (host->busy_status) {
983 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
984 base + MMCIMASK0);
985 host->busy_status = 0;
986 }
987
988 host->cmd = NULL;
989
990 if (status & MCI_CMDTIMEOUT) {
991 cmd->error = -ETIMEDOUT;
992 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
993 cmd->error = -EILSEQ;
994 } else {
995 cmd->resp[0] = readl(base + MMCIRESPONSE0);
996 cmd->resp[1] = readl(base + MMCIRESPONSE1);
997 cmd->resp[2] = readl(base + MMCIRESPONSE2);
998 cmd->resp[3] = readl(base + MMCIRESPONSE3);
999 }
1000
1001 if ((!sbc && !cmd->data) || cmd->error) {
1002 if (host->data) {
1003 /* Terminate the DMA transfer */
1004 if (dma_inprogress(host)) {
1005 mmci_dma_data_error(host);
1006 mmci_dma_unmap(host, host->data);
1007 }
1008 mmci_stop_data(host);
1009 }
1010 mmci_request_end(host, host->mrq);
1011 } else if (sbc) {
1012 mmci_start_command(host, host->mrq->cmd, 0);
1013 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1014 mmci_start_data(host, cmd->data);
1015 }
1016 }
1017
1018 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1019 {
1020 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1021 }
1022
1023 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1024 {
1025 /*
1026 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1027 * from the fifo range should be used
1028 */
1029 if (status & MCI_RXFIFOHALFFULL)
1030 return host->variant->fifohalfsize;
1031 else if (status & MCI_RXDATAAVLBL)
1032 return 4;
1033
1034 return 0;
1035 }
1036
1037 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1038 {
1039 void __iomem *base = host->base;
1040 char *ptr = buffer;
1041 u32 status = readl(host->base + MMCISTATUS);
1042 int host_remain = host->size;
1043
1044 do {
1045 int count = host->get_rx_fifocnt(host, status, host_remain);
1046
1047 if (count > remain)
1048 count = remain;
1049
1050 if (count <= 0)
1051 break;
1052
1053 /*
1054 * SDIO especially may want to send something that is
1055 * not divisible by 4 (as opposed to card sectors
1056 * etc). Therefore make sure to always read the last bytes
1057 * while only doing full 32-bit reads towards the FIFO.
1058 */
1059 if (unlikely(count & 0x3)) {
1060 if (count < 4) {
1061 unsigned char buf[4];
1062 ioread32_rep(base + MMCIFIFO, buf, 1);
1063 memcpy(ptr, buf, count);
1064 } else {
1065 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1066 count &= ~0x3;
1067 }
1068 } else {
1069 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1070 }
1071
1072 ptr += count;
1073 remain -= count;
1074 host_remain -= count;
1075
1076 if (remain == 0)
1077 break;
1078
1079 status = readl(base + MMCISTATUS);
1080 } while (status & MCI_RXDATAAVLBL);
1081
1082 return ptr - buffer;
1083 }
1084
1085 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1086 {
1087 struct variant_data *variant = host->variant;
1088 void __iomem *base = host->base;
1089 char *ptr = buffer;
1090
1091 do {
1092 unsigned int count, maxcnt;
1093
1094 maxcnt = status & MCI_TXFIFOEMPTY ?
1095 variant->fifosize : variant->fifohalfsize;
1096 count = min(remain, maxcnt);
1097
1098 /*
1099 * SDIO especially may want to send something that is
1100 * not divisible by 4 (as opposed to card sectors
1101 * etc), and the FIFO only accept full 32-bit writes.
1102 * So compensate by adding +3 on the count, a single
1103 * byte become a 32bit write, 7 bytes will be two
1104 * 32bit writes etc.
1105 */
1106 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1107
1108 ptr += count;
1109 remain -= count;
1110
1111 if (remain == 0)
1112 break;
1113
1114 status = readl(base + MMCISTATUS);
1115 } while (status & MCI_TXFIFOHALFEMPTY);
1116
1117 return ptr - buffer;
1118 }
1119
1120 /*
1121 * PIO data transfer IRQ handler.
1122 */
1123 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1124 {
1125 struct mmci_host *host = dev_id;
1126 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1127 struct variant_data *variant = host->variant;
1128 void __iomem *base = host->base;
1129 unsigned long flags;
1130 u32 status;
1131
1132 status = readl(base + MMCISTATUS);
1133
1134 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1135
1136 local_irq_save(flags);
1137
1138 do {
1139 unsigned int remain, len;
1140 char *buffer;
1141
1142 /*
1143 * For write, we only need to test the half-empty flag
1144 * here - if the FIFO is completely empty, then by
1145 * definition it is more than half empty.
1146 *
1147 * For read, check for data available.
1148 */
1149 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1150 break;
1151
1152 if (!sg_miter_next(sg_miter))
1153 break;
1154
1155 buffer = sg_miter->addr;
1156 remain = sg_miter->length;
1157
1158 len = 0;
1159 if (status & MCI_RXACTIVE)
1160 len = mmci_pio_read(host, buffer, remain);
1161 if (status & MCI_TXACTIVE)
1162 len = mmci_pio_write(host, buffer, remain, status);
1163
1164 sg_miter->consumed = len;
1165
1166 host->size -= len;
1167 remain -= len;
1168
1169 if (remain)
1170 break;
1171
1172 status = readl(base + MMCISTATUS);
1173 } while (1);
1174
1175 sg_miter_stop(sg_miter);
1176
1177 local_irq_restore(flags);
1178
1179 /*
1180 * If we have less than the fifo 'half-full' threshold to transfer,
1181 * trigger a PIO interrupt as soon as any data is available.
1182 */
1183 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1184 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1185
1186 /*
1187 * If we run out of data, disable the data IRQs; this
1188 * prevents a race where the FIFO becomes empty before
1189 * the chip itself has disabled the data path, and
1190 * stops us racing with our data end IRQ.
1191 */
1192 if (host->size == 0) {
1193 mmci_set_mask1(host, 0);
1194 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1195 }
1196
1197 return IRQ_HANDLED;
1198 }
1199
1200 /*
1201 * Handle completion of command and data transfers.
1202 */
1203 static irqreturn_t mmci_irq(int irq, void *dev_id)
1204 {
1205 struct mmci_host *host = dev_id;
1206 u32 status;
1207 int ret = 0;
1208
1209 spin_lock(&host->lock);
1210
1211 do {
1212 struct mmc_command *cmd;
1213
1214 status = readl(host->base + MMCISTATUS);
1215
1216 if (host->singleirq) {
1217 if (status & readl(host->base + MMCIMASK1))
1218 mmci_pio_irq(irq, dev_id);
1219
1220 status &= ~MCI_IRQ1MASK;
1221 }
1222
1223 /*
1224 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1225 * enabled) since the HW seems to be triggering the IRQ on both
1226 * edges while monitoring DAT0 for busy completion.
1227 */
1228 status &= readl(host->base + MMCIMASK0);
1229 writel(status, host->base + MMCICLEAR);
1230
1231 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1232
1233 cmd = host->cmd;
1234 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
1235 MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1236 mmci_cmd_irq(host, cmd, status);
1237
1238 mmci_data_irq(host, host->data, status);
1239
1240 /* Don't poll for busy completion in irq context. */
1241 if (host->busy_status)
1242 status &= ~MCI_ST_CARDBUSY;
1243
1244 ret = 1;
1245 } while (status);
1246
1247 spin_unlock(&host->lock);
1248
1249 return IRQ_RETVAL(ret);
1250 }
1251
1252 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1253 {
1254 struct mmci_host *host = mmc_priv(mmc);
1255 unsigned long flags;
1256
1257 WARN_ON(host->mrq != NULL);
1258
1259 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1260 if (mrq->cmd->error) {
1261 mmc_request_done(mmc, mrq);
1262 return;
1263 }
1264
1265 pm_runtime_get_sync(mmc_dev(mmc));
1266
1267 spin_lock_irqsave(&host->lock, flags);
1268
1269 host->mrq = mrq;
1270
1271 if (mrq->data)
1272 mmci_get_next_data(host, mrq->data);
1273
1274 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1275 mmci_start_data(host, mrq->data);
1276
1277 if (mrq->sbc)
1278 mmci_start_command(host, mrq->sbc, 0);
1279 else
1280 mmci_start_command(host, mrq->cmd, 0);
1281
1282 spin_unlock_irqrestore(&host->lock, flags);
1283 }
1284
1285 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1286 {
1287 struct mmci_host *host = mmc_priv(mmc);
1288 struct variant_data *variant = host->variant;
1289 u32 pwr = 0;
1290 unsigned long flags;
1291 int ret;
1292
1293 pm_runtime_get_sync(mmc_dev(mmc));
1294
1295 if (host->plat->ios_handler &&
1296 host->plat->ios_handler(mmc_dev(mmc), ios))
1297 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1298
1299 switch (ios->power_mode) {
1300 case MMC_POWER_OFF:
1301 if (!IS_ERR(mmc->supply.vmmc))
1302 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1303
1304 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1305 regulator_disable(mmc->supply.vqmmc);
1306 host->vqmmc_enabled = false;
1307 }
1308
1309 break;
1310 case MMC_POWER_UP:
1311 if (!IS_ERR(mmc->supply.vmmc))
1312 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1313
1314 /*
1315 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1316 * and instead uses MCI_PWR_ON so apply whatever value is
1317 * configured in the variant data.
1318 */
1319 pwr |= variant->pwrreg_powerup;
1320
1321 break;
1322 case MMC_POWER_ON:
1323 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1324 ret = regulator_enable(mmc->supply.vqmmc);
1325 if (ret < 0)
1326 dev_err(mmc_dev(mmc),
1327 "failed to enable vqmmc regulator\n");
1328 else
1329 host->vqmmc_enabled = true;
1330 }
1331
1332 pwr |= MCI_PWR_ON;
1333 break;
1334 }
1335
1336 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1337 /*
1338 * The ST Micro variant has some additional bits
1339 * indicating signal direction for the signals in
1340 * the SD/MMC bus and feedback-clock usage.
1341 */
1342 pwr |= host->pwr_reg_add;
1343
1344 if (ios->bus_width == MMC_BUS_WIDTH_4)
1345 pwr &= ~MCI_ST_DATA74DIREN;
1346 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1347 pwr &= (~MCI_ST_DATA74DIREN &
1348 ~MCI_ST_DATA31DIREN &
1349 ~MCI_ST_DATA2DIREN);
1350 }
1351
1352 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1353 if (host->hw_designer != AMBA_VENDOR_ST)
1354 pwr |= MCI_ROD;
1355 else {
1356 /*
1357 * The ST Micro variant use the ROD bit for something
1358 * else and only has OD (Open Drain).
1359 */
1360 pwr |= MCI_OD;
1361 }
1362 }
1363
1364 /*
1365 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1366 * gating the clock, the MCI_PWR_ON bit is cleared.
1367 */
1368 if (!ios->clock && variant->pwrreg_clkgate)
1369 pwr &= ~MCI_PWR_ON;
1370
1371 if (host->variant->explicit_mclk_control &&
1372 ios->clock != host->clock_cache) {
1373 ret = clk_set_rate(host->clk, ios->clock);
1374 if (ret < 0)
1375 dev_err(mmc_dev(host->mmc),
1376 "Error setting clock rate (%d)\n", ret);
1377 else
1378 host->mclk = clk_get_rate(host->clk);
1379 }
1380 host->clock_cache = ios->clock;
1381
1382 spin_lock_irqsave(&host->lock, flags);
1383
1384 mmci_set_clkreg(host, ios->clock);
1385 mmci_write_pwrreg(host, pwr);
1386 mmci_reg_delay(host);
1387
1388 spin_unlock_irqrestore(&host->lock, flags);
1389
1390 pm_runtime_mark_last_busy(mmc_dev(mmc));
1391 pm_runtime_put_autosuspend(mmc_dev(mmc));
1392 }
1393
1394 static int mmci_get_cd(struct mmc_host *mmc)
1395 {
1396 struct mmci_host *host = mmc_priv(mmc);
1397 struct mmci_platform_data *plat = host->plat;
1398 unsigned int status = mmc_gpio_get_cd(mmc);
1399
1400 if (status == -ENOSYS) {
1401 if (!plat->status)
1402 return 1; /* Assume always present */
1403
1404 status = plat->status(mmc_dev(host->mmc));
1405 }
1406 return status;
1407 }
1408
1409 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1410 {
1411 int ret = 0;
1412
1413 if (!IS_ERR(mmc->supply.vqmmc)) {
1414
1415 pm_runtime_get_sync(mmc_dev(mmc));
1416
1417 switch (ios->signal_voltage) {
1418 case MMC_SIGNAL_VOLTAGE_330:
1419 ret = regulator_set_voltage(mmc->supply.vqmmc,
1420 2700000, 3600000);
1421 break;
1422 case MMC_SIGNAL_VOLTAGE_180:
1423 ret = regulator_set_voltage(mmc->supply.vqmmc,
1424 1700000, 1950000);
1425 break;
1426 case MMC_SIGNAL_VOLTAGE_120:
1427 ret = regulator_set_voltage(mmc->supply.vqmmc,
1428 1100000, 1300000);
1429 break;
1430 }
1431
1432 if (ret)
1433 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1434
1435 pm_runtime_mark_last_busy(mmc_dev(mmc));
1436 pm_runtime_put_autosuspend(mmc_dev(mmc));
1437 }
1438
1439 return ret;
1440 }
1441
1442 static struct mmc_host_ops mmci_ops = {
1443 .request = mmci_request,
1444 .pre_req = mmci_pre_request,
1445 .post_req = mmci_post_request,
1446 .set_ios = mmci_set_ios,
1447 .get_ro = mmc_gpio_get_ro,
1448 .get_cd = mmci_get_cd,
1449 .start_signal_voltage_switch = mmci_sig_volt_switch,
1450 };
1451
1452 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1453 {
1454 struct mmci_host *host = mmc_priv(mmc);
1455 int ret = mmc_of_parse(mmc);
1456
1457 if (ret)
1458 return ret;
1459
1460 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1461 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1462 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1463 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1464 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1465 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1466 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1467 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1468 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1469 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1470 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1471 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1472
1473 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1474 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1475 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1476 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1477
1478 return 0;
1479 }
1480
1481 static int mmci_probe(struct amba_device *dev,
1482 const struct amba_id *id)
1483 {
1484 struct mmci_platform_data *plat = dev->dev.platform_data;
1485 struct device_node *np = dev->dev.of_node;
1486 struct variant_data *variant = id->data;
1487 struct mmci_host *host;
1488 struct mmc_host *mmc;
1489 int ret;
1490
1491 /* Must have platform data or Device Tree. */
1492 if (!plat && !np) {
1493 dev_err(&dev->dev, "No plat data or DT found\n");
1494 return -EINVAL;
1495 }
1496
1497 if (!plat) {
1498 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1499 if (!plat)
1500 return -ENOMEM;
1501 }
1502
1503 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1504 if (!mmc)
1505 return -ENOMEM;
1506
1507 ret = mmci_of_parse(np, mmc);
1508 if (ret)
1509 goto host_free;
1510
1511 host = mmc_priv(mmc);
1512 host->mmc = mmc;
1513
1514 host->hw_designer = amba_manf(dev);
1515 host->hw_revision = amba_rev(dev);
1516 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1517 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1518
1519 host->clk = devm_clk_get(&dev->dev, NULL);
1520 if (IS_ERR(host->clk)) {
1521 ret = PTR_ERR(host->clk);
1522 goto host_free;
1523 }
1524
1525 ret = clk_prepare_enable(host->clk);
1526 if (ret)
1527 goto host_free;
1528
1529 if (variant->qcom_fifo)
1530 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1531 else
1532 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1533
1534 host->plat = plat;
1535 host->variant = variant;
1536 host->mclk = clk_get_rate(host->clk);
1537 /*
1538 * According to the spec, mclk is max 100 MHz,
1539 * so we try to adjust the clock down to this,
1540 * (if possible).
1541 */
1542 if (host->mclk > variant->f_max) {
1543 ret = clk_set_rate(host->clk, variant->f_max);
1544 if (ret < 0)
1545 goto clk_disable;
1546 host->mclk = clk_get_rate(host->clk);
1547 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1548 host->mclk);
1549 }
1550
1551 host->phybase = dev->res.start;
1552 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1553 if (IS_ERR(host->base)) {
1554 ret = PTR_ERR(host->base);
1555 goto clk_disable;
1556 }
1557
1558 /*
1559 * The ARM and ST versions of the block have slightly different
1560 * clock divider equations which means that the minimum divider
1561 * differs too.
1562 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1563 */
1564 if (variant->st_clkdiv)
1565 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1566 else if (variant->explicit_mclk_control)
1567 mmc->f_min = clk_round_rate(host->clk, 100000);
1568 else
1569 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1570 /*
1571 * If no maximum operating frequency is supplied, fall back to use
1572 * the module parameter, which has a (low) default value in case it
1573 * is not specified. Either value must not exceed the clock rate into
1574 * the block, of course.
1575 */
1576 if (mmc->f_max)
1577 mmc->f_max = variant->explicit_mclk_control ?
1578 min(variant->f_max, mmc->f_max) :
1579 min(host->mclk, mmc->f_max);
1580 else
1581 mmc->f_max = variant->explicit_mclk_control ?
1582 fmax : min(host->mclk, fmax);
1583
1584
1585 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1586
1587 /* Get regulators and the supported OCR mask */
1588 mmc_regulator_get_supply(mmc);
1589 if (!mmc->ocr_avail)
1590 mmc->ocr_avail = plat->ocr_mask;
1591 else if (plat->ocr_mask)
1592 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1593
1594 /* DT takes precedence over platform data. */
1595 if (!np) {
1596 if (!plat->cd_invert)
1597 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1598 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1599 }
1600
1601 /* We support these capabilities. */
1602 mmc->caps |= MMC_CAP_CMD23;
1603
1604 if (variant->busy_detect) {
1605 mmci_ops.card_busy = mmci_card_busy;
1606 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1607 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1608 mmc->max_busy_timeout = 0;
1609 }
1610
1611 mmc->ops = &mmci_ops;
1612
1613 /* We support these PM capabilities. */
1614 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1615
1616 /*
1617 * We can do SGIO
1618 */
1619 mmc->max_segs = NR_SG;
1620
1621 /*
1622 * Since only a certain number of bits are valid in the data length
1623 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1624 * single request.
1625 */
1626 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1627
1628 /*
1629 * Set the maximum segment size. Since we aren't doing DMA
1630 * (yet) we are only limited by the data length register.
1631 */
1632 mmc->max_seg_size = mmc->max_req_size;
1633
1634 /*
1635 * Block size can be up to 2048 bytes, but must be a power of two.
1636 */
1637 mmc->max_blk_size = 1 << 11;
1638
1639 /*
1640 * Limit the number of blocks transferred so that we don't overflow
1641 * the maximum request size.
1642 */
1643 mmc->max_blk_count = mmc->max_req_size >> 11;
1644
1645 spin_lock_init(&host->lock);
1646
1647 writel(0, host->base + MMCIMASK0);
1648 writel(0, host->base + MMCIMASK1);
1649 writel(0xfff, host->base + MMCICLEAR);
1650
1651 /* If DT, cd/wp gpios must be supplied through it. */
1652 if (!np && gpio_is_valid(plat->gpio_cd)) {
1653 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1654 if (ret)
1655 goto clk_disable;
1656 }
1657 if (!np && gpio_is_valid(plat->gpio_wp)) {
1658 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1659 if (ret)
1660 goto clk_disable;
1661 }
1662
1663 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1664 DRIVER_NAME " (cmd)", host);
1665 if (ret)
1666 goto clk_disable;
1667
1668 if (!dev->irq[1])
1669 host->singleirq = true;
1670 else {
1671 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1672 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1673 if (ret)
1674 goto clk_disable;
1675 }
1676
1677 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1678
1679 amba_set_drvdata(dev, mmc);
1680
1681 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1682 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1683 amba_rev(dev), (unsigned long long)dev->res.start,
1684 dev->irq[0], dev->irq[1]);
1685
1686 mmci_dma_setup(host);
1687
1688 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1689 pm_runtime_use_autosuspend(&dev->dev);
1690 pm_runtime_put(&dev->dev);
1691
1692 mmc_add_host(mmc);
1693
1694 return 0;
1695
1696 clk_disable:
1697 clk_disable_unprepare(host->clk);
1698 host_free:
1699 mmc_free_host(mmc);
1700 return ret;
1701 }
1702
1703 static int mmci_remove(struct amba_device *dev)
1704 {
1705 struct mmc_host *mmc = amba_get_drvdata(dev);
1706
1707 if (mmc) {
1708 struct mmci_host *host = mmc_priv(mmc);
1709
1710 /*
1711 * Undo pm_runtime_put() in probe. We use the _sync
1712 * version here so that we can access the primecell.
1713 */
1714 pm_runtime_get_sync(&dev->dev);
1715
1716 mmc_remove_host(mmc);
1717
1718 writel(0, host->base + MMCIMASK0);
1719 writel(0, host->base + MMCIMASK1);
1720
1721 writel(0, host->base + MMCICOMMAND);
1722 writel(0, host->base + MMCIDATACTRL);
1723
1724 mmci_dma_release(host);
1725 clk_disable_unprepare(host->clk);
1726 mmc_free_host(mmc);
1727 }
1728
1729 return 0;
1730 }
1731
1732 #ifdef CONFIG_PM
1733 static void mmci_save(struct mmci_host *host)
1734 {
1735 unsigned long flags;
1736
1737 spin_lock_irqsave(&host->lock, flags);
1738
1739 writel(0, host->base + MMCIMASK0);
1740 if (host->variant->pwrreg_nopower) {
1741 writel(0, host->base + MMCIDATACTRL);
1742 writel(0, host->base + MMCIPOWER);
1743 writel(0, host->base + MMCICLOCK);
1744 }
1745 mmci_reg_delay(host);
1746
1747 spin_unlock_irqrestore(&host->lock, flags);
1748 }
1749
1750 static void mmci_restore(struct mmci_host *host)
1751 {
1752 unsigned long flags;
1753
1754 spin_lock_irqsave(&host->lock, flags);
1755
1756 if (host->variant->pwrreg_nopower) {
1757 writel(host->clk_reg, host->base + MMCICLOCK);
1758 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1759 writel(host->pwr_reg, host->base + MMCIPOWER);
1760 }
1761 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1762 mmci_reg_delay(host);
1763
1764 spin_unlock_irqrestore(&host->lock, flags);
1765 }
1766
1767 static int mmci_runtime_suspend(struct device *dev)
1768 {
1769 struct amba_device *adev = to_amba_device(dev);
1770 struct mmc_host *mmc = amba_get_drvdata(adev);
1771
1772 if (mmc) {
1773 struct mmci_host *host = mmc_priv(mmc);
1774 pinctrl_pm_select_sleep_state(dev);
1775 mmci_save(host);
1776 clk_disable_unprepare(host->clk);
1777 }
1778
1779 return 0;
1780 }
1781
1782 static int mmci_runtime_resume(struct device *dev)
1783 {
1784 struct amba_device *adev = to_amba_device(dev);
1785 struct mmc_host *mmc = amba_get_drvdata(adev);
1786
1787 if (mmc) {
1788 struct mmci_host *host = mmc_priv(mmc);
1789 clk_prepare_enable(host->clk);
1790 mmci_restore(host);
1791 pinctrl_pm_select_default_state(dev);
1792 }
1793
1794 return 0;
1795 }
1796 #endif
1797
1798 static const struct dev_pm_ops mmci_dev_pm_ops = {
1799 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1800 pm_runtime_force_resume)
1801 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1802 };
1803
1804 static struct amba_id mmci_ids[] = {
1805 {
1806 .id = 0x00041180,
1807 .mask = 0xff0fffff,
1808 .data = &variant_arm,
1809 },
1810 {
1811 .id = 0x01041180,
1812 .mask = 0xff0fffff,
1813 .data = &variant_arm_extended_fifo,
1814 },
1815 {
1816 .id = 0x02041180,
1817 .mask = 0xff0fffff,
1818 .data = &variant_arm_extended_fifo_hwfc,
1819 },
1820 {
1821 .id = 0x00041181,
1822 .mask = 0x000fffff,
1823 .data = &variant_arm,
1824 },
1825 /* ST Micro variants */
1826 {
1827 .id = 0x00180180,
1828 .mask = 0x00ffffff,
1829 .data = &variant_u300,
1830 },
1831 {
1832 .id = 0x10180180,
1833 .mask = 0xf0ffffff,
1834 .data = &variant_nomadik,
1835 },
1836 {
1837 .id = 0x00280180,
1838 .mask = 0x00ffffff,
1839 .data = &variant_u300,
1840 },
1841 {
1842 .id = 0x00480180,
1843 .mask = 0xf0ffffff,
1844 .data = &variant_ux500,
1845 },
1846 {
1847 .id = 0x10480180,
1848 .mask = 0xf0ffffff,
1849 .data = &variant_ux500v2,
1850 },
1851 /* Qualcomm variants */
1852 {
1853 .id = 0x00051180,
1854 .mask = 0x000fffff,
1855 .data = &variant_qcom,
1856 },
1857 { 0, 0 },
1858 };
1859
1860 MODULE_DEVICE_TABLE(amba, mmci_ids);
1861
1862 static struct amba_driver mmci_driver = {
1863 .drv = {
1864 .name = DRIVER_NAME,
1865 .pm = &mmci_dev_pm_ops,
1866 },
1867 .probe = mmci_probe,
1868 .remove = mmci_remove,
1869 .id_table = mmci_ids,
1870 };
1871
1872 module_amba_driver(mmci_driver);
1873
1874 module_param(fmax, uint, 0444);
1875
1876 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1877 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.071167 seconds and 6 git commands to generate.