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mmc: mmci: Add Qualcomm Id to amba id table
[deliverable/linux.git] / drivers / mmc / host / mmci.c
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
40
41 #include <asm/div64.h>
42 #include <asm/io.h>
43 #include <asm/sizes.h>
44
45 #include "mmci.h"
46
47 #define DRIVER_NAME "mmci-pl18x"
48
49 static unsigned int fmax = 515633;
50
51 /**
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
54 * @clkreg_enable: enable value for MMCICLOCK register
55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
57 * @datalength_bits: number of bits in the MMCIDATALENGTH register
58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
59 * is asserted (likewise for RX)
60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
61 * is asserted (likewise for RX)
62 * @data_cmd_enable: enable value for data commands.
63 * @sdio: variant supports SDIO
64 * @st_clkdiv: true if using a ST-specific clock divider algorithm
65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
68 * register
69 * @pwrreg_powerup: power up value for MMCIPOWER register
70 * @f_max: maximum clk frequency supported by the controller.
71 * @signal_direction: input/out direction of bus signals can be indicated
72 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
73 * @busy_detect: true if busy detection on dat0 is supported
74 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
75 * @explicit_mclk_control: enable explicit mclk control in driver.
76 * @qcom_fifo: enables qcom specific fifo pio read logic.
77 */
78 struct variant_data {
79 unsigned int clkreg;
80 unsigned int clkreg_enable;
81 unsigned int clkreg_8bit_bus_enable;
82 unsigned int clkreg_neg_edge_enable;
83 unsigned int datalength_bits;
84 unsigned int fifosize;
85 unsigned int fifohalfsize;
86 unsigned int data_cmd_enable;
87 unsigned int datactrl_mask_ddrmode;
88 bool sdio;
89 bool st_clkdiv;
90 bool blksz_datactrl16;
91 bool blksz_datactrl4;
92 u32 pwrreg_powerup;
93 u32 f_max;
94 bool signal_direction;
95 bool pwrreg_clkgate;
96 bool busy_detect;
97 bool pwrreg_nopower;
98 bool explicit_mclk_control;
99 bool qcom_fifo;
100 };
101
102 static struct variant_data variant_arm = {
103 .fifosize = 16 * 4,
104 .fifohalfsize = 8 * 4,
105 .datalength_bits = 16,
106 .pwrreg_powerup = MCI_PWR_UP,
107 .f_max = 100000000,
108 };
109
110 static struct variant_data variant_arm_extended_fifo = {
111 .fifosize = 128 * 4,
112 .fifohalfsize = 64 * 4,
113 .datalength_bits = 16,
114 .pwrreg_powerup = MCI_PWR_UP,
115 .f_max = 100000000,
116 };
117
118 static struct variant_data variant_arm_extended_fifo_hwfc = {
119 .fifosize = 128 * 4,
120 .fifohalfsize = 64 * 4,
121 .clkreg_enable = MCI_ARM_HWFCEN,
122 .datalength_bits = 16,
123 .pwrreg_powerup = MCI_PWR_UP,
124 .f_max = 100000000,
125 };
126
127 static struct variant_data variant_u300 = {
128 .fifosize = 16 * 4,
129 .fifohalfsize = 8 * 4,
130 .clkreg_enable = MCI_ST_U300_HWFCEN,
131 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
132 .datalength_bits = 16,
133 .sdio = true,
134 .pwrreg_powerup = MCI_PWR_ON,
135 .f_max = 100000000,
136 .signal_direction = true,
137 .pwrreg_clkgate = true,
138 .pwrreg_nopower = true,
139 };
140
141 static struct variant_data variant_nomadik = {
142 .fifosize = 16 * 4,
143 .fifohalfsize = 8 * 4,
144 .clkreg = MCI_CLK_ENABLE,
145 .datalength_bits = 24,
146 .sdio = true,
147 .st_clkdiv = true,
148 .pwrreg_powerup = MCI_PWR_ON,
149 .f_max = 100000000,
150 .signal_direction = true,
151 .pwrreg_clkgate = true,
152 .pwrreg_nopower = true,
153 };
154
155 static struct variant_data variant_ux500 = {
156 .fifosize = 30 * 4,
157 .fifohalfsize = 8 * 4,
158 .clkreg = MCI_CLK_ENABLE,
159 .clkreg_enable = MCI_ST_UX500_HWFCEN,
160 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
161 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
162 .datalength_bits = 24,
163 .sdio = true,
164 .st_clkdiv = true,
165 .pwrreg_powerup = MCI_PWR_ON,
166 .f_max = 100000000,
167 .signal_direction = true,
168 .pwrreg_clkgate = true,
169 .busy_detect = true,
170 .pwrreg_nopower = true,
171 };
172
173 static struct variant_data variant_ux500v2 = {
174 .fifosize = 30 * 4,
175 .fifohalfsize = 8 * 4,
176 .clkreg = MCI_CLK_ENABLE,
177 .clkreg_enable = MCI_ST_UX500_HWFCEN,
178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
180 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
181 .datalength_bits = 24,
182 .sdio = true,
183 .st_clkdiv = true,
184 .blksz_datactrl16 = true,
185 .pwrreg_powerup = MCI_PWR_ON,
186 .f_max = 100000000,
187 .signal_direction = true,
188 .pwrreg_clkgate = true,
189 .busy_detect = true,
190 .pwrreg_nopower = true,
191 };
192
193 static struct variant_data variant_qcom = {
194 .fifosize = 16 * 4,
195 .fifohalfsize = 8 * 4,
196 .clkreg = MCI_CLK_ENABLE,
197 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
198 MCI_QCOM_CLK_SELECT_IN_FBCLK,
199 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
200 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
201 .data_cmd_enable = MCI_QCOM_CSPM_DATCMD,
202 .blksz_datactrl4 = true,
203 .datalength_bits = 24,
204 .pwrreg_powerup = MCI_PWR_UP,
205 .f_max = 208000000,
206 .explicit_mclk_control = true,
207 .qcom_fifo = true,
208 };
209
210 static int mmci_card_busy(struct mmc_host *mmc)
211 {
212 struct mmci_host *host = mmc_priv(mmc);
213 unsigned long flags;
214 int busy = 0;
215
216 pm_runtime_get_sync(mmc_dev(mmc));
217
218 spin_lock_irqsave(&host->lock, flags);
219 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
220 busy = 1;
221 spin_unlock_irqrestore(&host->lock, flags);
222
223 pm_runtime_mark_last_busy(mmc_dev(mmc));
224 pm_runtime_put_autosuspend(mmc_dev(mmc));
225
226 return busy;
227 }
228
229 /*
230 * Validate mmc prerequisites
231 */
232 static int mmci_validate_data(struct mmci_host *host,
233 struct mmc_data *data)
234 {
235 if (!data)
236 return 0;
237
238 if (!is_power_of_2(data->blksz)) {
239 dev_err(mmc_dev(host->mmc),
240 "unsupported block size (%d bytes)\n", data->blksz);
241 return -EINVAL;
242 }
243
244 return 0;
245 }
246
247 static void mmci_reg_delay(struct mmci_host *host)
248 {
249 /*
250 * According to the spec, at least three feedback clock cycles
251 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
252 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
253 * Worst delay time during card init is at 100 kHz => 30 us.
254 * Worst delay time when up and running is at 25 MHz => 120 ns.
255 */
256 if (host->cclk < 25000000)
257 udelay(30);
258 else
259 ndelay(120);
260 }
261
262 /*
263 * This must be called with host->lock held
264 */
265 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
266 {
267 if (host->clk_reg != clk) {
268 host->clk_reg = clk;
269 writel(clk, host->base + MMCICLOCK);
270 }
271 }
272
273 /*
274 * This must be called with host->lock held
275 */
276 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
277 {
278 if (host->pwr_reg != pwr) {
279 host->pwr_reg = pwr;
280 writel(pwr, host->base + MMCIPOWER);
281 }
282 }
283
284 /*
285 * This must be called with host->lock held
286 */
287 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
288 {
289 /* Keep ST Micro busy mode if enabled */
290 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
291
292 if (host->datactrl_reg != datactrl) {
293 host->datactrl_reg = datactrl;
294 writel(datactrl, host->base + MMCIDATACTRL);
295 }
296 }
297
298 /*
299 * This must be called with host->lock held
300 */
301 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
302 {
303 struct variant_data *variant = host->variant;
304 u32 clk = variant->clkreg;
305
306 /* Make sure cclk reflects the current calculated clock */
307 host->cclk = 0;
308
309 if (desired) {
310 if (variant->explicit_mclk_control) {
311 host->cclk = host->mclk;
312 } else if (desired >= host->mclk) {
313 clk = MCI_CLK_BYPASS;
314 if (variant->st_clkdiv)
315 clk |= MCI_ST_UX500_NEG_EDGE;
316 host->cclk = host->mclk;
317 } else if (variant->st_clkdiv) {
318 /*
319 * DB8500 TRM says f = mclk / (clkdiv + 2)
320 * => clkdiv = (mclk / f) - 2
321 * Round the divider up so we don't exceed the max
322 * frequency
323 */
324 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
325 if (clk >= 256)
326 clk = 255;
327 host->cclk = host->mclk / (clk + 2);
328 } else {
329 /*
330 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
331 * => clkdiv = mclk / (2 * f) - 1
332 */
333 clk = host->mclk / (2 * desired) - 1;
334 if (clk >= 256)
335 clk = 255;
336 host->cclk = host->mclk / (2 * (clk + 1));
337 }
338
339 clk |= variant->clkreg_enable;
340 clk |= MCI_CLK_ENABLE;
341 /* This hasn't proven to be worthwhile */
342 /* clk |= MCI_CLK_PWRSAVE; */
343 }
344
345 /* Set actual clock for debug */
346 host->mmc->actual_clock = host->cclk;
347
348 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
349 clk |= MCI_4BIT_BUS;
350 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
351 clk |= variant->clkreg_8bit_bus_enable;
352
353 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
354 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
355 clk |= variant->clkreg_neg_edge_enable;
356
357 mmci_write_clkreg(host, clk);
358 }
359
360 static void
361 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
362 {
363 writel(0, host->base + MMCICOMMAND);
364
365 BUG_ON(host->data);
366
367 host->mrq = NULL;
368 host->cmd = NULL;
369
370 mmc_request_done(host->mmc, mrq);
371
372 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
373 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
374 }
375
376 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
377 {
378 void __iomem *base = host->base;
379
380 if (host->singleirq) {
381 unsigned int mask0 = readl(base + MMCIMASK0);
382
383 mask0 &= ~MCI_IRQ1MASK;
384 mask0 |= mask;
385
386 writel(mask0, base + MMCIMASK0);
387 }
388
389 writel(mask, base + MMCIMASK1);
390 }
391
392 static void mmci_stop_data(struct mmci_host *host)
393 {
394 mmci_write_datactrlreg(host, 0);
395 mmci_set_mask1(host, 0);
396 host->data = NULL;
397 }
398
399 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
400 {
401 unsigned int flags = SG_MITER_ATOMIC;
402
403 if (data->flags & MMC_DATA_READ)
404 flags |= SG_MITER_TO_SG;
405 else
406 flags |= SG_MITER_FROM_SG;
407
408 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
409 }
410
411 /*
412 * All the DMA operation mode stuff goes inside this ifdef.
413 * This assumes that you have a generic DMA device interface,
414 * no custom DMA interfaces are supported.
415 */
416 #ifdef CONFIG_DMA_ENGINE
417 static void mmci_dma_setup(struct mmci_host *host)
418 {
419 const char *rxname, *txname;
420 dma_cap_mask_t mask;
421
422 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
423 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
424
425 /* initialize pre request cookie */
426 host->next_data.cookie = 1;
427
428 /* Try to acquire a generic DMA engine slave channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
432 /*
433 * If only an RX channel is specified, the driver will
434 * attempt to use it bidirectionally, however if it is
435 * is specified but cannot be located, DMA will be disabled.
436 */
437 if (host->dma_rx_channel && !host->dma_tx_channel)
438 host->dma_tx_channel = host->dma_rx_channel;
439
440 if (host->dma_rx_channel)
441 rxname = dma_chan_name(host->dma_rx_channel);
442 else
443 rxname = "none";
444
445 if (host->dma_tx_channel)
446 txname = dma_chan_name(host->dma_tx_channel);
447 else
448 txname = "none";
449
450 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
451 rxname, txname);
452
453 /*
454 * Limit the maximum segment size in any SG entry according to
455 * the parameters of the DMA engine device.
456 */
457 if (host->dma_tx_channel) {
458 struct device *dev = host->dma_tx_channel->device->dev;
459 unsigned int max_seg_size = dma_get_max_seg_size(dev);
460
461 if (max_seg_size < host->mmc->max_seg_size)
462 host->mmc->max_seg_size = max_seg_size;
463 }
464 if (host->dma_rx_channel) {
465 struct device *dev = host->dma_rx_channel->device->dev;
466 unsigned int max_seg_size = dma_get_max_seg_size(dev);
467
468 if (max_seg_size < host->mmc->max_seg_size)
469 host->mmc->max_seg_size = max_seg_size;
470 }
471 }
472
473 /*
474 * This is used in or so inline it
475 * so it can be discarded.
476 */
477 static inline void mmci_dma_release(struct mmci_host *host)
478 {
479 if (host->dma_rx_channel)
480 dma_release_channel(host->dma_rx_channel);
481 if (host->dma_tx_channel)
482 dma_release_channel(host->dma_tx_channel);
483 host->dma_rx_channel = host->dma_tx_channel = NULL;
484 }
485
486 static void mmci_dma_data_error(struct mmci_host *host)
487 {
488 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
489 dmaengine_terminate_all(host->dma_current);
490 host->dma_current = NULL;
491 host->dma_desc_current = NULL;
492 host->data->host_cookie = 0;
493 }
494
495 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
496 {
497 struct dma_chan *chan;
498 enum dma_data_direction dir;
499
500 if (data->flags & MMC_DATA_READ) {
501 dir = DMA_FROM_DEVICE;
502 chan = host->dma_rx_channel;
503 } else {
504 dir = DMA_TO_DEVICE;
505 chan = host->dma_tx_channel;
506 }
507
508 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
509 }
510
511 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
512 {
513 u32 status;
514 int i;
515
516 /* Wait up to 1ms for the DMA to complete */
517 for (i = 0; ; i++) {
518 status = readl(host->base + MMCISTATUS);
519 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
520 break;
521 udelay(10);
522 }
523
524 /*
525 * Check to see whether we still have some data left in the FIFO -
526 * this catches DMA controllers which are unable to monitor the
527 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
528 * contiguous buffers. On TX, we'll get a FIFO underrun error.
529 */
530 if (status & MCI_RXDATAAVLBLMASK) {
531 mmci_dma_data_error(host);
532 if (!data->error)
533 data->error = -EIO;
534 }
535
536 if (!data->host_cookie)
537 mmci_dma_unmap(host, data);
538
539 /*
540 * Use of DMA with scatter-gather is impossible.
541 * Give up with DMA and switch back to PIO mode.
542 */
543 if (status & MCI_RXDATAAVLBLMASK) {
544 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
545 mmci_dma_release(host);
546 }
547
548 host->dma_current = NULL;
549 host->dma_desc_current = NULL;
550 }
551
552 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
553 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
554 struct dma_chan **dma_chan,
555 struct dma_async_tx_descriptor **dma_desc)
556 {
557 struct variant_data *variant = host->variant;
558 struct dma_slave_config conf = {
559 .src_addr = host->phybase + MMCIFIFO,
560 .dst_addr = host->phybase + MMCIFIFO,
561 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
562 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
563 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
564 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
565 .device_fc = false,
566 };
567 struct dma_chan *chan;
568 struct dma_device *device;
569 struct dma_async_tx_descriptor *desc;
570 enum dma_data_direction buffer_dirn;
571 int nr_sg;
572
573 if (data->flags & MMC_DATA_READ) {
574 conf.direction = DMA_DEV_TO_MEM;
575 buffer_dirn = DMA_FROM_DEVICE;
576 chan = host->dma_rx_channel;
577 } else {
578 conf.direction = DMA_MEM_TO_DEV;
579 buffer_dirn = DMA_TO_DEVICE;
580 chan = host->dma_tx_channel;
581 }
582
583 /* If there's no DMA channel, fall back to PIO */
584 if (!chan)
585 return -EINVAL;
586
587 /* If less than or equal to the fifo size, don't bother with DMA */
588 if (data->blksz * data->blocks <= variant->fifosize)
589 return -EINVAL;
590
591 device = chan->device;
592 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
593 if (nr_sg == 0)
594 return -EINVAL;
595
596 dmaengine_slave_config(chan, &conf);
597 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
598 conf.direction, DMA_CTRL_ACK);
599 if (!desc)
600 goto unmap_exit;
601
602 *dma_chan = chan;
603 *dma_desc = desc;
604
605 return 0;
606
607 unmap_exit:
608 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
609 return -ENOMEM;
610 }
611
612 static inline int mmci_dma_prep_data(struct mmci_host *host,
613 struct mmc_data *data)
614 {
615 /* Check if next job is already prepared. */
616 if (host->dma_current && host->dma_desc_current)
617 return 0;
618
619 /* No job were prepared thus do it now. */
620 return __mmci_dma_prep_data(host, data, &host->dma_current,
621 &host->dma_desc_current);
622 }
623
624 static inline int mmci_dma_prep_next(struct mmci_host *host,
625 struct mmc_data *data)
626 {
627 struct mmci_host_next *nd = &host->next_data;
628 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
629 }
630
631 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
632 {
633 int ret;
634 struct mmc_data *data = host->data;
635
636 ret = mmci_dma_prep_data(host, host->data);
637 if (ret)
638 return ret;
639
640 /* Okay, go for it. */
641 dev_vdbg(mmc_dev(host->mmc),
642 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
643 data->sg_len, data->blksz, data->blocks, data->flags);
644 dmaengine_submit(host->dma_desc_current);
645 dma_async_issue_pending(host->dma_current);
646
647 datactrl |= MCI_DPSM_DMAENABLE;
648
649 /* Trigger the DMA transfer */
650 mmci_write_datactrlreg(host, datactrl);
651
652 /*
653 * Let the MMCI say when the data is ended and it's time
654 * to fire next DMA request. When that happens, MMCI will
655 * call mmci_data_end()
656 */
657 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
658 host->base + MMCIMASK0);
659 return 0;
660 }
661
662 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
663 {
664 struct mmci_host_next *next = &host->next_data;
665
666 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
667 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
668
669 host->dma_desc_current = next->dma_desc;
670 host->dma_current = next->dma_chan;
671 next->dma_desc = NULL;
672 next->dma_chan = NULL;
673 }
674
675 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
676 bool is_first_req)
677 {
678 struct mmci_host *host = mmc_priv(mmc);
679 struct mmc_data *data = mrq->data;
680 struct mmci_host_next *nd = &host->next_data;
681
682 if (!data)
683 return;
684
685 BUG_ON(data->host_cookie);
686
687 if (mmci_validate_data(host, data))
688 return;
689
690 if (!mmci_dma_prep_next(host, data))
691 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
692 }
693
694 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
695 int err)
696 {
697 struct mmci_host *host = mmc_priv(mmc);
698 struct mmc_data *data = mrq->data;
699
700 if (!data || !data->host_cookie)
701 return;
702
703 mmci_dma_unmap(host, data);
704
705 if (err) {
706 struct mmci_host_next *next = &host->next_data;
707 struct dma_chan *chan;
708 if (data->flags & MMC_DATA_READ)
709 chan = host->dma_rx_channel;
710 else
711 chan = host->dma_tx_channel;
712 dmaengine_terminate_all(chan);
713
714 next->dma_desc = NULL;
715 next->dma_chan = NULL;
716 }
717 }
718
719 #else
720 /* Blank functions if the DMA engine is not available */
721 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
722 {
723 }
724 static inline void mmci_dma_setup(struct mmci_host *host)
725 {
726 }
727
728 static inline void mmci_dma_release(struct mmci_host *host)
729 {
730 }
731
732 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
733 {
734 }
735
736 static inline void mmci_dma_finalize(struct mmci_host *host,
737 struct mmc_data *data)
738 {
739 }
740
741 static inline void mmci_dma_data_error(struct mmci_host *host)
742 {
743 }
744
745 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
746 {
747 return -ENOSYS;
748 }
749
750 #define mmci_pre_request NULL
751 #define mmci_post_request NULL
752
753 #endif
754
755 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
756 {
757 struct variant_data *variant = host->variant;
758 unsigned int datactrl, timeout, irqmask;
759 unsigned long long clks;
760 void __iomem *base;
761 int blksz_bits;
762
763 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
764 data->blksz, data->blocks, data->flags);
765
766 host->data = data;
767 host->size = data->blksz * data->blocks;
768 data->bytes_xfered = 0;
769
770 clks = (unsigned long long)data->timeout_ns * host->cclk;
771 do_div(clks, NSEC_PER_SEC);
772
773 timeout = data->timeout_clks + (unsigned int)clks;
774
775 base = host->base;
776 writel(timeout, base + MMCIDATATIMER);
777 writel(host->size, base + MMCIDATALENGTH);
778
779 blksz_bits = ffs(data->blksz) - 1;
780 BUG_ON(1 << blksz_bits != data->blksz);
781
782 if (variant->blksz_datactrl16)
783 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
784 else if (variant->blksz_datactrl4)
785 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
786 else
787 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
788
789 if (data->flags & MMC_DATA_READ)
790 datactrl |= MCI_DPSM_DIRECTION;
791
792 /* The ST Micro variants has a special bit to enable SDIO */
793 if (variant->sdio && host->mmc->card)
794 if (mmc_card_sdio(host->mmc->card)) {
795 /*
796 * The ST Micro variants has a special bit
797 * to enable SDIO.
798 */
799 u32 clk;
800
801 datactrl |= MCI_ST_DPSM_SDIOEN;
802
803 /*
804 * The ST Micro variant for SDIO small write transfers
805 * needs to have clock H/W flow control disabled,
806 * otherwise the transfer will not start. The threshold
807 * depends on the rate of MCLK.
808 */
809 if (data->flags & MMC_DATA_WRITE &&
810 (host->size < 8 ||
811 (host->size <= 8 && host->mclk > 50000000)))
812 clk = host->clk_reg & ~variant->clkreg_enable;
813 else
814 clk = host->clk_reg | variant->clkreg_enable;
815
816 mmci_write_clkreg(host, clk);
817 }
818
819 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
820 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
821 datactrl |= variant->datactrl_mask_ddrmode;
822
823 /*
824 * Attempt to use DMA operation mode, if this
825 * should fail, fall back to PIO mode
826 */
827 if (!mmci_dma_start_data(host, datactrl))
828 return;
829
830 /* IRQ mode, map the SG list for CPU reading/writing */
831 mmci_init_sg(host, data);
832
833 if (data->flags & MMC_DATA_READ) {
834 irqmask = MCI_RXFIFOHALFFULLMASK;
835
836 /*
837 * If we have less than the fifo 'half-full' threshold to
838 * transfer, trigger a PIO interrupt as soon as any data
839 * is available.
840 */
841 if (host->size < variant->fifohalfsize)
842 irqmask |= MCI_RXDATAAVLBLMASK;
843 } else {
844 /*
845 * We don't actually need to include "FIFO empty" here
846 * since its implicit in "FIFO half empty".
847 */
848 irqmask = MCI_TXFIFOHALFEMPTYMASK;
849 }
850
851 mmci_write_datactrlreg(host, datactrl);
852 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
853 mmci_set_mask1(host, irqmask);
854 }
855
856 static void
857 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
858 {
859 void __iomem *base = host->base;
860
861 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
862 cmd->opcode, cmd->arg, cmd->flags);
863
864 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
865 writel(0, base + MMCICOMMAND);
866 mmci_reg_delay(host);
867 }
868
869 c |= cmd->opcode | MCI_CPSM_ENABLE;
870 if (cmd->flags & MMC_RSP_PRESENT) {
871 if (cmd->flags & MMC_RSP_136)
872 c |= MCI_CPSM_LONGRSP;
873 c |= MCI_CPSM_RESPONSE;
874 }
875 if (/*interrupt*/0)
876 c |= MCI_CPSM_INTERRUPT;
877
878 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
879 c |= host->variant->data_cmd_enable;
880
881 host->cmd = cmd;
882
883 writel(cmd->arg, base + MMCIARGUMENT);
884 writel(c, base + MMCICOMMAND);
885 }
886
887 static void
888 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
889 unsigned int status)
890 {
891 /* First check for errors */
892 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
893 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
894 u32 remain, success;
895
896 /* Terminate the DMA transfer */
897 if (dma_inprogress(host)) {
898 mmci_dma_data_error(host);
899 mmci_dma_unmap(host, data);
900 }
901
902 /*
903 * Calculate how far we are into the transfer. Note that
904 * the data counter gives the number of bytes transferred
905 * on the MMC bus, not on the host side. On reads, this
906 * can be as much as a FIFO-worth of data ahead. This
907 * matters for FIFO overruns only.
908 */
909 remain = readl(host->base + MMCIDATACNT);
910 success = data->blksz * data->blocks - remain;
911
912 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
913 status, success);
914 if (status & MCI_DATACRCFAIL) {
915 /* Last block was not successful */
916 success -= 1;
917 data->error = -EILSEQ;
918 } else if (status & MCI_DATATIMEOUT) {
919 data->error = -ETIMEDOUT;
920 } else if (status & MCI_STARTBITERR) {
921 data->error = -ECOMM;
922 } else if (status & MCI_TXUNDERRUN) {
923 data->error = -EIO;
924 } else if (status & MCI_RXOVERRUN) {
925 if (success > host->variant->fifosize)
926 success -= host->variant->fifosize;
927 else
928 success = 0;
929 data->error = -EIO;
930 }
931 data->bytes_xfered = round_down(success, data->blksz);
932 }
933
934 if (status & MCI_DATABLOCKEND)
935 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
936
937 if (status & MCI_DATAEND || data->error) {
938 if (dma_inprogress(host))
939 mmci_dma_finalize(host, data);
940 mmci_stop_data(host);
941
942 if (!data->error)
943 /* The error clause is handled above, success! */
944 data->bytes_xfered = data->blksz * data->blocks;
945
946 if (!data->stop || host->mrq->sbc) {
947 mmci_request_end(host, data->mrq);
948 } else {
949 mmci_start_command(host, data->stop, 0);
950 }
951 }
952 }
953
954 static void
955 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
956 unsigned int status)
957 {
958 void __iomem *base = host->base;
959 bool sbc = (cmd == host->mrq->sbc);
960 bool busy_resp = host->variant->busy_detect &&
961 (cmd->flags & MMC_RSP_BUSY);
962
963 /* Check if we need to wait for busy completion. */
964 if (host->busy_status && (status & MCI_ST_CARDBUSY))
965 return;
966
967 /* Enable busy completion if needed and supported. */
968 if (!host->busy_status && busy_resp &&
969 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
970 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
971 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
972 base + MMCIMASK0);
973 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
974 return;
975 }
976
977 /* At busy completion, mask the IRQ and complete the request. */
978 if (host->busy_status) {
979 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
980 base + MMCIMASK0);
981 host->busy_status = 0;
982 }
983
984 host->cmd = NULL;
985
986 if (status & MCI_CMDTIMEOUT) {
987 cmd->error = -ETIMEDOUT;
988 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
989 cmd->error = -EILSEQ;
990 } else {
991 cmd->resp[0] = readl(base + MMCIRESPONSE0);
992 cmd->resp[1] = readl(base + MMCIRESPONSE1);
993 cmd->resp[2] = readl(base + MMCIRESPONSE2);
994 cmd->resp[3] = readl(base + MMCIRESPONSE3);
995 }
996
997 if ((!sbc && !cmd->data) || cmd->error) {
998 if (host->data) {
999 /* Terminate the DMA transfer */
1000 if (dma_inprogress(host)) {
1001 mmci_dma_data_error(host);
1002 mmci_dma_unmap(host, host->data);
1003 }
1004 mmci_stop_data(host);
1005 }
1006 mmci_request_end(host, host->mrq);
1007 } else if (sbc) {
1008 mmci_start_command(host, host->mrq->cmd, 0);
1009 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1010 mmci_start_data(host, cmd->data);
1011 }
1012 }
1013
1014 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1015 {
1016 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1017 }
1018
1019 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1020 {
1021 /*
1022 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1023 * from the fifo range should be used
1024 */
1025 if (status & MCI_RXFIFOHALFFULL)
1026 return host->variant->fifohalfsize;
1027 else if (status & MCI_RXDATAAVLBL)
1028 return 4;
1029
1030 return 0;
1031 }
1032
1033 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1034 {
1035 void __iomem *base = host->base;
1036 char *ptr = buffer;
1037 u32 status = readl(host->base + MMCISTATUS);
1038 int host_remain = host->size;
1039
1040 do {
1041 int count = host->get_rx_fifocnt(host, status, host_remain);
1042
1043 if (count > remain)
1044 count = remain;
1045
1046 if (count <= 0)
1047 break;
1048
1049 /*
1050 * SDIO especially may want to send something that is
1051 * not divisible by 4 (as opposed to card sectors
1052 * etc). Therefore make sure to always read the last bytes
1053 * while only doing full 32-bit reads towards the FIFO.
1054 */
1055 if (unlikely(count & 0x3)) {
1056 if (count < 4) {
1057 unsigned char buf[4];
1058 ioread32_rep(base + MMCIFIFO, buf, 1);
1059 memcpy(ptr, buf, count);
1060 } else {
1061 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1062 count &= ~0x3;
1063 }
1064 } else {
1065 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1066 }
1067
1068 ptr += count;
1069 remain -= count;
1070 host_remain -= count;
1071
1072 if (remain == 0)
1073 break;
1074
1075 status = readl(base + MMCISTATUS);
1076 } while (status & MCI_RXDATAAVLBL);
1077
1078 return ptr - buffer;
1079 }
1080
1081 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1082 {
1083 struct variant_data *variant = host->variant;
1084 void __iomem *base = host->base;
1085 char *ptr = buffer;
1086
1087 do {
1088 unsigned int count, maxcnt;
1089
1090 maxcnt = status & MCI_TXFIFOEMPTY ?
1091 variant->fifosize : variant->fifohalfsize;
1092 count = min(remain, maxcnt);
1093
1094 /*
1095 * SDIO especially may want to send something that is
1096 * not divisible by 4 (as opposed to card sectors
1097 * etc), and the FIFO only accept full 32-bit writes.
1098 * So compensate by adding +3 on the count, a single
1099 * byte become a 32bit write, 7 bytes will be two
1100 * 32bit writes etc.
1101 */
1102 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1103
1104 ptr += count;
1105 remain -= count;
1106
1107 if (remain == 0)
1108 break;
1109
1110 status = readl(base + MMCISTATUS);
1111 } while (status & MCI_TXFIFOHALFEMPTY);
1112
1113 return ptr - buffer;
1114 }
1115
1116 /*
1117 * PIO data transfer IRQ handler.
1118 */
1119 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1120 {
1121 struct mmci_host *host = dev_id;
1122 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1123 struct variant_data *variant = host->variant;
1124 void __iomem *base = host->base;
1125 unsigned long flags;
1126 u32 status;
1127
1128 status = readl(base + MMCISTATUS);
1129
1130 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1131
1132 local_irq_save(flags);
1133
1134 do {
1135 unsigned int remain, len;
1136 char *buffer;
1137
1138 /*
1139 * For write, we only need to test the half-empty flag
1140 * here - if the FIFO is completely empty, then by
1141 * definition it is more than half empty.
1142 *
1143 * For read, check for data available.
1144 */
1145 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1146 break;
1147
1148 if (!sg_miter_next(sg_miter))
1149 break;
1150
1151 buffer = sg_miter->addr;
1152 remain = sg_miter->length;
1153
1154 len = 0;
1155 if (status & MCI_RXACTIVE)
1156 len = mmci_pio_read(host, buffer, remain);
1157 if (status & MCI_TXACTIVE)
1158 len = mmci_pio_write(host, buffer, remain, status);
1159
1160 sg_miter->consumed = len;
1161
1162 host->size -= len;
1163 remain -= len;
1164
1165 if (remain)
1166 break;
1167
1168 status = readl(base + MMCISTATUS);
1169 } while (1);
1170
1171 sg_miter_stop(sg_miter);
1172
1173 local_irq_restore(flags);
1174
1175 /*
1176 * If we have less than the fifo 'half-full' threshold to transfer,
1177 * trigger a PIO interrupt as soon as any data is available.
1178 */
1179 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1180 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1181
1182 /*
1183 * If we run out of data, disable the data IRQs; this
1184 * prevents a race where the FIFO becomes empty before
1185 * the chip itself has disabled the data path, and
1186 * stops us racing with our data end IRQ.
1187 */
1188 if (host->size == 0) {
1189 mmci_set_mask1(host, 0);
1190 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1191 }
1192
1193 return IRQ_HANDLED;
1194 }
1195
1196 /*
1197 * Handle completion of command and data transfers.
1198 */
1199 static irqreturn_t mmci_irq(int irq, void *dev_id)
1200 {
1201 struct mmci_host *host = dev_id;
1202 u32 status;
1203 int ret = 0;
1204
1205 spin_lock(&host->lock);
1206
1207 do {
1208 struct mmc_command *cmd;
1209 struct mmc_data *data;
1210
1211 status = readl(host->base + MMCISTATUS);
1212
1213 if (host->singleirq) {
1214 if (status & readl(host->base + MMCIMASK1))
1215 mmci_pio_irq(irq, dev_id);
1216
1217 status &= ~MCI_IRQ1MASK;
1218 }
1219
1220 /*
1221 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1222 * enabled) since the HW seems to be triggering the IRQ on both
1223 * edges while monitoring DAT0 for busy completion.
1224 */
1225 status &= readl(host->base + MMCIMASK0);
1226 writel(status, host->base + MMCICLEAR);
1227
1228 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1229
1230 cmd = host->cmd;
1231 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
1232 MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1233 mmci_cmd_irq(host, cmd, status);
1234
1235 data = host->data;
1236 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1237 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1238 MCI_DATABLOCKEND) && data)
1239 mmci_data_irq(host, data, status);
1240
1241 /* Don't poll for busy completion in irq context. */
1242 if (host->busy_status)
1243 status &= ~MCI_ST_CARDBUSY;
1244
1245 ret = 1;
1246 } while (status);
1247
1248 spin_unlock(&host->lock);
1249
1250 return IRQ_RETVAL(ret);
1251 }
1252
1253 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1254 {
1255 struct mmci_host *host = mmc_priv(mmc);
1256 unsigned long flags;
1257
1258 WARN_ON(host->mrq != NULL);
1259
1260 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1261 if (mrq->cmd->error) {
1262 mmc_request_done(mmc, mrq);
1263 return;
1264 }
1265
1266 pm_runtime_get_sync(mmc_dev(mmc));
1267
1268 spin_lock_irqsave(&host->lock, flags);
1269
1270 host->mrq = mrq;
1271
1272 if (mrq->data)
1273 mmci_get_next_data(host, mrq->data);
1274
1275 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1276 mmci_start_data(host, mrq->data);
1277
1278 if (mrq->sbc)
1279 mmci_start_command(host, mrq->sbc, 0);
1280 else
1281 mmci_start_command(host, mrq->cmd, 0);
1282
1283 spin_unlock_irqrestore(&host->lock, flags);
1284 }
1285
1286 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1287 {
1288 struct mmci_host *host = mmc_priv(mmc);
1289 struct variant_data *variant = host->variant;
1290 u32 pwr = 0;
1291 unsigned long flags;
1292 int ret;
1293
1294 pm_runtime_get_sync(mmc_dev(mmc));
1295
1296 if (host->plat->ios_handler &&
1297 host->plat->ios_handler(mmc_dev(mmc), ios))
1298 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1299
1300 switch (ios->power_mode) {
1301 case MMC_POWER_OFF:
1302 if (!IS_ERR(mmc->supply.vmmc))
1303 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1304
1305 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1306 regulator_disable(mmc->supply.vqmmc);
1307 host->vqmmc_enabled = false;
1308 }
1309
1310 break;
1311 case MMC_POWER_UP:
1312 if (!IS_ERR(mmc->supply.vmmc))
1313 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1314
1315 /*
1316 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1317 * and instead uses MCI_PWR_ON so apply whatever value is
1318 * configured in the variant data.
1319 */
1320 pwr |= variant->pwrreg_powerup;
1321
1322 break;
1323 case MMC_POWER_ON:
1324 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1325 ret = regulator_enable(mmc->supply.vqmmc);
1326 if (ret < 0)
1327 dev_err(mmc_dev(mmc),
1328 "failed to enable vqmmc regulator\n");
1329 else
1330 host->vqmmc_enabled = true;
1331 }
1332
1333 pwr |= MCI_PWR_ON;
1334 break;
1335 }
1336
1337 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1338 /*
1339 * The ST Micro variant has some additional bits
1340 * indicating signal direction for the signals in
1341 * the SD/MMC bus and feedback-clock usage.
1342 */
1343 pwr |= host->pwr_reg_add;
1344
1345 if (ios->bus_width == MMC_BUS_WIDTH_4)
1346 pwr &= ~MCI_ST_DATA74DIREN;
1347 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1348 pwr &= (~MCI_ST_DATA74DIREN &
1349 ~MCI_ST_DATA31DIREN &
1350 ~MCI_ST_DATA2DIREN);
1351 }
1352
1353 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1354 if (host->hw_designer != AMBA_VENDOR_ST)
1355 pwr |= MCI_ROD;
1356 else {
1357 /*
1358 * The ST Micro variant use the ROD bit for something
1359 * else and only has OD (Open Drain).
1360 */
1361 pwr |= MCI_OD;
1362 }
1363 }
1364
1365 /*
1366 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1367 * gating the clock, the MCI_PWR_ON bit is cleared.
1368 */
1369 if (!ios->clock && variant->pwrreg_clkgate)
1370 pwr &= ~MCI_PWR_ON;
1371
1372 if (host->variant->explicit_mclk_control &&
1373 ios->clock != host->clock_cache) {
1374 ret = clk_set_rate(host->clk, ios->clock);
1375 if (ret < 0)
1376 dev_err(mmc_dev(host->mmc),
1377 "Error setting clock rate (%d)\n", ret);
1378 else
1379 host->mclk = clk_get_rate(host->clk);
1380 }
1381 host->clock_cache = ios->clock;
1382
1383 spin_lock_irqsave(&host->lock, flags);
1384
1385 mmci_set_clkreg(host, ios->clock);
1386 mmci_write_pwrreg(host, pwr);
1387 mmci_reg_delay(host);
1388
1389 spin_unlock_irqrestore(&host->lock, flags);
1390
1391 pm_runtime_mark_last_busy(mmc_dev(mmc));
1392 pm_runtime_put_autosuspend(mmc_dev(mmc));
1393 }
1394
1395 static int mmci_get_cd(struct mmc_host *mmc)
1396 {
1397 struct mmci_host *host = mmc_priv(mmc);
1398 struct mmci_platform_data *plat = host->plat;
1399 unsigned int status = mmc_gpio_get_cd(mmc);
1400
1401 if (status == -ENOSYS) {
1402 if (!plat->status)
1403 return 1; /* Assume always present */
1404
1405 status = plat->status(mmc_dev(host->mmc));
1406 }
1407 return status;
1408 }
1409
1410 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1411 {
1412 int ret = 0;
1413
1414 if (!IS_ERR(mmc->supply.vqmmc)) {
1415
1416 pm_runtime_get_sync(mmc_dev(mmc));
1417
1418 switch (ios->signal_voltage) {
1419 case MMC_SIGNAL_VOLTAGE_330:
1420 ret = regulator_set_voltage(mmc->supply.vqmmc,
1421 2700000, 3600000);
1422 break;
1423 case MMC_SIGNAL_VOLTAGE_180:
1424 ret = regulator_set_voltage(mmc->supply.vqmmc,
1425 1700000, 1950000);
1426 break;
1427 case MMC_SIGNAL_VOLTAGE_120:
1428 ret = regulator_set_voltage(mmc->supply.vqmmc,
1429 1100000, 1300000);
1430 break;
1431 }
1432
1433 if (ret)
1434 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1435
1436 pm_runtime_mark_last_busy(mmc_dev(mmc));
1437 pm_runtime_put_autosuspend(mmc_dev(mmc));
1438 }
1439
1440 return ret;
1441 }
1442
1443 static struct mmc_host_ops mmci_ops = {
1444 .request = mmci_request,
1445 .pre_req = mmci_pre_request,
1446 .post_req = mmci_post_request,
1447 .set_ios = mmci_set_ios,
1448 .get_ro = mmc_gpio_get_ro,
1449 .get_cd = mmci_get_cd,
1450 .start_signal_voltage_switch = mmci_sig_volt_switch,
1451 };
1452
1453 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1454 {
1455 struct mmci_host *host = mmc_priv(mmc);
1456 int ret = mmc_of_parse(mmc);
1457
1458 if (ret)
1459 return ret;
1460
1461 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1462 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1463 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1464 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1465 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1466 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1467 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1468 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1469 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1470 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1471 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1472 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1473
1474 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1475 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1476 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1477 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1478
1479 return 0;
1480 }
1481
1482 static int mmci_probe(struct amba_device *dev,
1483 const struct amba_id *id)
1484 {
1485 struct mmci_platform_data *plat = dev->dev.platform_data;
1486 struct device_node *np = dev->dev.of_node;
1487 struct variant_data *variant = id->data;
1488 struct mmci_host *host;
1489 struct mmc_host *mmc;
1490 int ret;
1491
1492 /* Must have platform data or Device Tree. */
1493 if (!plat && !np) {
1494 dev_err(&dev->dev, "No plat data or DT found\n");
1495 return -EINVAL;
1496 }
1497
1498 if (!plat) {
1499 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1500 if (!plat)
1501 return -ENOMEM;
1502 }
1503
1504 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1505 if (!mmc)
1506 return -ENOMEM;
1507
1508 ret = mmci_of_parse(np, mmc);
1509 if (ret)
1510 goto host_free;
1511
1512 host = mmc_priv(mmc);
1513 host->mmc = mmc;
1514
1515 host->hw_designer = amba_manf(dev);
1516 host->hw_revision = amba_rev(dev);
1517 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1518 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1519
1520 host->clk = devm_clk_get(&dev->dev, NULL);
1521 if (IS_ERR(host->clk)) {
1522 ret = PTR_ERR(host->clk);
1523 goto host_free;
1524 }
1525
1526 ret = clk_prepare_enable(host->clk);
1527 if (ret)
1528 goto host_free;
1529
1530 if (variant->qcom_fifo)
1531 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1532 else
1533 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1534
1535 host->plat = plat;
1536 host->variant = variant;
1537 host->mclk = clk_get_rate(host->clk);
1538 /*
1539 * According to the spec, mclk is max 100 MHz,
1540 * so we try to adjust the clock down to this,
1541 * (if possible).
1542 */
1543 if (host->mclk > variant->f_max) {
1544 ret = clk_set_rate(host->clk, variant->f_max);
1545 if (ret < 0)
1546 goto clk_disable;
1547 host->mclk = clk_get_rate(host->clk);
1548 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1549 host->mclk);
1550 }
1551
1552 host->phybase = dev->res.start;
1553 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1554 if (IS_ERR(host->base)) {
1555 ret = PTR_ERR(host->base);
1556 goto clk_disable;
1557 }
1558
1559 /*
1560 * The ARM and ST versions of the block have slightly different
1561 * clock divider equations which means that the minimum divider
1562 * differs too.
1563 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1564 */
1565 if (variant->st_clkdiv)
1566 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1567 else if (variant->explicit_mclk_control)
1568 mmc->f_min = clk_round_rate(host->clk, 100000);
1569 else
1570 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1571 /*
1572 * If no maximum operating frequency is supplied, fall back to use
1573 * the module parameter, which has a (low) default value in case it
1574 * is not specified. Either value must not exceed the clock rate into
1575 * the block, of course.
1576 */
1577 if (mmc->f_max)
1578 mmc->f_max = variant->explicit_mclk_control ?
1579 min(variant->f_max, mmc->f_max) :
1580 min(host->mclk, mmc->f_max);
1581 else
1582 mmc->f_max = variant->explicit_mclk_control ?
1583 fmax : min(host->mclk, fmax);
1584
1585
1586 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1587
1588 /* Get regulators and the supported OCR mask */
1589 mmc_regulator_get_supply(mmc);
1590 if (!mmc->ocr_avail)
1591 mmc->ocr_avail = plat->ocr_mask;
1592 else if (plat->ocr_mask)
1593 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1594
1595 /* DT takes precedence over platform data. */
1596 if (!np) {
1597 if (!plat->cd_invert)
1598 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1599 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1600 }
1601
1602 /* We support these capabilities. */
1603 mmc->caps |= MMC_CAP_CMD23;
1604
1605 if (variant->busy_detect) {
1606 mmci_ops.card_busy = mmci_card_busy;
1607 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1608 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1609 mmc->max_busy_timeout = 0;
1610 }
1611
1612 mmc->ops = &mmci_ops;
1613
1614 /* We support these PM capabilities. */
1615 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1616
1617 /*
1618 * We can do SGIO
1619 */
1620 mmc->max_segs = NR_SG;
1621
1622 /*
1623 * Since only a certain number of bits are valid in the data length
1624 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1625 * single request.
1626 */
1627 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1628
1629 /*
1630 * Set the maximum segment size. Since we aren't doing DMA
1631 * (yet) we are only limited by the data length register.
1632 */
1633 mmc->max_seg_size = mmc->max_req_size;
1634
1635 /*
1636 * Block size can be up to 2048 bytes, but must be a power of two.
1637 */
1638 mmc->max_blk_size = 1 << 11;
1639
1640 /*
1641 * Limit the number of blocks transferred so that we don't overflow
1642 * the maximum request size.
1643 */
1644 mmc->max_blk_count = mmc->max_req_size >> 11;
1645
1646 spin_lock_init(&host->lock);
1647
1648 writel(0, host->base + MMCIMASK0);
1649 writel(0, host->base + MMCIMASK1);
1650 writel(0xfff, host->base + MMCICLEAR);
1651
1652 /* If DT, cd/wp gpios must be supplied through it. */
1653 if (!np && gpio_is_valid(plat->gpio_cd)) {
1654 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1655 if (ret)
1656 goto clk_disable;
1657 }
1658 if (!np && gpio_is_valid(plat->gpio_wp)) {
1659 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1660 if (ret)
1661 goto clk_disable;
1662 }
1663
1664 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1665 DRIVER_NAME " (cmd)", host);
1666 if (ret)
1667 goto clk_disable;
1668
1669 if (!dev->irq[1])
1670 host->singleirq = true;
1671 else {
1672 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1673 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1674 if (ret)
1675 goto clk_disable;
1676 }
1677
1678 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1679
1680 amba_set_drvdata(dev, mmc);
1681
1682 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1683 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1684 amba_rev(dev), (unsigned long long)dev->res.start,
1685 dev->irq[0], dev->irq[1]);
1686
1687 mmci_dma_setup(host);
1688
1689 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1690 pm_runtime_use_autosuspend(&dev->dev);
1691 pm_runtime_put(&dev->dev);
1692
1693 mmc_add_host(mmc);
1694
1695 return 0;
1696
1697 clk_disable:
1698 clk_disable_unprepare(host->clk);
1699 host_free:
1700 mmc_free_host(mmc);
1701 return ret;
1702 }
1703
1704 static int mmci_remove(struct amba_device *dev)
1705 {
1706 struct mmc_host *mmc = amba_get_drvdata(dev);
1707
1708 if (mmc) {
1709 struct mmci_host *host = mmc_priv(mmc);
1710
1711 /*
1712 * Undo pm_runtime_put() in probe. We use the _sync
1713 * version here so that we can access the primecell.
1714 */
1715 pm_runtime_get_sync(&dev->dev);
1716
1717 mmc_remove_host(mmc);
1718
1719 writel(0, host->base + MMCIMASK0);
1720 writel(0, host->base + MMCIMASK1);
1721
1722 writel(0, host->base + MMCICOMMAND);
1723 writel(0, host->base + MMCIDATACTRL);
1724
1725 mmci_dma_release(host);
1726 clk_disable_unprepare(host->clk);
1727 mmc_free_host(mmc);
1728 }
1729
1730 return 0;
1731 }
1732
1733 #ifdef CONFIG_PM
1734 static void mmci_save(struct mmci_host *host)
1735 {
1736 unsigned long flags;
1737
1738 spin_lock_irqsave(&host->lock, flags);
1739
1740 writel(0, host->base + MMCIMASK0);
1741 if (host->variant->pwrreg_nopower) {
1742 writel(0, host->base + MMCIDATACTRL);
1743 writel(0, host->base + MMCIPOWER);
1744 writel(0, host->base + MMCICLOCK);
1745 }
1746 mmci_reg_delay(host);
1747
1748 spin_unlock_irqrestore(&host->lock, flags);
1749 }
1750
1751 static void mmci_restore(struct mmci_host *host)
1752 {
1753 unsigned long flags;
1754
1755 spin_lock_irqsave(&host->lock, flags);
1756
1757 if (host->variant->pwrreg_nopower) {
1758 writel(host->clk_reg, host->base + MMCICLOCK);
1759 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1760 writel(host->pwr_reg, host->base + MMCIPOWER);
1761 }
1762 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1763 mmci_reg_delay(host);
1764
1765 spin_unlock_irqrestore(&host->lock, flags);
1766 }
1767
1768 static int mmci_runtime_suspend(struct device *dev)
1769 {
1770 struct amba_device *adev = to_amba_device(dev);
1771 struct mmc_host *mmc = amba_get_drvdata(adev);
1772
1773 if (mmc) {
1774 struct mmci_host *host = mmc_priv(mmc);
1775 pinctrl_pm_select_sleep_state(dev);
1776 mmci_save(host);
1777 clk_disable_unprepare(host->clk);
1778 }
1779
1780 return 0;
1781 }
1782
1783 static int mmci_runtime_resume(struct device *dev)
1784 {
1785 struct amba_device *adev = to_amba_device(dev);
1786 struct mmc_host *mmc = amba_get_drvdata(adev);
1787
1788 if (mmc) {
1789 struct mmci_host *host = mmc_priv(mmc);
1790 clk_prepare_enable(host->clk);
1791 mmci_restore(host);
1792 pinctrl_pm_select_default_state(dev);
1793 }
1794
1795 return 0;
1796 }
1797 #endif
1798
1799 static const struct dev_pm_ops mmci_dev_pm_ops = {
1800 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1801 pm_runtime_force_resume)
1802 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1803 };
1804
1805 static struct amba_id mmci_ids[] = {
1806 {
1807 .id = 0x00041180,
1808 .mask = 0xff0fffff,
1809 .data = &variant_arm,
1810 },
1811 {
1812 .id = 0x01041180,
1813 .mask = 0xff0fffff,
1814 .data = &variant_arm_extended_fifo,
1815 },
1816 {
1817 .id = 0x02041180,
1818 .mask = 0xff0fffff,
1819 .data = &variant_arm_extended_fifo_hwfc,
1820 },
1821 {
1822 .id = 0x00041181,
1823 .mask = 0x000fffff,
1824 .data = &variant_arm,
1825 },
1826 /* ST Micro variants */
1827 {
1828 .id = 0x00180180,
1829 .mask = 0x00ffffff,
1830 .data = &variant_u300,
1831 },
1832 {
1833 .id = 0x10180180,
1834 .mask = 0xf0ffffff,
1835 .data = &variant_nomadik,
1836 },
1837 {
1838 .id = 0x00280180,
1839 .mask = 0x00ffffff,
1840 .data = &variant_u300,
1841 },
1842 {
1843 .id = 0x00480180,
1844 .mask = 0xf0ffffff,
1845 .data = &variant_ux500,
1846 },
1847 {
1848 .id = 0x10480180,
1849 .mask = 0xf0ffffff,
1850 .data = &variant_ux500v2,
1851 },
1852 /* Qualcomm variants */
1853 {
1854 .id = 0x00051180,
1855 .mask = 0x000fffff,
1856 .data = &variant_qcom,
1857 },
1858 { 0, 0 },
1859 };
1860
1861 MODULE_DEVICE_TABLE(amba, mmci_ids);
1862
1863 static struct amba_driver mmci_driver = {
1864 .drv = {
1865 .name = DRIVER_NAME,
1866 .pm = &mmci_dev_pm_ops,
1867 },
1868 .probe = mmci_probe,
1869 .remove = mmci_remove,
1870 .id_table = mmci_ids,
1871 };
1872
1873 module_amba_driver(mmci_driver);
1874
1875 module_param(fmax, uint, 0444);
1876
1877 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1878 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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