2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
41 #include <asm/div64.h>
43 #include <asm/sizes.h>
47 #define DRIVER_NAME "mmci-pl18x"
49 static unsigned int fmax
= 515633;
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
54 * @clkreg_enable: enable value for MMCICLOCK register
55 * @datalength_bits: number of bits in the MMCIDATALENGTH register
56 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
57 * is asserted (likewise for RX)
58 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
59 * is asserted (likewise for RX)
60 * @sdio: variant supports SDIO
61 * @st_clkdiv: true if using a ST-specific clock divider algorithm
62 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
63 * @pwrreg_powerup: power up value for MMCIPOWER register
64 * @signal_direction: input/out direction of bus signals can be indicated
65 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
66 * @busy_detect: true if busy detection on dat0 is supported
67 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
71 unsigned int clkreg_enable
;
72 unsigned int datalength_bits
;
73 unsigned int fifosize
;
74 unsigned int fifohalfsize
;
77 bool blksz_datactrl16
;
79 bool signal_direction
;
85 static struct variant_data variant_arm
= {
87 .fifohalfsize
= 8 * 4,
88 .datalength_bits
= 16,
89 .pwrreg_powerup
= MCI_PWR_UP
,
92 static struct variant_data variant_arm_extended_fifo
= {
94 .fifohalfsize
= 64 * 4,
95 .datalength_bits
= 16,
96 .pwrreg_powerup
= MCI_PWR_UP
,
99 static struct variant_data variant_arm_extended_fifo_hwfc
= {
101 .fifohalfsize
= 64 * 4,
102 .clkreg_enable
= MCI_ARM_HWFCEN
,
103 .datalength_bits
= 16,
104 .pwrreg_powerup
= MCI_PWR_UP
,
107 static struct variant_data variant_u300
= {
109 .fifohalfsize
= 8 * 4,
110 .clkreg_enable
= MCI_ST_U300_HWFCEN
,
111 .datalength_bits
= 16,
113 .pwrreg_powerup
= MCI_PWR_ON
,
114 .signal_direction
= true,
115 .pwrreg_clkgate
= true,
116 .pwrreg_nopower
= true,
119 static struct variant_data variant_nomadik
= {
121 .fifohalfsize
= 8 * 4,
122 .clkreg
= MCI_CLK_ENABLE
,
123 .datalength_bits
= 24,
126 .pwrreg_powerup
= MCI_PWR_ON
,
127 .signal_direction
= true,
128 .pwrreg_clkgate
= true,
129 .pwrreg_nopower
= true,
132 static struct variant_data variant_ux500
= {
134 .fifohalfsize
= 8 * 4,
135 .clkreg
= MCI_CLK_ENABLE
,
136 .clkreg_enable
= MCI_ST_UX500_HWFCEN
,
137 .datalength_bits
= 24,
140 .pwrreg_powerup
= MCI_PWR_ON
,
141 .signal_direction
= true,
142 .pwrreg_clkgate
= true,
144 .pwrreg_nopower
= true,
147 static struct variant_data variant_ux500v2
= {
149 .fifohalfsize
= 8 * 4,
150 .clkreg
= MCI_CLK_ENABLE
,
151 .clkreg_enable
= MCI_ST_UX500_HWFCEN
,
152 .datalength_bits
= 24,
155 .blksz_datactrl16
= true,
156 .pwrreg_powerup
= MCI_PWR_ON
,
157 .signal_direction
= true,
158 .pwrreg_clkgate
= true,
160 .pwrreg_nopower
= true,
163 static int mmci_card_busy(struct mmc_host
*mmc
)
165 struct mmci_host
*host
= mmc_priv(mmc
);
169 pm_runtime_get_sync(mmc_dev(mmc
));
171 spin_lock_irqsave(&host
->lock
, flags
);
172 if (readl(host
->base
+ MMCISTATUS
) & MCI_ST_CARDBUSY
)
174 spin_unlock_irqrestore(&host
->lock
, flags
);
176 pm_runtime_mark_last_busy(mmc_dev(mmc
));
177 pm_runtime_put_autosuspend(mmc_dev(mmc
));
183 * Validate mmc prerequisites
185 static int mmci_validate_data(struct mmci_host
*host
,
186 struct mmc_data
*data
)
191 if (!is_power_of_2(data
->blksz
)) {
192 dev_err(mmc_dev(host
->mmc
),
193 "unsupported block size (%d bytes)\n", data
->blksz
);
200 static void mmci_reg_delay(struct mmci_host
*host
)
203 * According to the spec, at least three feedback clock cycles
204 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
205 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
206 * Worst delay time during card init is at 100 kHz => 30 us.
207 * Worst delay time when up and running is at 25 MHz => 120 ns.
209 if (host
->cclk
< 25000000)
216 * This must be called with host->lock held
218 static void mmci_write_clkreg(struct mmci_host
*host
, u32 clk
)
220 if (host
->clk_reg
!= clk
) {
222 writel(clk
, host
->base
+ MMCICLOCK
);
227 * This must be called with host->lock held
229 static void mmci_write_pwrreg(struct mmci_host
*host
, u32 pwr
)
231 if (host
->pwr_reg
!= pwr
) {
233 writel(pwr
, host
->base
+ MMCIPOWER
);
238 * This must be called with host->lock held
240 static void mmci_write_datactrlreg(struct mmci_host
*host
, u32 datactrl
)
242 /* Keep ST Micro busy mode if enabled */
243 datactrl
|= host
->datactrl_reg
& MCI_ST_DPSM_BUSYMODE
;
245 if (host
->datactrl_reg
!= datactrl
) {
246 host
->datactrl_reg
= datactrl
;
247 writel(datactrl
, host
->base
+ MMCIDATACTRL
);
252 * This must be called with host->lock held
254 static void mmci_set_clkreg(struct mmci_host
*host
, unsigned int desired
)
256 struct variant_data
*variant
= host
->variant
;
257 u32 clk
= variant
->clkreg
;
259 /* Make sure cclk reflects the current calculated clock */
263 if (desired
>= host
->mclk
) {
264 clk
= MCI_CLK_BYPASS
;
265 if (variant
->st_clkdiv
)
266 clk
|= MCI_ST_UX500_NEG_EDGE
;
267 host
->cclk
= host
->mclk
;
268 } else if (variant
->st_clkdiv
) {
270 * DB8500 TRM says f = mclk / (clkdiv + 2)
271 * => clkdiv = (mclk / f) - 2
272 * Round the divider up so we don't exceed the max
275 clk
= DIV_ROUND_UP(host
->mclk
, desired
) - 2;
278 host
->cclk
= host
->mclk
/ (clk
+ 2);
281 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
282 * => clkdiv = mclk / (2 * f) - 1
284 clk
= host
->mclk
/ (2 * desired
) - 1;
287 host
->cclk
= host
->mclk
/ (2 * (clk
+ 1));
290 clk
|= variant
->clkreg_enable
;
291 clk
|= MCI_CLK_ENABLE
;
292 /* This hasn't proven to be worthwhile */
293 /* clk |= MCI_CLK_PWRSAVE; */
296 /* Set actual clock for debug */
297 host
->mmc
->actual_clock
= host
->cclk
;
299 if (host
->mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
301 if (host
->mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
302 clk
|= MCI_ST_8BIT_BUS
;
304 if (host
->mmc
->ios
.timing
== MMC_TIMING_UHS_DDR50
)
305 clk
|= MCI_ST_UX500_NEG_EDGE
;
307 mmci_write_clkreg(host
, clk
);
311 mmci_request_end(struct mmci_host
*host
, struct mmc_request
*mrq
)
313 writel(0, host
->base
+ MMCICOMMAND
);
320 mmc_request_done(host
->mmc
, mrq
);
322 pm_runtime_mark_last_busy(mmc_dev(host
->mmc
));
323 pm_runtime_put_autosuspend(mmc_dev(host
->mmc
));
326 static void mmci_set_mask1(struct mmci_host
*host
, unsigned int mask
)
328 void __iomem
*base
= host
->base
;
330 if (host
->singleirq
) {
331 unsigned int mask0
= readl(base
+ MMCIMASK0
);
333 mask0
&= ~MCI_IRQ1MASK
;
336 writel(mask0
, base
+ MMCIMASK0
);
339 writel(mask
, base
+ MMCIMASK1
);
342 static void mmci_stop_data(struct mmci_host
*host
)
344 mmci_write_datactrlreg(host
, 0);
345 mmci_set_mask1(host
, 0);
349 static void mmci_init_sg(struct mmci_host
*host
, struct mmc_data
*data
)
351 unsigned int flags
= SG_MITER_ATOMIC
;
353 if (data
->flags
& MMC_DATA_READ
)
354 flags
|= SG_MITER_TO_SG
;
356 flags
|= SG_MITER_FROM_SG
;
358 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
362 * All the DMA operation mode stuff goes inside this ifdef.
363 * This assumes that you have a generic DMA device interface,
364 * no custom DMA interfaces are supported.
366 #ifdef CONFIG_DMA_ENGINE
367 static void mmci_dma_setup(struct mmci_host
*host
)
369 const char *rxname
, *txname
;
372 host
->dma_rx_channel
= dma_request_slave_channel(mmc_dev(host
->mmc
), "rx");
373 host
->dma_tx_channel
= dma_request_slave_channel(mmc_dev(host
->mmc
), "tx");
375 /* initialize pre request cookie */
376 host
->next_data
.cookie
= 1;
378 /* Try to acquire a generic DMA engine slave channel */
380 dma_cap_set(DMA_SLAVE
, mask
);
383 * If only an RX channel is specified, the driver will
384 * attempt to use it bidirectionally, however if it is
385 * is specified but cannot be located, DMA will be disabled.
387 if (host
->dma_rx_channel
&& !host
->dma_tx_channel
)
388 host
->dma_tx_channel
= host
->dma_rx_channel
;
390 if (host
->dma_rx_channel
)
391 rxname
= dma_chan_name(host
->dma_rx_channel
);
395 if (host
->dma_tx_channel
)
396 txname
= dma_chan_name(host
->dma_tx_channel
);
400 dev_info(mmc_dev(host
->mmc
), "DMA channels RX %s, TX %s\n",
404 * Limit the maximum segment size in any SG entry according to
405 * the parameters of the DMA engine device.
407 if (host
->dma_tx_channel
) {
408 struct device
*dev
= host
->dma_tx_channel
->device
->dev
;
409 unsigned int max_seg_size
= dma_get_max_seg_size(dev
);
411 if (max_seg_size
< host
->mmc
->max_seg_size
)
412 host
->mmc
->max_seg_size
= max_seg_size
;
414 if (host
->dma_rx_channel
) {
415 struct device
*dev
= host
->dma_rx_channel
->device
->dev
;
416 unsigned int max_seg_size
= dma_get_max_seg_size(dev
);
418 if (max_seg_size
< host
->mmc
->max_seg_size
)
419 host
->mmc
->max_seg_size
= max_seg_size
;
424 * This is used in or so inline it
425 * so it can be discarded.
427 static inline void mmci_dma_release(struct mmci_host
*host
)
429 if (host
->dma_rx_channel
)
430 dma_release_channel(host
->dma_rx_channel
);
431 if (host
->dma_tx_channel
)
432 dma_release_channel(host
->dma_tx_channel
);
433 host
->dma_rx_channel
= host
->dma_tx_channel
= NULL
;
436 static void mmci_dma_data_error(struct mmci_host
*host
)
438 dev_err(mmc_dev(host
->mmc
), "error during DMA transfer!\n");
439 dmaengine_terminate_all(host
->dma_current
);
440 host
->dma_current
= NULL
;
441 host
->dma_desc_current
= NULL
;
442 host
->data
->host_cookie
= 0;
445 static void mmci_dma_unmap(struct mmci_host
*host
, struct mmc_data
*data
)
447 struct dma_chan
*chan
;
448 enum dma_data_direction dir
;
450 if (data
->flags
& MMC_DATA_READ
) {
451 dir
= DMA_FROM_DEVICE
;
452 chan
= host
->dma_rx_channel
;
455 chan
= host
->dma_tx_channel
;
458 dma_unmap_sg(chan
->device
->dev
, data
->sg
, data
->sg_len
, dir
);
461 static void mmci_dma_finalize(struct mmci_host
*host
, struct mmc_data
*data
)
466 /* Wait up to 1ms for the DMA to complete */
468 status
= readl(host
->base
+ MMCISTATUS
);
469 if (!(status
& MCI_RXDATAAVLBLMASK
) || i
>= 100)
475 * Check to see whether we still have some data left in the FIFO -
476 * this catches DMA controllers which are unable to monitor the
477 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
478 * contiguous buffers. On TX, we'll get a FIFO underrun error.
480 if (status
& MCI_RXDATAAVLBLMASK
) {
481 mmci_dma_data_error(host
);
486 if (!data
->host_cookie
)
487 mmci_dma_unmap(host
, data
);
490 * Use of DMA with scatter-gather is impossible.
491 * Give up with DMA and switch back to PIO mode.
493 if (status
& MCI_RXDATAAVLBLMASK
) {
494 dev_err(mmc_dev(host
->mmc
), "buggy DMA detected. Taking evasive action.\n");
495 mmci_dma_release(host
);
498 host
->dma_current
= NULL
;
499 host
->dma_desc_current
= NULL
;
502 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
503 static int __mmci_dma_prep_data(struct mmci_host
*host
, struct mmc_data
*data
,
504 struct dma_chan
**dma_chan
,
505 struct dma_async_tx_descriptor
**dma_desc
)
507 struct variant_data
*variant
= host
->variant
;
508 struct dma_slave_config conf
= {
509 .src_addr
= host
->phybase
+ MMCIFIFO
,
510 .dst_addr
= host
->phybase
+ MMCIFIFO
,
511 .src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
,
512 .dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
,
513 .src_maxburst
= variant
->fifohalfsize
>> 2, /* # of words */
514 .dst_maxburst
= variant
->fifohalfsize
>> 2, /* # of words */
517 struct dma_chan
*chan
;
518 struct dma_device
*device
;
519 struct dma_async_tx_descriptor
*desc
;
520 enum dma_data_direction buffer_dirn
;
523 if (data
->flags
& MMC_DATA_READ
) {
524 conf
.direction
= DMA_DEV_TO_MEM
;
525 buffer_dirn
= DMA_FROM_DEVICE
;
526 chan
= host
->dma_rx_channel
;
528 conf
.direction
= DMA_MEM_TO_DEV
;
529 buffer_dirn
= DMA_TO_DEVICE
;
530 chan
= host
->dma_tx_channel
;
533 /* If there's no DMA channel, fall back to PIO */
537 /* If less than or equal to the fifo size, don't bother with DMA */
538 if (data
->blksz
* data
->blocks
<= variant
->fifosize
)
541 device
= chan
->device
;
542 nr_sg
= dma_map_sg(device
->dev
, data
->sg
, data
->sg_len
, buffer_dirn
);
546 dmaengine_slave_config(chan
, &conf
);
547 desc
= dmaengine_prep_slave_sg(chan
, data
->sg
, nr_sg
,
548 conf
.direction
, DMA_CTRL_ACK
);
558 dma_unmap_sg(device
->dev
, data
->sg
, data
->sg_len
, buffer_dirn
);
562 static inline int mmci_dma_prep_data(struct mmci_host
*host
,
563 struct mmc_data
*data
)
565 /* Check if next job is already prepared. */
566 if (host
->dma_current
&& host
->dma_desc_current
)
569 /* No job were prepared thus do it now. */
570 return __mmci_dma_prep_data(host
, data
, &host
->dma_current
,
571 &host
->dma_desc_current
);
574 static inline int mmci_dma_prep_next(struct mmci_host
*host
,
575 struct mmc_data
*data
)
577 struct mmci_host_next
*nd
= &host
->next_data
;
578 return __mmci_dma_prep_data(host
, data
, &nd
->dma_chan
, &nd
->dma_desc
);
581 static int mmci_dma_start_data(struct mmci_host
*host
, unsigned int datactrl
)
584 struct mmc_data
*data
= host
->data
;
586 ret
= mmci_dma_prep_data(host
, host
->data
);
590 /* Okay, go for it. */
591 dev_vdbg(mmc_dev(host
->mmc
),
592 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
593 data
->sg_len
, data
->blksz
, data
->blocks
, data
->flags
);
594 dmaengine_submit(host
->dma_desc_current
);
595 dma_async_issue_pending(host
->dma_current
);
597 datactrl
|= MCI_DPSM_DMAENABLE
;
599 /* Trigger the DMA transfer */
600 mmci_write_datactrlreg(host
, datactrl
);
603 * Let the MMCI say when the data is ended and it's time
604 * to fire next DMA request. When that happens, MMCI will
605 * call mmci_data_end()
607 writel(readl(host
->base
+ MMCIMASK0
) | MCI_DATAENDMASK
,
608 host
->base
+ MMCIMASK0
);
612 static void mmci_get_next_data(struct mmci_host
*host
, struct mmc_data
*data
)
614 struct mmci_host_next
*next
= &host
->next_data
;
616 WARN_ON(data
->host_cookie
&& data
->host_cookie
!= next
->cookie
);
617 WARN_ON(!data
->host_cookie
&& (next
->dma_desc
|| next
->dma_chan
));
619 host
->dma_desc_current
= next
->dma_desc
;
620 host
->dma_current
= next
->dma_chan
;
621 next
->dma_desc
= NULL
;
622 next
->dma_chan
= NULL
;
625 static void mmci_pre_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
628 struct mmci_host
*host
= mmc_priv(mmc
);
629 struct mmc_data
*data
= mrq
->data
;
630 struct mmci_host_next
*nd
= &host
->next_data
;
635 BUG_ON(data
->host_cookie
);
637 if (mmci_validate_data(host
, data
))
640 if (!mmci_dma_prep_next(host
, data
))
641 data
->host_cookie
= ++nd
->cookie
< 0 ? 1 : nd
->cookie
;
644 static void mmci_post_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
647 struct mmci_host
*host
= mmc_priv(mmc
);
648 struct mmc_data
*data
= mrq
->data
;
650 if (!data
|| !data
->host_cookie
)
653 mmci_dma_unmap(host
, data
);
656 struct mmci_host_next
*next
= &host
->next_data
;
657 struct dma_chan
*chan
;
658 if (data
->flags
& MMC_DATA_READ
)
659 chan
= host
->dma_rx_channel
;
661 chan
= host
->dma_tx_channel
;
662 dmaengine_terminate_all(chan
);
664 next
->dma_desc
= NULL
;
665 next
->dma_chan
= NULL
;
670 /* Blank functions if the DMA engine is not available */
671 static void mmci_get_next_data(struct mmci_host
*host
, struct mmc_data
*data
)
674 static inline void mmci_dma_setup(struct mmci_host
*host
)
678 static inline void mmci_dma_release(struct mmci_host
*host
)
682 static inline void mmci_dma_unmap(struct mmci_host
*host
, struct mmc_data
*data
)
686 static inline void mmci_dma_finalize(struct mmci_host
*host
,
687 struct mmc_data
*data
)
691 static inline void mmci_dma_data_error(struct mmci_host
*host
)
695 static inline int mmci_dma_start_data(struct mmci_host
*host
, unsigned int datactrl
)
700 #define mmci_pre_request NULL
701 #define mmci_post_request NULL
705 static void mmci_start_data(struct mmci_host
*host
, struct mmc_data
*data
)
707 struct variant_data
*variant
= host
->variant
;
708 unsigned int datactrl
, timeout
, irqmask
;
709 unsigned long long clks
;
713 dev_dbg(mmc_dev(host
->mmc
), "blksz %04x blks %04x flags %08x\n",
714 data
->blksz
, data
->blocks
, data
->flags
);
717 host
->size
= data
->blksz
* data
->blocks
;
718 data
->bytes_xfered
= 0;
720 clks
= (unsigned long long)data
->timeout_ns
* host
->cclk
;
721 do_div(clks
, 1000000000UL);
723 timeout
= data
->timeout_clks
+ (unsigned int)clks
;
726 writel(timeout
, base
+ MMCIDATATIMER
);
727 writel(host
->size
, base
+ MMCIDATALENGTH
);
729 blksz_bits
= ffs(data
->blksz
) - 1;
730 BUG_ON(1 << blksz_bits
!= data
->blksz
);
732 if (variant
->blksz_datactrl16
)
733 datactrl
= MCI_DPSM_ENABLE
| (data
->blksz
<< 16);
735 datactrl
= MCI_DPSM_ENABLE
| blksz_bits
<< 4;
737 if (data
->flags
& MMC_DATA_READ
)
738 datactrl
|= MCI_DPSM_DIRECTION
;
740 /* The ST Micro variants has a special bit to enable SDIO */
741 if (variant
->sdio
&& host
->mmc
->card
)
742 if (mmc_card_sdio(host
->mmc
->card
)) {
744 * The ST Micro variants has a special bit
749 datactrl
|= MCI_ST_DPSM_SDIOEN
;
752 * The ST Micro variant for SDIO small write transfers
753 * needs to have clock H/W flow control disabled,
754 * otherwise the transfer will not start. The threshold
755 * depends on the rate of MCLK.
757 if (data
->flags
& MMC_DATA_WRITE
&&
759 (host
->size
<= 8 && host
->mclk
> 50000000)))
760 clk
= host
->clk_reg
& ~variant
->clkreg_enable
;
762 clk
= host
->clk_reg
| variant
->clkreg_enable
;
764 mmci_write_clkreg(host
, clk
);
767 if (host
->mmc
->ios
.timing
== MMC_TIMING_UHS_DDR50
)
768 datactrl
|= MCI_ST_DPSM_DDRMODE
;
771 * Attempt to use DMA operation mode, if this
772 * should fail, fall back to PIO mode
774 if (!mmci_dma_start_data(host
, datactrl
))
777 /* IRQ mode, map the SG list for CPU reading/writing */
778 mmci_init_sg(host
, data
);
780 if (data
->flags
& MMC_DATA_READ
) {
781 irqmask
= MCI_RXFIFOHALFFULLMASK
;
784 * If we have less than the fifo 'half-full' threshold to
785 * transfer, trigger a PIO interrupt as soon as any data
788 if (host
->size
< variant
->fifohalfsize
)
789 irqmask
|= MCI_RXDATAAVLBLMASK
;
792 * We don't actually need to include "FIFO empty" here
793 * since its implicit in "FIFO half empty".
795 irqmask
= MCI_TXFIFOHALFEMPTYMASK
;
798 mmci_write_datactrlreg(host
, datactrl
);
799 writel(readl(base
+ MMCIMASK0
) & ~MCI_DATAENDMASK
, base
+ MMCIMASK0
);
800 mmci_set_mask1(host
, irqmask
);
804 mmci_start_command(struct mmci_host
*host
, struct mmc_command
*cmd
, u32 c
)
806 void __iomem
*base
= host
->base
;
808 dev_dbg(mmc_dev(host
->mmc
), "op %02x arg %08x flags %08x\n",
809 cmd
->opcode
, cmd
->arg
, cmd
->flags
);
811 if (readl(base
+ MMCICOMMAND
) & MCI_CPSM_ENABLE
) {
812 writel(0, base
+ MMCICOMMAND
);
816 c
|= cmd
->opcode
| MCI_CPSM_ENABLE
;
817 if (cmd
->flags
& MMC_RSP_PRESENT
) {
818 if (cmd
->flags
& MMC_RSP_136
)
819 c
|= MCI_CPSM_LONGRSP
;
820 c
|= MCI_CPSM_RESPONSE
;
823 c
|= MCI_CPSM_INTERRUPT
;
827 writel(cmd
->arg
, base
+ MMCIARGUMENT
);
828 writel(c
, base
+ MMCICOMMAND
);
832 mmci_data_irq(struct mmci_host
*host
, struct mmc_data
*data
,
835 /* First check for errors */
836 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_STARTBITERR
|
837 MCI_TXUNDERRUN
|MCI_RXOVERRUN
)) {
840 /* Terminate the DMA transfer */
841 if (dma_inprogress(host
)) {
842 mmci_dma_data_error(host
);
843 mmci_dma_unmap(host
, data
);
847 * Calculate how far we are into the transfer. Note that
848 * the data counter gives the number of bytes transferred
849 * on the MMC bus, not on the host side. On reads, this
850 * can be as much as a FIFO-worth of data ahead. This
851 * matters for FIFO overruns only.
853 remain
= readl(host
->base
+ MMCIDATACNT
);
854 success
= data
->blksz
* data
->blocks
- remain
;
856 dev_dbg(mmc_dev(host
->mmc
), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
858 if (status
& MCI_DATACRCFAIL
) {
859 /* Last block was not successful */
861 data
->error
= -EILSEQ
;
862 } else if (status
& MCI_DATATIMEOUT
) {
863 data
->error
= -ETIMEDOUT
;
864 } else if (status
& MCI_STARTBITERR
) {
865 data
->error
= -ECOMM
;
866 } else if (status
& MCI_TXUNDERRUN
) {
868 } else if (status
& MCI_RXOVERRUN
) {
869 if (success
> host
->variant
->fifosize
)
870 success
-= host
->variant
->fifosize
;
875 data
->bytes_xfered
= round_down(success
, data
->blksz
);
878 if (status
& MCI_DATABLOCKEND
)
879 dev_err(mmc_dev(host
->mmc
), "stray MCI_DATABLOCKEND interrupt\n");
881 if (status
& MCI_DATAEND
|| data
->error
) {
882 if (dma_inprogress(host
))
883 mmci_dma_finalize(host
, data
);
884 mmci_stop_data(host
);
887 /* The error clause is handled above, success! */
888 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
890 if (!data
->stop
|| host
->mrq
->sbc
) {
891 mmci_request_end(host
, data
->mrq
);
893 mmci_start_command(host
, data
->stop
, 0);
899 mmci_cmd_irq(struct mmci_host
*host
, struct mmc_command
*cmd
,
902 void __iomem
*base
= host
->base
;
903 bool sbc
= (cmd
== host
->mrq
->sbc
);
904 bool busy_resp
= host
->variant
->busy_detect
&&
905 (cmd
->flags
& MMC_RSP_BUSY
);
907 /* Check if we need to wait for busy completion. */
908 if (host
->busy_status
&& (status
& MCI_ST_CARDBUSY
))
911 /* Enable busy completion if needed and supported. */
912 if (!host
->busy_status
&& busy_resp
&&
913 !(status
& (MCI_CMDCRCFAIL
|MCI_CMDTIMEOUT
)) &&
914 (readl(base
+ MMCISTATUS
) & MCI_ST_CARDBUSY
)) {
915 writel(readl(base
+ MMCIMASK0
) | MCI_ST_BUSYEND
,
917 host
->busy_status
= status
& (MCI_CMDSENT
|MCI_CMDRESPEND
);
921 /* At busy completion, mask the IRQ and complete the request. */
922 if (host
->busy_status
) {
923 writel(readl(base
+ MMCIMASK0
) & ~MCI_ST_BUSYEND
,
925 host
->busy_status
= 0;
930 if (status
& MCI_CMDTIMEOUT
) {
931 cmd
->error
= -ETIMEDOUT
;
932 } else if (status
& MCI_CMDCRCFAIL
&& cmd
->flags
& MMC_RSP_CRC
) {
933 cmd
->error
= -EILSEQ
;
935 cmd
->resp
[0] = readl(base
+ MMCIRESPONSE0
);
936 cmd
->resp
[1] = readl(base
+ MMCIRESPONSE1
);
937 cmd
->resp
[2] = readl(base
+ MMCIRESPONSE2
);
938 cmd
->resp
[3] = readl(base
+ MMCIRESPONSE3
);
941 if ((!sbc
&& !cmd
->data
) || cmd
->error
) {
943 /* Terminate the DMA transfer */
944 if (dma_inprogress(host
)) {
945 mmci_dma_data_error(host
);
946 mmci_dma_unmap(host
, host
->data
);
948 mmci_stop_data(host
);
950 mmci_request_end(host
, host
->mrq
);
952 mmci_start_command(host
, host
->mrq
->cmd
, 0);
953 } else if (!(cmd
->data
->flags
& MMC_DATA_READ
)) {
954 mmci_start_data(host
, cmd
->data
);
958 static int mmci_pio_read(struct mmci_host
*host
, char *buffer
, unsigned int remain
)
960 void __iomem
*base
= host
->base
;
963 int host_remain
= host
->size
;
966 int count
= host_remain
- (readl(base
+ MMCIFIFOCNT
) << 2);
975 * SDIO especially may want to send something that is
976 * not divisible by 4 (as opposed to card sectors
977 * etc). Therefore make sure to always read the last bytes
978 * while only doing full 32-bit reads towards the FIFO.
980 if (unlikely(count
& 0x3)) {
982 unsigned char buf
[4];
983 ioread32_rep(base
+ MMCIFIFO
, buf
, 1);
984 memcpy(ptr
, buf
, count
);
986 ioread32_rep(base
+ MMCIFIFO
, ptr
, count
>> 2);
990 ioread32_rep(base
+ MMCIFIFO
, ptr
, count
>> 2);
995 host_remain
-= count
;
1000 status
= readl(base
+ MMCISTATUS
);
1001 } while (status
& MCI_RXDATAAVLBL
);
1003 return ptr
- buffer
;
1006 static int mmci_pio_write(struct mmci_host
*host
, char *buffer
, unsigned int remain
, u32 status
)
1008 struct variant_data
*variant
= host
->variant
;
1009 void __iomem
*base
= host
->base
;
1013 unsigned int count
, maxcnt
;
1015 maxcnt
= status
& MCI_TXFIFOEMPTY
?
1016 variant
->fifosize
: variant
->fifohalfsize
;
1017 count
= min(remain
, maxcnt
);
1020 * SDIO especially may want to send something that is
1021 * not divisible by 4 (as opposed to card sectors
1022 * etc), and the FIFO only accept full 32-bit writes.
1023 * So compensate by adding +3 on the count, a single
1024 * byte become a 32bit write, 7 bytes will be two
1027 iowrite32_rep(base
+ MMCIFIFO
, ptr
, (count
+ 3) >> 2);
1035 status
= readl(base
+ MMCISTATUS
);
1036 } while (status
& MCI_TXFIFOHALFEMPTY
);
1038 return ptr
- buffer
;
1042 * PIO data transfer IRQ handler.
1044 static irqreturn_t
mmci_pio_irq(int irq
, void *dev_id
)
1046 struct mmci_host
*host
= dev_id
;
1047 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
1048 struct variant_data
*variant
= host
->variant
;
1049 void __iomem
*base
= host
->base
;
1050 unsigned long flags
;
1053 status
= readl(base
+ MMCISTATUS
);
1055 dev_dbg(mmc_dev(host
->mmc
), "irq1 (pio) %08x\n", status
);
1057 local_irq_save(flags
);
1060 unsigned int remain
, len
;
1064 * For write, we only need to test the half-empty flag
1065 * here - if the FIFO is completely empty, then by
1066 * definition it is more than half empty.
1068 * For read, check for data available.
1070 if (!(status
& (MCI_TXFIFOHALFEMPTY
|MCI_RXDATAAVLBL
)))
1073 if (!sg_miter_next(sg_miter
))
1076 buffer
= sg_miter
->addr
;
1077 remain
= sg_miter
->length
;
1080 if (status
& MCI_RXACTIVE
)
1081 len
= mmci_pio_read(host
, buffer
, remain
);
1082 if (status
& MCI_TXACTIVE
)
1083 len
= mmci_pio_write(host
, buffer
, remain
, status
);
1085 sg_miter
->consumed
= len
;
1093 status
= readl(base
+ MMCISTATUS
);
1096 sg_miter_stop(sg_miter
);
1098 local_irq_restore(flags
);
1101 * If we have less than the fifo 'half-full' threshold to transfer,
1102 * trigger a PIO interrupt as soon as any data is available.
1104 if (status
& MCI_RXACTIVE
&& host
->size
< variant
->fifohalfsize
)
1105 mmci_set_mask1(host
, MCI_RXDATAAVLBLMASK
);
1108 * If we run out of data, disable the data IRQs; this
1109 * prevents a race where the FIFO becomes empty before
1110 * the chip itself has disabled the data path, and
1111 * stops us racing with our data end IRQ.
1113 if (host
->size
== 0) {
1114 mmci_set_mask1(host
, 0);
1115 writel(readl(base
+ MMCIMASK0
) | MCI_DATAENDMASK
, base
+ MMCIMASK0
);
1122 * Handle completion of command and data transfers.
1124 static irqreturn_t
mmci_irq(int irq
, void *dev_id
)
1126 struct mmci_host
*host
= dev_id
;
1130 spin_lock(&host
->lock
);
1133 struct mmc_command
*cmd
;
1134 struct mmc_data
*data
;
1136 status
= readl(host
->base
+ MMCISTATUS
);
1138 if (host
->singleirq
) {
1139 if (status
& readl(host
->base
+ MMCIMASK1
))
1140 mmci_pio_irq(irq
, dev_id
);
1142 status
&= ~MCI_IRQ1MASK
;
1146 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1147 * enabled) since the HW seems to be triggering the IRQ on both
1148 * edges while monitoring DAT0 for busy completion.
1150 status
&= readl(host
->base
+ MMCIMASK0
);
1151 writel(status
, host
->base
+ MMCICLEAR
);
1153 dev_dbg(mmc_dev(host
->mmc
), "irq0 (data+cmd) %08x\n", status
);
1156 if ((status
|host
->busy_status
) & (MCI_CMDCRCFAIL
|MCI_CMDTIMEOUT
|
1157 MCI_CMDSENT
|MCI_CMDRESPEND
) && cmd
)
1158 mmci_cmd_irq(host
, cmd
, status
);
1161 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_STARTBITERR
|
1162 MCI_TXUNDERRUN
|MCI_RXOVERRUN
|MCI_DATAEND
|
1163 MCI_DATABLOCKEND
) && data
)
1164 mmci_data_irq(host
, data
, status
);
1166 /* Don't poll for busy completion in irq context. */
1167 if (host
->busy_status
)
1168 status
&= ~MCI_ST_CARDBUSY
;
1173 spin_unlock(&host
->lock
);
1175 return IRQ_RETVAL(ret
);
1178 static void mmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1180 struct mmci_host
*host
= mmc_priv(mmc
);
1181 unsigned long flags
;
1183 WARN_ON(host
->mrq
!= NULL
);
1185 mrq
->cmd
->error
= mmci_validate_data(host
, mrq
->data
);
1186 if (mrq
->cmd
->error
) {
1187 mmc_request_done(mmc
, mrq
);
1191 pm_runtime_get_sync(mmc_dev(mmc
));
1193 spin_lock_irqsave(&host
->lock
, flags
);
1198 mmci_get_next_data(host
, mrq
->data
);
1200 if (mrq
->data
&& mrq
->data
->flags
& MMC_DATA_READ
)
1201 mmci_start_data(host
, mrq
->data
);
1204 mmci_start_command(host
, mrq
->sbc
, 0);
1206 mmci_start_command(host
, mrq
->cmd
, 0);
1208 spin_unlock_irqrestore(&host
->lock
, flags
);
1211 static void mmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1213 struct mmci_host
*host
= mmc_priv(mmc
);
1214 struct variant_data
*variant
= host
->variant
;
1216 unsigned long flags
;
1219 pm_runtime_get_sync(mmc_dev(mmc
));
1221 if (host
->plat
->ios_handler
&&
1222 host
->plat
->ios_handler(mmc_dev(mmc
), ios
))
1223 dev_err(mmc_dev(mmc
), "platform ios_handler failed\n");
1225 switch (ios
->power_mode
) {
1227 if (!IS_ERR(mmc
->supply
.vmmc
))
1228 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1230 if (!IS_ERR(mmc
->supply
.vqmmc
) && host
->vqmmc_enabled
) {
1231 regulator_disable(mmc
->supply
.vqmmc
);
1232 host
->vqmmc_enabled
= false;
1237 if (!IS_ERR(mmc
->supply
.vmmc
))
1238 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, ios
->vdd
);
1241 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1242 * and instead uses MCI_PWR_ON so apply whatever value is
1243 * configured in the variant data.
1245 pwr
|= variant
->pwrreg_powerup
;
1249 if (!IS_ERR(mmc
->supply
.vqmmc
) && !host
->vqmmc_enabled
) {
1250 ret
= regulator_enable(mmc
->supply
.vqmmc
);
1252 dev_err(mmc_dev(mmc
),
1253 "failed to enable vqmmc regulator\n");
1255 host
->vqmmc_enabled
= true;
1262 if (variant
->signal_direction
&& ios
->power_mode
!= MMC_POWER_OFF
) {
1264 * The ST Micro variant has some additional bits
1265 * indicating signal direction for the signals in
1266 * the SD/MMC bus and feedback-clock usage.
1268 pwr
|= host
->pwr_reg_add
;
1270 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1271 pwr
&= ~MCI_ST_DATA74DIREN
;
1272 else if (ios
->bus_width
== MMC_BUS_WIDTH_1
)
1273 pwr
&= (~MCI_ST_DATA74DIREN
&
1274 ~MCI_ST_DATA31DIREN
&
1275 ~MCI_ST_DATA2DIREN
);
1278 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
) {
1279 if (host
->hw_designer
!= AMBA_VENDOR_ST
)
1283 * The ST Micro variant use the ROD bit for something
1284 * else and only has OD (Open Drain).
1291 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1292 * gating the clock, the MCI_PWR_ON bit is cleared.
1294 if (!ios
->clock
&& variant
->pwrreg_clkgate
)
1297 spin_lock_irqsave(&host
->lock
, flags
);
1299 mmci_set_clkreg(host
, ios
->clock
);
1300 mmci_write_pwrreg(host
, pwr
);
1301 mmci_reg_delay(host
);
1303 spin_unlock_irqrestore(&host
->lock
, flags
);
1305 pm_runtime_mark_last_busy(mmc_dev(mmc
));
1306 pm_runtime_put_autosuspend(mmc_dev(mmc
));
1309 static int mmci_get_cd(struct mmc_host
*mmc
)
1311 struct mmci_host
*host
= mmc_priv(mmc
);
1312 struct mmci_platform_data
*plat
= host
->plat
;
1313 unsigned int status
= mmc_gpio_get_cd(mmc
);
1315 if (status
== -ENOSYS
) {
1317 return 1; /* Assume always present */
1319 status
= plat
->status(mmc_dev(host
->mmc
));
1324 static int mmci_sig_volt_switch(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1328 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1330 pm_runtime_get_sync(mmc_dev(mmc
));
1332 switch (ios
->signal_voltage
) {
1333 case MMC_SIGNAL_VOLTAGE_330
:
1334 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1337 case MMC_SIGNAL_VOLTAGE_180
:
1338 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1341 case MMC_SIGNAL_VOLTAGE_120
:
1342 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1348 dev_warn(mmc_dev(mmc
), "Voltage switch failed\n");
1350 pm_runtime_mark_last_busy(mmc_dev(mmc
));
1351 pm_runtime_put_autosuspend(mmc_dev(mmc
));
1357 static struct mmc_host_ops mmci_ops
= {
1358 .request
= mmci_request
,
1359 .pre_req
= mmci_pre_request
,
1360 .post_req
= mmci_post_request
,
1361 .set_ios
= mmci_set_ios
,
1362 .get_ro
= mmc_gpio_get_ro
,
1363 .get_cd
= mmci_get_cd
,
1364 .start_signal_voltage_switch
= mmci_sig_volt_switch
,
1367 static int mmci_of_parse(struct device_node
*np
, struct mmc_host
*mmc
)
1369 struct mmci_host
*host
= mmc_priv(mmc
);
1370 int ret
= mmc_of_parse(mmc
);
1375 if (of_get_property(np
, "st,sig-dir-dat0", NULL
))
1376 host
->pwr_reg_add
|= MCI_ST_DATA0DIREN
;
1377 if (of_get_property(np
, "st,sig-dir-dat2", NULL
))
1378 host
->pwr_reg_add
|= MCI_ST_DATA2DIREN
;
1379 if (of_get_property(np
, "st,sig-dir-dat31", NULL
))
1380 host
->pwr_reg_add
|= MCI_ST_DATA31DIREN
;
1381 if (of_get_property(np
, "st,sig-dir-dat74", NULL
))
1382 host
->pwr_reg_add
|= MCI_ST_DATA74DIREN
;
1383 if (of_get_property(np
, "st,sig-dir-cmd", NULL
))
1384 host
->pwr_reg_add
|= MCI_ST_CMDDIREN
;
1385 if (of_get_property(np
, "st,sig-pin-fbclk", NULL
))
1386 host
->pwr_reg_add
|= MCI_ST_FBCLKEN
;
1388 if (of_get_property(np
, "mmc-cap-mmc-highspeed", NULL
))
1389 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
;
1390 if (of_get_property(np
, "mmc-cap-sd-highspeed", NULL
))
1391 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
;
1396 static int mmci_probe(struct amba_device
*dev
,
1397 const struct amba_id
*id
)
1399 struct mmci_platform_data
*plat
= dev
->dev
.platform_data
;
1400 struct device_node
*np
= dev
->dev
.of_node
;
1401 struct variant_data
*variant
= id
->data
;
1402 struct mmci_host
*host
;
1403 struct mmc_host
*mmc
;
1406 /* Must have platform data or Device Tree. */
1408 dev_err(&dev
->dev
, "No plat data or DT found\n");
1413 plat
= devm_kzalloc(&dev
->dev
, sizeof(*plat
), GFP_KERNEL
);
1418 mmc
= mmc_alloc_host(sizeof(struct mmci_host
), &dev
->dev
);
1422 ret
= mmci_of_parse(np
, mmc
);
1426 host
= mmc_priv(mmc
);
1429 host
->hw_designer
= amba_manf(dev
);
1430 host
->hw_revision
= amba_rev(dev
);
1431 dev_dbg(mmc_dev(mmc
), "designer ID = 0x%02x\n", host
->hw_designer
);
1432 dev_dbg(mmc_dev(mmc
), "revision = 0x%01x\n", host
->hw_revision
);
1434 host
->clk
= devm_clk_get(&dev
->dev
, NULL
);
1435 if (IS_ERR(host
->clk
)) {
1436 ret
= PTR_ERR(host
->clk
);
1440 ret
= clk_prepare_enable(host
->clk
);
1445 host
->variant
= variant
;
1446 host
->mclk
= clk_get_rate(host
->clk
);
1448 * According to the spec, mclk is max 100 MHz,
1449 * so we try to adjust the clock down to this,
1452 if (host
->mclk
> 100000000) {
1453 ret
= clk_set_rate(host
->clk
, 100000000);
1456 host
->mclk
= clk_get_rate(host
->clk
);
1457 dev_dbg(mmc_dev(mmc
), "eventual mclk rate: %u Hz\n",
1461 host
->phybase
= dev
->res
.start
;
1462 host
->base
= devm_ioremap_resource(&dev
->dev
, &dev
->res
);
1463 if (IS_ERR(host
->base
)) {
1464 ret
= PTR_ERR(host
->base
);
1469 * The ARM and ST versions of the block have slightly different
1470 * clock divider equations which means that the minimum divider
1473 if (variant
->st_clkdiv
)
1474 mmc
->f_min
= DIV_ROUND_UP(host
->mclk
, 257);
1476 mmc
->f_min
= DIV_ROUND_UP(host
->mclk
, 512);
1478 * If no maximum operating frequency is supplied, fall back to use
1479 * the module parameter, which has a (low) default value in case it
1480 * is not specified. Either value must not exceed the clock rate into
1481 * the block, of course.
1484 mmc
->f_max
= min(host
->mclk
, mmc
->f_max
);
1486 mmc
->f_max
= min(host
->mclk
, fmax
);
1487 dev_dbg(mmc_dev(mmc
), "clocking block at %u Hz\n", mmc
->f_max
);
1489 /* Get regulators and the supported OCR mask */
1490 mmc_regulator_get_supply(mmc
);
1491 if (!mmc
->ocr_avail
)
1492 mmc
->ocr_avail
= plat
->ocr_mask
;
1493 else if (plat
->ocr_mask
)
1494 dev_warn(mmc_dev(mmc
), "Platform OCR mask is ignored\n");
1496 /* DT takes precedence over platform data. */
1498 if (!plat
->cd_invert
)
1499 mmc
->caps2
|= MMC_CAP2_CD_ACTIVE_HIGH
;
1500 mmc
->caps2
|= MMC_CAP2_RO_ACTIVE_HIGH
;
1503 /* We support these capabilities. */
1504 mmc
->caps
|= MMC_CAP_CMD23
;
1506 if (variant
->busy_detect
) {
1507 mmci_ops
.card_busy
= mmci_card_busy
;
1508 mmci_write_datactrlreg(host
, MCI_ST_DPSM_BUSYMODE
);
1509 mmc
->caps
|= MMC_CAP_WAIT_WHILE_BUSY
;
1510 mmc
->max_busy_timeout
= 0;
1513 mmc
->ops
= &mmci_ops
;
1515 /* We support these PM capabilities. */
1516 mmc
->pm_caps
|= MMC_PM_KEEP_POWER
;
1521 mmc
->max_segs
= NR_SG
;
1524 * Since only a certain number of bits are valid in the data length
1525 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1528 mmc
->max_req_size
= (1 << variant
->datalength_bits
) - 1;
1531 * Set the maximum segment size. Since we aren't doing DMA
1532 * (yet) we are only limited by the data length register.
1534 mmc
->max_seg_size
= mmc
->max_req_size
;
1537 * Block size can be up to 2048 bytes, but must be a power of two.
1539 mmc
->max_blk_size
= 1 << 11;
1542 * Limit the number of blocks transferred so that we don't overflow
1543 * the maximum request size.
1545 mmc
->max_blk_count
= mmc
->max_req_size
>> 11;
1547 spin_lock_init(&host
->lock
);
1549 writel(0, host
->base
+ MMCIMASK0
);
1550 writel(0, host
->base
+ MMCIMASK1
);
1551 writel(0xfff, host
->base
+ MMCICLEAR
);
1553 /* If DT, cd/wp gpios must be supplied through it. */
1554 if (!np
&& gpio_is_valid(plat
->gpio_cd
)) {
1555 ret
= mmc_gpio_request_cd(mmc
, plat
->gpio_cd
, 0);
1559 if (!np
&& gpio_is_valid(plat
->gpio_wp
)) {
1560 ret
= mmc_gpio_request_ro(mmc
, plat
->gpio_wp
);
1565 ret
= devm_request_irq(&dev
->dev
, dev
->irq
[0], mmci_irq
, IRQF_SHARED
,
1566 DRIVER_NAME
" (cmd)", host
);
1571 host
->singleirq
= true;
1573 ret
= devm_request_irq(&dev
->dev
, dev
->irq
[1], mmci_pio_irq
,
1574 IRQF_SHARED
, DRIVER_NAME
" (pio)", host
);
1579 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
1581 amba_set_drvdata(dev
, mmc
);
1583 dev_info(&dev
->dev
, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1584 mmc_hostname(mmc
), amba_part(dev
), amba_manf(dev
),
1585 amba_rev(dev
), (unsigned long long)dev
->res
.start
,
1586 dev
->irq
[0], dev
->irq
[1]);
1588 mmci_dma_setup(host
);
1590 pm_runtime_set_autosuspend_delay(&dev
->dev
, 50);
1591 pm_runtime_use_autosuspend(&dev
->dev
);
1592 pm_runtime_put(&dev
->dev
);
1599 clk_disable_unprepare(host
->clk
);
1605 static int mmci_remove(struct amba_device
*dev
)
1607 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
1610 struct mmci_host
*host
= mmc_priv(mmc
);
1613 * Undo pm_runtime_put() in probe. We use the _sync
1614 * version here so that we can access the primecell.
1616 pm_runtime_get_sync(&dev
->dev
);
1618 mmc_remove_host(mmc
);
1620 writel(0, host
->base
+ MMCIMASK0
);
1621 writel(0, host
->base
+ MMCIMASK1
);
1623 writel(0, host
->base
+ MMCICOMMAND
);
1624 writel(0, host
->base
+ MMCIDATACTRL
);
1626 mmci_dma_release(host
);
1627 clk_disable_unprepare(host
->clk
);
1635 static void mmci_save(struct mmci_host
*host
)
1637 unsigned long flags
;
1639 spin_lock_irqsave(&host
->lock
, flags
);
1641 writel(0, host
->base
+ MMCIMASK0
);
1642 if (host
->variant
->pwrreg_nopower
) {
1643 writel(0, host
->base
+ MMCIDATACTRL
);
1644 writel(0, host
->base
+ MMCIPOWER
);
1645 writel(0, host
->base
+ MMCICLOCK
);
1647 mmci_reg_delay(host
);
1649 spin_unlock_irqrestore(&host
->lock
, flags
);
1652 static void mmci_restore(struct mmci_host
*host
)
1654 unsigned long flags
;
1656 spin_lock_irqsave(&host
->lock
, flags
);
1658 if (host
->variant
->pwrreg_nopower
) {
1659 writel(host
->clk_reg
, host
->base
+ MMCICLOCK
);
1660 writel(host
->datactrl_reg
, host
->base
+ MMCIDATACTRL
);
1661 writel(host
->pwr_reg
, host
->base
+ MMCIPOWER
);
1663 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
1664 mmci_reg_delay(host
);
1666 spin_unlock_irqrestore(&host
->lock
, flags
);
1669 static int mmci_runtime_suspend(struct device
*dev
)
1671 struct amba_device
*adev
= to_amba_device(dev
);
1672 struct mmc_host
*mmc
= amba_get_drvdata(adev
);
1675 struct mmci_host
*host
= mmc_priv(mmc
);
1676 pinctrl_pm_select_sleep_state(dev
);
1678 clk_disable_unprepare(host
->clk
);
1684 static int mmci_runtime_resume(struct device
*dev
)
1686 struct amba_device
*adev
= to_amba_device(dev
);
1687 struct mmc_host
*mmc
= amba_get_drvdata(adev
);
1690 struct mmci_host
*host
= mmc_priv(mmc
);
1691 clk_prepare_enable(host
->clk
);
1693 pinctrl_pm_select_default_state(dev
);
1700 static const struct dev_pm_ops mmci_dev_pm_ops
= {
1701 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
1702 pm_runtime_force_resume
)
1703 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend
, mmci_runtime_resume
, NULL
)
1706 static struct amba_id mmci_ids
[] = {
1710 .data
= &variant_arm
,
1715 .data
= &variant_arm_extended_fifo
,
1720 .data
= &variant_arm_extended_fifo_hwfc
,
1725 .data
= &variant_arm
,
1727 /* ST Micro variants */
1731 .data
= &variant_u300
,
1736 .data
= &variant_nomadik
,
1741 .data
= &variant_u300
,
1746 .data
= &variant_ux500
,
1751 .data
= &variant_ux500v2
,
1756 MODULE_DEVICE_TABLE(amba
, mmci_ids
);
1758 static struct amba_driver mmci_driver
= {
1760 .name
= DRIVER_NAME
,
1761 .pm
= &mmci_dev_pm_ops
,
1763 .probe
= mmci_probe
,
1764 .remove
= mmci_remove
,
1765 .id_table
= mmci_ids
,
1768 module_amba_driver(mmci_driver
);
1770 module_param(fmax
, uint
, 0444);
1772 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1773 MODULE_LICENSE("GPL");