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mmc: mmci: add 8bit bus support in variant data
[deliverable/linux.git] / drivers / mmc / host / mmci.c
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
40
41 #include <asm/div64.h>
42 #include <asm/io.h>
43 #include <asm/sizes.h>
44
45 #include "mmci.h"
46
47 #define DRIVER_NAME "mmci-pl18x"
48
49 static unsigned int fmax = 515633;
50
51 /**
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
54 * @clkreg_enable: enable value for MMCICLOCK register
55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
56 * @datalength_bits: number of bits in the MMCIDATALENGTH register
57 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
58 * is asserted (likewise for RX)
59 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
60 * is asserted (likewise for RX)
61 * @sdio: variant supports SDIO
62 * @st_clkdiv: true if using a ST-specific clock divider algorithm
63 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
64 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
65 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
66 * register
67 * @pwrreg_powerup: power up value for MMCIPOWER register
68 * @signal_direction: input/out direction of bus signals can be indicated
69 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
70 * @busy_detect: true if busy detection on dat0 is supported
71 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
72 */
73 struct variant_data {
74 unsigned int clkreg;
75 unsigned int clkreg_enable;
76 unsigned int clkreg_8bit_bus_enable;
77 unsigned int datalength_bits;
78 unsigned int fifosize;
79 unsigned int fifohalfsize;
80 unsigned int datactrl_mask_ddrmode;
81 bool sdio;
82 bool st_clkdiv;
83 bool blksz_datactrl16;
84 bool blksz_datactrl4;
85 u32 pwrreg_powerup;
86 bool signal_direction;
87 bool pwrreg_clkgate;
88 bool busy_detect;
89 bool pwrreg_nopower;
90 };
91
92 static struct variant_data variant_arm = {
93 .fifosize = 16 * 4,
94 .fifohalfsize = 8 * 4,
95 .datalength_bits = 16,
96 .pwrreg_powerup = MCI_PWR_UP,
97 };
98
99 static struct variant_data variant_arm_extended_fifo = {
100 .fifosize = 128 * 4,
101 .fifohalfsize = 64 * 4,
102 .datalength_bits = 16,
103 .pwrreg_powerup = MCI_PWR_UP,
104 };
105
106 static struct variant_data variant_arm_extended_fifo_hwfc = {
107 .fifosize = 128 * 4,
108 .fifohalfsize = 64 * 4,
109 .clkreg_enable = MCI_ARM_HWFCEN,
110 .datalength_bits = 16,
111 .pwrreg_powerup = MCI_PWR_UP,
112 };
113
114 static struct variant_data variant_u300 = {
115 .fifosize = 16 * 4,
116 .fifohalfsize = 8 * 4,
117 .clkreg_enable = MCI_ST_U300_HWFCEN,
118 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
119 .datalength_bits = 16,
120 .sdio = true,
121 .pwrreg_powerup = MCI_PWR_ON,
122 .signal_direction = true,
123 .pwrreg_clkgate = true,
124 .pwrreg_nopower = true,
125 };
126
127 static struct variant_data variant_nomadik = {
128 .fifosize = 16 * 4,
129 .fifohalfsize = 8 * 4,
130 .clkreg = MCI_CLK_ENABLE,
131 .datalength_bits = 24,
132 .sdio = true,
133 .st_clkdiv = true,
134 .pwrreg_powerup = MCI_PWR_ON,
135 .signal_direction = true,
136 .pwrreg_clkgate = true,
137 .pwrreg_nopower = true,
138 };
139
140 static struct variant_data variant_ux500 = {
141 .fifosize = 30 * 4,
142 .fifohalfsize = 8 * 4,
143 .clkreg = MCI_CLK_ENABLE,
144 .clkreg_enable = MCI_ST_UX500_HWFCEN,
145 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
146 .datalength_bits = 24,
147 .sdio = true,
148 .st_clkdiv = true,
149 .pwrreg_powerup = MCI_PWR_ON,
150 .signal_direction = true,
151 .pwrreg_clkgate = true,
152 .busy_detect = true,
153 .pwrreg_nopower = true,
154 };
155
156 static struct variant_data variant_ux500v2 = {
157 .fifosize = 30 * 4,
158 .fifohalfsize = 8 * 4,
159 .clkreg = MCI_CLK_ENABLE,
160 .clkreg_enable = MCI_ST_UX500_HWFCEN,
161 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
162 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
163 .datalength_bits = 24,
164 .sdio = true,
165 .st_clkdiv = true,
166 .blksz_datactrl16 = true,
167 .pwrreg_powerup = MCI_PWR_ON,
168 .signal_direction = true,
169 .pwrreg_clkgate = true,
170 .busy_detect = true,
171 .pwrreg_nopower = true,
172 };
173
174 static int mmci_card_busy(struct mmc_host *mmc)
175 {
176 struct mmci_host *host = mmc_priv(mmc);
177 unsigned long flags;
178 int busy = 0;
179
180 pm_runtime_get_sync(mmc_dev(mmc));
181
182 spin_lock_irqsave(&host->lock, flags);
183 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
184 busy = 1;
185 spin_unlock_irqrestore(&host->lock, flags);
186
187 pm_runtime_mark_last_busy(mmc_dev(mmc));
188 pm_runtime_put_autosuspend(mmc_dev(mmc));
189
190 return busy;
191 }
192
193 /*
194 * Validate mmc prerequisites
195 */
196 static int mmci_validate_data(struct mmci_host *host,
197 struct mmc_data *data)
198 {
199 if (!data)
200 return 0;
201
202 if (!is_power_of_2(data->blksz)) {
203 dev_err(mmc_dev(host->mmc),
204 "unsupported block size (%d bytes)\n", data->blksz);
205 return -EINVAL;
206 }
207
208 return 0;
209 }
210
211 static void mmci_reg_delay(struct mmci_host *host)
212 {
213 /*
214 * According to the spec, at least three feedback clock cycles
215 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
216 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
217 * Worst delay time during card init is at 100 kHz => 30 us.
218 * Worst delay time when up and running is at 25 MHz => 120 ns.
219 */
220 if (host->cclk < 25000000)
221 udelay(30);
222 else
223 ndelay(120);
224 }
225
226 /*
227 * This must be called with host->lock held
228 */
229 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
230 {
231 if (host->clk_reg != clk) {
232 host->clk_reg = clk;
233 writel(clk, host->base + MMCICLOCK);
234 }
235 }
236
237 /*
238 * This must be called with host->lock held
239 */
240 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
241 {
242 if (host->pwr_reg != pwr) {
243 host->pwr_reg = pwr;
244 writel(pwr, host->base + MMCIPOWER);
245 }
246 }
247
248 /*
249 * This must be called with host->lock held
250 */
251 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
252 {
253 /* Keep ST Micro busy mode if enabled */
254 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
255
256 if (host->datactrl_reg != datactrl) {
257 host->datactrl_reg = datactrl;
258 writel(datactrl, host->base + MMCIDATACTRL);
259 }
260 }
261
262 /*
263 * This must be called with host->lock held
264 */
265 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
266 {
267 struct variant_data *variant = host->variant;
268 u32 clk = variant->clkreg;
269
270 /* Make sure cclk reflects the current calculated clock */
271 host->cclk = 0;
272
273 if (desired) {
274 if (desired >= host->mclk) {
275 clk = MCI_CLK_BYPASS;
276 if (variant->st_clkdiv)
277 clk |= MCI_ST_UX500_NEG_EDGE;
278 host->cclk = host->mclk;
279 } else if (variant->st_clkdiv) {
280 /*
281 * DB8500 TRM says f = mclk / (clkdiv + 2)
282 * => clkdiv = (mclk / f) - 2
283 * Round the divider up so we don't exceed the max
284 * frequency
285 */
286 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
287 if (clk >= 256)
288 clk = 255;
289 host->cclk = host->mclk / (clk + 2);
290 } else {
291 /*
292 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
293 * => clkdiv = mclk / (2 * f) - 1
294 */
295 clk = host->mclk / (2 * desired) - 1;
296 if (clk >= 256)
297 clk = 255;
298 host->cclk = host->mclk / (2 * (clk + 1));
299 }
300
301 clk |= variant->clkreg_enable;
302 clk |= MCI_CLK_ENABLE;
303 /* This hasn't proven to be worthwhile */
304 /* clk |= MCI_CLK_PWRSAVE; */
305 }
306
307 /* Set actual clock for debug */
308 host->mmc->actual_clock = host->cclk;
309
310 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
311 clk |= MCI_4BIT_BUS;
312 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
313 clk |= variant->clkreg_8bit_bus_enable;
314
315 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
316 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
317 clk |= MCI_ST_UX500_NEG_EDGE;
318
319 mmci_write_clkreg(host, clk);
320 }
321
322 static void
323 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
324 {
325 writel(0, host->base + MMCICOMMAND);
326
327 BUG_ON(host->data);
328
329 host->mrq = NULL;
330 host->cmd = NULL;
331
332 mmc_request_done(host->mmc, mrq);
333
334 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
335 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
336 }
337
338 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
339 {
340 void __iomem *base = host->base;
341
342 if (host->singleirq) {
343 unsigned int mask0 = readl(base + MMCIMASK0);
344
345 mask0 &= ~MCI_IRQ1MASK;
346 mask0 |= mask;
347
348 writel(mask0, base + MMCIMASK0);
349 }
350
351 writel(mask, base + MMCIMASK1);
352 }
353
354 static void mmci_stop_data(struct mmci_host *host)
355 {
356 mmci_write_datactrlreg(host, 0);
357 mmci_set_mask1(host, 0);
358 host->data = NULL;
359 }
360
361 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
362 {
363 unsigned int flags = SG_MITER_ATOMIC;
364
365 if (data->flags & MMC_DATA_READ)
366 flags |= SG_MITER_TO_SG;
367 else
368 flags |= SG_MITER_FROM_SG;
369
370 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
371 }
372
373 /*
374 * All the DMA operation mode stuff goes inside this ifdef.
375 * This assumes that you have a generic DMA device interface,
376 * no custom DMA interfaces are supported.
377 */
378 #ifdef CONFIG_DMA_ENGINE
379 static void mmci_dma_setup(struct mmci_host *host)
380 {
381 const char *rxname, *txname;
382 dma_cap_mask_t mask;
383
384 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
385 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
386
387 /* initialize pre request cookie */
388 host->next_data.cookie = 1;
389
390 /* Try to acquire a generic DMA engine slave channel */
391 dma_cap_zero(mask);
392 dma_cap_set(DMA_SLAVE, mask);
393
394 /*
395 * If only an RX channel is specified, the driver will
396 * attempt to use it bidirectionally, however if it is
397 * is specified but cannot be located, DMA will be disabled.
398 */
399 if (host->dma_rx_channel && !host->dma_tx_channel)
400 host->dma_tx_channel = host->dma_rx_channel;
401
402 if (host->dma_rx_channel)
403 rxname = dma_chan_name(host->dma_rx_channel);
404 else
405 rxname = "none";
406
407 if (host->dma_tx_channel)
408 txname = dma_chan_name(host->dma_tx_channel);
409 else
410 txname = "none";
411
412 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
413 rxname, txname);
414
415 /*
416 * Limit the maximum segment size in any SG entry according to
417 * the parameters of the DMA engine device.
418 */
419 if (host->dma_tx_channel) {
420 struct device *dev = host->dma_tx_channel->device->dev;
421 unsigned int max_seg_size = dma_get_max_seg_size(dev);
422
423 if (max_seg_size < host->mmc->max_seg_size)
424 host->mmc->max_seg_size = max_seg_size;
425 }
426 if (host->dma_rx_channel) {
427 struct device *dev = host->dma_rx_channel->device->dev;
428 unsigned int max_seg_size = dma_get_max_seg_size(dev);
429
430 if (max_seg_size < host->mmc->max_seg_size)
431 host->mmc->max_seg_size = max_seg_size;
432 }
433 }
434
435 /*
436 * This is used in or so inline it
437 * so it can be discarded.
438 */
439 static inline void mmci_dma_release(struct mmci_host *host)
440 {
441 if (host->dma_rx_channel)
442 dma_release_channel(host->dma_rx_channel);
443 if (host->dma_tx_channel)
444 dma_release_channel(host->dma_tx_channel);
445 host->dma_rx_channel = host->dma_tx_channel = NULL;
446 }
447
448 static void mmci_dma_data_error(struct mmci_host *host)
449 {
450 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
451 dmaengine_terminate_all(host->dma_current);
452 host->dma_current = NULL;
453 host->dma_desc_current = NULL;
454 host->data->host_cookie = 0;
455 }
456
457 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
458 {
459 struct dma_chan *chan;
460 enum dma_data_direction dir;
461
462 if (data->flags & MMC_DATA_READ) {
463 dir = DMA_FROM_DEVICE;
464 chan = host->dma_rx_channel;
465 } else {
466 dir = DMA_TO_DEVICE;
467 chan = host->dma_tx_channel;
468 }
469
470 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
471 }
472
473 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
474 {
475 u32 status;
476 int i;
477
478 /* Wait up to 1ms for the DMA to complete */
479 for (i = 0; ; i++) {
480 status = readl(host->base + MMCISTATUS);
481 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
482 break;
483 udelay(10);
484 }
485
486 /*
487 * Check to see whether we still have some data left in the FIFO -
488 * this catches DMA controllers which are unable to monitor the
489 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
490 * contiguous buffers. On TX, we'll get a FIFO underrun error.
491 */
492 if (status & MCI_RXDATAAVLBLMASK) {
493 mmci_dma_data_error(host);
494 if (!data->error)
495 data->error = -EIO;
496 }
497
498 if (!data->host_cookie)
499 mmci_dma_unmap(host, data);
500
501 /*
502 * Use of DMA with scatter-gather is impossible.
503 * Give up with DMA and switch back to PIO mode.
504 */
505 if (status & MCI_RXDATAAVLBLMASK) {
506 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
507 mmci_dma_release(host);
508 }
509
510 host->dma_current = NULL;
511 host->dma_desc_current = NULL;
512 }
513
514 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
515 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
516 struct dma_chan **dma_chan,
517 struct dma_async_tx_descriptor **dma_desc)
518 {
519 struct variant_data *variant = host->variant;
520 struct dma_slave_config conf = {
521 .src_addr = host->phybase + MMCIFIFO,
522 .dst_addr = host->phybase + MMCIFIFO,
523 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
524 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
525 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
526 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
527 .device_fc = false,
528 };
529 struct dma_chan *chan;
530 struct dma_device *device;
531 struct dma_async_tx_descriptor *desc;
532 enum dma_data_direction buffer_dirn;
533 int nr_sg;
534
535 if (data->flags & MMC_DATA_READ) {
536 conf.direction = DMA_DEV_TO_MEM;
537 buffer_dirn = DMA_FROM_DEVICE;
538 chan = host->dma_rx_channel;
539 } else {
540 conf.direction = DMA_MEM_TO_DEV;
541 buffer_dirn = DMA_TO_DEVICE;
542 chan = host->dma_tx_channel;
543 }
544
545 /* If there's no DMA channel, fall back to PIO */
546 if (!chan)
547 return -EINVAL;
548
549 /* If less than or equal to the fifo size, don't bother with DMA */
550 if (data->blksz * data->blocks <= variant->fifosize)
551 return -EINVAL;
552
553 device = chan->device;
554 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
555 if (nr_sg == 0)
556 return -EINVAL;
557
558 dmaengine_slave_config(chan, &conf);
559 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
560 conf.direction, DMA_CTRL_ACK);
561 if (!desc)
562 goto unmap_exit;
563
564 *dma_chan = chan;
565 *dma_desc = desc;
566
567 return 0;
568
569 unmap_exit:
570 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
571 return -ENOMEM;
572 }
573
574 static inline int mmci_dma_prep_data(struct mmci_host *host,
575 struct mmc_data *data)
576 {
577 /* Check if next job is already prepared. */
578 if (host->dma_current && host->dma_desc_current)
579 return 0;
580
581 /* No job were prepared thus do it now. */
582 return __mmci_dma_prep_data(host, data, &host->dma_current,
583 &host->dma_desc_current);
584 }
585
586 static inline int mmci_dma_prep_next(struct mmci_host *host,
587 struct mmc_data *data)
588 {
589 struct mmci_host_next *nd = &host->next_data;
590 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
591 }
592
593 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
594 {
595 int ret;
596 struct mmc_data *data = host->data;
597
598 ret = mmci_dma_prep_data(host, host->data);
599 if (ret)
600 return ret;
601
602 /* Okay, go for it. */
603 dev_vdbg(mmc_dev(host->mmc),
604 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
605 data->sg_len, data->blksz, data->blocks, data->flags);
606 dmaengine_submit(host->dma_desc_current);
607 dma_async_issue_pending(host->dma_current);
608
609 datactrl |= MCI_DPSM_DMAENABLE;
610
611 /* Trigger the DMA transfer */
612 mmci_write_datactrlreg(host, datactrl);
613
614 /*
615 * Let the MMCI say when the data is ended and it's time
616 * to fire next DMA request. When that happens, MMCI will
617 * call mmci_data_end()
618 */
619 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
620 host->base + MMCIMASK0);
621 return 0;
622 }
623
624 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
625 {
626 struct mmci_host_next *next = &host->next_data;
627
628 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
629 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
630
631 host->dma_desc_current = next->dma_desc;
632 host->dma_current = next->dma_chan;
633 next->dma_desc = NULL;
634 next->dma_chan = NULL;
635 }
636
637 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
638 bool is_first_req)
639 {
640 struct mmci_host *host = mmc_priv(mmc);
641 struct mmc_data *data = mrq->data;
642 struct mmci_host_next *nd = &host->next_data;
643
644 if (!data)
645 return;
646
647 BUG_ON(data->host_cookie);
648
649 if (mmci_validate_data(host, data))
650 return;
651
652 if (!mmci_dma_prep_next(host, data))
653 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
654 }
655
656 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
657 int err)
658 {
659 struct mmci_host *host = mmc_priv(mmc);
660 struct mmc_data *data = mrq->data;
661
662 if (!data || !data->host_cookie)
663 return;
664
665 mmci_dma_unmap(host, data);
666
667 if (err) {
668 struct mmci_host_next *next = &host->next_data;
669 struct dma_chan *chan;
670 if (data->flags & MMC_DATA_READ)
671 chan = host->dma_rx_channel;
672 else
673 chan = host->dma_tx_channel;
674 dmaengine_terminate_all(chan);
675
676 next->dma_desc = NULL;
677 next->dma_chan = NULL;
678 }
679 }
680
681 #else
682 /* Blank functions if the DMA engine is not available */
683 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
684 {
685 }
686 static inline void mmci_dma_setup(struct mmci_host *host)
687 {
688 }
689
690 static inline void mmci_dma_release(struct mmci_host *host)
691 {
692 }
693
694 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
695 {
696 }
697
698 static inline void mmci_dma_finalize(struct mmci_host *host,
699 struct mmc_data *data)
700 {
701 }
702
703 static inline void mmci_dma_data_error(struct mmci_host *host)
704 {
705 }
706
707 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
708 {
709 return -ENOSYS;
710 }
711
712 #define mmci_pre_request NULL
713 #define mmci_post_request NULL
714
715 #endif
716
717 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
718 {
719 struct variant_data *variant = host->variant;
720 unsigned int datactrl, timeout, irqmask;
721 unsigned long long clks;
722 void __iomem *base;
723 int blksz_bits;
724
725 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
726 data->blksz, data->blocks, data->flags);
727
728 host->data = data;
729 host->size = data->blksz * data->blocks;
730 data->bytes_xfered = 0;
731
732 clks = (unsigned long long)data->timeout_ns * host->cclk;
733 do_div(clks, NSEC_PER_SEC);
734
735 timeout = data->timeout_clks + (unsigned int)clks;
736
737 base = host->base;
738 writel(timeout, base + MMCIDATATIMER);
739 writel(host->size, base + MMCIDATALENGTH);
740
741 blksz_bits = ffs(data->blksz) - 1;
742 BUG_ON(1 << blksz_bits != data->blksz);
743
744 if (variant->blksz_datactrl16)
745 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
746 else if (variant->blksz_datactrl4)
747 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
748 else
749 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
750
751 if (data->flags & MMC_DATA_READ)
752 datactrl |= MCI_DPSM_DIRECTION;
753
754 /* The ST Micro variants has a special bit to enable SDIO */
755 if (variant->sdio && host->mmc->card)
756 if (mmc_card_sdio(host->mmc->card)) {
757 /*
758 * The ST Micro variants has a special bit
759 * to enable SDIO.
760 */
761 u32 clk;
762
763 datactrl |= MCI_ST_DPSM_SDIOEN;
764
765 /*
766 * The ST Micro variant for SDIO small write transfers
767 * needs to have clock H/W flow control disabled,
768 * otherwise the transfer will not start. The threshold
769 * depends on the rate of MCLK.
770 */
771 if (data->flags & MMC_DATA_WRITE &&
772 (host->size < 8 ||
773 (host->size <= 8 && host->mclk > 50000000)))
774 clk = host->clk_reg & ~variant->clkreg_enable;
775 else
776 clk = host->clk_reg | variant->clkreg_enable;
777
778 mmci_write_clkreg(host, clk);
779 }
780
781 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
782 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
783 datactrl |= variant->datactrl_mask_ddrmode;
784
785 /*
786 * Attempt to use DMA operation mode, if this
787 * should fail, fall back to PIO mode
788 */
789 if (!mmci_dma_start_data(host, datactrl))
790 return;
791
792 /* IRQ mode, map the SG list for CPU reading/writing */
793 mmci_init_sg(host, data);
794
795 if (data->flags & MMC_DATA_READ) {
796 irqmask = MCI_RXFIFOHALFFULLMASK;
797
798 /*
799 * If we have less than the fifo 'half-full' threshold to
800 * transfer, trigger a PIO interrupt as soon as any data
801 * is available.
802 */
803 if (host->size < variant->fifohalfsize)
804 irqmask |= MCI_RXDATAAVLBLMASK;
805 } else {
806 /*
807 * We don't actually need to include "FIFO empty" here
808 * since its implicit in "FIFO half empty".
809 */
810 irqmask = MCI_TXFIFOHALFEMPTYMASK;
811 }
812
813 mmci_write_datactrlreg(host, datactrl);
814 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
815 mmci_set_mask1(host, irqmask);
816 }
817
818 static void
819 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
820 {
821 void __iomem *base = host->base;
822
823 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
824 cmd->opcode, cmd->arg, cmd->flags);
825
826 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
827 writel(0, base + MMCICOMMAND);
828 mmci_reg_delay(host);
829 }
830
831 c |= cmd->opcode | MCI_CPSM_ENABLE;
832 if (cmd->flags & MMC_RSP_PRESENT) {
833 if (cmd->flags & MMC_RSP_136)
834 c |= MCI_CPSM_LONGRSP;
835 c |= MCI_CPSM_RESPONSE;
836 }
837 if (/*interrupt*/0)
838 c |= MCI_CPSM_INTERRUPT;
839
840 host->cmd = cmd;
841
842 writel(cmd->arg, base + MMCIARGUMENT);
843 writel(c, base + MMCICOMMAND);
844 }
845
846 static void
847 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
848 unsigned int status)
849 {
850 /* First check for errors */
851 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
852 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
853 u32 remain, success;
854
855 /* Terminate the DMA transfer */
856 if (dma_inprogress(host)) {
857 mmci_dma_data_error(host);
858 mmci_dma_unmap(host, data);
859 }
860
861 /*
862 * Calculate how far we are into the transfer. Note that
863 * the data counter gives the number of bytes transferred
864 * on the MMC bus, not on the host side. On reads, this
865 * can be as much as a FIFO-worth of data ahead. This
866 * matters for FIFO overruns only.
867 */
868 remain = readl(host->base + MMCIDATACNT);
869 success = data->blksz * data->blocks - remain;
870
871 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
872 status, success);
873 if (status & MCI_DATACRCFAIL) {
874 /* Last block was not successful */
875 success -= 1;
876 data->error = -EILSEQ;
877 } else if (status & MCI_DATATIMEOUT) {
878 data->error = -ETIMEDOUT;
879 } else if (status & MCI_STARTBITERR) {
880 data->error = -ECOMM;
881 } else if (status & MCI_TXUNDERRUN) {
882 data->error = -EIO;
883 } else if (status & MCI_RXOVERRUN) {
884 if (success > host->variant->fifosize)
885 success -= host->variant->fifosize;
886 else
887 success = 0;
888 data->error = -EIO;
889 }
890 data->bytes_xfered = round_down(success, data->blksz);
891 }
892
893 if (status & MCI_DATABLOCKEND)
894 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
895
896 if (status & MCI_DATAEND || data->error) {
897 if (dma_inprogress(host))
898 mmci_dma_finalize(host, data);
899 mmci_stop_data(host);
900
901 if (!data->error)
902 /* The error clause is handled above, success! */
903 data->bytes_xfered = data->blksz * data->blocks;
904
905 if (!data->stop || host->mrq->sbc) {
906 mmci_request_end(host, data->mrq);
907 } else {
908 mmci_start_command(host, data->stop, 0);
909 }
910 }
911 }
912
913 static void
914 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
915 unsigned int status)
916 {
917 void __iomem *base = host->base;
918 bool sbc = (cmd == host->mrq->sbc);
919 bool busy_resp = host->variant->busy_detect &&
920 (cmd->flags & MMC_RSP_BUSY);
921
922 /* Check if we need to wait for busy completion. */
923 if (host->busy_status && (status & MCI_ST_CARDBUSY))
924 return;
925
926 /* Enable busy completion if needed and supported. */
927 if (!host->busy_status && busy_resp &&
928 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
929 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
930 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
931 base + MMCIMASK0);
932 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
933 return;
934 }
935
936 /* At busy completion, mask the IRQ and complete the request. */
937 if (host->busy_status) {
938 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
939 base + MMCIMASK0);
940 host->busy_status = 0;
941 }
942
943 host->cmd = NULL;
944
945 if (status & MCI_CMDTIMEOUT) {
946 cmd->error = -ETIMEDOUT;
947 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
948 cmd->error = -EILSEQ;
949 } else {
950 cmd->resp[0] = readl(base + MMCIRESPONSE0);
951 cmd->resp[1] = readl(base + MMCIRESPONSE1);
952 cmd->resp[2] = readl(base + MMCIRESPONSE2);
953 cmd->resp[3] = readl(base + MMCIRESPONSE3);
954 }
955
956 if ((!sbc && !cmd->data) || cmd->error) {
957 if (host->data) {
958 /* Terminate the DMA transfer */
959 if (dma_inprogress(host)) {
960 mmci_dma_data_error(host);
961 mmci_dma_unmap(host, host->data);
962 }
963 mmci_stop_data(host);
964 }
965 mmci_request_end(host, host->mrq);
966 } else if (sbc) {
967 mmci_start_command(host, host->mrq->cmd, 0);
968 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
969 mmci_start_data(host, cmd->data);
970 }
971 }
972
973 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
974 {
975 void __iomem *base = host->base;
976 char *ptr = buffer;
977 u32 status;
978 int host_remain = host->size;
979
980 do {
981 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
982
983 if (count > remain)
984 count = remain;
985
986 if (count <= 0)
987 break;
988
989 /*
990 * SDIO especially may want to send something that is
991 * not divisible by 4 (as opposed to card sectors
992 * etc). Therefore make sure to always read the last bytes
993 * while only doing full 32-bit reads towards the FIFO.
994 */
995 if (unlikely(count & 0x3)) {
996 if (count < 4) {
997 unsigned char buf[4];
998 ioread32_rep(base + MMCIFIFO, buf, 1);
999 memcpy(ptr, buf, count);
1000 } else {
1001 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1002 count &= ~0x3;
1003 }
1004 } else {
1005 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1006 }
1007
1008 ptr += count;
1009 remain -= count;
1010 host_remain -= count;
1011
1012 if (remain == 0)
1013 break;
1014
1015 status = readl(base + MMCISTATUS);
1016 } while (status & MCI_RXDATAAVLBL);
1017
1018 return ptr - buffer;
1019 }
1020
1021 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1022 {
1023 struct variant_data *variant = host->variant;
1024 void __iomem *base = host->base;
1025 char *ptr = buffer;
1026
1027 do {
1028 unsigned int count, maxcnt;
1029
1030 maxcnt = status & MCI_TXFIFOEMPTY ?
1031 variant->fifosize : variant->fifohalfsize;
1032 count = min(remain, maxcnt);
1033
1034 /*
1035 * SDIO especially may want to send something that is
1036 * not divisible by 4 (as opposed to card sectors
1037 * etc), and the FIFO only accept full 32-bit writes.
1038 * So compensate by adding +3 on the count, a single
1039 * byte become a 32bit write, 7 bytes will be two
1040 * 32bit writes etc.
1041 */
1042 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1043
1044 ptr += count;
1045 remain -= count;
1046
1047 if (remain == 0)
1048 break;
1049
1050 status = readl(base + MMCISTATUS);
1051 } while (status & MCI_TXFIFOHALFEMPTY);
1052
1053 return ptr - buffer;
1054 }
1055
1056 /*
1057 * PIO data transfer IRQ handler.
1058 */
1059 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1060 {
1061 struct mmci_host *host = dev_id;
1062 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1063 struct variant_data *variant = host->variant;
1064 void __iomem *base = host->base;
1065 unsigned long flags;
1066 u32 status;
1067
1068 status = readl(base + MMCISTATUS);
1069
1070 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1071
1072 local_irq_save(flags);
1073
1074 do {
1075 unsigned int remain, len;
1076 char *buffer;
1077
1078 /*
1079 * For write, we only need to test the half-empty flag
1080 * here - if the FIFO is completely empty, then by
1081 * definition it is more than half empty.
1082 *
1083 * For read, check for data available.
1084 */
1085 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1086 break;
1087
1088 if (!sg_miter_next(sg_miter))
1089 break;
1090
1091 buffer = sg_miter->addr;
1092 remain = sg_miter->length;
1093
1094 len = 0;
1095 if (status & MCI_RXACTIVE)
1096 len = mmci_pio_read(host, buffer, remain);
1097 if (status & MCI_TXACTIVE)
1098 len = mmci_pio_write(host, buffer, remain, status);
1099
1100 sg_miter->consumed = len;
1101
1102 host->size -= len;
1103 remain -= len;
1104
1105 if (remain)
1106 break;
1107
1108 status = readl(base + MMCISTATUS);
1109 } while (1);
1110
1111 sg_miter_stop(sg_miter);
1112
1113 local_irq_restore(flags);
1114
1115 /*
1116 * If we have less than the fifo 'half-full' threshold to transfer,
1117 * trigger a PIO interrupt as soon as any data is available.
1118 */
1119 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1120 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1121
1122 /*
1123 * If we run out of data, disable the data IRQs; this
1124 * prevents a race where the FIFO becomes empty before
1125 * the chip itself has disabled the data path, and
1126 * stops us racing with our data end IRQ.
1127 */
1128 if (host->size == 0) {
1129 mmci_set_mask1(host, 0);
1130 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1131 }
1132
1133 return IRQ_HANDLED;
1134 }
1135
1136 /*
1137 * Handle completion of command and data transfers.
1138 */
1139 static irqreturn_t mmci_irq(int irq, void *dev_id)
1140 {
1141 struct mmci_host *host = dev_id;
1142 u32 status;
1143 int ret = 0;
1144
1145 spin_lock(&host->lock);
1146
1147 do {
1148 struct mmc_command *cmd;
1149 struct mmc_data *data;
1150
1151 status = readl(host->base + MMCISTATUS);
1152
1153 if (host->singleirq) {
1154 if (status & readl(host->base + MMCIMASK1))
1155 mmci_pio_irq(irq, dev_id);
1156
1157 status &= ~MCI_IRQ1MASK;
1158 }
1159
1160 /*
1161 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1162 * enabled) since the HW seems to be triggering the IRQ on both
1163 * edges while monitoring DAT0 for busy completion.
1164 */
1165 status &= readl(host->base + MMCIMASK0);
1166 writel(status, host->base + MMCICLEAR);
1167
1168 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1169
1170 cmd = host->cmd;
1171 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
1172 MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1173 mmci_cmd_irq(host, cmd, status);
1174
1175 data = host->data;
1176 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1177 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1178 MCI_DATABLOCKEND) && data)
1179 mmci_data_irq(host, data, status);
1180
1181 /* Don't poll for busy completion in irq context. */
1182 if (host->busy_status)
1183 status &= ~MCI_ST_CARDBUSY;
1184
1185 ret = 1;
1186 } while (status);
1187
1188 spin_unlock(&host->lock);
1189
1190 return IRQ_RETVAL(ret);
1191 }
1192
1193 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1194 {
1195 struct mmci_host *host = mmc_priv(mmc);
1196 unsigned long flags;
1197
1198 WARN_ON(host->mrq != NULL);
1199
1200 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1201 if (mrq->cmd->error) {
1202 mmc_request_done(mmc, mrq);
1203 return;
1204 }
1205
1206 pm_runtime_get_sync(mmc_dev(mmc));
1207
1208 spin_lock_irqsave(&host->lock, flags);
1209
1210 host->mrq = mrq;
1211
1212 if (mrq->data)
1213 mmci_get_next_data(host, mrq->data);
1214
1215 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1216 mmci_start_data(host, mrq->data);
1217
1218 if (mrq->sbc)
1219 mmci_start_command(host, mrq->sbc, 0);
1220 else
1221 mmci_start_command(host, mrq->cmd, 0);
1222
1223 spin_unlock_irqrestore(&host->lock, flags);
1224 }
1225
1226 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1227 {
1228 struct mmci_host *host = mmc_priv(mmc);
1229 struct variant_data *variant = host->variant;
1230 u32 pwr = 0;
1231 unsigned long flags;
1232 int ret;
1233
1234 pm_runtime_get_sync(mmc_dev(mmc));
1235
1236 if (host->plat->ios_handler &&
1237 host->plat->ios_handler(mmc_dev(mmc), ios))
1238 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1239
1240 switch (ios->power_mode) {
1241 case MMC_POWER_OFF:
1242 if (!IS_ERR(mmc->supply.vmmc))
1243 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1244
1245 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1246 regulator_disable(mmc->supply.vqmmc);
1247 host->vqmmc_enabled = false;
1248 }
1249
1250 break;
1251 case MMC_POWER_UP:
1252 if (!IS_ERR(mmc->supply.vmmc))
1253 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1254
1255 /*
1256 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1257 * and instead uses MCI_PWR_ON so apply whatever value is
1258 * configured in the variant data.
1259 */
1260 pwr |= variant->pwrreg_powerup;
1261
1262 break;
1263 case MMC_POWER_ON:
1264 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1265 ret = regulator_enable(mmc->supply.vqmmc);
1266 if (ret < 0)
1267 dev_err(mmc_dev(mmc),
1268 "failed to enable vqmmc regulator\n");
1269 else
1270 host->vqmmc_enabled = true;
1271 }
1272
1273 pwr |= MCI_PWR_ON;
1274 break;
1275 }
1276
1277 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1278 /*
1279 * The ST Micro variant has some additional bits
1280 * indicating signal direction for the signals in
1281 * the SD/MMC bus and feedback-clock usage.
1282 */
1283 pwr |= host->pwr_reg_add;
1284
1285 if (ios->bus_width == MMC_BUS_WIDTH_4)
1286 pwr &= ~MCI_ST_DATA74DIREN;
1287 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1288 pwr &= (~MCI_ST_DATA74DIREN &
1289 ~MCI_ST_DATA31DIREN &
1290 ~MCI_ST_DATA2DIREN);
1291 }
1292
1293 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1294 if (host->hw_designer != AMBA_VENDOR_ST)
1295 pwr |= MCI_ROD;
1296 else {
1297 /*
1298 * The ST Micro variant use the ROD bit for something
1299 * else and only has OD (Open Drain).
1300 */
1301 pwr |= MCI_OD;
1302 }
1303 }
1304
1305 /*
1306 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1307 * gating the clock, the MCI_PWR_ON bit is cleared.
1308 */
1309 if (!ios->clock && variant->pwrreg_clkgate)
1310 pwr &= ~MCI_PWR_ON;
1311
1312 spin_lock_irqsave(&host->lock, flags);
1313
1314 mmci_set_clkreg(host, ios->clock);
1315 mmci_write_pwrreg(host, pwr);
1316 mmci_reg_delay(host);
1317
1318 spin_unlock_irqrestore(&host->lock, flags);
1319
1320 pm_runtime_mark_last_busy(mmc_dev(mmc));
1321 pm_runtime_put_autosuspend(mmc_dev(mmc));
1322 }
1323
1324 static int mmci_get_cd(struct mmc_host *mmc)
1325 {
1326 struct mmci_host *host = mmc_priv(mmc);
1327 struct mmci_platform_data *plat = host->plat;
1328 unsigned int status = mmc_gpio_get_cd(mmc);
1329
1330 if (status == -ENOSYS) {
1331 if (!plat->status)
1332 return 1; /* Assume always present */
1333
1334 status = plat->status(mmc_dev(host->mmc));
1335 }
1336 return status;
1337 }
1338
1339 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1340 {
1341 int ret = 0;
1342
1343 if (!IS_ERR(mmc->supply.vqmmc)) {
1344
1345 pm_runtime_get_sync(mmc_dev(mmc));
1346
1347 switch (ios->signal_voltage) {
1348 case MMC_SIGNAL_VOLTAGE_330:
1349 ret = regulator_set_voltage(mmc->supply.vqmmc,
1350 2700000, 3600000);
1351 break;
1352 case MMC_SIGNAL_VOLTAGE_180:
1353 ret = regulator_set_voltage(mmc->supply.vqmmc,
1354 1700000, 1950000);
1355 break;
1356 case MMC_SIGNAL_VOLTAGE_120:
1357 ret = regulator_set_voltage(mmc->supply.vqmmc,
1358 1100000, 1300000);
1359 break;
1360 }
1361
1362 if (ret)
1363 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1364
1365 pm_runtime_mark_last_busy(mmc_dev(mmc));
1366 pm_runtime_put_autosuspend(mmc_dev(mmc));
1367 }
1368
1369 return ret;
1370 }
1371
1372 static struct mmc_host_ops mmci_ops = {
1373 .request = mmci_request,
1374 .pre_req = mmci_pre_request,
1375 .post_req = mmci_post_request,
1376 .set_ios = mmci_set_ios,
1377 .get_ro = mmc_gpio_get_ro,
1378 .get_cd = mmci_get_cd,
1379 .start_signal_voltage_switch = mmci_sig_volt_switch,
1380 };
1381
1382 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1383 {
1384 struct mmci_host *host = mmc_priv(mmc);
1385 int ret = mmc_of_parse(mmc);
1386
1387 if (ret)
1388 return ret;
1389
1390 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1391 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1392 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1393 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1394 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1395 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1396 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1397 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1398 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1399 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1400 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1401 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1402
1403 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1404 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1405 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1406 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1407
1408 return 0;
1409 }
1410
1411 static int mmci_probe(struct amba_device *dev,
1412 const struct amba_id *id)
1413 {
1414 struct mmci_platform_data *plat = dev->dev.platform_data;
1415 struct device_node *np = dev->dev.of_node;
1416 struct variant_data *variant = id->data;
1417 struct mmci_host *host;
1418 struct mmc_host *mmc;
1419 int ret;
1420
1421 /* Must have platform data or Device Tree. */
1422 if (!plat && !np) {
1423 dev_err(&dev->dev, "No plat data or DT found\n");
1424 return -EINVAL;
1425 }
1426
1427 if (!plat) {
1428 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1429 if (!plat)
1430 return -ENOMEM;
1431 }
1432
1433 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1434 if (!mmc)
1435 return -ENOMEM;
1436
1437 ret = mmci_of_parse(np, mmc);
1438 if (ret)
1439 goto host_free;
1440
1441 host = mmc_priv(mmc);
1442 host->mmc = mmc;
1443
1444 host->hw_designer = amba_manf(dev);
1445 host->hw_revision = amba_rev(dev);
1446 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1447 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1448
1449 host->clk = devm_clk_get(&dev->dev, NULL);
1450 if (IS_ERR(host->clk)) {
1451 ret = PTR_ERR(host->clk);
1452 goto host_free;
1453 }
1454
1455 ret = clk_prepare_enable(host->clk);
1456 if (ret)
1457 goto host_free;
1458
1459 host->plat = plat;
1460 host->variant = variant;
1461 host->mclk = clk_get_rate(host->clk);
1462 /*
1463 * According to the spec, mclk is max 100 MHz,
1464 * so we try to adjust the clock down to this,
1465 * (if possible).
1466 */
1467 if (host->mclk > 100000000) {
1468 ret = clk_set_rate(host->clk, 100000000);
1469 if (ret < 0)
1470 goto clk_disable;
1471 host->mclk = clk_get_rate(host->clk);
1472 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1473 host->mclk);
1474 }
1475
1476 host->phybase = dev->res.start;
1477 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1478 if (IS_ERR(host->base)) {
1479 ret = PTR_ERR(host->base);
1480 goto clk_disable;
1481 }
1482
1483 /*
1484 * The ARM and ST versions of the block have slightly different
1485 * clock divider equations which means that the minimum divider
1486 * differs too.
1487 */
1488 if (variant->st_clkdiv)
1489 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1490 else
1491 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1492 /*
1493 * If no maximum operating frequency is supplied, fall back to use
1494 * the module parameter, which has a (low) default value in case it
1495 * is not specified. Either value must not exceed the clock rate into
1496 * the block, of course.
1497 */
1498 if (mmc->f_max)
1499 mmc->f_max = min(host->mclk, mmc->f_max);
1500 else
1501 mmc->f_max = min(host->mclk, fmax);
1502 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1503
1504 /* Get regulators and the supported OCR mask */
1505 mmc_regulator_get_supply(mmc);
1506 if (!mmc->ocr_avail)
1507 mmc->ocr_avail = plat->ocr_mask;
1508 else if (plat->ocr_mask)
1509 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1510
1511 /* DT takes precedence over platform data. */
1512 if (!np) {
1513 if (!plat->cd_invert)
1514 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1515 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1516 }
1517
1518 /* We support these capabilities. */
1519 mmc->caps |= MMC_CAP_CMD23;
1520
1521 if (variant->busy_detect) {
1522 mmci_ops.card_busy = mmci_card_busy;
1523 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1524 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1525 mmc->max_busy_timeout = 0;
1526 }
1527
1528 mmc->ops = &mmci_ops;
1529
1530 /* We support these PM capabilities. */
1531 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1532
1533 /*
1534 * We can do SGIO
1535 */
1536 mmc->max_segs = NR_SG;
1537
1538 /*
1539 * Since only a certain number of bits are valid in the data length
1540 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1541 * single request.
1542 */
1543 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1544
1545 /*
1546 * Set the maximum segment size. Since we aren't doing DMA
1547 * (yet) we are only limited by the data length register.
1548 */
1549 mmc->max_seg_size = mmc->max_req_size;
1550
1551 /*
1552 * Block size can be up to 2048 bytes, but must be a power of two.
1553 */
1554 mmc->max_blk_size = 1 << 11;
1555
1556 /*
1557 * Limit the number of blocks transferred so that we don't overflow
1558 * the maximum request size.
1559 */
1560 mmc->max_blk_count = mmc->max_req_size >> 11;
1561
1562 spin_lock_init(&host->lock);
1563
1564 writel(0, host->base + MMCIMASK0);
1565 writel(0, host->base + MMCIMASK1);
1566 writel(0xfff, host->base + MMCICLEAR);
1567
1568 /* If DT, cd/wp gpios must be supplied through it. */
1569 if (!np && gpio_is_valid(plat->gpio_cd)) {
1570 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1571 if (ret)
1572 goto clk_disable;
1573 }
1574 if (!np && gpio_is_valid(plat->gpio_wp)) {
1575 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1576 if (ret)
1577 goto clk_disable;
1578 }
1579
1580 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1581 DRIVER_NAME " (cmd)", host);
1582 if (ret)
1583 goto clk_disable;
1584
1585 if (!dev->irq[1])
1586 host->singleirq = true;
1587 else {
1588 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1589 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1590 if (ret)
1591 goto clk_disable;
1592 }
1593
1594 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1595
1596 amba_set_drvdata(dev, mmc);
1597
1598 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1599 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1600 amba_rev(dev), (unsigned long long)dev->res.start,
1601 dev->irq[0], dev->irq[1]);
1602
1603 mmci_dma_setup(host);
1604
1605 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1606 pm_runtime_use_autosuspend(&dev->dev);
1607 pm_runtime_put(&dev->dev);
1608
1609 mmc_add_host(mmc);
1610
1611 return 0;
1612
1613 clk_disable:
1614 clk_disable_unprepare(host->clk);
1615 host_free:
1616 mmc_free_host(mmc);
1617 return ret;
1618 }
1619
1620 static int mmci_remove(struct amba_device *dev)
1621 {
1622 struct mmc_host *mmc = amba_get_drvdata(dev);
1623
1624 if (mmc) {
1625 struct mmci_host *host = mmc_priv(mmc);
1626
1627 /*
1628 * Undo pm_runtime_put() in probe. We use the _sync
1629 * version here so that we can access the primecell.
1630 */
1631 pm_runtime_get_sync(&dev->dev);
1632
1633 mmc_remove_host(mmc);
1634
1635 writel(0, host->base + MMCIMASK0);
1636 writel(0, host->base + MMCIMASK1);
1637
1638 writel(0, host->base + MMCICOMMAND);
1639 writel(0, host->base + MMCIDATACTRL);
1640
1641 mmci_dma_release(host);
1642 clk_disable_unprepare(host->clk);
1643 mmc_free_host(mmc);
1644 }
1645
1646 return 0;
1647 }
1648
1649 #ifdef CONFIG_PM
1650 static void mmci_save(struct mmci_host *host)
1651 {
1652 unsigned long flags;
1653
1654 spin_lock_irqsave(&host->lock, flags);
1655
1656 writel(0, host->base + MMCIMASK0);
1657 if (host->variant->pwrreg_nopower) {
1658 writel(0, host->base + MMCIDATACTRL);
1659 writel(0, host->base + MMCIPOWER);
1660 writel(0, host->base + MMCICLOCK);
1661 }
1662 mmci_reg_delay(host);
1663
1664 spin_unlock_irqrestore(&host->lock, flags);
1665 }
1666
1667 static void mmci_restore(struct mmci_host *host)
1668 {
1669 unsigned long flags;
1670
1671 spin_lock_irqsave(&host->lock, flags);
1672
1673 if (host->variant->pwrreg_nopower) {
1674 writel(host->clk_reg, host->base + MMCICLOCK);
1675 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1676 writel(host->pwr_reg, host->base + MMCIPOWER);
1677 }
1678 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1679 mmci_reg_delay(host);
1680
1681 spin_unlock_irqrestore(&host->lock, flags);
1682 }
1683
1684 static int mmci_runtime_suspend(struct device *dev)
1685 {
1686 struct amba_device *adev = to_amba_device(dev);
1687 struct mmc_host *mmc = amba_get_drvdata(adev);
1688
1689 if (mmc) {
1690 struct mmci_host *host = mmc_priv(mmc);
1691 pinctrl_pm_select_sleep_state(dev);
1692 mmci_save(host);
1693 clk_disable_unprepare(host->clk);
1694 }
1695
1696 return 0;
1697 }
1698
1699 static int mmci_runtime_resume(struct device *dev)
1700 {
1701 struct amba_device *adev = to_amba_device(dev);
1702 struct mmc_host *mmc = amba_get_drvdata(adev);
1703
1704 if (mmc) {
1705 struct mmci_host *host = mmc_priv(mmc);
1706 clk_prepare_enable(host->clk);
1707 mmci_restore(host);
1708 pinctrl_pm_select_default_state(dev);
1709 }
1710
1711 return 0;
1712 }
1713 #endif
1714
1715 static const struct dev_pm_ops mmci_dev_pm_ops = {
1716 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1717 pm_runtime_force_resume)
1718 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1719 };
1720
1721 static struct amba_id mmci_ids[] = {
1722 {
1723 .id = 0x00041180,
1724 .mask = 0xff0fffff,
1725 .data = &variant_arm,
1726 },
1727 {
1728 .id = 0x01041180,
1729 .mask = 0xff0fffff,
1730 .data = &variant_arm_extended_fifo,
1731 },
1732 {
1733 .id = 0x02041180,
1734 .mask = 0xff0fffff,
1735 .data = &variant_arm_extended_fifo_hwfc,
1736 },
1737 {
1738 .id = 0x00041181,
1739 .mask = 0x000fffff,
1740 .data = &variant_arm,
1741 },
1742 /* ST Micro variants */
1743 {
1744 .id = 0x00180180,
1745 .mask = 0x00ffffff,
1746 .data = &variant_u300,
1747 },
1748 {
1749 .id = 0x10180180,
1750 .mask = 0xf0ffffff,
1751 .data = &variant_nomadik,
1752 },
1753 {
1754 .id = 0x00280180,
1755 .mask = 0x00ffffff,
1756 .data = &variant_u300,
1757 },
1758 {
1759 .id = 0x00480180,
1760 .mask = 0xf0ffffff,
1761 .data = &variant_ux500,
1762 },
1763 {
1764 .id = 0x10480180,
1765 .mask = 0xf0ffffff,
1766 .data = &variant_ux500v2,
1767 },
1768 { 0, 0 },
1769 };
1770
1771 MODULE_DEVICE_TABLE(amba, mmci_ids);
1772
1773 static struct amba_driver mmci_driver = {
1774 .drv = {
1775 .name = DRIVER_NAME,
1776 .pm = &mmci_dev_pm_ops,
1777 },
1778 .probe = mmci_probe,
1779 .remove = mmci_remove,
1780 .id_table = mmci_ids,
1781 };
1782
1783 module_amba_driver(mmci_driver);
1784
1785 module_param(fmax, uint, 0444);
1786
1787 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1788 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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