2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Author: San Mehat (san@android.com)
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/ioport.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
26 #include <linux/highmem.h>
27 #include <linux/log2.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/mmc/sdio.h>
31 #include <linux/clk.h>
32 #include <linux/scatterlist.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/debugfs.h>
37 #include <linux/memory.h>
38 #include <linux/gfp.h>
40 #include <asm/cacheflush.h>
41 #include <asm/div64.h>
42 #include <asm/sizes.h>
45 #include <mach/msm_iomap.h>
51 #define DRIVER_NAME "msm-sdcc"
53 #define BUSCLK_PWRSAVE 1
54 #define BUSCLK_TIMEOUT (HZ)
55 static unsigned int msmsdcc_fmin
= 144000;
56 static unsigned int msmsdcc_fmax
= 50000000;
57 static unsigned int msmsdcc_4bit
= 1;
58 static unsigned int msmsdcc_pwrsave
= 1;
59 static unsigned int msmsdcc_piopoll
= 1;
60 static unsigned int msmsdcc_sdioirq
;
62 #define PIO_SPINMAX 30
63 #define CMD_SPINMAX 20
67 msmsdcc_disable_clocks(struct msmsdcc_host
*host
, int deferr
)
69 WARN_ON(!host
->clks_on
);
71 BUG_ON(host
->curr
.mrq
);
74 mod_timer(&host
->busclk_timer
, jiffies
+ BUSCLK_TIMEOUT
);
76 del_timer_sync(&host
->busclk_timer
);
77 /* Need to check clks_on again in case the busclk
81 clk_disable(host
->clk
);
82 clk_disable(host
->pclk
);
89 msmsdcc_enable_clocks(struct msmsdcc_host
*host
)
93 del_timer_sync(&host
->busclk_timer
);
96 rc
= clk_enable(host
->pclk
);
99 rc
= clk_enable(host
->clk
);
101 clk_disable(host
->pclk
);
104 udelay(1 + ((3 * USEC_PER_SEC
) /
105 (host
->clk_rate
? host
->clk_rate
: msmsdcc_fmin
)));
111 static inline unsigned int
112 msmsdcc_readl(struct msmsdcc_host
*host
, unsigned int reg
)
114 return readl(host
->base
+ reg
);
118 msmsdcc_writel(struct msmsdcc_host
*host
, u32 data
, unsigned int reg
)
120 writel(data
, host
->base
+ reg
);
121 /* 3 clk delay required! */
122 udelay(1 + ((3 * USEC_PER_SEC
) /
123 (host
->clk_rate
? host
->clk_rate
: msmsdcc_fmin
)));
127 msmsdcc_start_command(struct msmsdcc_host
*host
, struct mmc_command
*cmd
,
130 static void msmsdcc_reset_and_restore(struct msmsdcc_host
*host
)
136 /* Save the controller state */
137 mci_clk
= readl(host
->base
+ MMCICLOCK
);
138 mci_mask0
= readl(host
->base
+ MMCIMASK0
);
140 /* Reset the controller */
141 ret
= clk_reset(host
->clk
, CLK_RESET_ASSERT
);
143 pr_err("%s: Clock assert failed at %u Hz with err %d\n",
144 mmc_hostname(host
->mmc
), host
->clk_rate
, ret
);
146 ret
= clk_reset(host
->clk
, CLK_RESET_DEASSERT
);
148 pr_err("%s: Clock deassert failed at %u Hz with err %d\n",
149 mmc_hostname(host
->mmc
), host
->clk_rate
, ret
);
151 pr_info("%s: Controller has been re-initialiazed\n",
152 mmc_hostname(host
->mmc
));
154 /* Restore the contoller state */
155 writel(host
->pwr
, host
->base
+ MMCIPOWER
);
156 writel(mci_clk
, host
->base
+ MMCICLOCK
);
157 writel(mci_mask0
, host
->base
+ MMCIMASK0
);
158 ret
= clk_set_rate(host
->clk
, host
->clk_rate
);
160 pr_err("%s: Failed to set clk rate %u Hz (%d)\n",
161 mmc_hostname(host
->mmc
), host
->clk_rate
, ret
);
165 msmsdcc_request_end(struct msmsdcc_host
*host
, struct mmc_request
*mrq
)
167 BUG_ON(host
->curr
.data
);
169 host
->curr
.mrq
= NULL
;
170 host
->curr
.cmd
= NULL
;
173 mrq
->data
->bytes_xfered
= host
->curr
.data_xfered
;
174 if (mrq
->cmd
->error
== -ETIMEDOUT
)
178 msmsdcc_disable_clocks(host
, 1);
181 * Need to drop the host lock here; mmc_request_done may call
182 * back into the driver...
184 spin_unlock(&host
->lock
);
185 mmc_request_done(host
->mmc
, mrq
);
186 spin_lock(&host
->lock
);
190 msmsdcc_stop_data(struct msmsdcc_host
*host
)
192 host
->curr
.data
= NULL
;
193 host
->curr
.got_dataend
= host
->curr
.got_datablkend
= 0;
196 uint32_t msmsdcc_fifo_addr(struct msmsdcc_host
*host
)
198 return host
->memres
->start
+ MMCIFIFO
;
202 msmsdcc_start_command_exec(struct msmsdcc_host
*host
, u32 arg
, u32 c
) {
203 msmsdcc_writel(host
, arg
, MMCIARGUMENT
);
204 msmsdcc_writel(host
, c
, MMCICOMMAND
);
208 msmsdcc_dma_exec_func(struct msm_dmov_cmd
*cmd
)
210 struct msmsdcc_host
*host
= (struct msmsdcc_host
*)cmd
->data
;
212 msmsdcc_writel(host
, host
->cmd_timeout
, MMCIDATATIMER
);
213 msmsdcc_writel(host
, (unsigned int)host
->curr
.xfer_size
,
215 msmsdcc_writel(host
, host
->cmd_pio_irqmask
, MMCIMASK1
);
216 msmsdcc_writel(host
, host
->cmd_datactrl
, MMCIDATACTRL
);
219 msmsdcc_start_command_exec(host
,
220 (u32
) host
->cmd_cmd
->arg
,
223 host
->dma
.active
= 1;
227 msmsdcc_dma_complete_tlet(unsigned long data
)
229 struct msmsdcc_host
*host
= (struct msmsdcc_host
*)data
;
231 struct mmc_request
*mrq
;
232 struct msm_dmov_errdata err
;
234 spin_lock_irqsave(&host
->lock
, flags
);
235 host
->dma
.active
= 0;
238 mrq
= host
->curr
.mrq
;
242 if (!(host
->dma
.result
& DMOV_RSLT_VALID
)) {
243 pr_err("msmsdcc: Invalid DataMover result\n");
247 if (host
->dma
.result
& DMOV_RSLT_DONE
) {
248 host
->curr
.data_xfered
= host
->curr
.xfer_size
;
251 if (host
->dma
.result
& DMOV_RSLT_ERROR
)
252 pr_err("%s: DMA error (0x%.8x)\n",
253 mmc_hostname(host
->mmc
), host
->dma
.result
);
254 if (host
->dma
.result
& DMOV_RSLT_FLUSH
)
255 pr_err("%s: DMA channel flushed (0x%.8x)\n",
256 mmc_hostname(host
->mmc
), host
->dma
.result
);
258 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
259 err
.flush
[0], err
.flush
[1], err
.flush
[2],
260 err
.flush
[3], err
.flush
[4], err
.flush
[5]);
262 msmsdcc_reset_and_restore(host
);
263 if (!mrq
->data
->error
)
264 mrq
->data
->error
= -EIO
;
266 dma_unmap_sg(mmc_dev(host
->mmc
), host
->dma
.sg
, host
->dma
.num_ents
,
269 if (host
->curr
.user_pages
) {
270 struct scatterlist
*sg
= host
->dma
.sg
;
273 for (i
= 0; i
< host
->dma
.num_ents
; i
++)
274 flush_dcache_page(sg_page(sg
++));
280 if ((host
->curr
.got_dataend
&& host
->curr
.got_datablkend
)
281 || mrq
->data
->error
) {
284 * If we've already gotten our DATAEND / DATABLKEND
285 * for this request, then complete it through here.
287 msmsdcc_stop_data(host
);
289 if (!mrq
->data
->error
)
290 host
->curr
.data_xfered
= host
->curr
.xfer_size
;
291 if (!mrq
->data
->stop
|| mrq
->cmd
->error
) {
292 host
->curr
.mrq
= NULL
;
293 host
->curr
.cmd
= NULL
;
294 mrq
->data
->bytes_xfered
= host
->curr
.data_xfered
;
296 spin_unlock_irqrestore(&host
->lock
, flags
);
298 msmsdcc_disable_clocks(host
, 1);
300 mmc_request_done(host
->mmc
, mrq
);
303 msmsdcc_start_command(host
, mrq
->data
->stop
, 0);
307 spin_unlock_irqrestore(&host
->lock
, flags
);
312 msmsdcc_dma_complete_func(struct msm_dmov_cmd
*cmd
,
314 struct msm_dmov_errdata
*err
)
316 struct msmsdcc_dma_data
*dma_data
=
317 container_of(cmd
, struct msmsdcc_dma_data
, hdr
);
318 struct msmsdcc_host
*host
= dma_data
->host
;
320 dma_data
->result
= result
;
322 memcpy(&dma_data
->err
, err
, sizeof(struct msm_dmov_errdata
));
324 tasklet_schedule(&host
->dma_tlet
);
327 static int validate_dma(struct msmsdcc_host
*host
, struct mmc_data
*data
)
329 if (host
->dma
.channel
== -1)
332 if ((data
->blksz
* data
->blocks
) < MCI_FIFOSIZE
)
334 if ((data
->blksz
* data
->blocks
) % MCI_FIFOSIZE
)
339 static int msmsdcc_config_dma(struct msmsdcc_host
*host
, struct mmc_data
*data
)
341 struct msmsdcc_nc_dmadata
*nc
;
347 struct scatterlist
*sg
= data
->sg
;
349 rc
= validate_dma(host
, data
);
353 host
->dma
.sg
= data
->sg
;
354 host
->dma
.num_ents
= data
->sg_len
;
356 BUG_ON(host
->dma
.num_ents
> NR_SG
); /* Prevent memory corruption */
360 switch (host
->pdev_id
) {
362 crci
= MSMSDCC_CRCI_SDC1
;
365 crci
= MSMSDCC_CRCI_SDC2
;
368 crci
= MSMSDCC_CRCI_SDC3
;
371 crci
= MSMSDCC_CRCI_SDC4
;
375 host
->dma
.num_ents
= 0;
379 if (data
->flags
& MMC_DATA_READ
)
380 host
->dma
.dir
= DMA_FROM_DEVICE
;
382 host
->dma
.dir
= DMA_TO_DEVICE
;
384 host
->curr
.user_pages
= 0;
387 for (i
= 0; i
< host
->dma
.num_ents
; i
++) {
388 box
->cmd
= CMD_MODE_BOX
;
390 /* Initialize sg dma address */
391 sg
->dma_address
= page_to_dma(mmc_dev(host
->mmc
), sg_page(sg
))
394 if (i
== (host
->dma
.num_ents
- 1))
396 rows
= (sg_dma_len(sg
) % MCI_FIFOSIZE
) ?
397 (sg_dma_len(sg
) / MCI_FIFOSIZE
) + 1 :
398 (sg_dma_len(sg
) / MCI_FIFOSIZE
) ;
400 if (data
->flags
& MMC_DATA_READ
) {
401 box
->src_row_addr
= msmsdcc_fifo_addr(host
);
402 box
->dst_row_addr
= sg_dma_address(sg
);
404 box
->src_dst_len
= (MCI_FIFOSIZE
<< 16) |
406 box
->row_offset
= MCI_FIFOSIZE
;
408 box
->num_rows
= rows
* ((1 << 16) + 1);
409 box
->cmd
|= CMD_SRC_CRCI(crci
);
411 box
->src_row_addr
= sg_dma_address(sg
);
412 box
->dst_row_addr
= msmsdcc_fifo_addr(host
);
414 box
->src_dst_len
= (MCI_FIFOSIZE
<< 16) |
416 box
->row_offset
= (MCI_FIFOSIZE
<< 16);
418 box
->num_rows
= rows
* ((1 << 16) + 1);
419 box
->cmd
|= CMD_DST_CRCI(crci
);
425 /* location of command block must be 64 bit aligned */
426 BUG_ON(host
->dma
.cmd_busaddr
& 0x07);
428 nc
->cmdptr
= (host
->dma
.cmd_busaddr
>> 3) | CMD_PTR_LP
;
429 host
->dma
.hdr
.cmdptr
= DMOV_CMD_PTR_LIST
|
430 DMOV_CMD_ADDR(host
->dma
.cmdptr_busaddr
);
431 host
->dma
.hdr
.complete_func
= msmsdcc_dma_complete_func
;
433 n
= dma_map_sg(mmc_dev(host
->mmc
), host
->dma
.sg
,
434 host
->dma
.num_ents
, host
->dma
.dir
);
435 /* dsb inside dma_map_sg will write nc out to mem as well */
437 if (n
!= host
->dma
.num_ents
) {
438 printk(KERN_ERR
"%s: Unable to map in all sg elements\n",
439 mmc_hostname(host
->mmc
));
441 host
->dma
.num_ents
= 0;
449 snoop_cccr_abort(struct mmc_command
*cmd
)
451 if ((cmd
->opcode
== 52) &&
452 (cmd
->arg
& 0x80000000) &&
453 (((cmd
->arg
>> 9) & 0x1ffff) == SDIO_CCCR_ABORT
))
459 msmsdcc_start_command_deferred(struct msmsdcc_host
*host
,
460 struct mmc_command
*cmd
, u32
*c
)
462 *c
|= (cmd
->opcode
| MCI_CPSM_ENABLE
);
464 if (cmd
->flags
& MMC_RSP_PRESENT
) {
465 if (cmd
->flags
& MMC_RSP_136
)
466 *c
|= MCI_CPSM_LONGRSP
;
467 *c
|= MCI_CPSM_RESPONSE
;
471 *c
|= MCI_CPSM_INTERRUPT
;
473 if ((((cmd
->opcode
== 17) || (cmd
->opcode
== 18)) ||
474 ((cmd
->opcode
== 24) || (cmd
->opcode
== 25))) ||
476 *c
|= MCI_CSPM_DATCMD
;
478 if (host
->prog_scan
&& (cmd
->opcode
== 12)) {
479 *c
|= MCI_CPSM_PROGENA
;
480 host
->prog_enable
= true;
483 if (cmd
== cmd
->mrq
->stop
)
484 *c
|= MCI_CSPM_MCIABORT
;
486 if (snoop_cccr_abort(cmd
))
487 *c
|= MCI_CSPM_MCIABORT
;
489 if (host
->curr
.cmd
!= NULL
) {
490 printk(KERN_ERR
"%s: Overlapping command requests\n",
491 mmc_hostname(host
->mmc
));
493 host
->curr
.cmd
= cmd
;
497 msmsdcc_start_data(struct msmsdcc_host
*host
, struct mmc_data
*data
,
498 struct mmc_command
*cmd
, u32 c
)
500 unsigned int datactrl
, timeout
;
501 unsigned long long clks
;
502 unsigned int pio_irqmask
= 0;
504 host
->curr
.data
= data
;
505 host
->curr
.xfer_size
= data
->blksz
* data
->blocks
;
506 host
->curr
.xfer_remain
= host
->curr
.xfer_size
;
507 host
->curr
.data_xfered
= 0;
508 host
->curr
.got_dataend
= 0;
509 host
->curr
.got_datablkend
= 0;
511 memset(&host
->pio
, 0, sizeof(host
->pio
));
513 datactrl
= MCI_DPSM_ENABLE
| (data
->blksz
<< 4);
515 if (!msmsdcc_config_dma(host
, data
))
516 datactrl
|= MCI_DPSM_DMAENABLE
;
518 host
->pio
.sg
= data
->sg
;
519 host
->pio
.sg_len
= data
->sg_len
;
520 host
->pio
.sg_off
= 0;
522 if (data
->flags
& MMC_DATA_READ
) {
523 pio_irqmask
= MCI_RXFIFOHALFFULLMASK
;
524 if (host
->curr
.xfer_remain
< MCI_FIFOSIZE
)
525 pio_irqmask
|= MCI_RXDATAAVLBLMASK
;
527 pio_irqmask
= MCI_TXFIFOHALFEMPTYMASK
;
530 if (data
->flags
& MMC_DATA_READ
)
531 datactrl
|= MCI_DPSM_DIRECTION
;
533 clks
= (unsigned long long)data
->timeout_ns
* host
->clk_rate
;
534 do_div(clks
, NSEC_PER_SEC
);
535 timeout
= data
->timeout_clks
+ (unsigned int)clks
*2 ;
537 if (datactrl
& MCI_DPSM_DMAENABLE
) {
538 /* Save parameters for the exec function */
539 host
->cmd_timeout
= timeout
;
540 host
->cmd_pio_irqmask
= pio_irqmask
;
541 host
->cmd_datactrl
= datactrl
;
544 host
->dma
.hdr
.execute_func
= msmsdcc_dma_exec_func
;
545 host
->dma
.hdr
.data
= (void *)host
;
549 msmsdcc_start_command_deferred(host
, cmd
, &c
);
552 msm_dmov_enqueue_cmd(host
->dma
.channel
, &host
->dma
.hdr
);
553 if (data
->flags
& MMC_DATA_WRITE
)
554 host
->prog_scan
= true;
556 msmsdcc_writel(host
, timeout
, MMCIDATATIMER
);
558 msmsdcc_writel(host
, host
->curr
.xfer_size
, MMCIDATALENGTH
);
560 msmsdcc_writel(host
, pio_irqmask
, MMCIMASK1
);
561 msmsdcc_writel(host
, datactrl
, MMCIDATACTRL
);
564 /* Daisy-chain the command if requested */
565 msmsdcc_start_command(host
, cmd
, c
);
571 msmsdcc_start_command(struct msmsdcc_host
*host
, struct mmc_command
*cmd
, u32 c
)
573 if (cmd
== cmd
->mrq
->stop
)
574 c
|= MCI_CSPM_MCIABORT
;
578 msmsdcc_start_command_deferred(host
, cmd
, &c
);
579 msmsdcc_start_command_exec(host
, cmd
->arg
, c
);
583 msmsdcc_data_err(struct msmsdcc_host
*host
, struct mmc_data
*data
,
586 if (status
& MCI_DATACRCFAIL
) {
587 pr_err("%s: Data CRC error\n", mmc_hostname(host
->mmc
));
588 pr_err("%s: opcode 0x%.8x\n", __func__
,
589 data
->mrq
->cmd
->opcode
);
590 pr_err("%s: blksz %d, blocks %d\n", __func__
,
591 data
->blksz
, data
->blocks
);
592 data
->error
= -EILSEQ
;
593 } else if (status
& MCI_DATATIMEOUT
) {
594 pr_err("%s: Data timeout\n", mmc_hostname(host
->mmc
));
595 data
->error
= -ETIMEDOUT
;
596 } else if (status
& MCI_RXOVERRUN
) {
597 pr_err("%s: RX overrun\n", mmc_hostname(host
->mmc
));
599 } else if (status
& MCI_TXUNDERRUN
) {
600 pr_err("%s: TX underrun\n", mmc_hostname(host
->mmc
));
603 pr_err("%s: Unknown error (0x%.8x)\n",
604 mmc_hostname(host
->mmc
), status
);
611 msmsdcc_pio_read(struct msmsdcc_host
*host
, char *buffer
, unsigned int remain
)
613 uint32_t *ptr
= (uint32_t *) buffer
;
617 remain
= ((remain
>> 2) + 1) << 2;
619 while (msmsdcc_readl(host
, MMCISTATUS
) & MCI_RXDATAAVLBL
) {
620 *ptr
= msmsdcc_readl(host
, MMCIFIFO
+ (count
% MCI_FIFOSIZE
));
622 count
+= sizeof(uint32_t);
624 remain
-= sizeof(uint32_t);
632 msmsdcc_pio_write(struct msmsdcc_host
*host
, char *buffer
,
633 unsigned int remain
, u32 status
)
635 void __iomem
*base
= host
->base
;
639 unsigned int count
, maxcnt
, sz
;
641 maxcnt
= status
& MCI_TXFIFOEMPTY
? MCI_FIFOSIZE
:
643 count
= min(remain
, maxcnt
);
645 sz
= count
% 4 ? (count
>> 2) + 1 : (count
>> 2);
646 writesl(base
+ MMCIFIFO
, ptr
, sz
);
653 status
= msmsdcc_readl(host
, MMCISTATUS
);
654 } while (status
& MCI_TXFIFOHALFEMPTY
);
660 msmsdcc_spin_on_status(struct msmsdcc_host
*host
, uint32_t mask
, int maxspin
)
663 if ((msmsdcc_readl(host
, MMCISTATUS
) & mask
))
672 msmsdcc_pio_irq(int irq
, void *dev_id
)
674 struct msmsdcc_host
*host
= dev_id
;
677 status
= msmsdcc_readl(host
, MMCISTATUS
);
681 unsigned int remain
, len
;
684 if (!(status
& (MCI_TXFIFOHALFEMPTY
| MCI_RXDATAAVLBL
))) {
685 if (host
->curr
.xfer_remain
== 0 || !msmsdcc_piopoll
)
688 if (msmsdcc_spin_on_status(host
,
689 (MCI_TXFIFOHALFEMPTY
|
696 /* Map the current scatter buffer */
697 local_irq_save(flags
);
698 buffer
= kmap_atomic(sg_page(host
->pio
.sg
),
699 KM_BIO_SRC_IRQ
) + host
->pio
.sg
->offset
;
700 buffer
+= host
->pio
.sg_off
;
701 remain
= host
->pio
.sg
->length
- host
->pio
.sg_off
;
703 if (status
& MCI_RXACTIVE
)
704 len
= msmsdcc_pio_read(host
, buffer
, remain
);
705 if (status
& MCI_TXACTIVE
)
706 len
= msmsdcc_pio_write(host
, buffer
, remain
, status
);
708 /* Unmap the buffer */
709 kunmap_atomic(buffer
, KM_BIO_SRC_IRQ
);
710 local_irq_restore(flags
);
712 host
->pio
.sg_off
+= len
;
713 host
->curr
.xfer_remain
-= len
;
714 host
->curr
.data_xfered
+= len
;
718 /* This sg page is full - do some housekeeping */
719 if (status
& MCI_RXACTIVE
&& host
->curr
.user_pages
)
720 flush_dcache_page(sg_page(host
->pio
.sg
));
722 if (!--host
->pio
.sg_len
) {
723 memset(&host
->pio
, 0, sizeof(host
->pio
));
727 /* Advance to next sg */
729 host
->pio
.sg_off
= 0;
732 status
= msmsdcc_readl(host
, MMCISTATUS
);
735 if (status
& MCI_RXACTIVE
&& host
->curr
.xfer_remain
< MCI_FIFOSIZE
)
736 msmsdcc_writel(host
, MCI_RXDATAAVLBLMASK
, MMCIMASK1
);
738 if (!host
->curr
.xfer_remain
)
739 msmsdcc_writel(host
, 0, MMCIMASK1
);
744 static void msmsdcc_do_cmdirq(struct msmsdcc_host
*host
, uint32_t status
)
746 struct mmc_command
*cmd
= host
->curr
.cmd
;
748 host
->curr
.cmd
= NULL
;
749 cmd
->resp
[0] = msmsdcc_readl(host
, MMCIRESPONSE0
);
750 cmd
->resp
[1] = msmsdcc_readl(host
, MMCIRESPONSE1
);
751 cmd
->resp
[2] = msmsdcc_readl(host
, MMCIRESPONSE2
);
752 cmd
->resp
[3] = msmsdcc_readl(host
, MMCIRESPONSE3
);
754 if (status
& MCI_CMDTIMEOUT
) {
755 cmd
->error
= -ETIMEDOUT
;
756 } else if (status
& MCI_CMDCRCFAIL
&&
757 cmd
->flags
& MMC_RSP_CRC
) {
758 pr_err("%s: Command CRC error\n", mmc_hostname(host
->mmc
));
759 cmd
->error
= -EILSEQ
;
762 if (!cmd
->data
|| cmd
->error
) {
763 if (host
->curr
.data
&& host
->dma
.sg
)
764 msm_dmov_stop_cmd(host
->dma
.channel
,
766 else if (host
->curr
.data
) { /* Non DMA */
767 msmsdcc_reset_and_restore(host
);
768 msmsdcc_stop_data(host
);
769 msmsdcc_request_end(host
, cmd
->mrq
);
770 } else { /* host->data == NULL */
771 if (!cmd
->error
&& host
->prog_enable
) {
772 if (status
& MCI_PROGDONE
) {
773 host
->prog_scan
= false;
774 host
->prog_enable
= false;
775 msmsdcc_request_end(host
, cmd
->mrq
);
777 host
->curr
.cmd
= cmd
;
780 if (host
->prog_enable
) {
781 host
->prog_scan
= false;
782 host
->prog_enable
= false;
784 msmsdcc_request_end(host
, cmd
->mrq
);
787 } else if (cmd
->data
)
788 if (!(cmd
->data
->flags
& MMC_DATA_READ
))
789 msmsdcc_start_data(host
, cmd
->data
,
794 msmsdcc_handle_irq_data(struct msmsdcc_host
*host
, u32 status
,
797 struct mmc_data
*data
= host
->curr
.data
;
799 if (status
& (MCI_CMDSENT
| MCI_CMDRESPEND
| MCI_CMDCRCFAIL
|
800 MCI_CMDTIMEOUT
| MCI_PROGDONE
) && host
->curr
.cmd
) {
801 msmsdcc_do_cmdirq(host
, status
);
807 /* Check for data errors */
808 if (status
& (MCI_DATACRCFAIL
| MCI_DATATIMEOUT
|
809 MCI_TXUNDERRUN
| MCI_RXOVERRUN
)) {
810 msmsdcc_data_err(host
, data
, status
);
811 host
->curr
.data_xfered
= 0;
813 msm_dmov_stop_cmd(host
->dma
.channel
,
816 msmsdcc_reset_and_restore(host
);
818 msmsdcc_stop_data(host
);
820 msmsdcc_request_end(host
, data
->mrq
);
822 msmsdcc_start_command(host
, data
->stop
, 0);
826 /* Check for data done */
827 if (!host
->curr
.got_dataend
&& (status
& MCI_DATAEND
))
828 host
->curr
.got_dataend
= 1;
830 if (!host
->curr
.got_datablkend
&& (status
& MCI_DATABLOCKEND
))
831 host
->curr
.got_datablkend
= 1;
834 * If DMA is still in progress, we complete via the completion handler
836 if (host
->curr
.got_dataend
&& host
->curr
.got_datablkend
&&
839 * There appears to be an issue in the controller where
840 * if you request a small block transfer (< fifo size),
841 * you may get your DATAEND/DATABLKEND irq without the
844 * Check to see if there is still data to be read,
845 * and simulate a PIO irq.
847 if (readl(base
+ MMCISTATUS
) & MCI_RXDATAAVLBL
)
848 msmsdcc_pio_irq(1, host
);
850 msmsdcc_stop_data(host
);
852 host
->curr
.data_xfered
= host
->curr
.xfer_size
;
855 msmsdcc_request_end(host
, data
->mrq
);
857 msmsdcc_start_command(host
, data
->stop
, 0);
862 msmsdcc_irq(int irq
, void *dev_id
)
864 struct msmsdcc_host
*host
= dev_id
;
865 void __iomem
*base
= host
->base
;
870 spin_lock(&host
->lock
);
873 status
= msmsdcc_readl(host
, MMCISTATUS
);
874 status
&= (msmsdcc_readl(host
, MMCIMASK0
) |
875 MCI_DATABLOCKENDMASK
);
876 msmsdcc_writel(host
, status
, MMCICLEAR
);
878 if (status
& MCI_SDIOINTR
)
879 status
&= ~MCI_SDIOINTR
;
884 msmsdcc_handle_irq_data(host
, status
, base
);
886 if (status
& MCI_SDIOINTOPER
) {
888 status
&= ~MCI_SDIOINTOPER
;
893 spin_unlock(&host
->lock
);
896 * We have to delay handling the card interrupt as it calls
897 * back into the driver.
900 mmc_signal_sdio_irq(host
->mmc
);
902 return IRQ_RETVAL(ret
);
906 msmsdcc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
908 struct msmsdcc_host
*host
= mmc_priv(mmc
);
911 WARN_ON(host
->curr
.mrq
!= NULL
);
912 WARN_ON(host
->pwr
== 0);
914 spin_lock_irqsave(&host
->lock
, flags
);
919 if (mrq
->data
&& !(mrq
->data
->flags
& MMC_DATA_READ
)) {
921 mrq
->data
->bytes_xfered
= mrq
->data
->blksz
*
924 mrq
->cmd
->error
= -ENOMEDIUM
;
926 spin_unlock_irqrestore(&host
->lock
, flags
);
927 mmc_request_done(mmc
, mrq
);
931 msmsdcc_enable_clocks(host
);
933 host
->curr
.mrq
= mrq
;
935 if (mrq
->data
&& mrq
->data
->flags
& MMC_DATA_READ
)
936 /* Queue/read data, daisy-chain command when data starts */
937 msmsdcc_start_data(host
, mrq
->data
, mrq
->cmd
, 0);
939 msmsdcc_start_command(host
, mrq
->cmd
, 0);
941 if (host
->cmdpoll
&& !msmsdcc_spin_on_status(host
,
942 MCI_CMDRESPEND
|MCI_CMDCRCFAIL
|MCI_CMDTIMEOUT
,
944 uint32_t status
= msmsdcc_readl(host
, MMCISTATUS
);
945 msmsdcc_do_cmdirq(host
, status
);
947 MCI_CMDRESPEND
| MCI_CMDCRCFAIL
| MCI_CMDTIMEOUT
,
949 host
->stats
.cmdpoll_hits
++;
951 host
->stats
.cmdpoll_misses
++;
953 spin_unlock_irqrestore(&host
->lock
, flags
);
957 msmsdcc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
959 struct msmsdcc_host
*host
= mmc_priv(mmc
);
960 u32 clk
= 0, pwr
= 0;
964 spin_lock_irqsave(&host
->lock
, flags
);
966 msmsdcc_enable_clocks(host
);
969 if (ios
->clock
!= host
->clk_rate
) {
970 rc
= clk_set_rate(host
->clk
, ios
->clock
);
972 pr_err("%s: Error setting clock rate (%d)\n",
973 mmc_hostname(host
->mmc
), rc
);
975 host
->clk_rate
= ios
->clock
;
977 clk
|= MCI_CLK_ENABLE
;
980 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
981 clk
|= (2 << 10); /* Set WIDEBUS */
983 if (ios
->clock
> 400000 && msmsdcc_pwrsave
)
984 clk
|= (1 << 9); /* PWRSAVE */
986 clk
|= (1 << 12); /* FLOW_ENA */
987 clk
|= (1 << 15); /* feedback clock */
989 if (host
->plat
->translate_vdd
)
990 pwr
|= host
->plat
->translate_vdd(mmc_dev(mmc
), ios
->vdd
);
992 switch (ios
->power_mode
) {
1003 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
1006 msmsdcc_writel(host
, clk
, MMCICLOCK
);
1008 if (host
->pwr
!= pwr
) {
1010 msmsdcc_writel(host
, pwr
, MMCIPOWER
);
1013 msmsdcc_disable_clocks(host
, 1);
1015 spin_unlock_irqrestore(&host
->lock
, flags
);
1018 static void msmsdcc_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1020 struct msmsdcc_host
*host
= mmc_priv(mmc
);
1021 unsigned long flags
;
1024 spin_lock_irqsave(&host
->lock
, flags
);
1025 if (msmsdcc_sdioirq
== 1) {
1026 status
= msmsdcc_readl(host
, MMCIMASK0
);
1028 status
|= MCI_SDIOINTOPERMASK
;
1030 status
&= ~MCI_SDIOINTOPERMASK
;
1031 host
->saved_irq0mask
= status
;
1032 msmsdcc_writel(host
, status
, MMCIMASK0
);
1034 spin_unlock_irqrestore(&host
->lock
, flags
);
1037 static const struct mmc_host_ops msmsdcc_ops
= {
1038 .request
= msmsdcc_request
,
1039 .set_ios
= msmsdcc_set_ios
,
1040 .enable_sdio_irq
= msmsdcc_enable_sdio_irq
,
1044 msmsdcc_check_status(unsigned long data
)
1046 struct msmsdcc_host
*host
= (struct msmsdcc_host
*)data
;
1047 unsigned int status
;
1049 if (!host
->plat
->status
) {
1050 mmc_detect_change(host
->mmc
, 0);
1054 status
= host
->plat
->status(mmc_dev(host
->mmc
));
1055 host
->eject
= !status
;
1056 if (status
^ host
->oldstat
) {
1057 pr_info("%s: Slot status change detected (%d -> %d)\n",
1058 mmc_hostname(host
->mmc
), host
->oldstat
, status
);
1060 mmc_detect_change(host
->mmc
, (5 * HZ
) / 2);
1062 mmc_detect_change(host
->mmc
, 0);
1065 host
->oldstat
= status
;
1068 if (host
->timer
.function
)
1069 mod_timer(&host
->timer
, jiffies
+ HZ
);
1073 msmsdcc_platform_status_irq(int irq
, void *dev_id
)
1075 struct msmsdcc_host
*host
= dev_id
;
1077 printk(KERN_DEBUG
"%s: %d\n", __func__
, irq
);
1078 msmsdcc_check_status((unsigned long) host
);
1083 msmsdcc_status_notify_cb(int card_present
, void *dev_id
)
1085 struct msmsdcc_host
*host
= dev_id
;
1087 printk(KERN_DEBUG
"%s: card_present %d\n", mmc_hostname(host
->mmc
),
1089 msmsdcc_check_status((unsigned long) host
);
1093 msmsdcc_busclk_expired(unsigned long _data
)
1095 struct msmsdcc_host
*host
= (struct msmsdcc_host
*) _data
;
1098 msmsdcc_disable_clocks(host
, 0);
1102 msmsdcc_init_dma(struct msmsdcc_host
*host
)
1104 memset(&host
->dma
, 0, sizeof(struct msmsdcc_dma_data
));
1105 host
->dma
.host
= host
;
1106 host
->dma
.channel
= -1;
1111 host
->dma
.nc
= dma_alloc_coherent(NULL
,
1112 sizeof(struct msmsdcc_nc_dmadata
),
1113 &host
->dma
.nc_busaddr
,
1115 if (host
->dma
.nc
== NULL
) {
1116 pr_err("Unable to allocate DMA buffer\n");
1119 memset(host
->dma
.nc
, 0x00, sizeof(struct msmsdcc_nc_dmadata
));
1120 host
->dma
.cmd_busaddr
= host
->dma
.nc_busaddr
;
1121 host
->dma
.cmdptr_busaddr
= host
->dma
.nc_busaddr
+
1122 offsetof(struct msmsdcc_nc_dmadata
, cmdptr
);
1123 host
->dma
.channel
= host
->dmares
->start
;
1129 msmsdcc_probe(struct platform_device
*pdev
)
1131 struct msm_mmc_platform_data
*plat
= pdev
->dev
.platform_data
;
1132 struct msmsdcc_host
*host
;
1133 struct mmc_host
*mmc
;
1134 struct resource
*cmd_irqres
= NULL
;
1135 struct resource
*pio_irqres
= NULL
;
1136 struct resource
*stat_irqres
= NULL
;
1137 struct resource
*memres
= NULL
;
1138 struct resource
*dmares
= NULL
;
1141 /* must have platform data */
1143 pr_err("%s: Platform data not available\n", __func__
);
1148 if (pdev
->id
< 1 || pdev
->id
> 4)
1151 if (pdev
->resource
== NULL
|| pdev
->num_resources
< 2) {
1152 pr_err("%s: Invalid resource\n", __func__
);
1156 memres
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1157 dmares
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1158 cmd_irqres
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1160 pio_irqres
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1162 stat_irqres
= platform_get_resource_byname(pdev
, IORESOURCE_IRQ
,
1165 if (!cmd_irqres
|| !pio_irqres
|| !memres
) {
1166 pr_err("%s: Invalid resource\n", __func__
);
1171 * Setup our host structure
1174 mmc
= mmc_alloc_host(sizeof(struct msmsdcc_host
), &pdev
->dev
);
1180 host
= mmc_priv(mmc
);
1181 host
->pdev_id
= pdev
->id
;
1184 host
->curr
.cmd
= NULL
;
1188 host
->base
= ioremap(memres
->start
, PAGE_SIZE
);
1194 host
->cmd_irqres
= cmd_irqres
;
1195 host
->pio_irqres
= pio_irqres
;
1196 host
->memres
= memres
;
1197 host
->dmares
= dmares
;
1198 spin_lock_init(&host
->lock
);
1200 tasklet_init(&host
->dma_tlet
, msmsdcc_dma_complete_tlet
,
1201 (unsigned long)host
);
1206 msmsdcc_init_dma(host
);
1208 /* Get our clocks */
1209 host
->pclk
= clk_get(&pdev
->dev
, "sdc_pclk");
1210 if (IS_ERR(host
->pclk
)) {
1211 ret
= PTR_ERR(host
->pclk
);
1215 host
->clk
= clk_get(&pdev
->dev
, "sdc_clk");
1216 if (IS_ERR(host
->clk
)) {
1217 ret
= PTR_ERR(host
->clk
);
1222 ret
= msmsdcc_enable_clocks(host
);
1226 ret
= clk_set_rate(host
->clk
, msmsdcc_fmin
);
1228 pr_err("%s: Clock rate set failed (%d)\n", __func__
, ret
);
1232 host
->pclk_rate
= clk_get_rate(host
->pclk
);
1233 host
->clk_rate
= clk_get_rate(host
->clk
);
1236 * Setup MMC host structure
1238 mmc
->ops
= &msmsdcc_ops
;
1239 mmc
->f_min
= msmsdcc_fmin
;
1240 mmc
->f_max
= msmsdcc_fmax
;
1241 mmc
->ocr_avail
= plat
->ocr_mask
;
1244 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
1245 if (msmsdcc_sdioirq
)
1246 mmc
->caps
|= MMC_CAP_SDIO_IRQ
;
1247 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
;
1249 mmc
->max_segs
= NR_SG
;
1250 mmc
->max_blk_size
= 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1251 mmc
->max_blk_count
= 65536;
1253 mmc
->max_req_size
= 33554432; /* MCI_DATA_LENGTH is 25 bits */
1254 mmc
->max_seg_size
= mmc
->max_req_size
;
1256 msmsdcc_writel(host
, 0, MMCIMASK0
);
1257 msmsdcc_writel(host
, 0x5e007ff, MMCICLEAR
);
1259 msmsdcc_writel(host
, MCI_IRQENABLE
, MMCIMASK0
);
1260 host
->saved_irq0mask
= MCI_IRQENABLE
;
1263 * Setup card detect change
1266 memset(&host
->timer
, 0, sizeof(host
->timer
));
1268 if (stat_irqres
&& !(stat_irqres
->flags
& IORESOURCE_DISABLED
)) {
1269 unsigned long irqflags
= IRQF_SHARED
|
1270 (stat_irqres
->flags
& IRQF_TRIGGER_MASK
);
1272 host
->stat_irq
= stat_irqres
->start
;
1273 ret
= request_irq(host
->stat_irq
,
1274 msmsdcc_platform_status_irq
,
1276 DRIVER_NAME
" (slot)",
1279 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1280 mmc_hostname(mmc
), host
->stat_irq
, ret
);
1283 } else if (plat
->register_status_notify
) {
1284 plat
->register_status_notify(msmsdcc_status_notify_cb
, host
);
1285 } else if (!plat
->status
)
1286 pr_err("%s: No card detect facilities available\n",
1289 init_timer(&host
->timer
);
1290 host
->timer
.data
= (unsigned long)host
;
1291 host
->timer
.function
= msmsdcc_check_status
;
1292 host
->timer
.expires
= jiffies
+ HZ
;
1293 add_timer(&host
->timer
);
1297 host
->oldstat
= host
->plat
->status(mmc_dev(host
->mmc
));
1298 host
->eject
= !host
->oldstat
;
1301 init_timer(&host
->busclk_timer
);
1302 host
->busclk_timer
.data
= (unsigned long) host
;
1303 host
->busclk_timer
.function
= msmsdcc_busclk_expired
;
1305 ret
= request_irq(cmd_irqres
->start
, msmsdcc_irq
, IRQF_SHARED
,
1306 DRIVER_NAME
" (cmd)", host
);
1310 ret
= request_irq(pio_irqres
->start
, msmsdcc_pio_irq
, IRQF_SHARED
,
1311 DRIVER_NAME
" (pio)", host
);
1315 mmc_set_drvdata(pdev
, mmc
);
1318 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1319 mmc_hostname(mmc
), (unsigned long long)memres
->start
,
1320 (unsigned int) cmd_irqres
->start
,
1321 (unsigned int) host
->stat_irq
, host
->dma
.channel
);
1322 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc
),
1323 (mmc
->caps
& MMC_CAP_4_BIT_DATA
? "enabled" : "disabled"));
1324 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1325 mmc_hostname(mmc
), msmsdcc_fmin
, msmsdcc_fmax
, host
->pclk_rate
);
1326 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc
), host
->eject
);
1327 pr_info("%s: Power save feature enable = %d\n",
1328 mmc_hostname(mmc
), msmsdcc_pwrsave
);
1330 if (host
->dma
.channel
!= -1) {
1331 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1332 mmc_hostname(mmc
), host
->dma
.nc
, host
->dma
.nc_busaddr
);
1333 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1334 mmc_hostname(mmc
), host
->dma
.cmd_busaddr
,
1335 host
->dma
.cmdptr_busaddr
);
1337 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc
));
1338 if (host
->timer
.function
)
1339 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc
));
1342 msmsdcc_disable_clocks(host
, 1);
1346 free_irq(cmd_irqres
->start
, host
);
1349 free_irq(host
->stat_irq
, host
);
1351 msmsdcc_disable_clocks(host
, 0);
1355 clk_put(host
->pclk
);
1363 #ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1365 do_resume_work(struct work_struct
*work
)
1367 struct msmsdcc_host
*host
=
1368 container_of(work
, struct msmsdcc_host
, resume_task
);
1369 struct mmc_host
*mmc
= host
->mmc
;
1372 mmc_resume_host(mmc
);
1374 enable_irq(host
->stat_irq
);
1381 msmsdcc_suspend(struct platform_device
*dev
, pm_message_t state
)
1383 struct mmc_host
*mmc
= mmc_get_drvdata(dev
);
1387 struct msmsdcc_host
*host
= mmc_priv(mmc
);
1390 disable_irq(host
->stat_irq
);
1392 if (mmc
->card
&& mmc
->card
->type
!= MMC_TYPE_SDIO
)
1393 rc
= mmc_suspend_host(mmc
);
1395 msmsdcc_writel(host
, 0, MMCIMASK0
);
1397 msmsdcc_disable_clocks(host
, 0);
1403 msmsdcc_resume(struct platform_device
*dev
)
1405 struct mmc_host
*mmc
= mmc_get_drvdata(dev
);
1408 struct msmsdcc_host
*host
= mmc_priv(mmc
);
1410 msmsdcc_enable_clocks(host
);
1412 msmsdcc_writel(host
, host
->saved_irq0mask
, MMCIMASK0
);
1414 if (mmc
->card
&& mmc
->card
->type
!= MMC_TYPE_SDIO
)
1415 mmc_resume_host(mmc
);
1417 enable_irq(host
->stat_irq
);
1419 msmsdcc_disable_clocks(host
, 1);
1425 #define msmsdcc_suspend 0
1426 #define msmsdcc_resume 0
1429 static struct platform_driver msmsdcc_driver
= {
1430 .probe
= msmsdcc_probe
,
1431 .suspend
= msmsdcc_suspend
,
1432 .resume
= msmsdcc_resume
,
1438 static int __init
msmsdcc_init(void)
1440 return platform_driver_register(&msmsdcc_driver
);
1443 static void __exit
msmsdcc_exit(void)
1445 platform_driver_unregister(&msmsdcc_driver
);
1448 module_init(msmsdcc_init
);
1449 module_exit(msmsdcc_exit
);
1451 MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1452 MODULE_LICENSE("GPL");