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mmc: mvsdio: implement a Device Tree binding
[deliverable/linux.git] / drivers / mmc / host / mvsdio.c
1 /*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/platform_device.h>
16 #include <linux/mbus.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <linux/of_gpio.h>
25 #include <linux/of_irq.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/slot-gpio.h>
28
29 #include <asm/sizes.h>
30 #include <asm/unaligned.h>
31 #include <linux/platform_data/mmc-mvsdio.h>
32
33 #include "mvsdio.h"
34
35 #define DRIVER_NAME "mvsdio"
36
37 static int maxfreq = MVSD_CLOCKRATE_MAX;
38 static int nodma;
39
40 struct mvsd_host {
41 void __iomem *base;
42 struct mmc_request *mrq;
43 spinlock_t lock;
44 unsigned int xfer_mode;
45 unsigned int intr_en;
46 unsigned int ctrl;
47 unsigned int pio_size;
48 void *pio_ptr;
49 unsigned int sg_frags;
50 unsigned int ns_per_clk;
51 unsigned int clock;
52 unsigned int base_clock;
53 struct timer_list timer;
54 struct mmc_host *mmc;
55 struct device *dev;
56 struct clk *clk;
57 };
58
59 #define mvsd_write(offs, val) writel(val, iobase + (offs))
60 #define mvsd_read(offs) readl(iobase + (offs))
61
62 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
63 {
64 void __iomem *iobase = host->base;
65 unsigned int tmout;
66 int tmout_index;
67
68 /*
69 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
70 * register is sometimes not set before a while when some
71 * "unusual" data block sizes are used (such as with the SWITCH
72 * command), even despite the fact that the XFER_DONE interrupt
73 * was raised. And if another data transfer starts before
74 * this bit comes to good sense (which eventually happens by
75 * itself) then the new transfer simply fails with a timeout.
76 */
77 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
78 unsigned long t = jiffies + HZ;
79 unsigned int hw_state, count = 0;
80 do {
81 if (time_after(jiffies, t)) {
82 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
83 break;
84 }
85 hw_state = mvsd_read(MVSD_HW_STATE);
86 count++;
87 } while (!(hw_state & (1 << 13)));
88 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
89 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
90 hw_state, count, jiffies - (t - HZ));
91 }
92
93 /* If timeout=0 then maximum timeout index is used. */
94 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
95 tmout += data->timeout_clks;
96 tmout_index = fls(tmout - 1) - 12;
97 if (tmout_index < 0)
98 tmout_index = 0;
99 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
100 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
101
102 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
103 (data->flags & MMC_DATA_READ) ? "read" : "write",
104 (u32)sg_virt(data->sg), data->blocks, data->blksz,
105 tmout, tmout_index);
106
107 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
108 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
109 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
110 mvsd_write(MVSD_BLK_COUNT, data->blocks);
111 mvsd_write(MVSD_BLK_SIZE, data->blksz);
112
113 if (nodma || (data->blksz | data->sg->offset) & 3) {
114 /*
115 * We cannot do DMA on a buffer which offset or size
116 * is not aligned on a 4-byte boundary.
117 */
118 host->pio_size = data->blocks * data->blksz;
119 host->pio_ptr = sg_virt(data->sg);
120 if (!nodma)
121 pr_debug("%s: fallback to PIO for data "
122 "at 0x%p size %d\n",
123 mmc_hostname(host->mmc),
124 host->pio_ptr, host->pio_size);
125 return 1;
126 } else {
127 dma_addr_t phys_addr;
128 int dma_dir = (data->flags & MMC_DATA_READ) ?
129 DMA_FROM_DEVICE : DMA_TO_DEVICE;
130 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
131 data->sg_len, dma_dir);
132 phys_addr = sg_dma_address(data->sg);
133 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
134 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
135 return 0;
136 }
137 }
138
139 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
140 {
141 struct mvsd_host *host = mmc_priv(mmc);
142 void __iomem *iobase = host->base;
143 struct mmc_command *cmd = mrq->cmd;
144 u32 cmdreg = 0, xfer = 0, intr = 0;
145 unsigned long flags;
146
147 BUG_ON(host->mrq != NULL);
148 host->mrq = mrq;
149
150 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
151 cmd->opcode, mvsd_read(MVSD_HW_STATE));
152
153 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
154
155 if (cmd->flags & MMC_RSP_BUSY)
156 cmdreg |= MVSD_CMD_RSP_48BUSY;
157 else if (cmd->flags & MMC_RSP_136)
158 cmdreg |= MVSD_CMD_RSP_136;
159 else if (cmd->flags & MMC_RSP_PRESENT)
160 cmdreg |= MVSD_CMD_RSP_48;
161 else
162 cmdreg |= MVSD_CMD_RSP_NONE;
163
164 if (cmd->flags & MMC_RSP_CRC)
165 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
166
167 if (cmd->flags & MMC_RSP_OPCODE)
168 cmdreg |= MVSD_CMD_INDX_CHECK;
169
170 if (cmd->flags & MMC_RSP_PRESENT) {
171 cmdreg |= MVSD_UNEXPECTED_RESP;
172 intr |= MVSD_NOR_UNEXP_RSP;
173 }
174
175 if (mrq->data) {
176 struct mmc_data *data = mrq->data;
177 int pio;
178
179 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
180 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
181 if (data->flags & MMC_DATA_READ)
182 xfer |= MVSD_XFER_MODE_TO_HOST;
183
184 pio = mvsd_setup_data(host, data);
185 if (pio) {
186 xfer |= MVSD_XFER_MODE_PIO;
187 /* PIO section of mvsd_irq has comments on those bits */
188 if (data->flags & MMC_DATA_WRITE)
189 intr |= MVSD_NOR_TX_AVAIL;
190 else if (host->pio_size > 32)
191 intr |= MVSD_NOR_RX_FIFO_8W;
192 else
193 intr |= MVSD_NOR_RX_READY;
194 }
195
196 if (data->stop) {
197 struct mmc_command *stop = data->stop;
198 u32 cmd12reg = 0;
199
200 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
201 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
202
203 if (stop->flags & MMC_RSP_BUSY)
204 cmd12reg |= MVSD_AUTOCMD12_BUSY;
205 if (stop->flags & MMC_RSP_OPCODE)
206 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
207 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
208 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
209
210 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
211 intr |= MVSD_NOR_AUTOCMD12_DONE;
212 } else {
213 intr |= MVSD_NOR_XFER_DONE;
214 }
215 } else {
216 intr |= MVSD_NOR_CMD_DONE;
217 }
218
219 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
220 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
221
222 spin_lock_irqsave(&host->lock, flags);
223
224 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
225 host->xfer_mode |= xfer;
226 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
227
228 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
229 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
230 mvsd_write(MVSD_CMD, cmdreg);
231
232 host->intr_en &= MVSD_NOR_CARD_INT;
233 host->intr_en |= intr | MVSD_NOR_ERROR;
234 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
235 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
236
237 mod_timer(&host->timer, jiffies + 5 * HZ);
238
239 spin_unlock_irqrestore(&host->lock, flags);
240 }
241
242 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
243 u32 err_status)
244 {
245 void __iomem *iobase = host->base;
246
247 if (cmd->flags & MMC_RSP_136) {
248 unsigned int response[8], i;
249 for (i = 0; i < 8; i++)
250 response[i] = mvsd_read(MVSD_RSP(i));
251 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
252 ((response[1] & 0xffff) << 6) |
253 ((response[2] & 0xfc00) >> 10);
254 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
255 ((response[3] & 0xffff) << 6) |
256 ((response[4] & 0xfc00) >> 10);
257 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
258 ((response[5] & 0xffff) << 6) |
259 ((response[6] & 0xfc00) >> 10);
260 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
261 ((response[7] & 0x3fff) << 8);
262 } else if (cmd->flags & MMC_RSP_PRESENT) {
263 unsigned int response[3], i;
264 for (i = 0; i < 3; i++)
265 response[i] = mvsd_read(MVSD_RSP(i));
266 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
267 ((response[1] & 0xffff) << (14 - 8)) |
268 ((response[0] & 0x03ff) << (30 - 8));
269 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
270 cmd->resp[2] = 0;
271 cmd->resp[3] = 0;
272 }
273
274 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
275 cmd->error = -ETIMEDOUT;
276 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
277 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
278 cmd->error = -EILSEQ;
279 }
280 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
281 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
282 MVSD_ERR_CMD_STARTBIT);
283
284 return err_status;
285 }
286
287 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
288 u32 err_status)
289 {
290 void __iomem *iobase = host->base;
291
292 if (host->pio_ptr) {
293 host->pio_ptr = NULL;
294 host->pio_size = 0;
295 } else {
296 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
297 (data->flags & MMC_DATA_READ) ?
298 DMA_FROM_DEVICE : DMA_TO_DEVICE);
299 }
300
301 if (err_status & MVSD_ERR_DATA_TIMEOUT)
302 data->error = -ETIMEDOUT;
303 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
304 data->error = -EILSEQ;
305 else if (err_status & MVSD_ERR_XFER_SIZE)
306 data->error = -EBADE;
307 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
308 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
309
310 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
311 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
312 data->bytes_xfered =
313 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
314 /* We can't be sure about the last block when errors are detected */
315 if (data->bytes_xfered && data->error)
316 data->bytes_xfered -= data->blksz;
317
318 /* Handle Auto cmd 12 response */
319 if (data->stop) {
320 unsigned int response[3], i;
321 for (i = 0; i < 3; i++)
322 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
323 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
324 ((response[1] & 0xffff) << (14 - 8)) |
325 ((response[0] & 0x03ff) << (30 - 8));
326 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
327 data->stop->resp[2] = 0;
328 data->stop->resp[3] = 0;
329
330 if (err_status & MVSD_ERR_AUTOCMD12) {
331 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
332 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
333 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
334 data->stop->error = -ENOEXEC;
335 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
336 data->stop->error = -ETIMEDOUT;
337 else if (err_cmd12)
338 data->stop->error = -EILSEQ;
339 err_status &= ~MVSD_ERR_AUTOCMD12;
340 }
341 }
342
343 return err_status;
344 }
345
346 static irqreturn_t mvsd_irq(int irq, void *dev)
347 {
348 struct mvsd_host *host = dev;
349 void __iomem *iobase = host->base;
350 u32 intr_status, intr_done_mask;
351 int irq_handled = 0;
352
353 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
354 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
355 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
356 mvsd_read(MVSD_HW_STATE));
357
358 spin_lock(&host->lock);
359
360 /* PIO handling, if needed. Messy business... */
361 if (host->pio_size &&
362 (intr_status & host->intr_en &
363 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
364 u16 *p = host->pio_ptr;
365 int s = host->pio_size;
366 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
367 readsw(iobase + MVSD_FIFO, p, 16);
368 p += 16;
369 s -= 32;
370 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
371 }
372 /*
373 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
374 * doesn't appear to assert when there is exactly 32 bytes
375 * (8 words) left to fetch in a transfer.
376 */
377 if (s <= 32) {
378 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
379 put_unaligned(mvsd_read(MVSD_FIFO), p++);
380 put_unaligned(mvsd_read(MVSD_FIFO), p++);
381 s -= 4;
382 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
383 }
384 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
385 u16 val[2] = {0, 0};
386 val[0] = mvsd_read(MVSD_FIFO);
387 val[1] = mvsd_read(MVSD_FIFO);
388 memcpy(p, ((void *)&val) + 4 - s, s);
389 s = 0;
390 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
391 }
392 if (s == 0) {
393 host->intr_en &=
394 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
395 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
396 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
397 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
398 host->intr_en |= MVSD_NOR_RX_READY;
399 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
400 }
401 }
402 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
403 s, intr_status, mvsd_read(MVSD_HW_STATE));
404 host->pio_ptr = p;
405 host->pio_size = s;
406 irq_handled = 1;
407 } else if (host->pio_size &&
408 (intr_status & host->intr_en &
409 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
410 u16 *p = host->pio_ptr;
411 int s = host->pio_size;
412 /*
413 * The TX_FIFO_8W bit is unreliable. When set, bursting
414 * 16 halfwords all at once in the FIFO drops data. Actually
415 * TX_AVAIL does go off after only one word is pushed even if
416 * TX_FIFO_8W remains set.
417 */
418 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
419 mvsd_write(MVSD_FIFO, get_unaligned(p++));
420 mvsd_write(MVSD_FIFO, get_unaligned(p++));
421 s -= 4;
422 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
423 }
424 if (s < 4) {
425 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
426 u16 val[2] = {0, 0};
427 memcpy(((void *)&val) + 4 - s, p, s);
428 mvsd_write(MVSD_FIFO, val[0]);
429 mvsd_write(MVSD_FIFO, val[1]);
430 s = 0;
431 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
432 }
433 if (s == 0) {
434 host->intr_en &=
435 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
436 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
437 }
438 }
439 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
440 s, intr_status, mvsd_read(MVSD_HW_STATE));
441 host->pio_ptr = p;
442 host->pio_size = s;
443 irq_handled = 1;
444 }
445
446 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
447
448 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
449 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
450 if (intr_status & host->intr_en & ~intr_done_mask) {
451 struct mmc_request *mrq = host->mrq;
452 struct mmc_command *cmd = mrq->cmd;
453 u32 err_status = 0;
454
455 del_timer(&host->timer);
456 host->mrq = NULL;
457
458 host->intr_en &= MVSD_NOR_CARD_INT;
459 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
460 mvsd_write(MVSD_ERR_INTR_EN, 0);
461
462 spin_unlock(&host->lock);
463
464 if (intr_status & MVSD_NOR_UNEXP_RSP) {
465 cmd->error = -EPROTO;
466 } else if (intr_status & MVSD_NOR_ERROR) {
467 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
468 dev_dbg(host->dev, "err 0x%04x\n", err_status);
469 }
470
471 err_status = mvsd_finish_cmd(host, cmd, err_status);
472 if (mrq->data)
473 err_status = mvsd_finish_data(host, mrq->data, err_status);
474 if (err_status) {
475 pr_err("%s: unhandled error status %#04x\n",
476 mmc_hostname(host->mmc), err_status);
477 cmd->error = -ENOMSG;
478 }
479
480 mmc_request_done(host->mmc, mrq);
481 irq_handled = 1;
482 } else
483 spin_unlock(&host->lock);
484
485 if (intr_status & MVSD_NOR_CARD_INT) {
486 mmc_signal_sdio_irq(host->mmc);
487 irq_handled = 1;
488 }
489
490 if (irq_handled)
491 return IRQ_HANDLED;
492
493 pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x "
494 "pio=%d\n", mmc_hostname(host->mmc), intr_status,
495 host->intr_en, host->pio_size);
496 return IRQ_NONE;
497 }
498
499 static void mvsd_timeout_timer(unsigned long data)
500 {
501 struct mvsd_host *host = (struct mvsd_host *)data;
502 void __iomem *iobase = host->base;
503 struct mmc_request *mrq;
504 unsigned long flags;
505
506 spin_lock_irqsave(&host->lock, flags);
507 mrq = host->mrq;
508 if (mrq) {
509 pr_err("%s: Timeout waiting for hardware interrupt.\n",
510 mmc_hostname(host->mmc));
511 pr_err("%s: hw_state=0x%04x, intr_status=0x%04x "
512 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
513 mvsd_read(MVSD_HW_STATE),
514 mvsd_read(MVSD_NOR_INTR_STATUS),
515 mvsd_read(MVSD_NOR_INTR_EN));
516
517 host->mrq = NULL;
518
519 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
520
521 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
522 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
523
524 host->intr_en &= MVSD_NOR_CARD_INT;
525 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
526 mvsd_write(MVSD_ERR_INTR_EN, 0);
527 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
528
529 mrq->cmd->error = -ETIMEDOUT;
530 mvsd_finish_cmd(host, mrq->cmd, 0);
531 if (mrq->data) {
532 mrq->data->error = -ETIMEDOUT;
533 mvsd_finish_data(host, mrq->data, 0);
534 }
535 }
536 spin_unlock_irqrestore(&host->lock, flags);
537
538 if (mrq)
539 mmc_request_done(host->mmc, mrq);
540 }
541
542 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
543 {
544 struct mvsd_host *host = mmc_priv(mmc);
545 void __iomem *iobase = host->base;
546 unsigned long flags;
547
548 spin_lock_irqsave(&host->lock, flags);
549 if (enable) {
550 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
551 host->intr_en |= MVSD_NOR_CARD_INT;
552 } else {
553 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
554 host->intr_en &= ~MVSD_NOR_CARD_INT;
555 }
556 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
557 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
558 spin_unlock_irqrestore(&host->lock, flags);
559 }
560
561 static void mvsd_power_up(struct mvsd_host *host)
562 {
563 void __iomem *iobase = host->base;
564 dev_dbg(host->dev, "power up\n");
565 mvsd_write(MVSD_NOR_INTR_EN, 0);
566 mvsd_write(MVSD_ERR_INTR_EN, 0);
567 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
568 mvsd_write(MVSD_XFER_MODE, 0);
569 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
570 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
571 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
572 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
573 }
574
575 static void mvsd_power_down(struct mvsd_host *host)
576 {
577 void __iomem *iobase = host->base;
578 dev_dbg(host->dev, "power down\n");
579 mvsd_write(MVSD_NOR_INTR_EN, 0);
580 mvsd_write(MVSD_ERR_INTR_EN, 0);
581 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
582 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
583 mvsd_write(MVSD_NOR_STATUS_EN, 0);
584 mvsd_write(MVSD_ERR_STATUS_EN, 0);
585 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
586 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
587 }
588
589 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
590 {
591 struct mvsd_host *host = mmc_priv(mmc);
592 void __iomem *iobase = host->base;
593 u32 ctrl_reg = 0;
594
595 if (ios->power_mode == MMC_POWER_UP)
596 mvsd_power_up(host);
597
598 if (ios->clock == 0) {
599 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
600 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
601 host->clock = 0;
602 dev_dbg(host->dev, "clock off\n");
603 } else if (ios->clock != host->clock) {
604 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
605 if (m > MVSD_BASE_DIV_MAX)
606 m = MVSD_BASE_DIV_MAX;
607 mvsd_write(MVSD_CLK_DIV, m);
608 host->clock = ios->clock;
609 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
610 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
611 ios->clock, host->base_clock / (m+1), m);
612 }
613
614 /* default transfer mode */
615 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
616 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
617
618 /* default to maximum timeout */
619 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
620 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
621
622 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
623 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
624
625 if (ios->bus_width == MMC_BUS_WIDTH_4)
626 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
627
628 /*
629 * The HI_SPEED_EN bit is causing trouble with many (but not all)
630 * high speed SD, SDHC and SDIO cards. Not enabling that bit
631 * makes all cards work. So let's just ignore that bit for now
632 * and revisit this issue if problems for not enabling this bit
633 * are ever reported.
634 */
635 #if 0
636 if (ios->timing == MMC_TIMING_MMC_HS ||
637 ios->timing == MMC_TIMING_SD_HS)
638 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
639 #endif
640
641 host->ctrl = ctrl_reg;
642 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
643 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
644 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
645 "push-pull" : "open-drain",
646 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
647 "4bit-width" : "1bit-width",
648 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
649 "high-speed" : "");
650
651 if (ios->power_mode == MMC_POWER_OFF)
652 mvsd_power_down(host);
653 }
654
655 static const struct mmc_host_ops mvsd_ops = {
656 .request = mvsd_request,
657 .get_ro = mmc_gpio_get_ro,
658 .set_ios = mvsd_set_ios,
659 .enable_sdio_irq = mvsd_enable_sdio_irq,
660 };
661
662 static void __init
663 mv_conf_mbus_windows(struct mvsd_host *host,
664 const struct mbus_dram_target_info *dram)
665 {
666 void __iomem *iobase = host->base;
667 int i;
668
669 for (i = 0; i < 4; i++) {
670 writel(0, iobase + MVSD_WINDOW_CTRL(i));
671 writel(0, iobase + MVSD_WINDOW_BASE(i));
672 }
673
674 for (i = 0; i < dram->num_cs; i++) {
675 const struct mbus_dram_window *cs = dram->cs + i;
676 writel(((cs->size - 1) & 0xffff0000) |
677 (cs->mbus_attr << 8) |
678 (dram->mbus_dram_target_id << 4) | 1,
679 iobase + MVSD_WINDOW_CTRL(i));
680 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
681 }
682 }
683
684 static int __init mvsd_probe(struct platform_device *pdev)
685 {
686 struct device_node *np = pdev->dev.of_node;
687 struct mmc_host *mmc = NULL;
688 struct mvsd_host *host = NULL;
689 const struct mbus_dram_target_info *dram;
690 struct resource *r;
691 int ret, irq;
692 int gpio_card_detect, gpio_write_protect;
693
694 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
695 irq = platform_get_irq(pdev, 0);
696 if (!r || irq < 0)
697 return -ENXIO;
698
699 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
700 if (!mmc) {
701 ret = -ENOMEM;
702 goto out;
703 }
704
705 host = mmc_priv(mmc);
706 host->mmc = mmc;
707 host->dev = &pdev->dev;
708
709 /*
710 * Some non-DT platforms do not pass a clock, and the clock
711 * frequency is passed through platform_data. On DT platforms,
712 * a clock must always be passed, even if there is no gatable
713 * clock associated to the SDIO interface (it can simply be a
714 * fixed rate clock).
715 */
716 host->clk = devm_clk_get(&pdev->dev, NULL);
717 if (!IS_ERR(host->clk))
718 clk_prepare_enable(host->clk);
719
720 if (np) {
721 if (IS_ERR(host->clk)) {
722 dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
723 ret = -EINVAL;
724 goto out;
725 }
726
727 host->base_clock = clk_get_rate(host->clk) / 2;
728 gpio_card_detect = of_get_named_gpio(np, "cd-gpios", 0);
729 gpio_write_protect = of_get_named_gpio(np, "wp-gpios", 0);
730 } else {
731 const struct mvsdio_platform_data *mvsd_data;
732 mvsd_data = pdev->dev.platform_data;
733 if (!mvsd_data) {
734 ret = -ENXIO;
735 goto out;
736 }
737 host->base_clock = mvsd_data->clock / 2;
738 gpio_card_detect = mvsd_data->gpio_card_detect;
739 gpio_write_protect = mvsd_data->gpio_write_protect;
740 }
741
742 mmc->ops = &mvsd_ops;
743
744 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
745 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
746 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
747
748 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
749 mmc->f_max = maxfreq;
750
751 mmc->max_blk_size = 2048;
752 mmc->max_blk_count = 65535;
753
754 mmc->max_segs = 1;
755 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
756 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
757
758 spin_lock_init(&host->lock);
759
760 host->base = devm_request_and_ioremap(&pdev->dev, r);
761 if (!host->base) {
762 ret = -ENOMEM;
763 goto out;
764 }
765
766 /* (Re-)program MBUS remapping windows if we are asked to. */
767 dram = mv_mbus_dram_info();
768 if (dram)
769 mv_conf_mbus_windows(host, dram);
770
771 mvsd_power_down(host);
772
773 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
774 if (ret) {
775 pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq);
776 goto out;
777 }
778
779 if (gpio_is_valid(gpio_card_detect)) {
780 ret = mmc_gpio_request_cd(mmc, gpio_card_detect);
781 if (ret)
782 goto out;
783 } else
784 mmc->caps |= MMC_CAP_NEEDS_POLL;
785
786 mmc_gpio_request_ro(mmc, gpio_write_protect);
787
788 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
789 platform_set_drvdata(pdev, mmc);
790 ret = mmc_add_host(mmc);
791 if (ret)
792 goto out;
793
794 pr_notice("%s: %s driver initialized, ",
795 mmc_hostname(mmc), DRIVER_NAME);
796 if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
797 printk("using GPIO %d for card detection\n",
798 gpio_card_detect);
799 else
800 printk("lacking card detect (fall back to polling)\n");
801 return 0;
802
803 out:
804 if (mmc) {
805 mmc_gpio_free_cd(mmc);
806 mmc_gpio_free_ro(mmc);
807 if (!IS_ERR(host->clk))
808 clk_disable_unprepare(host->clk);
809 mmc_free_host(mmc);
810 }
811
812 return ret;
813 }
814
815 static int __exit mvsd_remove(struct platform_device *pdev)
816 {
817 struct mmc_host *mmc = platform_get_drvdata(pdev);
818
819 struct mvsd_host *host = mmc_priv(mmc);
820
821 mmc_gpio_free_cd(mmc);
822 mmc_gpio_free_ro(mmc);
823 mmc_remove_host(mmc);
824 del_timer_sync(&host->timer);
825 mvsd_power_down(host);
826
827 if (!IS_ERR(host->clk))
828 clk_disable_unprepare(host->clk);
829 mmc_free_host(mmc);
830
831 platform_set_drvdata(pdev, NULL);
832 return 0;
833 }
834
835 #ifdef CONFIG_PM
836 static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
837 {
838 struct mmc_host *mmc = platform_get_drvdata(dev);
839 int ret = 0;
840
841 if (mmc)
842 ret = mmc_suspend_host(mmc);
843
844 return ret;
845 }
846
847 static int mvsd_resume(struct platform_device *dev)
848 {
849 struct mmc_host *mmc = platform_get_drvdata(dev);
850 int ret = 0;
851
852 if (mmc)
853 ret = mmc_resume_host(mmc);
854
855 return ret;
856 }
857 #else
858 #define mvsd_suspend NULL
859 #define mvsd_resume NULL
860 #endif
861
862 static const struct of_device_id mvsdio_dt_ids[] = {
863 { .compatible = "marvell,orion-sdio" },
864 { /* sentinel */ }
865 };
866 MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
867
868 static struct platform_driver mvsd_driver = {
869 .remove = __exit_p(mvsd_remove),
870 .suspend = mvsd_suspend,
871 .resume = mvsd_resume,
872 .driver = {
873 .name = DRIVER_NAME,
874 .of_match_table = mvsdio_dt_ids,
875 },
876 };
877
878 static int __init mvsd_init(void)
879 {
880 return platform_driver_probe(&mvsd_driver, mvsd_probe);
881 }
882
883 static void __exit mvsd_exit(void)
884 {
885 platform_driver_unregister(&mvsd_driver);
886 }
887
888 module_init(mvsd_init);
889 module_exit(mvsd_exit);
890
891 /* maximum card clock frequency (default 50MHz) */
892 module_param(maxfreq, int, 0);
893
894 /* force PIO transfers all the time */
895 module_param(nodma, int, 0);
896
897 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
898 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
899 MODULE_LICENSE("GPL");
900 MODULE_ALIAS("platform:mvsdio");
Linux kernel - Deliverables
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