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oprofile: introduce module_param oprofile.cpu_type
[deliverable/linux.git] / drivers / mmc / host / mvsdio.c
1 /*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/io.h>
15 #include <linux/platform_device.h>
16 #include <linux/mbus.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/mmc/host.h>
24
25 #include <asm/sizes.h>
26 #include <asm/unaligned.h>
27 #include <plat/mvsdio.h>
28
29 #include "mvsdio.h"
30
31 #define DRIVER_NAME "mvsdio"
32
33 static int maxfreq = MVSD_CLOCKRATE_MAX;
34 static int nodma;
35
36 struct mvsd_host {
37 void __iomem *base;
38 struct mmc_request *mrq;
39 spinlock_t lock;
40 unsigned int xfer_mode;
41 unsigned int intr_en;
42 unsigned int ctrl;
43 unsigned int pio_size;
44 void *pio_ptr;
45 unsigned int sg_frags;
46 unsigned int ns_per_clk;
47 unsigned int clock;
48 unsigned int base_clock;
49 struct timer_list timer;
50 struct mmc_host *mmc;
51 struct device *dev;
52 struct resource *res;
53 int irq;
54 int gpio_card_detect;
55 int gpio_write_protect;
56 };
57
58 #define mvsd_write(offs, val) writel(val, iobase + (offs))
59 #define mvsd_read(offs) readl(iobase + (offs))
60
61 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
62 {
63 void __iomem *iobase = host->base;
64 unsigned int tmout;
65 int tmout_index;
66
67 /* If timeout=0 then maximum timeout index is used. */
68 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
69 tmout += data->timeout_clks;
70 tmout_index = fls(tmout - 1) - 12;
71 if (tmout_index < 0)
72 tmout_index = 0;
73 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
74 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
75
76 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
77 (data->flags & MMC_DATA_READ) ? "read" : "write",
78 (u32)sg_virt(data->sg), data->blocks, data->blksz,
79 tmout, tmout_index);
80
81 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
82 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
83 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
84 mvsd_write(MVSD_BLK_COUNT, data->blocks);
85 mvsd_write(MVSD_BLK_SIZE, data->blksz);
86
87 if (nodma || (data->blksz | data->sg->offset) & 3) {
88 /*
89 * We cannot do DMA on a buffer which offset or size
90 * is not aligned on a 4-byte boundary.
91 */
92 host->pio_size = data->blocks * data->blksz;
93 host->pio_ptr = sg_virt(data->sg);
94 if (!nodma)
95 printk(KERN_DEBUG "%s: fallback to PIO for data "
96 "at 0x%p size %d\n",
97 mmc_hostname(host->mmc),
98 host->pio_ptr, host->pio_size);
99 return 1;
100 } else {
101 dma_addr_t phys_addr;
102 int dma_dir = (data->flags & MMC_DATA_READ) ?
103 DMA_FROM_DEVICE : DMA_TO_DEVICE;
104 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
105 data->sg_len, dma_dir);
106 phys_addr = sg_dma_address(data->sg);
107 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
108 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
109 return 0;
110 }
111 }
112
113 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
114 {
115 struct mvsd_host *host = mmc_priv(mmc);
116 void __iomem *iobase = host->base;
117 struct mmc_command *cmd = mrq->cmd;
118 u32 cmdreg = 0, xfer = 0, intr = 0;
119 unsigned long flags;
120
121 BUG_ON(host->mrq != NULL);
122 host->mrq = mrq;
123
124 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
125 cmd->opcode, mvsd_read(MVSD_HW_STATE));
126
127 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
128
129 if (cmd->flags & MMC_RSP_BUSY)
130 cmdreg |= MVSD_CMD_RSP_48BUSY;
131 else if (cmd->flags & MMC_RSP_136)
132 cmdreg |= MVSD_CMD_RSP_136;
133 else if (cmd->flags & MMC_RSP_PRESENT)
134 cmdreg |= MVSD_CMD_RSP_48;
135 else
136 cmdreg |= MVSD_CMD_RSP_NONE;
137
138 if (cmd->flags & MMC_RSP_CRC)
139 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
140
141 if (cmd->flags & MMC_RSP_OPCODE)
142 cmdreg |= MVSD_CMD_INDX_CHECK;
143
144 if (cmd->flags & MMC_RSP_PRESENT) {
145 cmdreg |= MVSD_UNEXPECTED_RESP;
146 intr |= MVSD_NOR_UNEXP_RSP;
147 }
148
149 if (mrq->data) {
150 struct mmc_data *data = mrq->data;
151 int pio;
152
153 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
154 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
155 if (data->flags & MMC_DATA_READ)
156 xfer |= MVSD_XFER_MODE_TO_HOST;
157
158 pio = mvsd_setup_data(host, data);
159 if (pio) {
160 xfer |= MVSD_XFER_MODE_PIO;
161 /* PIO section of mvsd_irq has comments on those bits */
162 if (data->flags & MMC_DATA_WRITE)
163 intr |= MVSD_NOR_TX_AVAIL;
164 else if (host->pio_size > 32)
165 intr |= MVSD_NOR_RX_FIFO_8W;
166 else
167 intr |= MVSD_NOR_RX_READY;
168 }
169
170 if (data->stop) {
171 struct mmc_command *stop = data->stop;
172 u32 cmd12reg = 0;
173
174 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
175 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
176
177 if (stop->flags & MMC_RSP_BUSY)
178 cmd12reg |= MVSD_AUTOCMD12_BUSY;
179 if (stop->flags & MMC_RSP_OPCODE)
180 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
181 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
182 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
183
184 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
185 intr |= MVSD_NOR_AUTOCMD12_DONE;
186 } else {
187 intr |= MVSD_NOR_XFER_DONE;
188 }
189 } else {
190 intr |= MVSD_NOR_CMD_DONE;
191 }
192
193 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
194 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
195
196 spin_lock_irqsave(&host->lock, flags);
197
198 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
199 host->xfer_mode |= xfer;
200 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
201
202 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
203 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
204 mvsd_write(MVSD_CMD, cmdreg);
205
206 host->intr_en &= MVSD_NOR_CARD_INT;
207 host->intr_en |= intr | MVSD_NOR_ERROR;
208 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
209 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
210
211 mod_timer(&host->timer, jiffies + 5 * HZ);
212
213 spin_unlock_irqrestore(&host->lock, flags);
214 }
215
216 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
217 u32 err_status)
218 {
219 void __iomem *iobase = host->base;
220
221 if (cmd->flags & MMC_RSP_136) {
222 unsigned int response[8], i;
223 for (i = 0; i < 8; i++)
224 response[i] = mvsd_read(MVSD_RSP(i));
225 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
226 ((response[1] & 0xffff) << 6) |
227 ((response[2] & 0xfc00) >> 10);
228 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
229 ((response[3] & 0xffff) << 6) |
230 ((response[4] & 0xfc00) >> 10);
231 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
232 ((response[5] & 0xffff) << 6) |
233 ((response[6] & 0xfc00) >> 10);
234 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
235 ((response[7] & 0x3fff) << 8);
236 } else if (cmd->flags & MMC_RSP_PRESENT) {
237 unsigned int response[3], i;
238 for (i = 0; i < 3; i++)
239 response[i] = mvsd_read(MVSD_RSP(i));
240 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
241 ((response[1] & 0xffff) << (14 - 8)) |
242 ((response[0] & 0x03ff) << (30 - 8));
243 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
244 cmd->resp[2] = 0;
245 cmd->resp[3] = 0;
246 }
247
248 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
249 cmd->error = -ETIMEDOUT;
250 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
251 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
252 cmd->error = -EILSEQ;
253 }
254 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
255 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
256 MVSD_ERR_CMD_STARTBIT);
257
258 return err_status;
259 }
260
261 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
262 u32 err_status)
263 {
264 void __iomem *iobase = host->base;
265
266 if (host->pio_ptr) {
267 host->pio_ptr = NULL;
268 host->pio_size = 0;
269 } else {
270 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
271 (data->flags & MMC_DATA_READ) ?
272 DMA_FROM_DEVICE : DMA_TO_DEVICE);
273 }
274
275 if (err_status & MVSD_ERR_DATA_TIMEOUT)
276 data->error = -ETIMEDOUT;
277 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
278 data->error = -EILSEQ;
279 else if (err_status & MVSD_ERR_XFER_SIZE)
280 data->error = -EBADE;
281 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
282 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
283
284 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
285 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
286 data->bytes_xfered =
287 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
288 /* We can't be sure about the last block when errors are detected */
289 if (data->bytes_xfered && data->error)
290 data->bytes_xfered -= data->blksz;
291
292 /* Handle Auto cmd 12 response */
293 if (data->stop) {
294 unsigned int response[3], i;
295 for (i = 0; i < 3; i++)
296 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
297 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
298 ((response[1] & 0xffff) << (14 - 8)) |
299 ((response[0] & 0x03ff) << (30 - 8));
300 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
301 data->stop->resp[2] = 0;
302 data->stop->resp[3] = 0;
303
304 if (err_status & MVSD_ERR_AUTOCMD12) {
305 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
306 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
307 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
308 data->stop->error = -ENOEXEC;
309 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
310 data->stop->error = -ETIMEDOUT;
311 else if (err_cmd12)
312 data->stop->error = -EILSEQ;
313 err_status &= ~MVSD_ERR_AUTOCMD12;
314 }
315 }
316
317 return err_status;
318 }
319
320 static irqreturn_t mvsd_irq(int irq, void *dev)
321 {
322 struct mvsd_host *host = dev;
323 void __iomem *iobase = host->base;
324 u32 intr_status, intr_done_mask;
325 int irq_handled = 0;
326
327 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
328 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
329 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
330 mvsd_read(MVSD_HW_STATE));
331
332 spin_lock(&host->lock);
333
334 /* PIO handling, if needed. Messy business... */
335 if (host->pio_size &&
336 (intr_status & host->intr_en &
337 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
338 u16 *p = host->pio_ptr;
339 int s = host->pio_size;
340 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
341 readsw(iobase + MVSD_FIFO, p, 16);
342 p += 16;
343 s -= 32;
344 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
345 }
346 /*
347 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
348 * doesn't appear to assert when there is exactly 32 bytes
349 * (8 words) left to fetch in a transfer.
350 */
351 if (s <= 32) {
352 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
353 put_unaligned(mvsd_read(MVSD_FIFO), p++);
354 put_unaligned(mvsd_read(MVSD_FIFO), p++);
355 s -= 4;
356 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
357 }
358 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
359 u16 val[2] = {0, 0};
360 val[0] = mvsd_read(MVSD_FIFO);
361 val[1] = mvsd_read(MVSD_FIFO);
362 memcpy(p, &val, s);
363 s = 0;
364 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
365 }
366 if (s == 0) {
367 host->intr_en &=
368 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
369 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
370 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
371 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
372 host->intr_en |= MVSD_NOR_RX_READY;
373 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
374 }
375 }
376 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
377 s, intr_status, mvsd_read(MVSD_HW_STATE));
378 host->pio_ptr = p;
379 host->pio_size = s;
380 irq_handled = 1;
381 } else if (host->pio_size &&
382 (intr_status & host->intr_en &
383 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
384 u16 *p = host->pio_ptr;
385 int s = host->pio_size;
386 /*
387 * The TX_FIFO_8W bit is unreliable. When set, bursting
388 * 16 halfwords all at once in the FIFO drops data. Actually
389 * TX_AVAIL does go off after only one word is pushed even if
390 * TX_FIFO_8W remains set.
391 */
392 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
393 mvsd_write(MVSD_FIFO, get_unaligned(p++));
394 mvsd_write(MVSD_FIFO, get_unaligned(p++));
395 s -= 4;
396 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
397 }
398 if (s < 4) {
399 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
400 u16 val[2] = {0, 0};
401 memcpy(&val, p, s);
402 mvsd_write(MVSD_FIFO, val[0]);
403 mvsd_write(MVSD_FIFO, val[1]);
404 s = 0;
405 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
406 }
407 if (s == 0) {
408 host->intr_en &=
409 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
410 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
411 }
412 }
413 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
414 s, intr_status, mvsd_read(MVSD_HW_STATE));
415 host->pio_ptr = p;
416 host->pio_size = s;
417 irq_handled = 1;
418 }
419
420 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
421
422 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
423 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
424 if (intr_status & host->intr_en & ~intr_done_mask) {
425 struct mmc_request *mrq = host->mrq;
426 struct mmc_command *cmd = mrq->cmd;
427 u32 err_status = 0;
428
429 del_timer(&host->timer);
430 host->mrq = NULL;
431
432 host->intr_en &= MVSD_NOR_CARD_INT;
433 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
434 mvsd_write(MVSD_ERR_INTR_EN, 0);
435
436 spin_unlock(&host->lock);
437
438 if (intr_status & MVSD_NOR_UNEXP_RSP) {
439 cmd->error = -EPROTO;
440 } else if (intr_status & MVSD_NOR_ERROR) {
441 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
442 dev_dbg(host->dev, "err 0x%04x\n", err_status);
443 }
444
445 err_status = mvsd_finish_cmd(host, cmd, err_status);
446 if (mrq->data)
447 err_status = mvsd_finish_data(host, mrq->data, err_status);
448 if (err_status) {
449 printk(KERN_ERR "%s: unhandled error status %#04x\n",
450 mmc_hostname(host->mmc), err_status);
451 cmd->error = -ENOMSG;
452 }
453
454 mmc_request_done(host->mmc, mrq);
455 irq_handled = 1;
456 } else
457 spin_unlock(&host->lock);
458
459 if (intr_status & MVSD_NOR_CARD_INT) {
460 mmc_signal_sdio_irq(host->mmc);
461 irq_handled = 1;
462 }
463
464 if (irq_handled)
465 return IRQ_HANDLED;
466
467 printk(KERN_ERR "%s: unhandled interrupt status=0x%04x en=0x%04x "
468 "pio=%d\n", mmc_hostname(host->mmc), intr_status,
469 host->intr_en, host->pio_size);
470 return IRQ_NONE;
471 }
472
473 static void mvsd_timeout_timer(unsigned long data)
474 {
475 struct mvsd_host *host = (struct mvsd_host *)data;
476 void __iomem *iobase = host->base;
477 struct mmc_request *mrq;
478 unsigned long flags;
479
480 spin_lock_irqsave(&host->lock, flags);
481 mrq = host->mrq;
482 if (mrq) {
483 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt.\n",
484 mmc_hostname(host->mmc));
485 printk(KERN_ERR "%s: hw_state=0x%04x, intr_status=0x%04x "
486 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
487 mvsd_read(MVSD_HW_STATE),
488 mvsd_read(MVSD_NOR_INTR_STATUS),
489 mvsd_read(MVSD_NOR_INTR_EN));
490
491 host->mrq = NULL;
492
493 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
494
495 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
496 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
497
498 host->intr_en &= MVSD_NOR_CARD_INT;
499 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
500 mvsd_write(MVSD_ERR_INTR_EN, 0);
501 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
502
503 mrq->cmd->error = -ETIMEDOUT;
504 mvsd_finish_cmd(host, mrq->cmd, 0);
505 if (mrq->data) {
506 mrq->data->error = -ETIMEDOUT;
507 mvsd_finish_data(host, mrq->data, 0);
508 }
509 }
510 spin_unlock_irqrestore(&host->lock, flags);
511
512 if (mrq)
513 mmc_request_done(host->mmc, mrq);
514 }
515
516 static irqreturn_t mvsd_card_detect_irq(int irq, void *dev)
517 {
518 struct mvsd_host *host = dev;
519 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
520 return IRQ_HANDLED;
521 }
522
523 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
524 {
525 struct mvsd_host *host = mmc_priv(mmc);
526 void __iomem *iobase = host->base;
527 unsigned long flags;
528
529 spin_lock_irqsave(&host->lock, flags);
530 if (enable) {
531 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
532 host->intr_en |= MVSD_NOR_CARD_INT;
533 } else {
534 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
535 host->intr_en &= ~MVSD_NOR_CARD_INT;
536 }
537 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
538 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
539 spin_unlock_irqrestore(&host->lock, flags);
540 }
541
542 static int mvsd_get_ro(struct mmc_host *mmc)
543 {
544 struct mvsd_host *host = mmc_priv(mmc);
545
546 if (host->gpio_write_protect)
547 return gpio_get_value(host->gpio_write_protect);
548
549 /*
550 * Board doesn't support read only detection; let the mmc core
551 * decide what to do.
552 */
553 return -ENOSYS;
554 }
555
556 static void mvsd_power_up(struct mvsd_host *host)
557 {
558 void __iomem *iobase = host->base;
559 dev_dbg(host->dev, "power up\n");
560 mvsd_write(MVSD_NOR_INTR_EN, 0);
561 mvsd_write(MVSD_ERR_INTR_EN, 0);
562 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
563 mvsd_write(MVSD_XFER_MODE, 0);
564 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
565 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
566 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
567 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
568 }
569
570 static void mvsd_power_down(struct mvsd_host *host)
571 {
572 void __iomem *iobase = host->base;
573 dev_dbg(host->dev, "power down\n");
574 mvsd_write(MVSD_NOR_INTR_EN, 0);
575 mvsd_write(MVSD_ERR_INTR_EN, 0);
576 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
577 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
578 mvsd_write(MVSD_NOR_STATUS_EN, 0);
579 mvsd_write(MVSD_ERR_STATUS_EN, 0);
580 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
581 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
582 }
583
584 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
585 {
586 struct mvsd_host *host = mmc_priv(mmc);
587 void __iomem *iobase = host->base;
588 u32 ctrl_reg = 0;
589
590 if (ios->power_mode == MMC_POWER_UP)
591 mvsd_power_up(host);
592
593 if (ios->clock == 0) {
594 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
595 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
596 host->clock = 0;
597 dev_dbg(host->dev, "clock off\n");
598 } else if (ios->clock != host->clock) {
599 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
600 if (m > MVSD_BASE_DIV_MAX)
601 m = MVSD_BASE_DIV_MAX;
602 mvsd_write(MVSD_CLK_DIV, m);
603 host->clock = ios->clock;
604 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
605 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
606 ios->clock, host->base_clock / (m+1), m);
607 }
608
609 /* default transfer mode */
610 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
611 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
612
613 /* default to maximum timeout */
614 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
615 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
616
617 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
618 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
619
620 if (ios->bus_width == MMC_BUS_WIDTH_4)
621 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
622
623 if (ios->timing == MMC_TIMING_MMC_HS ||
624 ios->timing == MMC_TIMING_SD_HS)
625 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
626
627 host->ctrl = ctrl_reg;
628 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
629 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
630 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
631 "push-pull" : "open-drain",
632 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
633 "4bit-width" : "1bit-width",
634 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
635 "high-speed" : "");
636
637 if (ios->power_mode == MMC_POWER_OFF)
638 mvsd_power_down(host);
639 }
640
641 static const struct mmc_host_ops mvsd_ops = {
642 .request = mvsd_request,
643 .get_ro = mvsd_get_ro,
644 .set_ios = mvsd_set_ios,
645 .enable_sdio_irq = mvsd_enable_sdio_irq,
646 };
647
648 static void __init mv_conf_mbus_windows(struct mvsd_host *host,
649 struct mbus_dram_target_info *dram)
650 {
651 void __iomem *iobase = host->base;
652 int i;
653
654 for (i = 0; i < 4; i++) {
655 writel(0, iobase + MVSD_WINDOW_CTRL(i));
656 writel(0, iobase + MVSD_WINDOW_BASE(i));
657 }
658
659 for (i = 0; i < dram->num_cs; i++) {
660 struct mbus_dram_window *cs = dram->cs + i;
661 writel(((cs->size - 1) & 0xffff0000) |
662 (cs->mbus_attr << 8) |
663 (dram->mbus_dram_target_id << 4) | 1,
664 iobase + MVSD_WINDOW_CTRL(i));
665 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
666 }
667 }
668
669 static int __init mvsd_probe(struct platform_device *pdev)
670 {
671 struct mmc_host *mmc = NULL;
672 struct mvsd_host *host = NULL;
673 const struct mvsdio_platform_data *mvsd_data;
674 struct resource *r;
675 int ret, irq;
676
677 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
678 irq = platform_get_irq(pdev, 0);
679 mvsd_data = pdev->dev.platform_data;
680 if (!r || irq < 0 || !mvsd_data)
681 return -ENXIO;
682
683 r = request_mem_region(r->start, SZ_1K, DRIVER_NAME);
684 if (!r)
685 return -EBUSY;
686
687 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
688 if (!mmc) {
689 ret = -ENOMEM;
690 goto out;
691 }
692
693 host = mmc_priv(mmc);
694 host->mmc = mmc;
695 host->dev = &pdev->dev;
696 host->res = r;
697 host->base_clock = mvsd_data->clock / 2;
698
699 mmc->ops = &mvsd_ops;
700
701 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
702 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
703 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
704
705 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
706 mmc->f_max = maxfreq;
707
708 mmc->max_blk_size = 2048;
709 mmc->max_blk_count = 65535;
710
711 mmc->max_hw_segs = 1;
712 mmc->max_phys_segs = 1;
713 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
714 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
715
716 spin_lock_init(&host->lock);
717
718 host->base = ioremap(r->start, SZ_4K);
719 if (!host->base) {
720 ret = -ENOMEM;
721 goto out;
722 }
723
724 /* (Re-)program MBUS remapping windows if we are asked to. */
725 if (mvsd_data->dram != NULL)
726 mv_conf_mbus_windows(host, mvsd_data->dram);
727
728 mvsd_power_down(host);
729
730 ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host);
731 if (ret) {
732 printk(KERN_ERR "%s: cannot assign irq %d\n", DRIVER_NAME, irq);
733 goto out;
734 } else
735 host->irq = irq;
736
737 if (mvsd_data->gpio_card_detect) {
738 ret = gpio_request(mvsd_data->gpio_card_detect,
739 DRIVER_NAME " cd");
740 if (ret == 0) {
741 gpio_direction_input(mvsd_data->gpio_card_detect);
742 irq = gpio_to_irq(mvsd_data->gpio_card_detect);
743 ret = request_irq(irq, mvsd_card_detect_irq,
744 IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
745 DRIVER_NAME " cd", host);
746 if (ret == 0)
747 host->gpio_card_detect =
748 mvsd_data->gpio_card_detect;
749 else
750 gpio_free(mvsd_data->gpio_card_detect);
751 }
752 }
753 if (!host->gpio_card_detect)
754 mmc->caps |= MMC_CAP_NEEDS_POLL;
755
756 if (mvsd_data->gpio_write_protect) {
757 ret = gpio_request(mvsd_data->gpio_write_protect,
758 DRIVER_NAME " wp");
759 if (ret == 0) {
760 gpio_direction_input(mvsd_data->gpio_write_protect);
761 host->gpio_write_protect =
762 mvsd_data->gpio_write_protect;
763 }
764 }
765
766 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
767 platform_set_drvdata(pdev, mmc);
768 ret = mmc_add_host(mmc);
769 if (ret)
770 goto out;
771
772 printk(KERN_NOTICE "%s: %s driver initialized, ",
773 mmc_hostname(mmc), DRIVER_NAME);
774 if (host->gpio_card_detect)
775 printk("using GPIO %d for card detection\n",
776 host->gpio_card_detect);
777 else
778 printk("lacking card detect (fall back to polling)\n");
779 return 0;
780
781 out:
782 if (host) {
783 if (host->irq)
784 free_irq(host->irq, host);
785 if (host->gpio_card_detect) {
786 free_irq(gpio_to_irq(host->gpio_card_detect), host);
787 gpio_free(host->gpio_card_detect);
788 }
789 if (host->gpio_write_protect)
790 gpio_free(host->gpio_write_protect);
791 if (host->base)
792 iounmap(host->base);
793 }
794 if (r)
795 release_resource(r);
796 if (mmc)
797 mmc_free_host(mmc);
798
799 return ret;
800 }
801
802 static int __exit mvsd_remove(struct platform_device *pdev)
803 {
804 struct mmc_host *mmc = platform_get_drvdata(pdev);
805
806 if (mmc) {
807 struct mvsd_host *host = mmc_priv(mmc);
808
809 if (host->gpio_card_detect) {
810 free_irq(gpio_to_irq(host->gpio_card_detect), host);
811 gpio_free(host->gpio_card_detect);
812 }
813 mmc_remove_host(mmc);
814 free_irq(host->irq, host);
815 if (host->gpio_write_protect)
816 gpio_free(host->gpio_write_protect);
817 del_timer_sync(&host->timer);
818 mvsd_power_down(host);
819 iounmap(host->base);
820 release_resource(host->res);
821 mmc_free_host(mmc);
822 }
823 platform_set_drvdata(pdev, NULL);
824 return 0;
825 }
826
827 #ifdef CONFIG_PM
828 static int mvsd_suspend(struct platform_device *dev, pm_message_t state,
829 u32 level)
830 {
831 struct mmc_host *mmc = platform_get_drvdata(dev);
832 int ret = 0;
833
834 if (mmc && level == SUSPEND_DISABLE)
835 ret = mmc_suspend_host(mmc, state);
836
837 return ret;
838 }
839
840 static int mvsd_resume(struct platform_device *dev, u32 level)
841 {
842 struct mmc_host *mmc = platform_dev_get_drvdata(dev);
843 int ret = 0;
844
845 if (mmc && level == RESUME_ENABLE)
846 ret = mmc_resume_host(mmc);
847
848 return ret;
849 }
850 #else
851 #define mvsd_suspend NULL
852 #define mvsd_resume NULL
853 #endif
854
855 static struct platform_driver mvsd_driver = {
856 .remove = __exit_p(mvsd_remove),
857 .suspend = mvsd_suspend,
858 .resume = mvsd_resume,
859 .driver = {
860 .name = DRIVER_NAME,
861 },
862 };
863
864 static int __init mvsd_init(void)
865 {
866 return platform_driver_probe(&mvsd_driver, mvsd_probe);
867 }
868
869 static void __exit mvsd_exit(void)
870 {
871 platform_driver_unregister(&mvsd_driver);
872 }
873
874 module_init(mvsd_init);
875 module_exit(mvsd_exit);
876
877 /* maximum card clock frequency (default 50MHz) */
878 module_param(maxfreq, int, 0);
879
880 /* force PIO transfers all the time */
881 module_param(nodma, int, 0);
882
883 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
884 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
885 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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