2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
36 #include <linux/types.h>
40 #include <asm/sizes.h>
41 #include <linux/platform_data/mmc-mxcmmc.h>
43 #include <linux/platform_data/dma-imx.h>
45 #define DRIVER_NAME "mxc-mmc"
46 #define MXCMCI_TIMEOUT_MS 10000
48 #define MMC_REG_STR_STP_CLK 0x00
49 #define MMC_REG_STATUS 0x04
50 #define MMC_REG_CLK_RATE 0x08
51 #define MMC_REG_CMD_DAT_CONT 0x0C
52 #define MMC_REG_RES_TO 0x10
53 #define MMC_REG_READ_TO 0x14
54 #define MMC_REG_BLK_LEN 0x18
55 #define MMC_REG_NOB 0x1C
56 #define MMC_REG_REV_NO 0x20
57 #define MMC_REG_INT_CNTR 0x24
58 #define MMC_REG_CMD 0x28
59 #define MMC_REG_ARG 0x2C
60 #define MMC_REG_RES_FIFO 0x34
61 #define MMC_REG_BUFFER_ACCESS 0x38
63 #define STR_STP_CLK_RESET (1 << 3)
64 #define STR_STP_CLK_START_CLK (1 << 1)
65 #define STR_STP_CLK_STOP_CLK (1 << 0)
67 #define STATUS_CARD_INSERTION (1 << 31)
68 #define STATUS_CARD_REMOVAL (1 << 30)
69 #define STATUS_YBUF_EMPTY (1 << 29)
70 #define STATUS_XBUF_EMPTY (1 << 28)
71 #define STATUS_YBUF_FULL (1 << 27)
72 #define STATUS_XBUF_FULL (1 << 26)
73 #define STATUS_BUF_UND_RUN (1 << 25)
74 #define STATUS_BUF_OVFL (1 << 24)
75 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
76 #define STATUS_END_CMD_RESP (1 << 13)
77 #define STATUS_WRITE_OP_DONE (1 << 12)
78 #define STATUS_DATA_TRANS_DONE (1 << 11)
79 #define STATUS_READ_OP_DONE (1 << 11)
80 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
81 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
82 #define STATUS_BUF_READ_RDY (1 << 7)
83 #define STATUS_BUF_WRITE_RDY (1 << 6)
84 #define STATUS_RESP_CRC_ERR (1 << 5)
85 #define STATUS_CRC_READ_ERR (1 << 3)
86 #define STATUS_CRC_WRITE_ERR (1 << 2)
87 #define STATUS_TIME_OUT_RESP (1 << 1)
88 #define STATUS_TIME_OUT_READ (1 << 0)
89 #define STATUS_ERR_MASK 0x2f
91 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
92 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
93 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
94 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
95 #define CMD_DAT_CONT_INIT (1 << 7)
96 #define CMD_DAT_CONT_WRITE (1 << 4)
97 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
98 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
99 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
100 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
102 #define INT_SDIO_INT_WKP_EN (1 << 18)
103 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
104 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
105 #define INT_CARD_INSERTION_EN (1 << 15)
106 #define INT_CARD_REMOVAL_EN (1 << 14)
107 #define INT_SDIO_IRQ_EN (1 << 13)
108 #define INT_DAT0_EN (1 << 12)
109 #define INT_BUF_READ_EN (1 << 4)
110 #define INT_BUF_WRITE_EN (1 << 3)
111 #define INT_END_CMD_RES_EN (1 << 2)
112 #define INT_WRITE_OP_DONE_EN (1 << 1)
113 #define INT_READ_OP_EN (1 << 0)
121 struct mmc_host
*mmc
;
122 struct resource
*res
;
126 struct dma_chan
*dma
;
127 struct dma_async_tx_descriptor
*desc
;
129 int default_irq_mask
;
131 unsigned int power_mode
;
132 struct imxmmc_platform_data
*pdata
;
134 struct mmc_request
*req
;
135 struct mmc_command
*cmd
;
136 struct mmc_data
*data
;
138 unsigned int datasize
;
139 unsigned int dma_dir
;
149 struct work_struct datawork
;
152 struct regulator
*vcc
;
156 struct dma_slave_config dma_slave_config
;
157 struct imx_dma_data dma_data
;
159 struct timer_list watchdog
;
160 enum mxcmci_type devtype
;
163 static struct platform_device_id mxcmci_devtype
[] = {
166 .driver_data
= IMX21_MMC
,
169 .driver_data
= IMX31_MMC
,
174 MODULE_DEVICE_TABLE(platform
, mxcmci_devtype
);
176 static inline int is_imx31_mmc(struct mxcmci_host
*host
)
178 return host
->devtype
== IMX31_MMC
;
181 static void mxcmci_set_clk_rate(struct mxcmci_host
*host
, unsigned int clk_ios
);
183 static inline void mxcmci_init_ocr(struct mxcmci_host
*host
)
185 host
->vcc
= regulator_get(mmc_dev(host
->mmc
), "vmmc");
187 if (IS_ERR(host
->vcc
)) {
190 host
->mmc
->ocr_avail
= mmc_regulator_get_ocrmask(host
->vcc
);
191 if (host
->pdata
&& host
->pdata
->ocr_avail
)
192 dev_warn(mmc_dev(host
->mmc
),
193 "pdata->ocr_avail will not be used\n");
196 if (host
->vcc
== NULL
) {
197 /* fall-back to platform data */
198 if (host
->pdata
&& host
->pdata
->ocr_avail
)
199 host
->mmc
->ocr_avail
= host
->pdata
->ocr_avail
;
201 host
->mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
205 static inline void mxcmci_set_power(struct mxcmci_host
*host
,
206 unsigned char power_mode
,
210 if (power_mode
== MMC_POWER_UP
)
211 mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, vdd
);
212 else if (power_mode
== MMC_POWER_OFF
)
213 mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, 0);
216 if (host
->pdata
&& host
->pdata
->setpower
)
217 host
->pdata
->setpower(mmc_dev(host
->mmc
), vdd
);
220 static inline int mxcmci_use_dma(struct mxcmci_host
*host
)
225 static void mxcmci_softreset(struct mxcmci_host
*host
)
229 dev_dbg(mmc_dev(host
->mmc
), "mxcmci_softreset\n");
232 writew(STR_STP_CLK_RESET
, host
->base
+ MMC_REG_STR_STP_CLK
);
233 writew(STR_STP_CLK_RESET
| STR_STP_CLK_START_CLK
,
234 host
->base
+ MMC_REG_STR_STP_CLK
);
236 for (i
= 0; i
< 8; i
++)
237 writew(STR_STP_CLK_START_CLK
, host
->base
+ MMC_REG_STR_STP_CLK
);
239 writew(0xff, host
->base
+ MMC_REG_RES_TO
);
241 static int mxcmci_setup_dma(struct mmc_host
*mmc
);
243 static int mxcmci_setup_data(struct mxcmci_host
*host
, struct mmc_data
*data
)
245 unsigned int nob
= data
->blocks
;
246 unsigned int blksz
= data
->blksz
;
247 unsigned int datasize
= nob
* blksz
;
248 struct scatterlist
*sg
;
249 enum dma_transfer_direction slave_dirn
;
252 if (data
->flags
& MMC_DATA_STREAM
)
256 data
->bytes_xfered
= 0;
258 writew(nob
, host
->base
+ MMC_REG_NOB
);
259 writew(blksz
, host
->base
+ MMC_REG_BLK_LEN
);
260 host
->datasize
= datasize
;
262 if (!mxcmci_use_dma(host
))
265 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
266 if (sg
->offset
& 3 || sg
->length
& 3) {
272 if (data
->flags
& MMC_DATA_READ
) {
273 host
->dma_dir
= DMA_FROM_DEVICE
;
274 slave_dirn
= DMA_DEV_TO_MEM
;
276 host
->dma_dir
= DMA_TO_DEVICE
;
277 slave_dirn
= DMA_MEM_TO_DEV
;
280 nents
= dma_map_sg(host
->dma
->device
->dev
, data
->sg
,
281 data
->sg_len
, host
->dma_dir
);
282 if (nents
!= data
->sg_len
)
285 host
->desc
= dmaengine_prep_slave_sg(host
->dma
,
286 data
->sg
, data
->sg_len
, slave_dirn
,
287 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
290 dma_unmap_sg(host
->dma
->device
->dev
, data
->sg
, data
->sg_len
,
293 return 0; /* Fall back to PIO */
297 dmaengine_submit(host
->desc
);
298 dma_async_issue_pending(host
->dma
);
300 mod_timer(&host
->watchdog
, jiffies
+ msecs_to_jiffies(MXCMCI_TIMEOUT_MS
));
305 static void mxcmci_cmd_done(struct mxcmci_host
*host
, unsigned int stat
);
306 static void mxcmci_data_done(struct mxcmci_host
*host
, unsigned int stat
);
308 static void mxcmci_dma_callback(void *data
)
310 struct mxcmci_host
*host
= data
;
313 del_timer(&host
->watchdog
);
315 stat
= readl(host
->base
+ MMC_REG_STATUS
);
316 writel(stat
& ~STATUS_DATA_TRANS_DONE
, host
->base
+ MMC_REG_STATUS
);
318 dev_dbg(mmc_dev(host
->mmc
), "%s: 0x%08x\n", __func__
, stat
);
320 if (stat
& STATUS_READ_OP_DONE
)
321 writel(STATUS_READ_OP_DONE
, host
->base
+ MMC_REG_STATUS
);
323 mxcmci_data_done(host
, stat
);
326 static int mxcmci_start_cmd(struct mxcmci_host
*host
, struct mmc_command
*cmd
,
329 u32 int_cntr
= host
->default_irq_mask
;
332 WARN_ON(host
->cmd
!= NULL
);
335 switch (mmc_resp_type(cmd
)) {
336 case MMC_RSP_R1
: /* short CRC, OPCODE */
337 case MMC_RSP_R1B
:/* short CRC, OPCODE, BUSY */
338 cmdat
|= CMD_DAT_CONT_RESPONSE_48BIT_CRC
;
340 case MMC_RSP_R2
: /* long 136 bit + CRC */
341 cmdat
|= CMD_DAT_CONT_RESPONSE_136BIT
;
343 case MMC_RSP_R3
: /* short */
344 cmdat
|= CMD_DAT_CONT_RESPONSE_48BIT
;
349 dev_err(mmc_dev(host
->mmc
), "unhandled response type 0x%x\n",
351 cmd
->error
= -EINVAL
;
355 int_cntr
= INT_END_CMD_RES_EN
;
357 if (mxcmci_use_dma(host
)) {
358 if (host
->dma_dir
== DMA_FROM_DEVICE
) {
359 host
->desc
->callback
= mxcmci_dma_callback
;
360 host
->desc
->callback_param
= host
;
362 int_cntr
|= INT_WRITE_OP_DONE_EN
;
366 spin_lock_irqsave(&host
->lock
, flags
);
368 int_cntr
|= INT_SDIO_IRQ_EN
;
369 writel(int_cntr
, host
->base
+ MMC_REG_INT_CNTR
);
370 spin_unlock_irqrestore(&host
->lock
, flags
);
372 writew(cmd
->opcode
, host
->base
+ MMC_REG_CMD
);
373 writel(cmd
->arg
, host
->base
+ MMC_REG_ARG
);
374 writew(cmdat
, host
->base
+ MMC_REG_CMD_DAT_CONT
);
379 static void mxcmci_finish_request(struct mxcmci_host
*host
,
380 struct mmc_request
*req
)
382 u32 int_cntr
= host
->default_irq_mask
;
385 spin_lock_irqsave(&host
->lock
, flags
);
387 int_cntr
|= INT_SDIO_IRQ_EN
;
388 writel(int_cntr
, host
->base
+ MMC_REG_INT_CNTR
);
389 spin_unlock_irqrestore(&host
->lock
, flags
);
395 mmc_request_done(host
->mmc
, req
);
398 static int mxcmci_finish_data(struct mxcmci_host
*host
, unsigned int stat
)
400 struct mmc_data
*data
= host
->data
;
403 if (mxcmci_use_dma(host
))
404 dma_unmap_sg(host
->dma
->device
->dev
, data
->sg
, data
->sg_len
,
407 if (stat
& STATUS_ERR_MASK
) {
408 dev_dbg(mmc_dev(host
->mmc
), "request failed. status: 0x%08x\n",
410 if (stat
& STATUS_CRC_READ_ERR
) {
411 dev_err(mmc_dev(host
->mmc
), "%s: -EILSEQ\n", __func__
);
412 data
->error
= -EILSEQ
;
413 } else if (stat
& STATUS_CRC_WRITE_ERR
) {
414 u32 err_code
= (stat
>> 9) & 0x3;
415 if (err_code
== 2) { /* No CRC response */
416 dev_err(mmc_dev(host
->mmc
),
417 "%s: No CRC -ETIMEDOUT\n", __func__
);
418 data
->error
= -ETIMEDOUT
;
420 dev_err(mmc_dev(host
->mmc
),
421 "%s: -EILSEQ\n", __func__
);
422 data
->error
= -EILSEQ
;
424 } else if (stat
& STATUS_TIME_OUT_READ
) {
425 dev_err(mmc_dev(host
->mmc
),
426 "%s: read -ETIMEDOUT\n", __func__
);
427 data
->error
= -ETIMEDOUT
;
429 dev_err(mmc_dev(host
->mmc
), "%s: -EIO\n", __func__
);
433 data
->bytes_xfered
= host
->datasize
;
436 data_error
= data
->error
;
443 static void mxcmci_read_response(struct mxcmci_host
*host
, unsigned int stat
)
445 struct mmc_command
*cmd
= host
->cmd
;
452 if (stat
& STATUS_TIME_OUT_RESP
) {
453 dev_dbg(mmc_dev(host
->mmc
), "CMD TIMEOUT\n");
454 cmd
->error
= -ETIMEDOUT
;
455 } else if (stat
& STATUS_RESP_CRC_ERR
&& cmd
->flags
& MMC_RSP_CRC
) {
456 dev_dbg(mmc_dev(host
->mmc
), "cmd crc error\n");
457 cmd
->error
= -EILSEQ
;
460 if (cmd
->flags
& MMC_RSP_PRESENT
) {
461 if (cmd
->flags
& MMC_RSP_136
) {
462 for (i
= 0; i
< 4; i
++) {
463 a
= readw(host
->base
+ MMC_REG_RES_FIFO
);
464 b
= readw(host
->base
+ MMC_REG_RES_FIFO
);
465 cmd
->resp
[i
] = a
<< 16 | b
;
468 a
= readw(host
->base
+ MMC_REG_RES_FIFO
);
469 b
= readw(host
->base
+ MMC_REG_RES_FIFO
);
470 c
= readw(host
->base
+ MMC_REG_RES_FIFO
);
471 cmd
->resp
[0] = a
<< 24 | b
<< 8 | c
>> 8;
476 static int mxcmci_poll_status(struct mxcmci_host
*host
, u32 mask
)
479 unsigned long timeout
= jiffies
+ HZ
;
482 stat
= readl(host
->base
+ MMC_REG_STATUS
);
483 if (stat
& STATUS_ERR_MASK
)
485 if (time_after(jiffies
, timeout
)) {
486 mxcmci_softreset(host
);
487 mxcmci_set_clk_rate(host
, host
->clock
);
488 return STATUS_TIME_OUT_READ
;
496 static int mxcmci_pull(struct mxcmci_host
*host
, void *_buf
, int bytes
)
502 stat
= mxcmci_poll_status(host
,
503 STATUS_BUF_READ_RDY
| STATUS_READ_OP_DONE
);
506 *buf
++ = readl(host
->base
+ MMC_REG_BUFFER_ACCESS
);
514 stat
= mxcmci_poll_status(host
,
515 STATUS_BUF_READ_RDY
| STATUS_READ_OP_DONE
);
518 tmp
= readl(host
->base
+ MMC_REG_BUFFER_ACCESS
);
519 memcpy(b
, &tmp
, bytes
);
525 static int mxcmci_push(struct mxcmci_host
*host
, void *_buf
, int bytes
)
531 stat
= mxcmci_poll_status(host
, STATUS_BUF_WRITE_RDY
);
534 writel(*buf
++, host
->base
+ MMC_REG_BUFFER_ACCESS
);
542 stat
= mxcmci_poll_status(host
, STATUS_BUF_WRITE_RDY
);
546 memcpy(&tmp
, b
, bytes
);
547 writel(tmp
, host
->base
+ MMC_REG_BUFFER_ACCESS
);
550 stat
= mxcmci_poll_status(host
, STATUS_BUF_WRITE_RDY
);
557 static int mxcmci_transfer_data(struct mxcmci_host
*host
)
559 struct mmc_data
*data
= host
->req
->data
;
560 struct scatterlist
*sg
;
566 if (data
->flags
& MMC_DATA_READ
) {
567 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
568 stat
= mxcmci_pull(host
, sg_virt(sg
), sg
->length
);
571 host
->datasize
+= sg
->length
;
574 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
575 stat
= mxcmci_push(host
, sg_virt(sg
), sg
->length
);
578 host
->datasize
+= sg
->length
;
580 stat
= mxcmci_poll_status(host
, STATUS_WRITE_OP_DONE
);
587 static void mxcmci_datawork(struct work_struct
*work
)
589 struct mxcmci_host
*host
= container_of(work
, struct mxcmci_host
,
591 int datastat
= mxcmci_transfer_data(host
);
593 writel(STATUS_READ_OP_DONE
| STATUS_WRITE_OP_DONE
,
594 host
->base
+ MMC_REG_STATUS
);
595 mxcmci_finish_data(host
, datastat
);
597 if (host
->req
->stop
) {
598 if (mxcmci_start_cmd(host
, host
->req
->stop
, 0)) {
599 mxcmci_finish_request(host
, host
->req
);
603 mxcmci_finish_request(host
, host
->req
);
607 static void mxcmci_data_done(struct mxcmci_host
*host
, unsigned int stat
)
609 struct mmc_data
*data
= host
->data
;
615 data_error
= mxcmci_finish_data(host
, stat
);
617 mxcmci_read_response(host
, stat
);
620 if (host
->req
->stop
) {
621 if (mxcmci_start_cmd(host
, host
->req
->stop
, 0)) {
622 mxcmci_finish_request(host
, host
->req
);
626 mxcmci_finish_request(host
, host
->req
);
630 static void mxcmci_cmd_done(struct mxcmci_host
*host
, unsigned int stat
)
632 mxcmci_read_response(host
, stat
);
635 if (!host
->data
&& host
->req
) {
636 mxcmci_finish_request(host
, host
->req
);
640 /* For the DMA case the DMA engine handles the data transfer
641 * automatically. For non DMA we have to do it ourselves.
642 * Don't do it in interrupt context though.
644 if (!mxcmci_use_dma(host
) && host
->data
)
645 schedule_work(&host
->datawork
);
649 static irqreturn_t
mxcmci_irq(int irq
, void *devid
)
651 struct mxcmci_host
*host
= devid
;
656 stat
= readl(host
->base
+ MMC_REG_STATUS
);
657 writel(stat
& ~(STATUS_SDIO_INT_ACTIVE
| STATUS_DATA_TRANS_DONE
|
658 STATUS_WRITE_OP_DONE
), host
->base
+ MMC_REG_STATUS
);
660 dev_dbg(mmc_dev(host
->mmc
), "%s: 0x%08x\n", __func__
, stat
);
662 spin_lock_irqsave(&host
->lock
, flags
);
663 sdio_irq
= (stat
& STATUS_SDIO_INT_ACTIVE
) && host
->use_sdio
;
664 spin_unlock_irqrestore(&host
->lock
, flags
);
666 if (mxcmci_use_dma(host
) &&
667 (stat
& (STATUS_READ_OP_DONE
| STATUS_WRITE_OP_DONE
)))
668 writel(STATUS_READ_OP_DONE
| STATUS_WRITE_OP_DONE
,
669 host
->base
+ MMC_REG_STATUS
);
672 writel(STATUS_SDIO_INT_ACTIVE
, host
->base
+ MMC_REG_STATUS
);
673 mmc_signal_sdio_irq(host
->mmc
);
676 if (stat
& STATUS_END_CMD_RESP
)
677 mxcmci_cmd_done(host
, stat
);
679 if (mxcmci_use_dma(host
) &&
680 (stat
& (STATUS_DATA_TRANS_DONE
| STATUS_WRITE_OP_DONE
))) {
681 del_timer(&host
->watchdog
);
682 mxcmci_data_done(host
, stat
);
685 if (host
->default_irq_mask
&&
686 (stat
& (STATUS_CARD_INSERTION
| STATUS_CARD_REMOVAL
)))
687 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
692 static void mxcmci_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
694 struct mxcmci_host
*host
= mmc_priv(mmc
);
695 unsigned int cmdat
= host
->cmdat
;
698 WARN_ON(host
->req
!= NULL
);
701 host
->cmdat
&= ~CMD_DAT_CONT_INIT
;
707 error
= mxcmci_setup_data(host
, req
->data
);
709 req
->cmd
->error
= error
;
714 cmdat
|= CMD_DAT_CONT_DATA_ENABLE
;
716 if (req
->data
->flags
& MMC_DATA_WRITE
)
717 cmdat
|= CMD_DAT_CONT_WRITE
;
720 error
= mxcmci_start_cmd(host
, req
->cmd
, cmdat
);
724 mxcmci_finish_request(host
, req
);
727 static void mxcmci_set_clk_rate(struct mxcmci_host
*host
, unsigned int clk_ios
)
729 unsigned int divider
;
731 unsigned int clk_in
= clk_get_rate(host
->clk_per
);
733 while (prescaler
<= 0x800) {
734 for (divider
= 1; divider
<= 0xF; divider
++) {
737 x
= (clk_in
/ (divider
+ 1));
740 x
/= (prescaler
* 2);
754 writew((prescaler
<< 4) | divider
, host
->base
+ MMC_REG_CLK_RATE
);
756 dev_dbg(mmc_dev(host
->mmc
), "scaler: %d divider: %d in: %d out: %d\n",
757 prescaler
, divider
, clk_in
, clk_ios
);
760 static int mxcmci_setup_dma(struct mmc_host
*mmc
)
762 struct mxcmci_host
*host
= mmc_priv(mmc
);
763 struct dma_slave_config
*config
= &host
->dma_slave_config
;
765 config
->dst_addr
= host
->res
->start
+ MMC_REG_BUFFER_ACCESS
;
766 config
->src_addr
= host
->res
->start
+ MMC_REG_BUFFER_ACCESS
;
767 config
->dst_addr_width
= 4;
768 config
->src_addr_width
= 4;
769 config
->dst_maxburst
= host
->burstlen
;
770 config
->src_maxburst
= host
->burstlen
;
771 config
->device_fc
= false;
773 return dmaengine_slave_config(host
->dma
, config
);
776 static void mxcmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
778 struct mxcmci_host
*host
= mmc_priv(mmc
);
782 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
783 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
785 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
790 if (mxcmci_use_dma(host
) && burstlen
!= host
->burstlen
) {
791 host
->burstlen
= burstlen
;
792 ret
= mxcmci_setup_dma(mmc
);
794 dev_err(mmc_dev(host
->mmc
),
795 "failed to config DMA channel. Falling back to PIO\n");
796 dma_release_channel(host
->dma
);
802 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
803 host
->cmdat
|= CMD_DAT_CONT_BUS_WIDTH_4
;
805 host
->cmdat
&= ~CMD_DAT_CONT_BUS_WIDTH_4
;
807 if (host
->power_mode
!= ios
->power_mode
) {
808 mxcmci_set_power(host
, ios
->power_mode
, ios
->vdd
);
809 host
->power_mode
= ios
->power_mode
;
811 if (ios
->power_mode
== MMC_POWER_ON
)
812 host
->cmdat
|= CMD_DAT_CONT_INIT
;
816 mxcmci_set_clk_rate(host
, ios
->clock
);
817 writew(STR_STP_CLK_START_CLK
, host
->base
+ MMC_REG_STR_STP_CLK
);
819 writew(STR_STP_CLK_STOP_CLK
, host
->base
+ MMC_REG_STR_STP_CLK
);
822 host
->clock
= ios
->clock
;
825 static irqreturn_t
mxcmci_detect_irq(int irq
, void *data
)
827 struct mmc_host
*mmc
= data
;
829 dev_dbg(mmc_dev(mmc
), "%s\n", __func__
);
831 mmc_detect_change(mmc
, msecs_to_jiffies(250));
835 static int mxcmci_get_ro(struct mmc_host
*mmc
)
837 struct mxcmci_host
*host
= mmc_priv(mmc
);
839 if (host
->pdata
&& host
->pdata
->get_ro
)
840 return !!host
->pdata
->get_ro(mmc_dev(mmc
));
842 * Board doesn't support read only detection; let the mmc core
848 static void mxcmci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
850 struct mxcmci_host
*host
= mmc_priv(mmc
);
854 spin_lock_irqsave(&host
->lock
, flags
);
855 host
->use_sdio
= enable
;
856 int_cntr
= readl(host
->base
+ MMC_REG_INT_CNTR
);
859 int_cntr
|= INT_SDIO_IRQ_EN
;
861 int_cntr
&= ~INT_SDIO_IRQ_EN
;
863 writel(int_cntr
, host
->base
+ MMC_REG_INT_CNTR
);
864 spin_unlock_irqrestore(&host
->lock
, flags
);
867 static void mxcmci_init_card(struct mmc_host
*host
, struct mmc_card
*card
)
869 struct mxcmci_host
*mxcmci
= mmc_priv(host
);
872 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
873 * multi-block transfers when connected SDIO peripheral doesn't
874 * drive the BUSY line as required by the specs.
875 * One way to prevent this is to only allow 1-bit transfers.
878 if (is_imx31_mmc(mxcmci
) && card
->type
== MMC_TYPE_SDIO
)
879 host
->caps
&= ~MMC_CAP_4_BIT_DATA
;
881 host
->caps
|= MMC_CAP_4_BIT_DATA
;
884 static bool filter(struct dma_chan
*chan
, void *param
)
886 struct mxcmci_host
*host
= param
;
888 if (!imx_dma_is_general_purpose(chan
))
891 chan
->private = &host
->dma_data
;
896 static void mxcmci_watchdog(unsigned long data
)
898 struct mmc_host
*mmc
= (struct mmc_host
*)data
;
899 struct mxcmci_host
*host
= mmc_priv(mmc
);
900 struct mmc_request
*req
= host
->req
;
901 unsigned int stat
= readl(host
->base
+ MMC_REG_STATUS
);
903 if (host
->dma_dir
== DMA_FROM_DEVICE
) {
904 dmaengine_terminate_all(host
->dma
);
905 dev_err(mmc_dev(host
->mmc
),
906 "%s: read time out (status = 0x%08x)\n",
909 dev_err(mmc_dev(host
->mmc
),
910 "%s: write time out (status = 0x%08x)\n",
912 mxcmci_softreset(host
);
915 /* Mark transfer as erroneus and inform the upper layers */
917 host
->data
->error
= -ETIMEDOUT
;
921 mmc_request_done(host
->mmc
, req
);
924 static const struct mmc_host_ops mxcmci_ops
= {
925 .request
= mxcmci_request
,
926 .set_ios
= mxcmci_set_ios
,
927 .get_ro
= mxcmci_get_ro
,
928 .enable_sdio_irq
= mxcmci_enable_sdio_irq
,
929 .init_card
= mxcmci_init_card
,
932 static int mxcmci_probe(struct platform_device
*pdev
)
934 struct mmc_host
*mmc
;
935 struct mxcmci_host
*host
= NULL
;
936 struct resource
*iores
, *r
;
940 pr_info("i.MX SDHC driver\n");
942 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
943 irq
= platform_get_irq(pdev
, 0);
944 if (!iores
|| irq
< 0)
947 r
= request_mem_region(iores
->start
, resource_size(iores
), pdev
->name
);
951 mmc
= mmc_alloc_host(sizeof(struct mxcmci_host
), &pdev
->dev
);
954 goto out_release_mem
;
957 mmc
->ops
= &mxcmci_ops
;
958 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SDIO_IRQ
;
960 /* MMC core transfer sizes tunable parameters */
962 mmc
->max_blk_size
= 2048;
963 mmc
->max_blk_count
= 65535;
964 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
965 mmc
->max_seg_size
= mmc
->max_req_size
;
967 host
= mmc_priv(mmc
);
968 host
->base
= ioremap(r
->start
, resource_size(r
));
975 host
->pdata
= pdev
->dev
.platform_data
;
976 host
->devtype
= pdev
->id_entry
->driver_data
;
977 spin_lock_init(&host
->lock
);
979 mxcmci_init_ocr(host
);
981 if (host
->pdata
&& host
->pdata
->dat3_card_detect
)
982 host
->default_irq_mask
=
983 INT_CARD_INSERTION_EN
| INT_CARD_REMOVAL_EN
;
985 host
->default_irq_mask
= 0;
990 host
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
991 if (IS_ERR(host
->clk_ipg
)) {
992 ret
= PTR_ERR(host
->clk_ipg
);
996 host
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
997 if (IS_ERR(host
->clk_per
)) {
998 ret
= PTR_ERR(host
->clk_per
);
1002 clk_prepare_enable(host
->clk_per
);
1003 clk_prepare_enable(host
->clk_ipg
);
1005 mxcmci_softreset(host
);
1007 host
->rev_no
= readw(host
->base
+ MMC_REG_REV_NO
);
1008 if (host
->rev_no
!= 0x400) {
1010 dev_err(mmc_dev(host
->mmc
), "wrong rev.no. 0x%08x. aborting.\n",
1015 mmc
->f_min
= clk_get_rate(host
->clk_per
) >> 16;
1016 mmc
->f_max
= clk_get_rate(host
->clk_per
) >> 1;
1018 /* recommended in data sheet */
1019 writew(0x2db4, host
->base
+ MMC_REG_READ_TO
);
1021 writel(host
->default_irq_mask
, host
->base
+ MMC_REG_INT_CNTR
);
1023 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1025 host
->dmareq
= r
->start
;
1026 host
->dma_data
.peripheral_type
= IMX_DMATYPE_SDHC
;
1027 host
->dma_data
.priority
= DMA_PRIO_LOW
;
1028 host
->dma_data
.dma_request
= host
->dmareq
;
1030 dma_cap_set(DMA_SLAVE
, mask
);
1031 host
->dma
= dma_request_channel(mask
, filter
, host
);
1033 mmc
->max_seg_size
= dma_get_max_seg_size(
1034 host
->dma
->device
->dev
);
1038 dev_info(mmc_dev(host
->mmc
), "dma not available. Using PIO\n");
1040 INIT_WORK(&host
->datawork
, mxcmci_datawork
);
1042 ret
= request_irq(host
->irq
, mxcmci_irq
, 0, DRIVER_NAME
, host
);
1046 platform_set_drvdata(pdev
, mmc
);
1048 if (host
->pdata
&& host
->pdata
->init
) {
1049 ret
= host
->pdata
->init(&pdev
->dev
, mxcmci_detect_irq
,
1057 init_timer(&host
->watchdog
);
1058 host
->watchdog
.function
= &mxcmci_watchdog
;
1059 host
->watchdog
.data
= (unsigned long)mmc
;
1064 free_irq(host
->irq
, host
);
1067 dma_release_channel(host
->dma
);
1069 clk_disable_unprepare(host
->clk_per
);
1070 clk_disable_unprepare(host
->clk_ipg
);
1072 iounmap(host
->base
);
1076 release_mem_region(iores
->start
, resource_size(iores
));
1080 static int mxcmci_remove(struct platform_device
*pdev
)
1082 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
1083 struct mxcmci_host
*host
= mmc_priv(mmc
);
1085 platform_set_drvdata(pdev
, NULL
);
1087 mmc_remove_host(mmc
);
1090 regulator_put(host
->vcc
);
1092 if (host
->pdata
&& host
->pdata
->exit
)
1093 host
->pdata
->exit(&pdev
->dev
, mmc
);
1095 free_irq(host
->irq
, host
);
1096 iounmap(host
->base
);
1099 dma_release_channel(host
->dma
);
1101 clk_disable_unprepare(host
->clk_per
);
1102 clk_disable_unprepare(host
->clk_ipg
);
1104 release_mem_region(host
->res
->start
, resource_size(host
->res
));
1112 static int mxcmci_suspend(struct device
*dev
)
1114 struct mmc_host
*mmc
= dev_get_drvdata(dev
);
1115 struct mxcmci_host
*host
= mmc_priv(mmc
);
1119 ret
= mmc_suspend_host(mmc
);
1120 clk_disable_unprepare(host
->clk_per
);
1121 clk_disable_unprepare(host
->clk_ipg
);
1126 static int mxcmci_resume(struct device
*dev
)
1128 struct mmc_host
*mmc
= dev_get_drvdata(dev
);
1129 struct mxcmci_host
*host
= mmc_priv(mmc
);
1132 clk_prepare_enable(host
->clk_per
);
1133 clk_prepare_enable(host
->clk_ipg
);
1135 ret
= mmc_resume_host(mmc
);
1140 static const struct dev_pm_ops mxcmci_pm_ops
= {
1141 .suspend
= mxcmci_suspend
,
1142 .resume
= mxcmci_resume
,
1146 static struct platform_driver mxcmci_driver
= {
1147 .probe
= mxcmci_probe
,
1148 .remove
= mxcmci_remove
,
1149 .id_table
= mxcmci_devtype
,
1151 .name
= DRIVER_NAME
,
1152 .owner
= THIS_MODULE
,
1154 .pm
= &mxcmci_pm_ops
,
1159 module_platform_driver(mxcmci_driver
);
1161 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1162 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1163 MODULE_LICENSE("GPL");
1164 MODULE_ALIAS("platform:imx-mmc");